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[mTask.git] / int / com / lib / CMSIS-hal / Device / ST / STM32F7xx / Include / stm32f767xx.h
1 /**
2 ******************************************************************************
3 * @file stm32f767xx.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral\92s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS_Device
45 * @{
46 */
47
48 /** @addtogroup stm32f767xx
49 * @{
50 */
51
52 #ifndef __STM32F767xx_H
53 #define __STM32F767xx_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63 /**
64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
65 * in @ref Library_configuration_section
66 */
67 typedef enum
68 {
69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
84 RCC_IRQn = 5, /*!< RCC global Interrupt */
85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
127 FMC_IRQn = 48, /*!< FMC global Interrupt */
128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
150 USART6_IRQn = 71, /*!< USART6 global interrupt */
151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
158 RNG_IRQn = 80, /*!< RNG global interrupt */
159 FPU_IRQn = 81, /*!< FPU global interrupt */
160 UART7_IRQn = 82, /*!< UART7 global interrupt */
161 UART8_IRQn = 83, /*!< UART8 global interrupt */
162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
175 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
176 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
177 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
178 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
179 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
180 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
181 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
182 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
183 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
184 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
185 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
186 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
187 } IRQn_Type;
188
189 /**
190 * @}
191 */
192
193 /**
194 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
195 */
196 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
197 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
198 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
199 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
200 #define __FPU_PRESENT 1 /*!< FPU present */
201 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
202 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
203 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
204
205
206 #include "system_stm32f7xx.h"
207 #include <stdint.h>
208
209 /** @addtogroup Peripheral_registers_structures
210 * @{
211 */
212
213 /**
214 * @brief Analog to Digital Converter
215 */
216
217 typedef struct
218 {
219 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
220 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
221 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
222 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
223 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
224 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
225 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
226 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
227 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
228 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
229 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
230 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
231 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
232 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
233 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
234 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
235 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
236 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
237 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
238 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
239 } ADC_TypeDef;
240
241 typedef struct
242 {
243 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
244 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
245 __IO uint32_t CDR; /*!< ADC common regular data register for dual
246 AND triple modes, Address offset: ADC1 base address + 0x308 */
247 } ADC_Common_TypeDef;
248
249
250 /**
251 * @brief Controller Area Network TxMailBox
252 */
253
254 typedef struct
255 {
256 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
257 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
258 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
259 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
260 } CAN_TxMailBox_TypeDef;
261
262 /**
263 * @brief Controller Area Network FIFOMailBox
264 */
265
266 typedef struct
267 {
268 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
269 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
270 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
271 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
272 } CAN_FIFOMailBox_TypeDef;
273
274 /**
275 * @brief Controller Area Network FilterRegister
276 */
277
278 typedef struct
279 {
280 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
281 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
282 } CAN_FilterRegister_TypeDef;
283
284 /**
285 * @brief Controller Area Network
286 */
287
288 typedef struct
289 {
290 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
291 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
292 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
293 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
294 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
295 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
296 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
297 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
298 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
299 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
300 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
301 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
302 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
303 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
304 uint32_t RESERVED2; /*!< Reserved, 0x208 */
305 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
306 uint32_t RESERVED3; /*!< Reserved, 0x210 */
307 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
308 uint32_t RESERVED4; /*!< Reserved, 0x218 */
309 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
310 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
311 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
312 } CAN_TypeDef;
313
314 /**
315 * @brief HDMI-CEC
316 */
317
318 typedef struct
319 {
320 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
321 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
322 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
323 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
324 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
325 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
326 }CEC_TypeDef;
327
328
329 /**
330 * @brief CRC calculation unit
331 */
332
333 typedef struct
334 {
335 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
336 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
337 uint8_t RESERVED0; /*!< Reserved, 0x05 */
338 uint16_t RESERVED1; /*!< Reserved, 0x06 */
339 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
340 uint32_t RESERVED2; /*!< Reserved, 0x0C */
341 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
342 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
343 } CRC_TypeDef;
344
345 /**
346 * @brief Digital to Analog Converter
347 */
348
349 typedef struct
350 {
351 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
352 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
353 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
354 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
355 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
356 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
357 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
358 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
359 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
360 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
361 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
362 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
363 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
364 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
365 } DAC_TypeDef;
366
367 /**
368 * @brief DFSDM module registers
369 */
370 typedef struct
371 {
372 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
373 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
374 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
375 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
376 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
377 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
378 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
379 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
380 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
381 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
382 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
383 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
384 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
385 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
386 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
387 } DFSDM_Filter_TypeDef;
388
389 /**
390 * @brief DFSDM channel configuration registers
391 */
392 typedef struct
393 {
394 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
395 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
396 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
397 short circuit detector register, Address offset: 0x08 */
398 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
399 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
400 } DFSDM_Channel_TypeDef;
401
402 /**
403 * @brief Debug MCU
404 */
405
406 typedef struct
407 {
408 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
409 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
410 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
411 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
412 }DBGMCU_TypeDef;
413
414 /**
415 * @brief DCMI
416 */
417
418 typedef struct
419 {
420 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
421 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
422 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
423 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
424 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
425 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
426 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
427 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
428 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
429 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
430 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
431 } DCMI_TypeDef;
432
433 /**
434 * @brief DMA Controller
435 */
436
437 typedef struct
438 {
439 __IO uint32_t CR; /*!< DMA stream x configuration register */
440 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
441 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
442 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
443 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
444 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
445 } DMA_Stream_TypeDef;
446
447 typedef struct
448 {
449 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
450 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
451 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
452 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
453 } DMA_TypeDef;
454
455
456 /**
457 * @brief DMA2D Controller
458 */
459
460 typedef struct
461 {
462 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
463 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
464 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
465 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
466 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
467 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
468 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
469 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
470 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
471 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
472 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
473 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
474 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
475 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
476 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
477 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
478 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
479 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
480 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
481 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
482 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
483 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
484 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
485 } DMA2D_TypeDef;
486
487
488 /**
489 * @brief Ethernet MAC
490 */
491
492 typedef struct
493 {
494 __IO uint32_t MACCR;
495 __IO uint32_t MACFFR;
496 __IO uint32_t MACHTHR;
497 __IO uint32_t MACHTLR;
498 __IO uint32_t MACMIIAR;
499 __IO uint32_t MACMIIDR;
500 __IO uint32_t MACFCR;
501 __IO uint32_t MACVLANTR; /* 8 */
502 uint32_t RESERVED0[2];
503 __IO uint32_t MACRWUFFR; /* 11 */
504 __IO uint32_t MACPMTCSR;
505 uint32_t RESERVED1[2];
506 __IO uint32_t MACSR; /* 15 */
507 __IO uint32_t MACIMR;
508 __IO uint32_t MACA0HR;
509 __IO uint32_t MACA0LR;
510 __IO uint32_t MACA1HR;
511 __IO uint32_t MACA1LR;
512 __IO uint32_t MACA2HR;
513 __IO uint32_t MACA2LR;
514 __IO uint32_t MACA3HR;
515 __IO uint32_t MACA3LR; /* 24 */
516 uint32_t RESERVED2[40];
517 __IO uint32_t MMCCR; /* 65 */
518 __IO uint32_t MMCRIR;
519 __IO uint32_t MMCTIR;
520 __IO uint32_t MMCRIMR;
521 __IO uint32_t MMCTIMR; /* 69 */
522 uint32_t RESERVED3[14];
523 __IO uint32_t MMCTGFSCCR; /* 84 */
524 __IO uint32_t MMCTGFMSCCR;
525 uint32_t RESERVED4[5];
526 __IO uint32_t MMCTGFCR;
527 uint32_t RESERVED5[10];
528 __IO uint32_t MMCRFCECR;
529 __IO uint32_t MMCRFAECR;
530 uint32_t RESERVED6[10];
531 __IO uint32_t MMCRGUFCR;
532 uint32_t RESERVED7[334];
533 __IO uint32_t PTPTSCR;
534 __IO uint32_t PTPSSIR;
535 __IO uint32_t PTPTSHR;
536 __IO uint32_t PTPTSLR;
537 __IO uint32_t PTPTSHUR;
538 __IO uint32_t PTPTSLUR;
539 __IO uint32_t PTPTSAR;
540 __IO uint32_t PTPTTHR;
541 __IO uint32_t PTPTTLR;
542 __IO uint32_t RESERVED8;
543 __IO uint32_t PTPTSSR;
544 uint32_t RESERVED9[565];
545 __IO uint32_t DMABMR;
546 __IO uint32_t DMATPDR;
547 __IO uint32_t DMARPDR;
548 __IO uint32_t DMARDLAR;
549 __IO uint32_t DMATDLAR;
550 __IO uint32_t DMASR;
551 __IO uint32_t DMAOMR;
552 __IO uint32_t DMAIER;
553 __IO uint32_t DMAMFBOCR;
554 __IO uint32_t DMARSWTR;
555 uint32_t RESERVED10[8];
556 __IO uint32_t DMACHTDR;
557 __IO uint32_t DMACHRDR;
558 __IO uint32_t DMACHTBAR;
559 __IO uint32_t DMACHRBAR;
560 } ETH_TypeDef;
561
562 /**
563 * @brief External Interrupt/Event Controller
564 */
565
566 typedef struct
567 {
568 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
569 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
570 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
571 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
572 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
573 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
574 } EXTI_TypeDef;
575
576 /**
577 * @brief FLASH Registers
578 */
579
580 typedef struct
581 {
582 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
583 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
584 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
585 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
586 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
587 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
588 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
589 } FLASH_TypeDef;
590
591
592
593 /**
594 * @brief Flexible Memory Controller
595 */
596
597 typedef struct
598 {
599 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
600 } FMC_Bank1_TypeDef;
601
602 /**
603 * @brief Flexible Memory Controller Bank1E
604 */
605
606 typedef struct
607 {
608 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
609 } FMC_Bank1E_TypeDef;
610
611 /**
612 * @brief Flexible Memory Controller Bank3
613 */
614
615 typedef struct
616 {
617 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
618 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
619 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
620 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
621 uint32_t RESERVED0; /*!< Reserved, 0x90 */
622 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
623 } FMC_Bank3_TypeDef;
624
625 /**
626 * @brief Flexible Memory Controller Bank5_6
627 */
628
629 typedef struct
630 {
631 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
632 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
633 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
634 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
635 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
636 } FMC_Bank5_6_TypeDef;
637
638
639 /**
640 * @brief General Purpose I/O
641 */
642
643 typedef struct
644 {
645 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
646 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
647 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
648 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
649 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
650 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
651 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
652 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
653 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
654 } GPIO_TypeDef;
655
656 /**
657 * @brief System configuration controller
658 */
659
660 typedef struct
661 {
662 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
663 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
664 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
665 uint32_t RESERVED; /*!< Reserved, 0x18 */
666 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
667 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
668 } SYSCFG_TypeDef;
669
670 /**
671 * @brief Inter-integrated Circuit Interface
672 */
673
674 typedef struct
675 {
676 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
677 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
678 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
679 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
680 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
681 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
682 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
683 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
684 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
685 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
686 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
687 } I2C_TypeDef;
688
689 /**
690 * @brief Independent WATCHDOG
691 */
692
693 typedef struct
694 {
695 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
696 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
697 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
698 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
699 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
700 } IWDG_TypeDef;
701
702
703 /**
704 * @brief LCD-TFT Display Controller
705 */
706
707 typedef struct
708 {
709 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
710 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
711 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
712 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
713 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
714 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
715 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
716 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
717 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
718 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
719 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
720 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
721 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
722 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
723 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
724 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
725 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
726 } LTDC_TypeDef;
727
728 /**
729 * @brief LCD-TFT Display layer x Controller
730 */
731
732 typedef struct
733 {
734 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
735 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
736 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
737 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
738 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
739 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
740 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
741 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
742 uint32_t RESERVED0[2]; /*!< Reserved */
743 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
744 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
745 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
746 uint32_t RESERVED1[3]; /*!< Reserved */
747 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
748
749 } LTDC_Layer_TypeDef;
750
751 /**
752 * @brief Power Control
753 */
754
755 typedef struct
756 {
757 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
758 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
759 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
760 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
761 } PWR_TypeDef;
762
763
764 /**
765 * @brief Reset and Clock Control
766 */
767
768 typedef struct
769 {
770 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
771 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
772 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
773 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
774 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
775 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
776 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
777 uint32_t RESERVED0; /*!< Reserved, 0x1C */
778 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
779 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
780 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
781 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
782 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
783 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
784 uint32_t RESERVED2; /*!< Reserved, 0x3C */
785 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
786 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
787 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
788 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
789 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
790 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
791 uint32_t RESERVED4; /*!< Reserved, 0x5C */
792 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
793 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
794 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
795 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
796 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
797 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
798 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
799 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
800 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
801 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
802 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
803
804 } RCC_TypeDef;
805
806 /**
807 * @brief Real-Time Clock
808 */
809
810 typedef struct
811 {
812 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
813 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
814 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
815 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
816 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
817 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
818 uint32_t reserved; /*!< Reserved */
819 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
820 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
821 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
822 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
823 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
824 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
825 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
826 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
827 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
828 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
829 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
830 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
831 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
832 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
833 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
834 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
835 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
836 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
837 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
838 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
839 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
840 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
841 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
842 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
843 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
844 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
845 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
846 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
847 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
848 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
849 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
850 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
851 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
852 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
853 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
854 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
855 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
856 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
857 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
858 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
859 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
860 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
861 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
862 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
863 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
864 } RTC_TypeDef;
865
866
867 /**
868 * @brief Serial Audio Interface
869 */
870
871 typedef struct
872 {
873 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
874 } SAI_TypeDef;
875
876 typedef struct
877 {
878 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
879 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
880 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
881 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
882 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
883 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
884 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
885 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
886 } SAI_Block_TypeDef;
887
888 /**
889 * @brief SPDIF-RX Interface
890 */
891
892 typedef struct
893 {
894 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
895 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
896 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
897 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
898 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
899 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
900 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
901 } SPDIFRX_TypeDef;
902
903
904 /**
905 * @brief SD host Interface
906 */
907
908 typedef struct
909 {
910 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
911 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
912 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
913 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
914 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
915 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
916 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
917 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
918 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
919 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
920 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
921 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
922 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
923 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
924 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
925 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
926 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
927 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
928 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
929 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
930 } SDMMC_TypeDef;
931
932 /**
933 * @brief Serial Peripheral Interface
934 */
935
936 typedef struct
937 {
938 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
939 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
940 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
941 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
942 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
943 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
944 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
945 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
946 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
947 } SPI_TypeDef;
948
949 /**
950 * @brief QUAD Serial Peripheral Interface
951 */
952
953 typedef struct
954 {
955 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
956 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
957 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
958 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
959 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
960 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
961 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
962 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
963 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
964 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
965 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
966 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
967 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
968 } QUADSPI_TypeDef;
969
970 /**
971 * @brief TIM
972 */
973
974 typedef struct
975 {
976 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
977 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
978 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
979 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
980 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
981 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
982 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
983 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
984 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
985 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
986 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
987 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
988 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
989 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
990 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
991 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
992 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
993 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
994 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
995 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
996 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
997 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
998 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
999 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
1000 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
1001 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
1002
1003 } TIM_TypeDef;
1004
1005 /**
1006 * @brief LPTIMIMER
1007 */
1008 typedef struct
1009 {
1010 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1011 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1012 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1013 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1014 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1015 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1016 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1017 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1018 } LPTIM_TypeDef;
1019
1020
1021 /**
1022 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1023 */
1024
1025 typedef struct
1026 {
1027 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1028 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1029 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1030 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1031 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1032 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1033 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1034 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1035 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1036 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1037 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1038 } USART_TypeDef;
1039
1040
1041 /**
1042 * @brief Window WATCHDOG
1043 */
1044
1045 typedef struct
1046 {
1047 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1048 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1049 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1050 } WWDG_TypeDef;
1051
1052
1053 /**
1054 * @brief RNG
1055 */
1056
1057 typedef struct
1058 {
1059 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1060 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1061 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1062 } RNG_TypeDef;
1063
1064 /**
1065 * @}
1066 */
1067
1068 /**
1069 * @brief USB_OTG_Core_Registers
1070 */
1071 typedef struct
1072 {
1073 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1074 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1075 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1076 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1077 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1078 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1079 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1080 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1081 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1082 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1083 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1084 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1085 uint32_t Reserved30[2]; /*!< Reserved 030h */
1086 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1087 __IO uint32_t CID; /*!< User ID Register 03Ch */
1088 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
1089 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1090 uint32_t Reserved6; /*!< Reserved 050h */
1091 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1092 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1093 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1094 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1095 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1096 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1097 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1098 } USB_OTG_GlobalTypeDef;
1099
1100
1101 /**
1102 * @brief USB_OTG_device_Registers
1103 */
1104 typedef struct
1105 {
1106 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1107 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1108 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1109 uint32_t Reserved0C; /*!< Reserved 80Ch */
1110 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1111 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1112 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1113 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1114 uint32_t Reserved20; /*!< Reserved 820h */
1115 uint32_t Reserved9; /*!< Reserved 824h */
1116 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1117 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1118 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1119 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1120 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1121 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1122 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1123 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1124 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1125 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1126 } USB_OTG_DeviceTypeDef;
1127
1128
1129 /**
1130 * @brief USB_OTG_IN_Endpoint-Specific_Register
1131 */
1132 typedef struct
1133 {
1134 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1135 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1136 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1137 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1138 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1139 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1140 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1141 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1142 } USB_OTG_INEndpointTypeDef;
1143
1144
1145 /**
1146 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1147 */
1148 typedef struct
1149 {
1150 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1151 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1152 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1153 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1154 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1155 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1156 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1157 } USB_OTG_OUTEndpointTypeDef;
1158
1159
1160 /**
1161 * @brief USB_OTG_Host_Mode_Register_Structures
1162 */
1163 typedef struct
1164 {
1165 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1166 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1167 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1168 uint32_t Reserved40C; /*!< Reserved 40Ch */
1169 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1170 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1171 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1172 } USB_OTG_HostTypeDef;
1173
1174 /**
1175 * @brief USB_OTG_Host_Channel_Specific_Registers
1176 */
1177 typedef struct
1178 {
1179 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1180 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1181 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1182 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1183 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1184 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1185 uint32_t Reserved[2]; /*!< Reserved */
1186 } USB_OTG_HostChannelTypeDef;
1187 /**
1188 * @}
1189 */
1190
1191 /**
1192 * @brief JPEG Codec
1193 */
1194 typedef struct
1195 {
1196 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1197 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1198 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1199 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1200 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1201 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1202 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1203 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1204 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1205 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1206 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1207 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1208 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1209 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1210 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1211 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1212 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1213 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1214 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1215 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1216 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1217 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1218 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1219 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1220 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1221 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
1222 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
1223 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
1224 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
1225
1226 } JPEG_TypeDef;
1227
1228 /**
1229 * @brief MDIOS
1230 */
1231
1232 typedef struct
1233 {
1234 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
1235 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
1236 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
1237 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
1238 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
1239 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
1240 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
1241 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
1242 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
1243 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
1244 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
1245 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
1246 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
1247 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
1248 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
1249 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
1250 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
1251 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
1252 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
1253 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
1254 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
1255 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
1256 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
1257 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
1258 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
1259 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
1260 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
1261 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
1262 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
1263 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
1264 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
1265 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
1266 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
1267 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
1268 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
1269 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
1270 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
1271 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
1272 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
1273 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
1274 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
1275 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
1276 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
1277 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
1278 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
1279 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
1280 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
1281 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
1282 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
1283 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
1284 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
1285 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
1286 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
1287 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
1288 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
1289 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
1290 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
1291 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
1292 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
1293 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
1294 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
1295 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
1296 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
1297 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
1298 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
1299 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
1300 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
1301 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
1302 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
1303 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
1304 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
1305 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
1306 } MDIOS_TypeDef;
1307
1308
1309 /** @addtogroup Peripheral_memory_map
1310 * @{
1311 */
1312 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
1313 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
1314 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1315 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
1316 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
1317 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
1318 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
1319 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
1320 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
1321 #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
1322 #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
1323 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1324
1325 /* Legacy define */
1326 #define FLASH_BASE FLASHAXI_BASE
1327
1328 /*!< Peripheral memory map */
1329 #define APB1PERIPH_BASE PERIPH_BASE
1330 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1331 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1332 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1333
1334 /*!< APB1 peripherals */
1335 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1336 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1337 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1338 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1339 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1340 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1341 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1342 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1343 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1344 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1345 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1346 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1347 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1348 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
1349 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1350 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1351 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1352 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1353 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1354 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1355 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1356 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1357 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1358 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1359 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1360 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1361 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1362 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1363 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1364 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1365 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1366 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1367
1368 /*!< APB2 peripherals */
1369 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1370 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1371 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1372 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1373 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
1374 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1375 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1376 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1377 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1378 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1379 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1380 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1381 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1382 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1383 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1384 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1385 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1386 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1387 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1388 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1389 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1390 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1391 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1392 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1393 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1394 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1395 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1396 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1397 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
1398 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
1399 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
1400 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
1401 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
1402 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
1403 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
1404 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
1405 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
1406 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
1407 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
1408 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
1409 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
1410 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
1411 /*!< AHB1 peripherals */
1412 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1413 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1414 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1415 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1416 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1417 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1418 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1419 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1420 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1421 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1422 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1423 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1424 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1425 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1426 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
1427 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
1428 #define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1429 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1430 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1431 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1432 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1433 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1434 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1435 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1436 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1437 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1438 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1439 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1440 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1441 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1442 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1443 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1444 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1445 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1446 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1447 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1448 #define ETH_MAC_BASE (ETH_BASE)
1449 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1450 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1451 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1452 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1453 /*!< AHB2 peripherals */
1454 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1455 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
1456 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1457 /*!< FMC Bankx registers base address */
1458 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1459 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1460 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1461 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1462
1463 /* Debug MCU registers base address */
1464 #define DBGMCU_BASE 0xE0042000U
1465
1466 /*!< USB registers base address */
1467 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1468 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1469
1470 #define USB_OTG_GLOBAL_BASE 0x000U
1471 #define USB_OTG_DEVICE_BASE 0x800U
1472 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1473 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1474 #define USB_OTG_EP_REG_SIZE 0x20U
1475 #define USB_OTG_HOST_BASE 0x400U
1476 #define USB_OTG_HOST_PORT_BASE 0x440U
1477 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1478 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1479 #define USB_OTG_PCGCCTL_BASE 0xE00U
1480 #define USB_OTG_FIFO_BASE 0x1000U
1481 #define USB_OTG_FIFO_SIZE 0x1000U
1482
1483 /**
1484 * @}
1485 */
1486
1487 /** @addtogroup Peripheral_declaration
1488 * @{
1489 */
1490 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1491 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1492 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1493 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1494 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1495 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1496 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1497 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1498 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1499 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1500 #define RTC ((RTC_TypeDef *) RTC_BASE)
1501 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1502 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1503 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1504 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1505 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1506 #define USART2 ((USART_TypeDef *) USART2_BASE)
1507 #define USART3 ((USART_TypeDef *) USART3_BASE)
1508 #define UART4 ((USART_TypeDef *) UART4_BASE)
1509 #define UART5 ((USART_TypeDef *) UART5_BASE)
1510 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1511 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1512 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1513 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1514 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1515 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1516 #define CEC ((CEC_TypeDef *) CEC_BASE)
1517 #define PWR ((PWR_TypeDef *) PWR_BASE)
1518 #define DAC ((DAC_TypeDef *) DAC_BASE)
1519 #define UART7 ((USART_TypeDef *) UART7_BASE)
1520 #define UART8 ((USART_TypeDef *) UART8_BASE)
1521 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1522 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1523 #define USART1 ((USART_TypeDef *) USART1_BASE)
1524 #define USART6 ((USART_TypeDef *) USART6_BASE)
1525 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1526 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1527 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1528 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1529 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1530 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1531 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1532 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1533 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1534 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1535 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1536 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1537 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1538 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1539 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1540 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1541 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1542 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1543 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1544 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1545 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1546 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1547 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1548 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1549 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1550 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1551 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1552 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1553 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1554 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1555 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1556 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1557 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1558 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1559 #define CRC ((CRC_TypeDef *) CRC_BASE)
1560 #define RCC ((RCC_TypeDef *) RCC_BASE)
1561 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1562 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1563 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1564 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1565 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1566 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1567 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1568 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1569 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1570 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1571 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1572 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1573 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1574 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1575 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1576 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1577 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1578 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1579 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1580 #define ETH ((ETH_TypeDef *) ETH_BASE)
1581 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1582 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1583 #define RNG ((RNG_TypeDef *) RNG_BASE)
1584 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1585 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1586 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1587 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1588 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1589 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1590 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1591 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1592 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1593 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
1594 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
1595 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1596 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1597 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1598 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1599 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1600 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1601 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1602 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1603 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1604 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1605 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1606 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1607 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
1608
1609 /**
1610 * @}
1611 */
1612
1613 /** @addtogroup Exported_constants
1614 * @{
1615 */
1616
1617 /** @addtogroup Peripheral_Registers_Bits_Definition
1618 * @{
1619 */
1620
1621 /******************************************************************************/
1622 /* Peripheral Registers_Bits_Definition */
1623 /******************************************************************************/
1624
1625 /******************************************************************************/
1626 /* */
1627 /* Analog to Digital Converter */
1628 /* */
1629 /******************************************************************************/
1630 /******************** Bit definition for ADC_SR register ********************/
1631 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
1632 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
1633 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
1634 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
1635 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
1636 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
1637
1638 /******************* Bit definition for ADC_CR1 register ********************/
1639 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1640 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
1641 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
1642 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
1643 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
1644 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
1645 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
1646 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
1647 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
1648 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
1649 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
1650 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
1651 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
1652 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
1653 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1654 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
1655 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
1656 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
1657 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
1658 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
1659 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
1660 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
1661 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
1662 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
1663
1664 /******************* Bit definition for ADC_CR2 register ********************/
1665 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
1666 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
1667 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
1668 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
1669 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
1670 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
1671 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1672 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
1673 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
1674 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
1675 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
1676 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1677 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
1678 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
1679 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
1680 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1681 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
1682 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
1683 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
1684 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
1685 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1686 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
1687 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
1688 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
1689
1690 /****************** Bit definition for ADC_SMPR1 register *******************/
1691 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1692 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
1693 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
1694 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
1695 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1696 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
1697 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
1698 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
1699 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1700 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
1701 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
1702 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
1703 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1704 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
1705 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
1706 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
1707 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1708 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
1709 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
1710 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
1711 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1712 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
1713 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
1714 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
1715 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1716 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
1717 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
1718 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
1719 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1720 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
1721 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
1722 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
1723 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1724 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
1725 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
1726 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
1727
1728 /****************** Bit definition for ADC_SMPR2 register *******************/
1729 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1730 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
1731 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
1732 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
1733 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1734 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
1735 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
1736 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
1737 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1738 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
1739 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
1740 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
1741 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1742 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
1743 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
1744 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
1745 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1746 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
1747 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
1748 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
1749 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1750 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
1751 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
1752 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
1753 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1754 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
1755 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
1756 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
1757 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1758 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
1759 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
1760 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
1761 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1762 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
1763 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
1764 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
1765 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1766 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
1767 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
1768 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
1769
1770 /****************** Bit definition for ADC_JOFR1 register *******************/
1771 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
1772
1773 /****************** Bit definition for ADC_JOFR2 register *******************/
1774 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
1775
1776 /****************** Bit definition for ADC_JOFR3 register *******************/
1777 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
1778
1779 /****************** Bit definition for ADC_JOFR4 register *******************/
1780 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
1781
1782 /******************* Bit definition for ADC_HTR register ********************/
1783 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
1784
1785 /******************* Bit definition for ADC_LTR register ********************/
1786 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
1787
1788 /******************* Bit definition for ADC_SQR1 register *******************/
1789 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1790 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
1791 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
1792 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
1793 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
1794 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
1795 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1796 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
1797 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
1798 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
1799 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
1800 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
1801 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1802 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
1803 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
1804 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
1805 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
1806 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
1807 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1808 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
1809 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
1810 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
1811 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
1812 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
1813 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
1814 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
1815 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
1816 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
1817 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
1818
1819 /******************* Bit definition for ADC_SQR2 register *******************/
1820 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1821 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
1822 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
1823 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
1824 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
1825 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
1826 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1827 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
1828 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
1829 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
1830 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
1831 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
1832 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1833 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
1834 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
1835 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
1836 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
1837 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
1838 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1839 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
1840 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
1841 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
1842 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
1843 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
1844 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1845 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
1846 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
1847 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
1848 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
1849 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
1850 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1851 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
1852 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
1853 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
1854 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
1855 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
1856
1857 /******************* Bit definition for ADC_SQR3 register *******************/
1858 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1859 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
1860 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
1861 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
1862 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
1863 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
1864 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1865 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
1866 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
1867 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
1868 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
1869 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
1870 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1871 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
1872 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
1873 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
1874 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
1875 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
1876 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1877 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
1878 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
1879 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
1880 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
1881 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
1882 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1883 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
1884 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
1885 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
1886 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
1887 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
1888 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1889 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
1890 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
1891 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
1892 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
1893 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
1894
1895 /******************* Bit definition for ADC_JSQR register *******************/
1896 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1897 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
1898 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
1899 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
1900 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
1901 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
1902 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1903 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
1904 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
1905 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
1906 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
1907 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
1908 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1909 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
1910 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
1911 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
1912 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
1913 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
1914 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1915 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
1916 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
1917 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
1918 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
1919 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
1920 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
1921 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
1922 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
1923
1924 /******************* Bit definition for ADC_JDR1 register *******************/
1925 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1926
1927 /******************* Bit definition for ADC_JDR2 register *******************/
1928 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1929
1930 /******************* Bit definition for ADC_JDR3 register *******************/
1931 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1932
1933 /******************* Bit definition for ADC_JDR4 register *******************/
1934 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1935
1936 /******************** Bit definition for ADC_DR register ********************/
1937 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
1938 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
1939
1940 /******************* Bit definition for ADC_CSR register ********************/
1941 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
1942 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
1943 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
1944 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
1945 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
1946 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 Overrun flag */
1947 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
1948 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
1949 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
1950 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
1951 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
1952 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 Overrun flag */
1953 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
1954 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
1955 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
1956 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
1957 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
1958 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 Overrun flag */
1959
1960 /* Legacy defines */
1961 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1962 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1963 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1964
1965
1966 /******************* Bit definition for ADC_CCR register ********************/
1967 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1968 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
1969 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
1970 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
1971 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
1972 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
1973 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1974 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
1975 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
1976 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
1977 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
1978 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
1979 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1980 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
1981 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
1982 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
1983 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
1984 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
1985 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
1986 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
1987
1988 /******************* Bit definition for ADC_CDR register ********************/
1989 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
1990 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
1991
1992 /******************************************************************************/
1993 /* */
1994 /* Controller Area Network */
1995 /* */
1996 /******************************************************************************/
1997 /*!<CAN control and status registers */
1998 /******************* Bit definition for CAN_MCR register ********************/
1999 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
2000 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
2001 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
2002 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
2003 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
2004 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
2005 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
2006 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
2007 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
2008
2009 /******************* Bit definition for CAN_MSR register ********************/
2010 #define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */
2011 #define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */
2012 #define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */
2013 #define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */
2014 #define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */
2015 #define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */
2016 #define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */
2017 #define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */
2018 #define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */
2019
2020 /******************* Bit definition for CAN_TSR register ********************/
2021 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
2022 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
2023 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
2024 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
2025 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
2026 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
2027 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
2028 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
2029 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
2030 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
2031 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
2032 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
2033 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
2034 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
2035 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
2036 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
2037
2038 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
2039 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
2040 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
2041 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
2042
2043 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
2044 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
2045 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
2046 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
2047
2048 /******************* Bit definition for CAN_RF0R register *******************/
2049 #define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */
2050 #define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */
2051 #define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */
2052 #define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */
2053
2054 /******************* Bit definition for CAN_RF1R register *******************/
2055 #define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */
2056 #define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */
2057 #define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */
2058 #define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */
2059
2060 /******************** Bit definition for CAN_IER register *******************/
2061 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
2062 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
2063 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
2064 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
2065 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
2066 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
2067 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
2068 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
2069 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
2070 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
2071 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
2072 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
2073 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
2074 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
2075
2076 /******************** Bit definition for CAN_ESR register *******************/
2077 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
2078 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
2079 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
2080
2081 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
2082 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
2083 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
2084 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
2085
2086 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
2087 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
2088
2089 /******************* Bit definition for CAN_BTR register ********************/
2090 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
2091 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
2092 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
2093 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
2094 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
2095 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
2096 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
2097 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
2098 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
2099 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
2100 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
2101 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
2102 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
2103 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
2104 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
2105
2106 /*!<Mailbox registers */
2107 /****************** Bit definition for CAN_TI0R register ********************/
2108 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
2109 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
2110 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
2111 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
2112 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
2113
2114 /****************** Bit definition for CAN_TDT0R register *******************/
2115 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
2116 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
2117 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
2118
2119 /****************** Bit definition for CAN_TDL0R register *******************/
2120 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
2121 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
2122 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
2123 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
2124
2125 /****************** Bit definition for CAN_TDH0R register *******************/
2126 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
2127 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
2128 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
2129 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
2130
2131 /******************* Bit definition for CAN_TI1R register *******************/
2132 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
2133 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
2134 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
2135 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
2136 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
2137
2138 /******************* Bit definition for CAN_TDT1R register ******************/
2139 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
2140 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
2141 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
2142
2143 /******************* Bit definition for CAN_TDL1R register ******************/
2144 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
2145 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
2146 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
2147 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
2148
2149 /******************* Bit definition for CAN_TDH1R register ******************/
2150 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
2151 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
2152 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
2153 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
2154
2155 /******************* Bit definition for CAN_TI2R register *******************/
2156 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
2157 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
2158 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
2159 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
2160 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
2161
2162 /******************* Bit definition for CAN_TDT2R register ******************/
2163 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
2164 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
2165 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
2166
2167 /******************* Bit definition for CAN_TDL2R register ******************/
2168 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
2169 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
2170 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
2171 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
2172
2173 /******************* Bit definition for CAN_TDH2R register ******************/
2174 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
2175 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
2176 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
2177 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
2178
2179 /******************* Bit definition for CAN_RI0R register *******************/
2180 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
2181 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
2182 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
2183 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
2184
2185 /******************* Bit definition for CAN_RDT0R register ******************/
2186 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
2187 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
2188 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
2189
2190 /******************* Bit definition for CAN_RDL0R register ******************/
2191 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
2192 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
2193 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
2194 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
2195
2196 /******************* Bit definition for CAN_RDH0R register ******************/
2197 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
2198 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
2199 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
2200 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
2201
2202 /******************* Bit definition for CAN_RI1R register *******************/
2203 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
2204 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
2205 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
2206 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
2207
2208 /******************* Bit definition for CAN_RDT1R register ******************/
2209 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
2210 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
2211 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
2212
2213 /******************* Bit definition for CAN_RDL1R register ******************/
2214 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
2215 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
2216 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
2217 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
2218
2219 /******************* Bit definition for CAN_RDH1R register ******************/
2220 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
2221 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
2222 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
2223 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
2224
2225 /*!<CAN filter registers */
2226 /******************* Bit definition for CAN_FMR register ********************/
2227 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
2228 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
2229
2230 /******************* Bit definition for CAN_FM1R register *******************/
2231 #define CAN_FM1R_FBM 0x3FFFU /*!<Filter Mode */
2232 #define CAN_FM1R_FBM0 0x0001U /*!<Filter Init Mode bit 0 */
2233 #define CAN_FM1R_FBM1 0x0002U /*!<Filter Init Mode bit 1 */
2234 #define CAN_FM1R_FBM2 0x0004U /*!<Filter Init Mode bit 2 */
2235 #define CAN_FM1R_FBM3 0x0008U /*!<Filter Init Mode bit 3 */
2236 #define CAN_FM1R_FBM4 0x0010U /*!<Filter Init Mode bit 4 */
2237 #define CAN_FM1R_FBM5 0x0020U /*!<Filter Init Mode bit 5 */
2238 #define CAN_FM1R_FBM6 0x0040U /*!<Filter Init Mode bit 6 */
2239 #define CAN_FM1R_FBM7 0x0080U /*!<Filter Init Mode bit 7 */
2240 #define CAN_FM1R_FBM8 0x0100U /*!<Filter Init Mode bit 8 */
2241 #define CAN_FM1R_FBM9 0x0200U /*!<Filter Init Mode bit 9 */
2242 #define CAN_FM1R_FBM10 0x0400U /*!<Filter Init Mode bit 10 */
2243 #define CAN_FM1R_FBM11 0x0800U /*!<Filter Init Mode bit 11 */
2244 #define CAN_FM1R_FBM12 0x1000U /*!<Filter Init Mode bit 12 */
2245 #define CAN_FM1R_FBM13 0x2000U /*!<Filter Init Mode bit 13 */
2246
2247 /******************* Bit definition for CAN_FS1R register *******************/
2248 #define CAN_FS1R_FSC 0x00003FFFU /*!<Filter Scale Configuration */
2249 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
2250 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
2251 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
2252 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
2253 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
2254 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
2255 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
2256 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
2257 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
2258 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
2259 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
2260 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
2261 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
2262 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
2263
2264 /****************** Bit definition for CAN_FFA1R register *******************/
2265 #define CAN_FFA1R_FFA 0x00003FFFU /*!<Filter FIFO Assignment */
2266 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment for Filter 0 */
2267 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment for Filter 1 */
2268 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment for Filter 2 */
2269 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment for Filter 3 */
2270 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment for Filter 4 */
2271 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment for Filter 5 */
2272 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment for Filter 6 */
2273 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment for Filter 7 */
2274 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment for Filter 8 */
2275 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment for Filter 9 */
2276 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment for Filter 10 */
2277 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment for Filter 11 */
2278 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment for Filter 12 */
2279 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment for Filter 13 */
2280
2281 /******************* Bit definition for CAN_FA1R register *******************/
2282 #define CAN_FA1R_FACT 0x00003FFFU /*!<Filter Active */
2283 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter 0 Active */
2284 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter 1 Active */
2285 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter 2 Active */
2286 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter 3 Active */
2287 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter 4 Active */
2288 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter 5 Active */
2289 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter 6 Active */
2290 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter 7 Active */
2291 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter 8 Active */
2292 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter 9 Active */
2293 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter 10 Active */
2294 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter 11 Active */
2295 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter 12 Active */
2296 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter 13 Active */
2297
2298 /******************* Bit definition for CAN_F0R1 register *******************/
2299 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
2300 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
2301 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
2302 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
2303 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
2304 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
2305 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
2306 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
2307 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
2308 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
2309 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
2310 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
2311 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
2312 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
2313 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
2314 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
2315 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
2316 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
2317 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
2318 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
2319 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
2320 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
2321 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
2322 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
2323 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
2324 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
2325 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
2326 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
2327 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
2328 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
2329 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
2330 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
2331
2332 /******************* Bit definition for CAN_F1R1 register *******************/
2333 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
2334 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
2335 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
2336 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
2337 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
2338 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
2339 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
2340 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
2341 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
2342 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
2343 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
2344 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
2345 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
2346 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
2347 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
2348 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
2349 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
2350 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
2351 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
2352 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
2353 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
2354 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
2355 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
2356 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
2357 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
2358 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
2359 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
2360 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
2361 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
2362 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
2363 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
2364 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
2365
2366 /******************* Bit definition for CAN_F2R1 register *******************/
2367 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
2368 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
2369 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
2370 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
2371 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
2372 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
2373 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
2374 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
2375 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
2376 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
2377 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
2378 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
2379 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
2380 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
2381 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
2382 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
2383 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
2384 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
2385 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
2386 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
2387 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
2388 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
2389 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
2390 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
2391 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
2392 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
2393 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
2394 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
2395 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
2396 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
2397 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
2398 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
2399
2400 /******************* Bit definition for CAN_F3R1 register *******************/
2401 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
2402 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
2403 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
2404 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
2405 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
2406 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
2407 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
2408 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
2409 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
2410 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
2411 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
2412 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
2413 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
2414 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
2415 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
2416 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
2417 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
2418 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
2419 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
2420 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
2421 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
2422 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
2423 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
2424 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
2425 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
2426 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
2427 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
2428 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
2429 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
2430 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
2431 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
2432 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
2433
2434 /******************* Bit definition for CAN_F4R1 register *******************/
2435 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
2436 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
2437 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
2438 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
2439 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
2440 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
2441 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
2442 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
2443 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
2444 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
2445 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
2446 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
2447 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
2448 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
2449 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
2450 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
2451 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
2452 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
2453 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
2454 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
2455 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
2456 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
2457 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
2458 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
2459 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
2460 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
2461 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
2462 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
2463 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
2464 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
2465 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
2466 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
2467
2468 /******************* Bit definition for CAN_F5R1 register *******************/
2469 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
2470 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
2471 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
2472 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
2473 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
2474 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
2475 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
2476 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
2477 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
2478 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
2479 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
2480 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
2481 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
2482 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
2483 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
2484 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
2485 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
2486 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
2487 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
2488 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
2489 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
2490 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
2491 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
2492 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
2493 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
2494 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
2495 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
2496 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
2497 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
2498 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
2499 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
2500 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
2501
2502 /******************* Bit definition for CAN_F6R1 register *******************/
2503 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
2504 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
2505 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
2506 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
2507 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
2508 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
2509 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
2510 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
2511 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
2512 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
2513 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
2514 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
2515 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
2516 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
2517 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
2518 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
2519 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
2520 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
2521 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
2522 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
2523 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
2524 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
2525 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
2526 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
2527 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
2528 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
2529 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
2530 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
2531 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
2532 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
2533 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
2534 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
2535
2536 /******************* Bit definition for CAN_F7R1 register *******************/
2537 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
2538 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
2539 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
2540 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
2541 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
2542 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
2543 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
2544 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
2545 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
2546 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
2547 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
2548 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
2549 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
2550 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
2551 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
2552 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
2553 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
2554 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
2555 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
2556 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
2557 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
2558 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
2559 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
2560 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
2561 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
2562 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
2563 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
2564 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
2565 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
2566 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
2567 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
2568 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
2569
2570 /******************* Bit definition for CAN_F8R1 register *******************/
2571 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
2572 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
2573 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
2574 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
2575 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
2576 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
2577 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
2578 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
2579 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
2580 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
2581 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
2582 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
2583 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
2584 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
2585 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
2586 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
2587 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
2588 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
2589 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
2590 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
2591 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
2592 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
2593 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
2594 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
2595 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
2596 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
2597 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
2598 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
2599 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
2600 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
2601 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
2602 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
2603
2604 /******************* Bit definition for CAN_F9R1 register *******************/
2605 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
2606 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
2607 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
2608 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
2609 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
2610 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
2611 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
2612 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
2613 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
2614 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
2615 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
2616 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
2617 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
2618 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
2619 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
2620 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
2621 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
2622 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
2623 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
2624 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
2625 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
2626 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
2627 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
2628 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
2629 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
2630 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
2631 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
2632 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
2633 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
2634 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
2635 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
2636 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
2637
2638 /******************* Bit definition for CAN_F10R1 register ******************/
2639 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
2640 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
2641 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
2642 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
2643 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
2644 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
2645 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
2646 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
2647 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
2648 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
2649 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
2650 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
2651 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
2652 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
2653 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
2654 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
2655 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
2656 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
2657 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
2658 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
2659 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
2660 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
2661 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
2662 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
2663 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
2664 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
2665 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
2666 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
2667 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
2668 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
2669 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
2670 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
2671
2672 /******************* Bit definition for CAN_F11R1 register ******************/
2673 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
2674 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
2675 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
2676 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
2677 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
2678 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
2679 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
2680 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
2681 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
2682 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
2683 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
2684 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
2685 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
2686 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
2687 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
2688 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
2689 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
2690 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
2691 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
2692 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
2693 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
2694 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
2695 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
2696 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
2697 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
2698 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
2699 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
2700 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
2701 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
2702 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
2703 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
2704 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
2705
2706 /******************* Bit definition for CAN_F12R1 register ******************/
2707 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
2708 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
2709 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
2710 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
2711 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
2712 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
2713 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
2714 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
2715 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
2716 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
2717 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
2718 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
2719 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
2720 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
2721 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
2722 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
2723 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
2724 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
2725 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
2726 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
2727 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
2728 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
2729 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
2730 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
2731 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
2732 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
2733 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
2734 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
2735 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
2736 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
2737 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
2738 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
2739
2740 /******************* Bit definition for CAN_F13R1 register ******************/
2741 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
2742 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
2743 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
2744 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
2745 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
2746 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
2747 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
2748 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
2749 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
2750 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
2751 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
2752 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
2753 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
2754 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
2755 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
2756 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
2757 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
2758 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
2759 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
2760 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
2761 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
2762 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
2763 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
2764 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
2765 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
2766 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
2767 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
2768 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
2769 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
2770 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
2771 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
2772 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
2773
2774 /******************* Bit definition for CAN_F0R2 register *******************/
2775 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
2776 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
2777 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
2778 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
2779 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
2780 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
2781 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
2782 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
2783 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
2784 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
2785 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
2786 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
2787 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
2788 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
2789 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
2790 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
2791 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
2792 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
2793 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
2794 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
2795 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
2796 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
2797 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
2798 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
2799 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
2800 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
2801 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
2802 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
2803 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
2804 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
2805 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
2806 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
2807
2808 /******************* Bit definition for CAN_F1R2 register *******************/
2809 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
2810 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
2811 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
2812 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
2813 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
2814 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
2815 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
2816 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
2817 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
2818 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
2819 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
2820 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
2821 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
2822 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
2823 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
2824 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
2825 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
2826 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
2827 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
2828 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
2829 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
2830 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
2831 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
2832 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
2833 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
2834 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
2835 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
2836 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
2837 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
2838 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
2839 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
2840 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
2841
2842 /******************* Bit definition for CAN_F2R2 register *******************/
2843 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
2844 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
2845 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
2846 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
2847 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
2848 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
2849 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
2850 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
2851 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
2852 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
2853 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
2854 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
2855 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
2856 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
2857 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
2858 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
2859 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
2860 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
2861 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
2862 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
2863 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
2864 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
2865 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
2866 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
2867 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
2868 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
2869 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
2870 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
2871 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
2872 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
2873 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
2874 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
2875
2876 /******************* Bit definition for CAN_F3R2 register *******************/
2877 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
2878 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
2879 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
2880 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
2881 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
2882 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
2883 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
2884 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
2885 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
2886 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
2887 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
2888 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
2889 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
2890 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
2891 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
2892 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
2893 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
2894 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
2895 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
2896 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
2897 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
2898 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
2899 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
2900 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
2901 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
2902 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
2903 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
2904 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
2905 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
2906 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
2907 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
2908 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
2909
2910 /******************* Bit definition for CAN_F4R2 register *******************/
2911 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
2912 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
2913 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
2914 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
2915 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
2916 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
2917 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
2918 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
2919 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
2920 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
2921 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
2922 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
2923 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
2924 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
2925 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
2926 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
2927 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
2928 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
2929 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
2930 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
2931 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
2932 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
2933 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
2934 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
2935 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
2936 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
2937 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
2938 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
2939 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
2940 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
2941 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
2942 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
2943
2944 /******************* Bit definition for CAN_F5R2 register *******************/
2945 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
2946 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
2947 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
2948 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
2949 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
2950 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
2951 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
2952 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
2953 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
2954 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
2955 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
2956 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
2957 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
2958 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
2959 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
2960 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
2961 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
2962 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
2963 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
2964 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
2965 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
2966 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
2967 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
2968 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
2969 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
2970 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
2971 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
2972 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
2973 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
2974 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
2975 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
2976 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
2977
2978 /******************* Bit definition for CAN_F6R2 register *******************/
2979 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
2980 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
2981 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
2982 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
2983 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
2984 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
2985 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
2986 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
2987 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
2988 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
2989 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
2990 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
2991 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
2992 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
2993 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
2994 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
2995 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
2996 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
2997 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
2998 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
2999 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
3000 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
3001 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
3002 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
3003 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
3004 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
3005 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
3006 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
3007 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
3008 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
3009 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
3010 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
3011
3012 /******************* Bit definition for CAN_F7R2 register *******************/
3013 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
3014 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
3015 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
3016 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
3017 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
3018 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
3019 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
3020 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
3021 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
3022 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
3023 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
3024 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
3025 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
3026 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
3027 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
3028 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
3029 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
3030 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
3031 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
3032 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
3033 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
3034 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
3035 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
3036 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
3037 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
3038 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
3039 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
3040 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
3041 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
3042 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
3043 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
3044 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
3045
3046 /******************* Bit definition for CAN_F8R2 register *******************/
3047 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
3048 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
3049 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
3050 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
3051 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
3052 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
3053 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
3054 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
3055 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
3056 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
3057 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
3058 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
3059 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
3060 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
3061 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
3062 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
3063 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
3064 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
3065 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
3066 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
3067 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
3068 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
3069 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
3070 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
3071 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
3072 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
3073 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
3074 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
3075 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
3076 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
3077 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
3078 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
3079
3080 /******************* Bit definition for CAN_F9R2 register *******************/
3081 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
3082 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
3083 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
3084 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
3085 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
3086 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
3087 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
3088 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
3089 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
3090 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
3091 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
3092 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
3093 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
3094 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
3095 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
3096 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
3097 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
3098 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
3099 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
3100 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
3101 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
3102 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
3103 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
3104 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
3105 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
3106 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
3107 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
3108 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
3109 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
3110 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
3111 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
3112 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
3113
3114 /******************* Bit definition for CAN_F10R2 register ******************/
3115 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
3116 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
3117 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
3118 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
3119 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
3120 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
3121 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
3122 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
3123 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
3124 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
3125 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
3126 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
3127 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
3128 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
3129 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
3130 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
3131 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
3132 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
3133 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
3134 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
3135 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
3136 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
3137 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
3138 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
3139 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
3140 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
3141 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
3142 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
3143 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
3144 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
3145 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
3146 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
3147
3148 /******************* Bit definition for CAN_F11R2 register ******************/
3149 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
3150 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
3151 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
3152 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
3153 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
3154 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
3155 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
3156 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
3157 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
3158 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
3159 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
3160 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
3161 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
3162 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
3163 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
3164 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
3165 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
3166 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
3167 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
3168 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
3169 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
3170 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
3171 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
3172 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
3173 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
3174 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
3175 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
3176 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
3177 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
3178 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
3179 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
3180 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
3181
3182 /******************* Bit definition for CAN_F12R2 register ******************/
3183 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
3184 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
3185 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
3186 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
3187 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
3188 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
3189 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
3190 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
3191 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
3192 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
3193 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
3194 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
3195 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
3196 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
3197 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
3198 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
3199 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
3200 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
3201 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
3202 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
3203 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
3204 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
3205 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
3206 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
3207 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
3208 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
3209 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
3210 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
3211 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
3212 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
3213 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
3214 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
3215
3216 /******************* Bit definition for CAN_F13R2 register ******************/
3217 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
3218 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
3219 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
3220 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
3221 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
3222 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
3223 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
3224 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
3225 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
3226 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
3227 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
3228 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
3229 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
3230 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
3231 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
3232 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
3233 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
3234 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
3235 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
3236 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
3237 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
3238 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
3239 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
3240 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
3241 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
3242 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
3243 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
3244 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
3245 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
3246 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
3247 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
3248 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
3249
3250 /******************************************************************************/
3251 /* */
3252 /* HDMI-CEC (CEC) */
3253 /* */
3254 /******************************************************************************/
3255
3256 /******************* Bit definition for CEC_CR register *********************/
3257 #define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
3258 #define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
3259 #define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
3260
3261 /******************* Bit definition for CEC_CFGR register *******************/
3262 #define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
3263 #define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
3264 #define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
3265 #define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
3266 #define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Period Error generation */
3267 #define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast no Error generation */
3268 #define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
3269 #define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
3270 #define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
3271
3272 /******************* Bit definition for CEC_TXDR register *******************/
3273 #define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
3274
3275 /******************* Bit definition for CEC_RXDR register *******************/
3276 #define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
3277
3278 /******************* Bit definition for CEC_ISR register ********************/
3279 #define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
3280 #define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
3281 #define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
3282 #define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
3283 #define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
3284 #define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
3285 #define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
3286 #define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
3287 #define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
3288 #define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
3289 #define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
3290 #define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
3291 #define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
3292
3293 /******************* Bit definition for CEC_IER register ********************/
3294 #define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
3295 #define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
3296 #define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
3297 #define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
3298 #define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable*/
3299 #define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
3300 #define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
3301 #define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
3302 #define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
3303 #define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
3304 #define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
3305 #define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
3306 #define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
3307
3308 /******************************************************************************/
3309 /* */
3310 /* CRC calculation unit */
3311 /* */
3312 /******************************************************************************/
3313 /******************* Bit definition for CRC_DR register *********************/
3314 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
3315
3316 /******************* Bit definition for CRC_IDR register ********************/
3317 #define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */
3318
3319 /******************** Bit definition for CRC_CR register ********************/
3320 #define CRC_CR_RESET 0x00000001U /*!< RESET the CRC computation unit bit */
3321 #define CRC_CR_POLYSIZE 0x00000018U /*!< Polynomial size bits */
3322 #define CRC_CR_POLYSIZE_0 0x00000008U /*!< Polynomial size bit 0 */
3323 #define CRC_CR_POLYSIZE_1 0x00000010U /*!< Polynomial size bit 1 */
3324 #define CRC_CR_REV_IN 0x00000060U /*!< REV_IN Reverse Input Data bits */
3325 #define CRC_CR_REV_IN_0 0x00000020U /*!< Bit 0 */
3326 #define CRC_CR_REV_IN_1 0x00000040U /*!< Bit 1 */
3327 #define CRC_CR_REV_OUT 0x00000080U /*!< REV_OUT Reverse Output Data bits */
3328
3329 /******************* Bit definition for CRC_INIT register *******************/
3330 #define CRC_INIT_INIT 0xFFFFFFFFU /*!< Initial CRC value bits */
3331
3332 /******************* Bit definition for CRC_POL register ********************/
3333 #define CRC_POL_POL 0xFFFFFFFFU /*!< Coefficients of the polynomial */
3334
3335
3336 /******************************************************************************/
3337 /* */
3338 /* Digital to Analog Converter */
3339 /* */
3340 /******************************************************************************/
3341 /******************** Bit definition for DAC_CR register ********************/
3342 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
3343 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
3344 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
3345 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3346 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
3347 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
3348 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
3349 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
3350 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
3351 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
3352 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3353 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
3354 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
3355 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
3356 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
3357 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
3358 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable */
3359 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
3360 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
3361 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
3362 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3363 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
3364 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
3365 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
3366 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3367 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
3368 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
3369 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3370 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
3371 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
3372 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
3373 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
3374 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enable */
3375 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable */
3376
3377 /***************** Bit definition for DAC_SWTRIGR register ******************/
3378 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
3379 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
3380
3381 /***************** Bit definition for DAC_DHR12R1 register ******************/
3382 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
3383
3384 /***************** Bit definition for DAC_DHR12L1 register ******************/
3385 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
3386
3387 /****************** Bit definition for DAC_DHR8R1 register ******************/
3388 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
3389
3390 /***************** Bit definition for DAC_DHR12R2 register ******************/
3391 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
3392
3393 /***************** Bit definition for DAC_DHR12L2 register ******************/
3394 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
3395
3396 /****************** Bit definition for DAC_DHR8R2 register ******************/
3397 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
3398
3399 /***************** Bit definition for DAC_DHR12RD register ******************/
3400 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
3401 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
3402
3403 /***************** Bit definition for DAC_DHR12LD register ******************/
3404 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
3405 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
3406
3407 /****************** Bit definition for DAC_DHR8RD register ******************/
3408 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
3409 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
3410
3411 /******************* Bit definition for DAC_DOR1 register *******************/
3412 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
3413
3414 /******************* Bit definition for DAC_DOR2 register *******************/
3415 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
3416
3417 /******************** Bit definition for DAC_SR register ********************/
3418 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
3419 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
3420
3421 /******************************************************************************/
3422 /* */
3423 /* Digital Filter for Sigma Delta Modulators */
3424 /* */
3425 /******************************************************************************/
3426
3427 /**************** DFSDM channel configuration registers ********************/
3428
3429 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
3430 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
3431 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
3432 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
3433 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
3434 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
3435 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
3436 #define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
3437 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
3438 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
3439 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
3440 #define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
3441 #define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
3442 #define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
3443 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
3444 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
3445 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
3446 #define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
3447 #define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
3448 #define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
3449
3450 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
3451 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
3452 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
3453
3454 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
3455 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
3456 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
3457 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
3458 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
3459 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
3460 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
3461
3462 /**************** Bit definition for DFSDM_CHWDATR register *******************/
3463 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
3464
3465 /**************** Bit definition for DFSDM_CHDATINR register *****************/
3466 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
3467 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
3468
3469 /************************ DFSDM module registers ****************************/
3470
3471 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
3472 #define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
3473 #define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
3474 #define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
3475 #define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
3476 #define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
3477 #define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
3478 #define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
3479 #define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
3480 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
3481 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
3482 #define DFSDM_FLTCR1_JEXTSEL 0x00001F00U /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
3483 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
3484 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
3485 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
3486 #define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U /*!< Trigger signal selection for launching injected conversions, Bit 3 */
3487 #define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U /*!< Trigger signal selection for launching injected conversions, Bit 4 */
3488 #define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
3489 #define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
3490 #define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
3491 #define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
3492 #define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
3493
3494 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
3495 #define DFSDM_FLTCR2_AWDCH 0x00FF0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
3496 #define DFSDM_FLTCR2_EXCH 0x0000FF00U /*!< EXCH[7:0] Extreme detector channel selection */
3497 #define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
3498 #define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
3499 #define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
3500 #define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
3501 #define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
3502 #define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
3503 #define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
3504
3505 /******************** Bit definition for DFSDM_FLTISR register *******************/
3506 #define DFSDM_FLTISR_SCDF 0xFF000000U /*!< SCDF[7:0] Short circuit detector flag */
3507 #define DFSDM_FLTISR_CKABF 0x00FF0000U /*!< CKABF[7:0] Clock absence flag */
3508 #define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
3509 #define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
3510 #define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
3511 #define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
3512 #define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
3513 #define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
3514 #define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
3515
3516 /******************** Bit definition for DFSDM_FLTICR register *******************/
3517 #define DFSDM_FLTICR_CLRSCSDF 0xFF000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
3518 #define DFSDM_FLTICR_CLRCKABF 0x00FF0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
3519 #define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
3520 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
3521
3522 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
3523 #define DFSDM_FLTJCHGR_JCHG 0x000000FFU /*!< JCHG[7:0] Injected channel group selection */
3524
3525 /******************** Bit definition for DFSDM_FLTFCR register *******************/
3526 #define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
3527 #define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
3528 #define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
3529 #define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
3530 #define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
3531 #define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
3532
3533 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
3534 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
3535 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
3536
3537 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
3538 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
3539 #define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
3540 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
3541
3542 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
3543 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
3544 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
3545
3546 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
3547 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
3548 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
3549
3550 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
3551 #define DFSDM_FLTAWSR_AWHTF 0x0000FF00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
3552 #define DFSDM_FLTAWSR_AWLTF 0x000000FFU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
3553
3554 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
3555 #define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
3556 #define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
3557
3558 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
3559 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
3560 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
3561
3562 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
3563 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
3564 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
3565
3566 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
3567 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
3568
3569 /******************************************************************************/
3570 /* */
3571 /* Debug MCU */
3572 /* */
3573 /******************************************************************************/
3574
3575 /******************************************************************************/
3576 /* */
3577 /* DCMI */
3578 /* */
3579 /******************************************************************************/
3580 /******************** Bits definition for DCMI_CR register ******************/
3581 #define DCMI_CR_CAPTURE 0x00000001U
3582 #define DCMI_CR_CM 0x00000002U
3583 #define DCMI_CR_CROP 0x00000004U
3584 #define DCMI_CR_JPEG 0x00000008U
3585 #define DCMI_CR_ESS 0x00000010U
3586 #define DCMI_CR_PCKPOL 0x00000020U
3587 #define DCMI_CR_HSPOL 0x00000040U
3588 #define DCMI_CR_VSPOL 0x00000080U
3589 #define DCMI_CR_FCRC_0 0x00000100U
3590 #define DCMI_CR_FCRC_1 0x00000200U
3591 #define DCMI_CR_EDM_0 0x00000400U
3592 #define DCMI_CR_EDM_1 0x00000800U
3593 #define DCMI_CR_CRE 0x00001000U
3594 #define DCMI_CR_ENABLE 0x00004000U
3595 #define DCMI_CR_BSM 0x00030000U
3596 #define DCMI_CR_BSM_0 0x00010000U
3597 #define DCMI_CR_BSM_1 0x00020000U
3598 #define DCMI_CR_OEBS 0x00040000U
3599 #define DCMI_CR_LSM 0x00080000U
3600 #define DCMI_CR_OELS 0x00100000U
3601
3602 /******************** Bits definition for DCMI_SR register ******************/
3603 #define DCMI_SR_HSYNC 0x00000001U
3604 #define DCMI_SR_VSYNC 0x00000002U
3605 #define DCMI_SR_FNE 0x00000004U
3606
3607 /******************** Bits definition for DCMI_RIS register ****************/
3608 #define DCMI_RIS_FRAME_RIS 0x00000001U
3609 #define DCMI_RIS_OVR_RIS 0x00000002U
3610 #define DCMI_RIS_ERR_RIS 0x00000004U
3611 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3612 #define DCMI_RIS_LINE_RIS 0x00000010U
3613
3614 /* Legacy defines */
3615 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3616 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3617 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3618 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3619 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3620
3621 /******************** Bits definition for DCMI_IER register *****************/
3622 #define DCMI_IER_FRAME_IE 0x00000001U
3623 #define DCMI_IER_OVR_IE 0x00000002U
3624 #define DCMI_IER_ERR_IE 0x00000004U
3625 #define DCMI_IER_VSYNC_IE 0x00000008U
3626 #define DCMI_IER_LINE_IE 0x00000010U
3627
3628
3629 /******************** Bits definition for DCMI_MIS register *****************/
3630 #define DCMI_MIS_FRAME_MIS 0x00000001U
3631 #define DCMI_MIS_OVR_MIS 0x00000002U
3632 #define DCMI_MIS_ERR_MIS 0x00000004U
3633 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3634 #define DCMI_MIS_LINE_MIS 0x00000010U
3635
3636
3637 /******************** Bits definition for DCMI_ICR register *****************/
3638 #define DCMI_ICR_FRAME_ISC 0x00000001U
3639 #define DCMI_ICR_OVR_ISC 0x00000002U
3640 #define DCMI_ICR_ERR_ISC 0x00000004U
3641 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3642 #define DCMI_ICR_LINE_ISC 0x00000010U
3643
3644
3645 /******************** Bits definition for DCMI_ESCR register ******************/
3646 #define DCMI_ESCR_FSC 0x000000FFU
3647 #define DCMI_ESCR_LSC 0x0000FF00U
3648 #define DCMI_ESCR_LEC 0x00FF0000U
3649 #define DCMI_ESCR_FEC 0xFF000000U
3650
3651 /******************** Bits definition for DCMI_ESUR register ******************/
3652 #define DCMI_ESUR_FSU 0x000000FFU
3653 #define DCMI_ESUR_LSU 0x0000FF00U
3654 #define DCMI_ESUR_LEU 0x00FF0000U
3655 #define DCMI_ESUR_FEU 0xFF000000U
3656
3657 /******************** Bits definition for DCMI_CWSTRT register ******************/
3658 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3659 #define DCMI_CWSTRT_VST 0x1FFF0000U
3660
3661 /******************** Bits definition for DCMI_CWSIZE register ******************/
3662 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3663 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3664
3665 /******************** Bits definition for DCMI_DR register ******************/
3666 #define DCMI_DR_BYTE0 0x000000FFU
3667 #define DCMI_DR_BYTE1 0x0000FF00U
3668 #define DCMI_DR_BYTE2 0x00FF0000U
3669 #define DCMI_DR_BYTE3 0xFF000000U
3670
3671 /******************************************************************************/
3672 /* */
3673 /* DMA Controller */
3674 /* */
3675 /******************************************************************************/
3676 /******************** Bits definition for DMA_SxCR register *****************/
3677 #define DMA_SxCR_CHSEL 0x1E000000U
3678 #define DMA_SxCR_CHSEL_0 0x02000000U
3679 #define DMA_SxCR_CHSEL_1 0x04000000U
3680 #define DMA_SxCR_CHSEL_2 0x08000000U
3681 #define DMA_SxCR_CHSEL_3 0x10000000U
3682 #define DMA_SxCR_MBURST 0x01800000U
3683 #define DMA_SxCR_MBURST_0 0x00800000U
3684 #define DMA_SxCR_MBURST_1 0x01000000U
3685 #define DMA_SxCR_PBURST 0x00600000U
3686 #define DMA_SxCR_PBURST_0 0x00200000U
3687 #define DMA_SxCR_PBURST_1 0x00400000U
3688 #define DMA_SxCR_CT 0x00080000U
3689 #define DMA_SxCR_DBM 0x00040000U
3690 #define DMA_SxCR_PL 0x00030000U
3691 #define DMA_SxCR_PL_0 0x00010000U
3692 #define DMA_SxCR_PL_1 0x00020000U
3693 #define DMA_SxCR_PINCOS 0x00008000U
3694 #define DMA_SxCR_MSIZE 0x00006000U
3695 #define DMA_SxCR_MSIZE_0 0x00002000U
3696 #define DMA_SxCR_MSIZE_1 0x00004000U
3697 #define DMA_SxCR_PSIZE 0x00001800U
3698 #define DMA_SxCR_PSIZE_0 0x00000800U
3699 #define DMA_SxCR_PSIZE_1 0x00001000U
3700 #define DMA_SxCR_MINC 0x00000400U
3701 #define DMA_SxCR_PINC 0x00000200U
3702 #define DMA_SxCR_CIRC 0x00000100U
3703 #define DMA_SxCR_DIR 0x000000C0U
3704 #define DMA_SxCR_DIR_0 0x00000040U
3705 #define DMA_SxCR_DIR_1 0x00000080U
3706 #define DMA_SxCR_PFCTRL 0x00000020U
3707 #define DMA_SxCR_TCIE 0x00000010U
3708 #define DMA_SxCR_HTIE 0x00000008U
3709 #define DMA_SxCR_TEIE 0x00000004U
3710 #define DMA_SxCR_DMEIE 0x00000002U
3711 #define DMA_SxCR_EN 0x00000001U
3712
3713 /******************** Bits definition for DMA_SxCNDTR register **************/
3714 #define DMA_SxNDT 0x0000FFFFU
3715 #define DMA_SxNDT_0 0x00000001U
3716 #define DMA_SxNDT_1 0x00000002U
3717 #define DMA_SxNDT_2 0x00000004U
3718 #define DMA_SxNDT_3 0x00000008U
3719 #define DMA_SxNDT_4 0x00000010U
3720 #define DMA_SxNDT_5 0x00000020U
3721 #define DMA_SxNDT_6 0x00000040U
3722 #define DMA_SxNDT_7 0x00000080U
3723 #define DMA_SxNDT_8 0x00000100U
3724 #define DMA_SxNDT_9 0x00000200U
3725 #define DMA_SxNDT_10 0x00000400U
3726 #define DMA_SxNDT_11 0x00000800U
3727 #define DMA_SxNDT_12 0x00001000U
3728 #define DMA_SxNDT_13 0x00002000U
3729 #define DMA_SxNDT_14 0x00004000U
3730 #define DMA_SxNDT_15 0x00008000U
3731
3732 /******************** Bits definition for DMA_SxFCR register ****************/
3733 #define DMA_SxFCR_FEIE 0x00000080U
3734 #define DMA_SxFCR_FS 0x00000038U
3735 #define DMA_SxFCR_FS_0 0x00000008U
3736 #define DMA_SxFCR_FS_1 0x00000010U
3737 #define DMA_SxFCR_FS_2 0x00000020U
3738 #define DMA_SxFCR_DMDIS 0x00000004U
3739 #define DMA_SxFCR_FTH 0x00000003U
3740 #define DMA_SxFCR_FTH_0 0x00000001U
3741 #define DMA_SxFCR_FTH_1 0x00000002U
3742
3743 /******************** Bits definition for DMA_LISR register *****************/
3744 #define DMA_LISR_TCIF3 0x08000000U
3745 #define DMA_LISR_HTIF3 0x04000000U
3746 #define DMA_LISR_TEIF3 0x02000000U
3747 #define DMA_LISR_DMEIF3 0x01000000U
3748 #define DMA_LISR_FEIF3 0x00400000U
3749 #define DMA_LISR_TCIF2 0x00200000U
3750 #define DMA_LISR_HTIF2 0x00100000U
3751 #define DMA_LISR_TEIF2 0x00080000U
3752 #define DMA_LISR_DMEIF2 0x00040000U
3753 #define DMA_LISR_FEIF2 0x00010000U
3754 #define DMA_LISR_TCIF1 0x00000800U
3755 #define DMA_LISR_HTIF1 0x00000400U
3756 #define DMA_LISR_TEIF1 0x00000200U
3757 #define DMA_LISR_DMEIF1 0x00000100U
3758 #define DMA_LISR_FEIF1 0x00000040U
3759 #define DMA_LISR_TCIF0 0x00000020U
3760 #define DMA_LISR_HTIF0 0x00000010U
3761 #define DMA_LISR_TEIF0 0x00000008U
3762 #define DMA_LISR_DMEIF0 0x00000004U
3763 #define DMA_LISR_FEIF0 0x00000001U
3764
3765 /******************** Bits definition for DMA_HISR register *****************/
3766 #define DMA_HISR_TCIF7 0x08000000U
3767 #define DMA_HISR_HTIF7 0x04000000U
3768 #define DMA_HISR_TEIF7 0x02000000U
3769 #define DMA_HISR_DMEIF7 0x01000000U
3770 #define DMA_HISR_FEIF7 0x00400000U
3771 #define DMA_HISR_TCIF6 0x00200000U
3772 #define DMA_HISR_HTIF6 0x00100000U
3773 #define DMA_HISR_TEIF6 0x00080000U
3774 #define DMA_HISR_DMEIF6 0x00040000U
3775 #define DMA_HISR_FEIF6 0x00010000U
3776 #define DMA_HISR_TCIF5 0x00000800U
3777 #define DMA_HISR_HTIF5 0x00000400U
3778 #define DMA_HISR_TEIF5 0x00000200U
3779 #define DMA_HISR_DMEIF5 0x00000100U
3780 #define DMA_HISR_FEIF5 0x00000040U
3781 #define DMA_HISR_TCIF4 0x00000020U
3782 #define DMA_HISR_HTIF4 0x00000010U
3783 #define DMA_HISR_TEIF4 0x00000008U
3784 #define DMA_HISR_DMEIF4 0x00000004U
3785 #define DMA_HISR_FEIF4 0x00000001U
3786
3787 /******************** Bits definition for DMA_LIFCR register ****************/
3788 #define DMA_LIFCR_CTCIF3 0x08000000U
3789 #define DMA_LIFCR_CHTIF3 0x04000000U
3790 #define DMA_LIFCR_CTEIF3 0x02000000U
3791 #define DMA_LIFCR_CDMEIF3 0x01000000U
3792 #define DMA_LIFCR_CFEIF3 0x00400000U
3793 #define DMA_LIFCR_CTCIF2 0x00200000U
3794 #define DMA_LIFCR_CHTIF2 0x00100000U
3795 #define DMA_LIFCR_CTEIF2 0x00080000U
3796 #define DMA_LIFCR_CDMEIF2 0x00040000U
3797 #define DMA_LIFCR_CFEIF2 0x00010000U
3798 #define DMA_LIFCR_CTCIF1 0x00000800U
3799 #define DMA_LIFCR_CHTIF1 0x00000400U
3800 #define DMA_LIFCR_CTEIF1 0x00000200U
3801 #define DMA_LIFCR_CDMEIF1 0x00000100U
3802 #define DMA_LIFCR_CFEIF1 0x00000040U
3803 #define DMA_LIFCR_CTCIF0 0x00000020U
3804 #define DMA_LIFCR_CHTIF0 0x00000010U
3805 #define DMA_LIFCR_CTEIF0 0x00000008U
3806 #define DMA_LIFCR_CDMEIF0 0x00000004U
3807 #define DMA_LIFCR_CFEIF0 0x00000001U
3808
3809 /******************** Bits definition for DMA_HIFCR register ****************/
3810 #define DMA_HIFCR_CTCIF7 0x08000000U
3811 #define DMA_HIFCR_CHTIF7 0x04000000U
3812 #define DMA_HIFCR_CTEIF7 0x02000000U
3813 #define DMA_HIFCR_CDMEIF7 0x01000000U
3814 #define DMA_HIFCR_CFEIF7 0x00400000U
3815 #define DMA_HIFCR_CTCIF6 0x00200000U
3816 #define DMA_HIFCR_CHTIF6 0x00100000U
3817 #define DMA_HIFCR_CTEIF6 0x00080000U
3818 #define DMA_HIFCR_CDMEIF6 0x00040000U
3819 #define DMA_HIFCR_CFEIF6 0x00010000U
3820 #define DMA_HIFCR_CTCIF5 0x00000800U
3821 #define DMA_HIFCR_CHTIF5 0x00000400U
3822 #define DMA_HIFCR_CTEIF5 0x00000200U
3823 #define DMA_HIFCR_CDMEIF5 0x00000100U
3824 #define DMA_HIFCR_CFEIF5 0x00000040U
3825 #define DMA_HIFCR_CTCIF4 0x00000020U
3826 #define DMA_HIFCR_CHTIF4 0x00000010U
3827 #define DMA_HIFCR_CTEIF4 0x00000008U
3828 #define DMA_HIFCR_CDMEIF4 0x00000004U
3829 #define DMA_HIFCR_CFEIF4 0x00000001U
3830
3831 /******************************************************************************/
3832 /* */
3833 /* AHB Master DMA2D Controller (DMA2D) */
3834 /* */
3835 /******************************************************************************/
3836
3837 /******************** Bit definition for DMA2D_CR register ******************/
3838
3839 #define DMA2D_CR_START 0x00000001U /*!< Start transfer */
3840 #define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
3841 #define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
3842 #define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
3843 #define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
3844 #define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
3845 #define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
3846 #define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
3847 #define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
3848 #define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
3849 #define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
3850 #define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
3851
3852 /******************** Bit definition for DMA2D_ISR register *****************/
3853
3854 #define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
3855 #define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
3856 #define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
3857 #define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
3858 #define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
3859 #define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
3860
3861 /******************** Bit definition for DMA2D_IFCR register ****************/
3862
3863 #define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
3864 #define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
3865 #define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
3866 #define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
3867 #define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
3868 #define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
3869
3870 /* Legacy defines */
3871 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
3872 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
3873 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
3874 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
3875 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
3876 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
3877
3878 /******************** Bit definition for DMA2D_FGMAR register ***************/
3879
3880 #define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
3881
3882 /******************** Bit definition for DMA2D_FGOR register ****************/
3883
3884 #define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
3885
3886 /******************** Bit definition for DMA2D_BGMAR register ***************/
3887
3888 #define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
3889
3890 /******************** Bit definition for DMA2D_BGOR register ****************/
3891
3892 #define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
3893
3894 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3895
3896 #define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
3897 #define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
3898 #define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
3899 #define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
3900 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
3901 #define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
3902 #define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
3903 #define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
3904 #define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
3905 #define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
3906 #define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
3907 #define DMA2D_FGPFCCR_AI 0x00100000U /*!< Foreground Input Alpha Inverted */
3908 #define DMA2D_FGPFCCR_RBS 0x00200000U /*!< Foreground Input Red Blue Swap */
3909 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
3910
3911 /******************** Bit definition for DMA2D_FGCOLR register **************/
3912
3913 #define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
3914 #define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
3915 #define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
3916
3917 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3918
3919 #define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
3920 #define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
3921 #define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
3922 #define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
3923 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
3924 #define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
3925 #define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
3926 #define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
3927 #define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
3928 #define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
3929 #define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
3930 #define DMA2D_BGPFCCR_AI 0x00100000U /*!< background Input Alpha Inverted */
3931 #define DMA2D_BGPFCCR_RBS 0x00200000U /*!< Background Input Red Blue Swap */
3932 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
3933
3934 /******************** Bit definition for DMA2D_BGCOLR register **************/
3935
3936 #define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
3937 #define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
3938 #define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
3939
3940 /******************** Bit definition for DMA2D_FGCMAR register **************/
3941
3942 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
3943
3944 /******************** Bit definition for DMA2D_BGCMAR register **************/
3945
3946 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
3947
3948 /******************** Bit definition for DMA2D_OPFCCR register **************/
3949
3950 #define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
3951 #define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
3952 #define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
3953 #define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
3954 #define DMA2D_OPFCCR_AI 0x00100000U /*!< Output Alpha Inverted */
3955 #define DMA2D_OPFCCR_RBS 0x00200000U /*!< Output Red Blue Swap */
3956
3957 /******************** Bit definition for DMA2D_OCOLR register ***************/
3958
3959 /*!<Mode_ARGB8888/RGB888 */
3960
3961 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
3962 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
3963 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
3964 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
3965
3966 /*!<Mode_RGB565 */
3967 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
3968 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
3969 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
3970
3971 /*!<Mode_ARGB1555 */
3972 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
3973 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
3974 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
3975 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
3976
3977 /*!<Mode_ARGB4444 */
3978 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
3979 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
3980 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
3981 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
3982
3983 /******************** Bit definition for DMA2D_OMAR register ****************/
3984
3985 #define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
3986
3987 /******************** Bit definition for DMA2D_OOR register *****************/
3988
3989 #define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
3990
3991 /******************** Bit definition for DMA2D_NLR register *****************/
3992
3993 #define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
3994 #define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
3995
3996 /******************** Bit definition for DMA2D_LWR register *****************/
3997
3998 #define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
3999
4000 /******************** Bit definition for DMA2D_AMTCR register ***************/
4001
4002 #define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
4003 #define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
4004
4005
4006 /******************** Bit definition for DMA2D_FGCLUT register **************/
4007
4008 /******************** Bit definition for DMA2D_BGCLUT register **************/
4009
4010
4011 /******************************************************************************/
4012 /* */
4013 /* External Interrupt/Event Controller */
4014 /* */
4015 /******************************************************************************/
4016 /******************* Bit definition for EXTI_IMR register *******************/
4017 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
4018 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
4019 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
4020 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
4021 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
4022 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
4023 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
4024 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
4025 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
4026 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
4027 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
4028 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
4029 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
4030 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
4031 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
4032 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
4033 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
4034 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
4035 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
4036 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
4037 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
4038 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
4039 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
4040 #define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
4041 #define EXTI_IMR_MR24 0x01000000U /*!< Interrupt Mask on line 24 */
4042
4043 /* Reference Defines */
4044 #define EXTI_IMR_IM0 EXTI_IMR_MR0
4045 #define EXTI_IMR_IM1 EXTI_IMR_MR1
4046 #define EXTI_IMR_IM2 EXTI_IMR_MR2
4047 #define EXTI_IMR_IM3 EXTI_IMR_MR3
4048 #define EXTI_IMR_IM4 EXTI_IMR_MR4
4049 #define EXTI_IMR_IM5 EXTI_IMR_MR5
4050 #define EXTI_IMR_IM6 EXTI_IMR_MR6
4051 #define EXTI_IMR_IM7 EXTI_IMR_MR7
4052 #define EXTI_IMR_IM8 EXTI_IMR_MR8
4053 #define EXTI_IMR_IM9 EXTI_IMR_MR9
4054 #define EXTI_IMR_IM10 EXTI_IMR_MR10
4055 #define EXTI_IMR_IM11 EXTI_IMR_MR11
4056 #define EXTI_IMR_IM12 EXTI_IMR_MR12
4057 #define EXTI_IMR_IM13 EXTI_IMR_MR13
4058 #define EXTI_IMR_IM14 EXTI_IMR_MR14
4059 #define EXTI_IMR_IM15 EXTI_IMR_MR15
4060 #define EXTI_IMR_IM16 EXTI_IMR_MR16
4061 #define EXTI_IMR_IM17 EXTI_IMR_MR17
4062 #define EXTI_IMR_IM18 EXTI_IMR_MR18
4063 #define EXTI_IMR_IM19 EXTI_IMR_MR19
4064 #define EXTI_IMR_IM20 EXTI_IMR_MR20
4065 #define EXTI_IMR_IM21 EXTI_IMR_MR21
4066 #define EXTI_IMR_IM22 EXTI_IMR_MR22
4067 #define EXTI_IMR_IM23 EXTI_IMR_MR23
4068 #define EXTI_IMR_IM24 EXTI_IMR_MR24
4069
4070 #define EXTI_IMR_IM 0x01FFFFFFU /*!< Interrupt Mask All */
4071
4072 /******************* Bit definition for EXTI_EMR register *******************/
4073 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
4074 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
4075 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
4076 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
4077 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
4078 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
4079 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
4080 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
4081 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
4082 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
4083 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
4084 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
4085 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
4086 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
4087 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
4088 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
4089 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
4090 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
4091 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
4092 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
4093 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
4094 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
4095 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
4096 #define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
4097 #define EXTI_EMR_MR24 0x01000000U /*!< Event Mask on line 24 */
4098
4099 /* Reference Defines */
4100 #define EXTI_EMR_EM0 EXTI_EMR_MR0
4101 #define EXTI_EMR_EM1 EXTI_EMR_MR1
4102 #define EXTI_EMR_EM2 EXTI_EMR_MR2
4103 #define EXTI_EMR_EM3 EXTI_EMR_MR3
4104 #define EXTI_EMR_EM4 EXTI_EMR_MR4
4105 #define EXTI_EMR_EM5 EXTI_EMR_MR5
4106 #define EXTI_EMR_EM6 EXTI_EMR_MR6
4107 #define EXTI_EMR_EM7 EXTI_EMR_MR7
4108 #define EXTI_EMR_EM8 EXTI_EMR_MR8
4109 #define EXTI_EMR_EM9 EXTI_EMR_MR9
4110 #define EXTI_EMR_EM10 EXTI_EMR_MR10
4111 #define EXTI_EMR_EM11 EXTI_EMR_MR11
4112 #define EXTI_EMR_EM12 EXTI_EMR_MR12
4113 #define EXTI_EMR_EM13 EXTI_EMR_MR13
4114 #define EXTI_EMR_EM14 EXTI_EMR_MR14
4115 #define EXTI_EMR_EM15 EXTI_EMR_MR15
4116 #define EXTI_EMR_EM16 EXTI_EMR_MR16
4117 #define EXTI_EMR_EM17 EXTI_EMR_MR17
4118 #define EXTI_EMR_EM18 EXTI_EMR_MR18
4119 #define EXTI_EMR_EM19 EXTI_EMR_MR19
4120 #define EXTI_EMR_EM20 EXTI_EMR_MR20
4121 #define EXTI_EMR_EM21 EXTI_EMR_MR21
4122 #define EXTI_EMR_EM22 EXTI_EMR_MR22
4123 #define EXTI_EMR_EM23 EXTI_EMR_MR23
4124 #define EXTI_EMR_EM24 EXTI_EMR_MR24
4125
4126
4127 /****************** Bit definition for EXTI_RTSR register *******************/
4128 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
4129 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
4130 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
4131 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
4132 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
4133 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
4134 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
4135 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
4136 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
4137 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
4138 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
4139 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
4140 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
4141 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
4142 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
4143 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
4144 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
4145 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
4146 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
4147 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
4148 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
4149 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
4150 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
4151 #define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
4152 #define EXTI_RTSR_TR24 0x01000000U /*!< Rising trigger event configuration bit of line 24 */
4153
4154 /****************** Bit definition for EXTI_FTSR register *******************/
4155 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
4156 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
4157 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
4158 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
4159 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
4160 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
4161 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
4162 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
4163 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
4164 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
4165 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
4166 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
4167 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
4168 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
4169 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
4170 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
4171 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
4172 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
4173 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
4174 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
4175 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
4176 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
4177 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
4178 #define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
4179 #define EXTI_FTSR_TR24 0x01000000U /*!< Falling trigger event configuration bit of line 24 */
4180
4181 /****************** Bit definition for EXTI_SWIER register ******************/
4182 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
4183 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
4184 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
4185 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
4186 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
4187 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
4188 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
4189 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
4190 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
4191 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
4192 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
4193 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
4194 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
4195 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
4196 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
4197 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
4198 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
4199 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
4200 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
4201 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
4202 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
4203 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
4204 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
4205 #define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
4206 #define EXTI_SWIER_SWIER24 0x01000000U /*!< Software Interrupt on line 24 */
4207
4208 /******************* Bit definition for EXTI_PR register ********************/
4209 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
4210 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
4211 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
4212 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
4213 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
4214 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
4215 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
4216 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
4217 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
4218 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
4219 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
4220 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
4221 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
4222 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
4223 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
4224 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
4225 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
4226 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
4227 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
4228 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
4229 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
4230 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
4231 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
4232 #define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
4233 #define EXTI_PR_PR24 0x01000000U /*!< Pending bit for line 24 */
4234
4235 /******************************************************************************/
4236 /* */
4237 /* FLASH */
4238 /* */
4239 /******************************************************************************/
4240 /*
4241 * @brief FLASH Total Sectors Number
4242 */
4243 #define FLASH_SECTOR_TOTAL 24
4244
4245 /******************* Bits definition for FLASH_ACR register *****************/
4246 #define FLASH_ACR_LATENCY 0x0000000FU
4247 #define FLASH_ACR_LATENCY_0WS 0x00000000U
4248 #define FLASH_ACR_LATENCY_1WS 0x00000001U
4249 #define FLASH_ACR_LATENCY_2WS 0x00000002U
4250 #define FLASH_ACR_LATENCY_3WS 0x00000003U
4251 #define FLASH_ACR_LATENCY_4WS 0x00000004U
4252 #define FLASH_ACR_LATENCY_5WS 0x00000005U
4253 #define FLASH_ACR_LATENCY_6WS 0x00000006U
4254 #define FLASH_ACR_LATENCY_7WS 0x00000007U
4255 #define FLASH_ACR_LATENCY_8WS 0x00000008U
4256 #define FLASH_ACR_LATENCY_9WS 0x00000009U
4257 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
4258 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
4259 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
4260 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
4261 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
4262 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
4263 #define FLASH_ACR_PRFTEN 0x00000100U
4264 #define FLASH_ACR_ARTEN 0x00000200U
4265 #define FLASH_ACR_ARTRST 0x00000800U
4266
4267 /******************* Bits definition for FLASH_SR register ******************/
4268 #define FLASH_SR_EOP 0x00000001U
4269 #define FLASH_SR_OPERR 0x00000002U
4270 #define FLASH_SR_WRPERR 0x00000010U
4271 #define FLASH_SR_PGAERR 0x00000020U
4272 #define FLASH_SR_PGPERR 0x00000040U
4273 #define FLASH_SR_ERSERR 0x00000080U
4274 #define FLASH_SR_BSY 0x00010000U
4275
4276 /******************* Bits definition for FLASH_CR register ******************/
4277 #define FLASH_CR_PG 0x00000001U
4278 #define FLASH_CR_SER 0x00000002U
4279 #define FLASH_CR_MER 0x00000004U
4280 #define FLASH_CR_MER1 FLASH_CR_MER
4281 #define FLASH_CR_SNB 0x000000F8U
4282 #define FLASH_CR_SNB_0 0x00000008U
4283 #define FLASH_CR_SNB_1 0x00000010U
4284 #define FLASH_CR_SNB_2 0x00000020U
4285 #define FLASH_CR_SNB_3 0x00000040U
4286 #define FLASH_CR_SNB_4 0x00000080U
4287 #define FLASH_CR_PSIZE 0x00000300U
4288 #define FLASH_CR_PSIZE_0 0x00000100U
4289 #define FLASH_CR_PSIZE_1 0x00000200U
4290 #define FLASH_CR_MER2 0x00008000U
4291 #define FLASH_CR_STRT 0x00010000U
4292 #define FLASH_CR_EOPIE 0x01000000U
4293 #define FLASH_CR_ERRIE 0x02000000U
4294 #define FLASH_CR_LOCK 0x80000000U
4295
4296 /******************* Bits definition for FLASH_OPTCR register ***************/
4297 #define FLASH_OPTCR_OPTLOCK 0x00000001U
4298 #define FLASH_OPTCR_OPTSTRT 0x00000002U
4299 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
4300 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
4301 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
4302 #define FLASH_OPTCR_WWDG_SW 0x00000010U
4303 #define FLASH_OPTCR_IWDG_SW 0x00000020U
4304 #define FLASH_OPTCR_nRST_STOP 0x00000040U
4305 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
4306 #define FLASH_OPTCR_RDP 0x0000FF00U
4307 #define FLASH_OPTCR_RDP_0 0x00000100U
4308 #define FLASH_OPTCR_RDP_1 0x00000200U
4309 #define FLASH_OPTCR_RDP_2 0x00000400U
4310 #define FLASH_OPTCR_RDP_3 0x00000800U
4311 #define FLASH_OPTCR_RDP_4 0x00001000U
4312 #define FLASH_OPTCR_RDP_5 0x00002000U
4313 #define FLASH_OPTCR_RDP_6 0x00004000U
4314 #define FLASH_OPTCR_RDP_7 0x00008000U
4315 #define FLASH_OPTCR_nWRP 0x0FFF0000U
4316 #define FLASH_OPTCR_nWRP_0 0x00010000U
4317 #define FLASH_OPTCR_nWRP_1 0x00020000U
4318 #define FLASH_OPTCR_nWRP_2 0x00040000U
4319 #define FLASH_OPTCR_nWRP_3 0x00080000U
4320 #define FLASH_OPTCR_nWRP_4 0x00100000U
4321 #define FLASH_OPTCR_nWRP_5 0x00200000U
4322 #define FLASH_OPTCR_nWRP_6 0x00400000U
4323 #define FLASH_OPTCR_nWRP_7 0x00800000U
4324 #define FLASH_OPTCR_nWRP_8 0x01000000U
4325 #define FLASH_OPTCR_nWRP_9 0x02000000U
4326 #define FLASH_OPTCR_nWRP_10 0x04000000U
4327 #define FLASH_OPTCR_nWRP_11 0x08000000U
4328 #define FLASH_OPTCR_nDBOOT 0x10000000U
4329 #define FLASH_OPTCR_nDBANK 0x20000000U
4330 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
4331 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
4332
4333 /******************* Bits definition for FLASH_OPTCR1 register ***************/
4334 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
4335 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
4336
4337 /******************************************************************************/
4338 /* */
4339 /* Flexible Memory Controller */
4340 /* */
4341 /******************************************************************************/
4342 /****************** Bit definition for FMC_BCR1 register *******************/
4343 #define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
4344 #define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
4345 #define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
4346 #define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
4347 #define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
4348 #define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
4349 #define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
4350 #define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
4351 #define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
4352 #define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
4353 #define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
4354 #define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
4355 #define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
4356 #define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
4357 #define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
4358 #define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
4359 #define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
4360 #define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
4361 #define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
4362 #define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
4363 #define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
4364 #define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
4365 #define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
4366 #define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
4367
4368 /****************** Bit definition for FMC_BCR2 register *******************/
4369 #define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
4370 #define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
4371 #define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
4372 #define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
4373 #define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
4374 #define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
4375 #define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
4376 #define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
4377 #define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
4378 #define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
4379 #define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
4380 #define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
4381 #define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
4382 #define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
4383 #define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
4384 #define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
4385 #define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
4386 #define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
4387 #define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
4388 #define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
4389 #define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
4390 #define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
4391
4392 /****************** Bit definition for FMC_BCR3 register *******************/
4393 #define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
4394 #define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
4395 #define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
4396 #define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
4397 #define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
4398 #define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
4399 #define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
4400 #define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
4401 #define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
4402 #define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
4403 #define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
4404 #define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
4405 #define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
4406 #define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
4407 #define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
4408 #define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
4409 #define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
4410 #define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
4411 #define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
4412 #define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
4413 #define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
4414 #define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
4415
4416 /****************** Bit definition for FMC_BCR4 register *******************/
4417 #define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
4418 #define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
4419 #define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
4420 #define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
4421 #define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
4422 #define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
4423 #define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
4424 #define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
4425 #define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
4426 #define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
4427 #define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
4428 #define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
4429 #define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
4430 #define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
4431 #define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
4432 #define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
4433 #define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
4434 #define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
4435 #define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
4436 #define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
4437 #define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
4438 #define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
4439
4440 /****************** Bit definition for FMC_BTR1 register ******************/
4441 #define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4442 #define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
4443 #define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
4444 #define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
4445 #define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
4446 #define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4447 #define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
4448 #define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
4449 #define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
4450 #define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
4451 #define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4452 #define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
4453 #define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
4454 #define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
4455 #define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
4456 #define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
4457 #define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
4458 #define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
4459 #define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
4460 #define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4461 #define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
4462 #define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
4463 #define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
4464 #define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
4465 #define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4466 #define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
4467 #define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
4468 #define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
4469 #define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
4470 #define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
4471 #define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
4472 #define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
4473 #define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
4474 #define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
4475 #define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4476 #define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
4477 #define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
4478
4479 /****************** Bit definition for FMC_BTR2 register *******************/
4480 #define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4481 #define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
4482 #define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
4483 #define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
4484 #define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
4485 #define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4486 #define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
4487 #define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
4488 #define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
4489 #define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
4490 #define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4491 #define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
4492 #define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
4493 #define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
4494 #define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
4495 #define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
4496 #define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
4497 #define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
4498 #define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
4499 #define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4500 #define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
4501 #define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
4502 #define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
4503 #define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
4504 #define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4505 #define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
4506 #define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
4507 #define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
4508 #define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
4509 #define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
4510 #define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
4511 #define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
4512 #define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
4513 #define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
4514 #define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4515 #define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
4516 #define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
4517
4518 /******************* Bit definition for FMC_BTR3 register *******************/
4519 #define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4520 #define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
4521 #define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
4522 #define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
4523 #define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
4524 #define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4525 #define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
4526 #define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
4527 #define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
4528 #define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
4529 #define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4530 #define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
4531 #define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
4532 #define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
4533 #define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
4534 #define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
4535 #define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
4536 #define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
4537 #define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
4538 #define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4539 #define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
4540 #define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
4541 #define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
4542 #define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
4543 #define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4544 #define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
4545 #define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
4546 #define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
4547 #define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
4548 #define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
4549 #define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
4550 #define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
4551 #define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
4552 #define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
4553 #define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4554 #define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
4555 #define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
4556
4557 /****************** Bit definition for FMC_BTR4 register *******************/
4558 #define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4559 #define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
4560 #define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
4561 #define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
4562 #define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
4563 #define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4564 #define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
4565 #define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
4566 #define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
4567 #define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
4568 #define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4569 #define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
4570 #define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
4571 #define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
4572 #define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
4573 #define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
4574 #define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
4575 #define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
4576 #define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
4577 #define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4578 #define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
4579 #define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
4580 #define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
4581 #define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
4582 #define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4583 #define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
4584 #define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
4585 #define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
4586 #define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
4587 #define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
4588 #define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
4589 #define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
4590 #define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
4591 #define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
4592 #define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4593 #define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
4594 #define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
4595
4596 /****************** Bit definition for FMC_BWTR1 register ******************/
4597 #define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4598 #define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
4599 #define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
4600 #define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
4601 #define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
4602 #define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4603 #define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
4604 #define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
4605 #define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
4606 #define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
4607 #define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4608 #define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
4609 #define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
4610 #define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
4611 #define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
4612 #define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
4613 #define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
4614 #define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
4615 #define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
4616 #define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4617 #define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
4618 #define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
4619 #define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
4620 #define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
4621 #define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4622 #define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
4623 #define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
4624
4625 /****************** Bit definition for FMC_BWTR2 register ******************/
4626 #define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4627 #define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
4628 #define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
4629 #define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
4630 #define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
4631 #define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4632 #define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
4633 #define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
4634 #define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
4635 #define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
4636 #define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4637 #define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
4638 #define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
4639 #define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
4640 #define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
4641 #define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
4642 #define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
4643 #define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
4644 #define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
4645 #define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4646 #define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
4647 #define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
4648 #define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
4649 #define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
4650 #define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4651 #define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
4652 #define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
4653
4654 /****************** Bit definition for FMC_BWTR3 register ******************/
4655 #define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4656 #define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
4657 #define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
4658 #define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
4659 #define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
4660 #define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4661 #define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
4662 #define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
4663 #define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
4664 #define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
4665 #define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4666 #define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
4667 #define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
4668 #define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
4669 #define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
4670 #define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
4671 #define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
4672 #define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
4673 #define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
4674 #define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4675 #define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
4676 #define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
4677 #define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
4678 #define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
4679 #define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4680 #define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
4681 #define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
4682
4683 /****************** Bit definition for FMC_BWTR4 register ******************/
4684 #define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
4685 #define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
4686 #define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
4687 #define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
4688 #define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
4689 #define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4690 #define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
4691 #define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
4692 #define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
4693 #define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
4694 #define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
4695 #define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
4696 #define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
4697 #define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
4698 #define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
4699 #define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
4700 #define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
4701 #define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
4702 #define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
4703 #define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4704 #define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
4705 #define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
4706 #define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
4707 #define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
4708 #define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
4709 #define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
4710 #define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
4711
4712 /****************** Bit definition for FMC_PCR register *******************/
4713 #define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
4714 #define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
4715 #define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
4716 #define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
4717 #define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
4718 #define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
4719 #define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
4720 #define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
4721 #define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
4722 #define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
4723 #define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
4724 #define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
4725 #define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
4726 #define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
4727 #define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
4728 #define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
4729 #define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
4730 #define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
4731 #define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
4732 #define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
4733 #define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
4734
4735 /******************* Bit definition for FMC_SR register *******************/
4736 #define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
4737 #define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
4738 #define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
4739 #define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
4740 #define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
4741 #define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
4742 #define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
4743
4744 /****************** Bit definition for FMC_PMEM register ******************/
4745 #define FMC_PMEM_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4746 #define FMC_PMEM_MEMSET3_0 0x00000001U /*!<Bit 0 */
4747 #define FMC_PMEM_MEMSET3_1 0x00000002U /*!<Bit 1 */
4748 #define FMC_PMEM_MEMSET3_2 0x00000004U /*!<Bit 2 */
4749 #define FMC_PMEM_MEMSET3_3 0x00000008U /*!<Bit 3 */
4750 #define FMC_PMEM_MEMSET3_4 0x00000010U /*!<Bit 4 */
4751 #define FMC_PMEM_MEMSET3_5 0x00000020U /*!<Bit 5 */
4752 #define FMC_PMEM_MEMSET3_6 0x00000040U /*!<Bit 6 */
4753 #define FMC_PMEM_MEMSET3_7 0x00000080U /*!<Bit 7 */
4754 #define FMC_PMEM_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4755 #define FMC_PMEM_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
4756 #define FMC_PMEM_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
4757 #define FMC_PMEM_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
4758 #define FMC_PMEM_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
4759 #define FMC_PMEM_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
4760 #define FMC_PMEM_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
4761 #define FMC_PMEM_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
4762 #define FMC_PMEM_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
4763 #define FMC_PMEM_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4764 #define FMC_PMEM_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
4765 #define FMC_PMEM_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
4766 #define FMC_PMEM_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
4767 #define FMC_PMEM_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
4768 #define FMC_PMEM_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
4769 #define FMC_PMEM_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
4770 #define FMC_PMEM_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
4771 #define FMC_PMEM_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
4772 #define FMC_PMEM_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4773 #define FMC_PMEM_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
4774 #define FMC_PMEM_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
4775 #define FMC_PMEM_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
4776 #define FMC_PMEM_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
4777 #define FMC_PMEM_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
4778 #define FMC_PMEM_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
4779 #define FMC_PMEM_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
4780 #define FMC_PMEM_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
4781
4782 /****************** Bit definition for FMC_PATT register ******************/
4783 #define FMC_PATT_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4784 #define FMC_PATT_ATTSET3_0 0x00000001U /*!<Bit 0 */
4785 #define FMC_PATT_ATTSET3_1 0x00000002U /*!<Bit 1 */
4786 #define FMC_PATT_ATTSET3_2 0x00000004U /*!<Bit 2 */
4787 #define FMC_PATT_ATTSET3_3 0x00000008U /*!<Bit 3 */
4788 #define FMC_PATT_ATTSET3_4 0x00000010U /*!<Bit 4 */
4789 #define FMC_PATT_ATTSET3_5 0x00000020U /*!<Bit 5 */
4790 #define FMC_PATT_ATTSET3_6 0x00000040U /*!<Bit 6 */
4791 #define FMC_PATT_ATTSET3_7 0x00000080U /*!<Bit 7 */
4792 #define FMC_PATT_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4793 #define FMC_PATT_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
4794 #define FMC_PATT_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
4795 #define FMC_PATT_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
4796 #define FMC_PATT_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
4797 #define FMC_PATT_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
4798 #define FMC_PATT_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
4799 #define FMC_PATT_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
4800 #define FMC_PATT_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
4801 #define FMC_PATT_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4802 #define FMC_PATT_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
4803 #define FMC_PATT_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
4804 #define FMC_PATT_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
4805 #define FMC_PATT_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
4806 #define FMC_PATT_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
4807 #define FMC_PATT_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
4808 #define FMC_PATT_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
4809 #define FMC_PATT_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
4810 #define FMC_PATT_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4811 #define FMC_PATT_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
4812 #define FMC_PATT_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
4813 #define FMC_PATT_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
4814 #define FMC_PATT_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
4815 #define FMC_PATT_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
4816 #define FMC_PATT_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
4817 #define FMC_PATT_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
4818 #define FMC_PATT_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
4819
4820 /****************** Bit definition for FMC_ECCR register ******************/
4821 #define FMC_ECCR_ECC3 0xFFFFFFFFU /*!<ECC result */
4822
4823 /****************** Bit definition for FMC_SDCR1 register ******************/
4824 #define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
4825 #define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
4826 #define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
4827 #define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
4828 #define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
4829 #define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
4830 #define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
4831 #define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
4832 #define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
4833 #define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
4834 #define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
4835 #define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
4836 #define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
4837 #define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
4838 #define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
4839 #define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
4840 #define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
4841 #define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
4842 #define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
4843 #define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
4844 #define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
4845
4846 /****************** Bit definition for FMC_SDCR2 register ******************/
4847 #define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
4848 #define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
4849 #define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
4850 #define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
4851 #define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
4852 #define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
4853 #define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
4854 #define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
4855 #define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
4856 #define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
4857 #define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
4858 #define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
4859 #define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
4860 #define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
4861 #define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
4862 #define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
4863 #define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
4864 #define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
4865 #define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
4866 #define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
4867 #define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
4868
4869 /****************** Bit definition for FMC_SDTR1 register ******************/
4870 #define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
4871 #define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
4872 #define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
4873 #define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
4874 #define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
4875 #define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
4876 #define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
4877 #define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
4878 #define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
4879 #define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
4880 #define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
4881 #define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
4882 #define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
4883 #define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
4884 #define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
4885 #define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
4886 #define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
4887 #define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
4888 #define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
4889 #define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
4890 #define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
4891 #define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
4892 #define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
4893 #define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
4894 #define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
4895 #define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
4896 #define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
4897 #define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
4898 #define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
4899 #define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
4900 #define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
4901
4902 /****************** Bit definition for FMC_SDTR2 register ******************/
4903 #define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
4904 #define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
4905 #define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
4906 #define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
4907 #define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
4908 #define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
4909 #define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
4910 #define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
4911 #define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
4912 #define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
4913 #define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
4914 #define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
4915 #define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
4916 #define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
4917 #define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
4918 #define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
4919 #define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
4920 #define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
4921 #define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
4922 #define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
4923 #define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
4924 #define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
4925 #define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
4926 #define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
4927 #define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
4928 #define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
4929 #define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
4930 #define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
4931 #define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
4932 #define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
4933 #define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
4934
4935 /****************** Bit definition for FMC_SDCMR register ******************/
4936 #define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
4937 #define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
4938 #define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
4939 #define FMC_SDCMR_MODE_2 0x00000003U /*!<Bit 2 */
4940 #define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
4941 #define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
4942 #define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
4943 #define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
4944 #define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
4945 #define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
4946 #define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
4947 #define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
4948
4949 /****************** Bit definition for FMC_SDRTR register ******************/
4950 #define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
4951 #define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
4952 #define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
4953
4954 /****************** Bit definition for FMC_SDSR register ******************/
4955 #define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
4956 #define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
4957 #define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
4958 #define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
4959 #define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
4960 #define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
4961 #define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
4962 #define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
4963
4964 /******************************************************************************/
4965 /* */
4966 /* General Purpose I/O */
4967 /* */
4968 /******************************************************************************/
4969 /****************** Bits definition for GPIO_MODER register *****************/
4970 #define GPIO_MODER_MODER0 0x00000003U
4971 #define GPIO_MODER_MODER0_0 0x00000001U
4972 #define GPIO_MODER_MODER0_1 0x00000002U
4973 #define GPIO_MODER_MODER1 0x0000000CU
4974 #define GPIO_MODER_MODER1_0 0x00000004U
4975 #define GPIO_MODER_MODER1_1 0x00000008U
4976 #define GPIO_MODER_MODER2 0x00000030U
4977 #define GPIO_MODER_MODER2_0 0x00000010U
4978 #define GPIO_MODER_MODER2_1 0x00000020U
4979 #define GPIO_MODER_MODER3 0x000000C0U
4980 #define GPIO_MODER_MODER3_0 0x00000040U
4981 #define GPIO_MODER_MODER3_1 0x00000080U
4982 #define GPIO_MODER_MODER4 0x00000300U
4983 #define GPIO_MODER_MODER4_0 0x00000100U
4984 #define GPIO_MODER_MODER4_1 0x00000200U
4985 #define GPIO_MODER_MODER5 0x00000C00U
4986 #define GPIO_MODER_MODER5_0 0x00000400U
4987 #define GPIO_MODER_MODER5_1 0x00000800U
4988 #define GPIO_MODER_MODER6 0x00003000U
4989 #define GPIO_MODER_MODER6_0 0x00001000U
4990 #define GPIO_MODER_MODER6_1 0x00002000U
4991 #define GPIO_MODER_MODER7 0x0000C000U
4992 #define GPIO_MODER_MODER7_0 0x00004000U
4993 #define GPIO_MODER_MODER7_1 0x00008000U
4994 #define GPIO_MODER_MODER8 0x00030000U
4995 #define GPIO_MODER_MODER8_0 0x00010000U
4996 #define GPIO_MODER_MODER8_1 0x00020000U
4997 #define GPIO_MODER_MODER9 0x000C0000U
4998 #define GPIO_MODER_MODER9_0 0x00040000U
4999 #define GPIO_MODER_MODER9_1 0x00080000U
5000 #define GPIO_MODER_MODER10 0x00300000U
5001 #define GPIO_MODER_MODER10_0 0x00100000U
5002 #define GPIO_MODER_MODER10_1 0x00200000U
5003 #define GPIO_MODER_MODER11 0x00C00000U
5004 #define GPIO_MODER_MODER11_0 0x00400000U
5005 #define GPIO_MODER_MODER11_1 0x00800000U
5006 #define GPIO_MODER_MODER12 0x03000000U
5007 #define GPIO_MODER_MODER12_0 0x01000000U
5008 #define GPIO_MODER_MODER12_1 0x02000000U
5009 #define GPIO_MODER_MODER13 0x0C000000U
5010 #define GPIO_MODER_MODER13_0 0x04000000U
5011 #define GPIO_MODER_MODER13_1 0x08000000U
5012 #define GPIO_MODER_MODER14 0x30000000U
5013 #define GPIO_MODER_MODER14_0 0x10000000U
5014 #define GPIO_MODER_MODER14_1 0x20000000U
5015 #define GPIO_MODER_MODER15 0xC0000000U
5016 #define GPIO_MODER_MODER15_0 0x40000000U
5017 #define GPIO_MODER_MODER15_1 0x80000000U
5018
5019 /****************** Bits definition for GPIO_OTYPER register ****************/
5020 #define GPIO_OTYPER_OT_0 0x00000001U
5021 #define GPIO_OTYPER_OT_1 0x00000002U
5022 #define GPIO_OTYPER_OT_2 0x00000004U
5023 #define GPIO_OTYPER_OT_3 0x00000008U
5024 #define GPIO_OTYPER_OT_4 0x00000010U
5025 #define GPIO_OTYPER_OT_5 0x00000020U
5026 #define GPIO_OTYPER_OT_6 0x00000040U
5027 #define GPIO_OTYPER_OT_7 0x00000080U
5028 #define GPIO_OTYPER_OT_8 0x00000100U
5029 #define GPIO_OTYPER_OT_9 0x00000200U
5030 #define GPIO_OTYPER_OT_10 0x00000400U
5031 #define GPIO_OTYPER_OT_11 0x00000800U
5032 #define GPIO_OTYPER_OT_12 0x00001000U
5033 #define GPIO_OTYPER_OT_13 0x00002000U
5034 #define GPIO_OTYPER_OT_14 0x00004000U
5035 #define GPIO_OTYPER_OT_15 0x00008000U
5036
5037 /****************** Bits definition for GPIO_OSPEEDR register ***************/
5038 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
5039 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
5040 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
5041 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
5042 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
5043 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
5044 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
5045 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
5046 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
5047 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
5048 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
5049 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
5050 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
5051 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
5052 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
5053 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
5054 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
5055 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
5056 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
5057 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
5058 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
5059 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
5060 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
5061 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
5062 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
5063 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
5064 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
5065 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
5066 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
5067 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
5068 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
5069 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
5070 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
5071 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
5072 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
5073 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
5074 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
5075 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
5076 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
5077 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
5078 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
5079 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
5080 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
5081 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
5082 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
5083 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
5084 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
5085 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
5086
5087 /****************** Bits definition for GPIO_PUPDR register *****************/
5088 #define GPIO_PUPDR_PUPDR0 0x00000003U
5089 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
5090 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
5091 #define GPIO_PUPDR_PUPDR1 0x0000000CU
5092 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
5093 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
5094 #define GPIO_PUPDR_PUPDR2 0x00000030U
5095 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
5096 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
5097 #define GPIO_PUPDR_PUPDR3 0x000000C0U
5098 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
5099 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
5100 #define GPIO_PUPDR_PUPDR4 0x00000300U
5101 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
5102 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
5103 #define GPIO_PUPDR_PUPDR5 0x00000C00U
5104 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
5105 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
5106 #define GPIO_PUPDR_PUPDR6 0x00003000U
5107 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
5108 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
5109 #define GPIO_PUPDR_PUPDR7 0x0000C000U
5110 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
5111 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
5112 #define GPIO_PUPDR_PUPDR8 0x00030000U
5113 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
5114 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
5115 #define GPIO_PUPDR_PUPDR9 0x000C0000U
5116 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
5117 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
5118 #define GPIO_PUPDR_PUPDR10 0x00300000U
5119 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
5120 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
5121 #define GPIO_PUPDR_PUPDR11 0x00C00000U
5122 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
5123 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
5124 #define GPIO_PUPDR_PUPDR12 0x03000000U
5125 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
5126 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
5127 #define GPIO_PUPDR_PUPDR13 0x0C000000U
5128 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
5129 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
5130 #define GPIO_PUPDR_PUPDR14 0x30000000U
5131 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
5132 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
5133 #define GPIO_PUPDR_PUPDR15 0xC0000000U
5134 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
5135 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
5136
5137 /****************** Bits definition for GPIO_IDR register *******************/
5138 #define GPIO_IDR_IDR_0 0x00000001U
5139 #define GPIO_IDR_IDR_1 0x00000002U
5140 #define GPIO_IDR_IDR_2 0x00000004U
5141 #define GPIO_IDR_IDR_3 0x00000008U
5142 #define GPIO_IDR_IDR_4 0x00000010U
5143 #define GPIO_IDR_IDR_5 0x00000020U
5144 #define GPIO_IDR_IDR_6 0x00000040U
5145 #define GPIO_IDR_IDR_7 0x00000080U
5146 #define GPIO_IDR_IDR_8 0x00000100U
5147 #define GPIO_IDR_IDR_9 0x00000200U
5148 #define GPIO_IDR_IDR_10 0x00000400U
5149 #define GPIO_IDR_IDR_11 0x00000800U
5150 #define GPIO_IDR_IDR_12 0x00001000U
5151 #define GPIO_IDR_IDR_13 0x00002000U
5152 #define GPIO_IDR_IDR_14 0x00004000U
5153 #define GPIO_IDR_IDR_15 0x00008000U
5154
5155 /****************** Bits definition for GPIO_ODR register *******************/
5156 #define GPIO_ODR_ODR_0 0x00000001U
5157 #define GPIO_ODR_ODR_1 0x00000002U
5158 #define GPIO_ODR_ODR_2 0x00000004U
5159 #define GPIO_ODR_ODR_3 0x00000008U
5160 #define GPIO_ODR_ODR_4 0x00000010U
5161 #define GPIO_ODR_ODR_5 0x00000020U
5162 #define GPIO_ODR_ODR_6 0x00000040U
5163 #define GPIO_ODR_ODR_7 0x00000080U
5164 #define GPIO_ODR_ODR_8 0x00000100U
5165 #define GPIO_ODR_ODR_9 0x00000200U
5166 #define GPIO_ODR_ODR_10 0x00000400U
5167 #define GPIO_ODR_ODR_11 0x00000800U
5168 #define GPIO_ODR_ODR_12 0x00001000U
5169 #define GPIO_ODR_ODR_13 0x00002000U
5170 #define GPIO_ODR_ODR_14 0x00004000U
5171 #define GPIO_ODR_ODR_15 0x00008000U
5172
5173 /****************** Bits definition for GPIO_BSRR register ******************/
5174 #define GPIO_BSRR_BS_0 0x00000001U
5175 #define GPIO_BSRR_BS_1 0x00000002U
5176 #define GPIO_BSRR_BS_2 0x00000004U
5177 #define GPIO_BSRR_BS_3 0x00000008U
5178 #define GPIO_BSRR_BS_4 0x00000010U
5179 #define GPIO_BSRR_BS_5 0x00000020U
5180 #define GPIO_BSRR_BS_6 0x00000040U
5181 #define GPIO_BSRR_BS_7 0x00000080U
5182 #define GPIO_BSRR_BS_8 0x00000100U
5183 #define GPIO_BSRR_BS_9 0x00000200U
5184 #define GPIO_BSRR_BS_10 0x00000400U
5185 #define GPIO_BSRR_BS_11 0x00000800U
5186 #define GPIO_BSRR_BS_12 0x00001000U
5187 #define GPIO_BSRR_BS_13 0x00002000U
5188 #define GPIO_BSRR_BS_14 0x00004000U
5189 #define GPIO_BSRR_BS_15 0x00008000U
5190 #define GPIO_BSRR_BR_0 0x00010000U
5191 #define GPIO_BSRR_BR_1 0x00020000U
5192 #define GPIO_BSRR_BR_2 0x00040000U
5193 #define GPIO_BSRR_BR_3 0x00080000U
5194 #define GPIO_BSRR_BR_4 0x00100000U
5195 #define GPIO_BSRR_BR_5 0x00200000U
5196 #define GPIO_BSRR_BR_6 0x00400000U
5197 #define GPIO_BSRR_BR_7 0x00800000U
5198 #define GPIO_BSRR_BR_8 0x01000000U
5199 #define GPIO_BSRR_BR_9 0x02000000U
5200 #define GPIO_BSRR_BR_10 0x04000000U
5201 #define GPIO_BSRR_BR_11 0x08000000U
5202 #define GPIO_BSRR_BR_12 0x10000000U
5203 #define GPIO_BSRR_BR_13 0x20000000U
5204 #define GPIO_BSRR_BR_14 0x40000000U
5205 #define GPIO_BSRR_BR_15 0x80000000U
5206
5207 /****************** Bit definition for GPIO_LCKR register *********************/
5208 #define GPIO_LCKR_LCK0 0x00000001U
5209 #define GPIO_LCKR_LCK1 0x00000002U
5210 #define GPIO_LCKR_LCK2 0x00000004U
5211 #define GPIO_LCKR_LCK3 0x00000008U
5212 #define GPIO_LCKR_LCK4 0x00000010U
5213 #define GPIO_LCKR_LCK5 0x00000020U
5214 #define GPIO_LCKR_LCK6 0x00000040U
5215 #define GPIO_LCKR_LCK7 0x00000080U
5216 #define GPIO_LCKR_LCK8 0x00000100U
5217 #define GPIO_LCKR_LCK9 0x00000200U
5218 #define GPIO_LCKR_LCK10 0x00000400U
5219 #define GPIO_LCKR_LCK11 0x00000800U
5220 #define GPIO_LCKR_LCK12 0x00001000U
5221 #define GPIO_LCKR_LCK13 0x00002000U
5222 #define GPIO_LCKR_LCK14 0x00004000U
5223 #define GPIO_LCKR_LCK15 0x00008000U
5224 #define GPIO_LCKR_LCKK 0x00010000U
5225
5226
5227 /******************************************************************************/
5228 /* */
5229 /* Inter-integrated Circuit Interface (I2C) */
5230 /* */
5231 /******************************************************************************/
5232 /******************* Bit definition for I2C_CR1 register *******************/
5233 #define I2C_CR1_PE 0x00000001U /*!< Peripheral enable */
5234 #define I2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
5235 #define I2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
5236 #define I2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
5237 #define I2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
5238 #define I2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
5239 #define I2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
5240 #define I2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
5241 #define I2C_CR1_DNF 0x00000F00U /*!< Digital noise filter */
5242 #define I2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
5243 #define I2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
5244 #define I2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
5245 #define I2C_CR1_SBC 0x00010000U /*!< Slave byte control */
5246 #define I2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
5247 #define I2C_CR1_GCEN 0x00080000U /*!< General call enable */
5248 #define I2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
5249 #define I2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
5250 #define I2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
5251 #define I2C_CR1_PECEN 0x00800000U /*!< PEC enable */
5252
5253
5254 /****************** Bit definition for I2C_CR2 register ********************/
5255 #define I2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
5256 #define I2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
5257 #define I2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
5258 #define I2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
5259 #define I2C_CR2_START 0x00002000U /*!< START generation */
5260 #define I2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
5261 #define I2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
5262 #define I2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
5263 #define I2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
5264 #define I2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
5265 #define I2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
5266
5267 /******************* Bit definition for I2C_OAR1 register ******************/
5268 #define I2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
5269 #define I2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
5270 #define I2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
5271
5272 /******************* Bit definition for I2C_OAR2 register ******************/
5273 #define I2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
5274 #define I2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
5275 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
5276 #define I2C_OAR2_OA2MASK01 0x00000100U /*!< OA2[1] is masked, Only OA2[7:2] are compared */
5277 #define I2C_OAR2_OA2MASK02 0x00000200U /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
5278 #define I2C_OAR2_OA2MASK03 0x00000300U /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
5279 #define I2C_OAR2_OA2MASK04 0x00000400U /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
5280 #define I2C_OAR2_OA2MASK05 0x00000500U /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
5281 #define I2C_OAR2_OA2MASK06 0x00000600U /*!< OA2[6:1] is masked, Only OA2[7] are compared */
5282 #define I2C_OAR2_OA2MASK07 0x00000700U /*!< OA2[7:1] is masked, No comparison is done */
5283 #define I2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
5284
5285 /******************* Bit definition for I2C_TIMINGR register *******************/
5286 #define I2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
5287 #define I2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
5288 #define I2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
5289 #define I2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
5290 #define I2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
5291
5292 /******************* Bit definition for I2C_TIMEOUTR register *******************/
5293 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
5294 #define I2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
5295 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
5296 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
5297 #define I2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
5298
5299 /****************** Bit definition for I2C_ISR register *********************/
5300 #define I2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
5301 #define I2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
5302 #define I2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
5303 #define I2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
5304 #define I2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
5305 #define I2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
5306 #define I2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
5307 #define I2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
5308 #define I2C_ISR_BERR 0x00000100U /*!< Bus error */
5309 #define I2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
5310 #define I2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
5311 #define I2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
5312 #define I2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
5313 #define I2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
5314 #define I2C_ISR_BUSY 0x00008000U /*!< Bus busy */
5315 #define I2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
5316 #define I2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
5317
5318 /****************** Bit definition for I2C_ICR register *********************/
5319 #define I2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
5320 #define I2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
5321 #define I2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
5322 #define I2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
5323 #define I2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
5324 #define I2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
5325 #define I2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
5326 #define I2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
5327 #define I2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
5328
5329 /****************** Bit definition for I2C_PECR register *********************/
5330 #define I2C_PECR_PEC 0x000000FFU /*!< PEC register */
5331
5332 /****************** Bit definition for I2C_RXDR register *********************/
5333 #define I2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
5334
5335 /****************** Bit definition for I2C_TXDR register *********************/
5336 #define I2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
5337
5338
5339 /******************************************************************************/
5340 /* */
5341 /* Independent WATCHDOG */
5342 /* */
5343 /******************************************************************************/
5344 /******************* Bit definition for IWDG_KR register ********************/
5345 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
5346
5347 /******************* Bit definition for IWDG_PR register ********************/
5348 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
5349 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
5350 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
5351 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
5352
5353 /******************* Bit definition for IWDG_RLR register *******************/
5354 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
5355
5356 /******************* Bit definition for IWDG_SR register ********************/
5357 #define IWDG_SR_PVU 0x01U /*!< Watchdog prescaler value update */
5358 #define IWDG_SR_RVU 0x02U /*!< Watchdog counter reload value update */
5359 #define IWDG_SR_WVU 0x04U /*!< Watchdog counter window value update */
5360
5361 /******************* Bit definition for IWDG_KR register ********************/
5362 #define IWDG_WINR_WIN 0x0FFFU /*!< Watchdog counter window value */
5363
5364 /******************************************************************************/
5365 /* */
5366 /* LCD-TFT Display Controller (LTDC) */
5367 /* */
5368 /******************************************************************************/
5369
5370 /******************** Bit definition for LTDC_SSCR register *****************/
5371
5372 #define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
5373 #define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
5374
5375 /******************** Bit definition for LTDC_BPCR register *****************/
5376
5377 #define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
5378 #define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
5379
5380 /******************** Bit definition for LTDC_AWCR register *****************/
5381
5382 #define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
5383 #define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
5384
5385 /******************** Bit definition for LTDC_TWCR register *****************/
5386
5387 #define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
5388 #define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
5389
5390 /******************** Bit definition for LTDC_GCR register ******************/
5391
5392 #define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
5393 #define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
5394 #define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
5395 #define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
5396 #define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
5397 #define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
5398 #define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
5399 #define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
5400 #define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
5401
5402
5403 /******************** Bit definition for LTDC_SRCR register *****************/
5404
5405 #define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
5406 #define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
5407
5408 /******************** Bit definition for LTDC_BCCR register *****************/
5409
5410 #define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
5411 #define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
5412 #define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
5413
5414 /******************** Bit definition for LTDC_IER register ******************/
5415
5416 #define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
5417 #define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
5418 #define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
5419 #define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
5420
5421 /******************** Bit definition for LTDC_ISR register ******************/
5422
5423 #define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
5424 #define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
5425 #define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
5426 #define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
5427
5428 /******************** Bit definition for LTDC_ICR register ******************/
5429
5430 #define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
5431 #define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
5432 #define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
5433 #define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
5434
5435 /******************** Bit definition for LTDC_LIPCR register ****************/
5436
5437 #define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
5438
5439 /******************** Bit definition for LTDC_CPSR register *****************/
5440
5441 #define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
5442 #define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
5443
5444 /******************** Bit definition for LTDC_CDSR register *****************/
5445
5446 #define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
5447 #define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
5448 #define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
5449 #define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
5450
5451 /******************** Bit definition for LTDC_LxCR register *****************/
5452
5453 #define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
5454 #define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
5455 #define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
5456
5457 /******************** Bit definition for LTDC_LxWHPCR register **************/
5458
5459 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
5460 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
5461
5462 /******************** Bit definition for LTDC_LxWVPCR register **************/
5463
5464 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
5465 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
5466
5467 /******************** Bit definition for LTDC_LxCKCR register ***************/
5468
5469 #define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
5470 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
5471 #define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
5472
5473 /******************** Bit definition for LTDC_LxPFCR register ***************/
5474
5475 #define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
5476
5477 /******************** Bit definition for LTDC_LxCACR register ***************/
5478
5479 #define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
5480
5481 /******************** Bit definition for LTDC_LxDCCR register ***************/
5482
5483 #define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
5484 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
5485 #define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
5486 #define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
5487
5488 /******************** Bit definition for LTDC_LxBFCR register ***************/
5489
5490 #define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
5491 #define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
5492
5493 /******************** Bit definition for LTDC_LxCFBAR register **************/
5494
5495 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
5496
5497 /******************** Bit definition for LTDC_LxCFBLR register **************/
5498
5499 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
5500 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
5501
5502 /******************** Bit definition for LTDC_LxCFBLNR register *************/
5503
5504 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
5505
5506 /******************** Bit definition for LTDC_LxCLUTWR register *************/
5507
5508 #define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
5509 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
5510 #define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
5511 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
5512
5513 /******************************************************************************/
5514 /* */
5515 /* Power Control */
5516 /* */
5517 /******************************************************************************/
5518 /******************** Bit definition for PWR_CR1 register ********************/
5519 #define PWR_CR1_LPDS 0x00000001U /*!< Low-Power Deepsleep */
5520 #define PWR_CR1_PDDS 0x00000002U /*!< Power Down Deepsleep */
5521 #define PWR_CR1_CSBF 0x00000008U /*!< Clear Standby Flag */
5522 #define PWR_CR1_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
5523 #define PWR_CR1_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
5524 #define PWR_CR1_PLS_0 0x00000020U /*!< Bit 0 */
5525 #define PWR_CR1_PLS_1 0x00000040U /*!< Bit 1 */
5526 #define PWR_CR1_PLS_2 0x00000080U /*!< Bit 2 */
5527
5528 /*!< PVD level configuration */
5529 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
5530 #define PWR_CR1_PLS_LEV1 0x00000020U /*!< PVD level 1 */
5531 #define PWR_CR1_PLS_LEV2 0x00000040U /*!< PVD level 2 */
5532 #define PWR_CR1_PLS_LEV3 0x00000060U /*!< PVD level 3 */
5533 #define PWR_CR1_PLS_LEV4 0x00000080U /*!< PVD level 4 */
5534 #define PWR_CR1_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
5535 #define PWR_CR1_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
5536 #define PWR_CR1_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
5537 #define PWR_CR1_DBP 0x00000100U /*!< Disable Backup Domain write protection */
5538 #define PWR_CR1_FPDS 0x00000200U /*!< Flash power down in Stop mode */
5539 #define PWR_CR1_LPUDS 0x00000400U /*!< Low-power regulator in deepsleep under-drive mode */
5540 #define PWR_CR1_MRUDS 0x00000800U /*!< Main regulator in deepsleep under-drive mode */
5541 #define PWR_CR1_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
5542 #define PWR_CR1_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
5543 #define PWR_CR1_VOS_0 0x00004000U /*!< Bit 0 */
5544 #define PWR_CR1_VOS_1 0x00008000U /*!< Bit 1 */
5545 #define PWR_CR1_ODEN 0x00010000U /*!< Over Drive enable */
5546 #define PWR_CR1_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
5547 #define PWR_CR1_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
5548 #define PWR_CR1_UDEN_0 0x00040000U /*!< Bit 0 */
5549 #define PWR_CR1_UDEN_1 0x00080000U /*!< Bit 1 */
5550
5551 /******************* Bit definition for PWR_CSR1 register ********************/
5552 #define PWR_CSR1_WUIF 0x00000001U /*!< Wake up internal Flag */
5553 #define PWR_CSR1_SBF 0x00000002U /*!< Standby Flag */
5554 #define PWR_CSR1_PVDO 0x00000004U /*!< PVD Output */
5555 #define PWR_CSR1_BRR 0x00000008U /*!< Backup regulator ready */
5556 #define PWR_CSR1_EIWUP 0x00000100U /*!< Enable internal wakeup */
5557 #define PWR_CSR1_BRE 0x00000200U /*!< Backup regulator enable */
5558 #define PWR_CSR1_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
5559 #define PWR_CSR1_ODRDY 0x00010000U /*!< Over Drive generator ready */
5560 #define PWR_CSR1_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
5561 #define PWR_CSR1_UDRDY 0x000C0000U /*!< Under Drive ready */
5562
5563
5564 /******************** Bit definition for PWR_CR2 register ********************/
5565 #define PWR_CR2_CWUPF1 0x00000001U /*!< Clear Wakeup Pin Flag for PA0 */
5566 #define PWR_CR2_CWUPF2 0x00000002U /*!< Clear Wakeup Pin Flag for PA2 */
5567 #define PWR_CR2_CWUPF3 0x00000004U /*!< Clear Wakeup Pin Flag for PC1 */
5568 #define PWR_CR2_CWUPF4 0x00000008U /*!< Clear Wakeup Pin Flag for PC13 */
5569 #define PWR_CR2_CWUPF5 0x00000010U /*!< Clear Wakeup Pin Flag for PI8 */
5570 #define PWR_CR2_CWUPF6 0x00000020U /*!< Clear Wakeup Pin Flag for PI11 */
5571 #define PWR_CR2_WUPP1 0x00000100U /*!< Wakeup Pin Polarity bit for PA0 */
5572 #define PWR_CR2_WUPP2 0x00000200U /*!< Wakeup Pin Polarity bit for PA2 */
5573 #define PWR_CR2_WUPP3 0x00000400U /*!< Wakeup Pin Polarity bit for PC1 */
5574 #define PWR_CR2_WUPP4 0x00000800U /*!< Wakeup Pin Polarity bit for PC13 */
5575 #define PWR_CR2_WUPP5 0x00001000U /*!< Wakeup Pin Polarity bit for PI8 */
5576 #define PWR_CR2_WUPP6 0x00002000U /*!< Wakeup Pin Polarity bit for PI11 */
5577
5578 /******************* Bit definition for PWR_CSR2 register ********************/
5579 #define PWR_CSR2_WUPF1 0x00000001U /*!< Wakeup Pin Flag for PA0 */
5580 #define PWR_CSR2_WUPF2 0x00000002U /*!< Wakeup Pin Flag for PA2 */
5581 #define PWR_CSR2_WUPF3 0x00000004U /*!< Wakeup Pin Flag for PC1 */
5582 #define PWR_CSR2_WUPF4 0x00000008U /*!< Wakeup Pin Flag for PC13 */
5583 #define PWR_CSR2_WUPF5 0x00000010U /*!< Wakeup Pin Flag for PI8 */
5584 #define PWR_CSR2_WUPF6 0x00000020U /*!< Wakeup Pin Flag for PI11 */
5585 #define PWR_CSR2_EWUP1 0x00000100U /*!< Enable Wakeup Pin PA0 */
5586 #define PWR_CSR2_EWUP2 0x00000200U /*!< Enable Wakeup Pin PA2 */
5587 #define PWR_CSR2_EWUP3 0x00000400U /*!< Enable Wakeup Pin PC1 */
5588 #define PWR_CSR2_EWUP4 0x00000800U /*!< Enable Wakeup Pin PC13 */
5589 #define PWR_CSR2_EWUP5 0x00001000U /*!< Enable Wakeup Pin PI8 */
5590 #define PWR_CSR2_EWUP6 0x00002000U /*!< Enable Wakeup Pin PI11 */
5591
5592 /******************************************************************************/
5593 /* */
5594 /* QUADSPI */
5595 /* */
5596 /******************************************************************************/
5597 /***************** Bit definition for QUADSPI_CR register *******************/
5598 #define QUADSPI_CR_EN 0x00000001U /*!< Enable */
5599 #define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
5600 #define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
5601 #define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
5602 #define QUADSPI_CR_SSHIFT 0x00000010U /*!< Sample Shift */
5603 #define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
5604 #define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
5605 #define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[4:0] FIFO Level */
5606 #define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
5607 #define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
5608 #define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
5609 #define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
5610 #define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
5611 #define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
5612 #define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
5613 #define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
5614 #define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
5615 #define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
5616 #define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
5617 #define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
5618 #define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
5619 #define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
5620 #define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
5621 #define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
5622 #define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
5623 #define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
5624 #define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
5625 #define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
5626 #define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
5627
5628 /***************** Bit definition for QUADSPI_DCR register ******************/
5629 #define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
5630 #define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
5631 #define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
5632 #define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
5633 #define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
5634 #define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
5635 #define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
5636 #define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
5637 #define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
5638 #define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
5639 #define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
5640
5641 /****************** Bit definition for QUADSPI_SR register *******************/
5642 #define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
5643 #define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
5644 #define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
5645 #define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
5646 #define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
5647 #define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
5648 #define QUADSPI_SR_FLEVEL 0x00001F00U /*!< FIFO Threshlod Flag */
5649 #define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
5650 #define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
5651 #define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
5652 #define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
5653 #define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
5654
5655 /****************** Bit definition for QUADSPI_FCR register ******************/
5656 #define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
5657 #define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
5658 #define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
5659 #define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
5660
5661 /****************** Bit definition for QUADSPI_DLR register ******************/
5662 #define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
5663
5664 /****************** Bit definition for QUADSPI_CCR register ******************/
5665 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
5666 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
5667 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
5668 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
5669 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
5670 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
5671 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
5672 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
5673 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
5674 #define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
5675 #define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
5676 #define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
5677 #define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
5678 #define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
5679 #define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
5680 #define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
5681 #define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
5682 #define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
5683 #define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
5684 #define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
5685 #define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
5686 #define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
5687 #define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
5688 #define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
5689 #define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
5690 #define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
5691 #define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
5692 #define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
5693 #define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
5694 #define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
5695 #define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
5696 #define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
5697 #define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
5698 #define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
5699 #define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
5700 #define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
5701 #define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
5702 #define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
5703 #define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
5704 /****************** Bit definition for QUADSPI_AR register *******************/
5705 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
5706
5707 /****************** Bit definition for QUADSPI_ABR register ******************/
5708 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
5709
5710 /****************** Bit definition for QUADSPI_DR register *******************/
5711 #define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
5712
5713 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5714 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
5715
5716 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5717 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
5718
5719 /****************** Bit definition for QUADSPI_PIR register *****************/
5720 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
5721
5722 /****************** Bit definition for QUADSPI_LPTR register *****************/
5723 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
5724
5725 /******************************************************************************/
5726 /* */
5727 /* Reset and Clock Control */
5728 /* */
5729 /******************************************************************************/
5730 /******************** Bit definition for RCC_CR register ********************/
5731 #define RCC_CR_HSION 0x00000001U
5732 #define RCC_CR_HSIRDY 0x00000002U
5733 #define RCC_CR_HSITRIM 0x000000F8U
5734 #define RCC_CR_HSITRIM_0 0x00000008U /*!<Bit 0 */
5735 #define RCC_CR_HSITRIM_1 0x00000010U /*!<Bit 1 */
5736 #define RCC_CR_HSITRIM_2 0x00000020U /*!<Bit 2 */
5737 #define RCC_CR_HSITRIM_3 0x00000040U /*!<Bit 3 */
5738 #define RCC_CR_HSITRIM_4 0x00000080U /*!<Bit 4 */
5739 #define RCC_CR_HSICAL 0x0000FF00U
5740 #define RCC_CR_HSICAL_0 0x00000100U /*!<Bit 0 */
5741 #define RCC_CR_HSICAL_1 0x00000200U /*!<Bit 1 */
5742 #define RCC_CR_HSICAL_2 0x00000400U /*!<Bit 2 */
5743 #define RCC_CR_HSICAL_3 0x00000800U /*!<Bit 3 */
5744 #define RCC_CR_HSICAL_4 0x00001000U /*!<Bit 4 */
5745 #define RCC_CR_HSICAL_5 0x00002000U /*!<Bit 5 */
5746 #define RCC_CR_HSICAL_6 0x00004000U /*!<Bit 6 */
5747 #define RCC_CR_HSICAL_7 0x00008000U /*!<Bit 7 */
5748 #define RCC_CR_HSEON 0x00010000U
5749 #define RCC_CR_HSERDY 0x00020000U
5750 #define RCC_CR_HSEBYP 0x00040000U
5751 #define RCC_CR_CSSON 0x00080000U
5752 #define RCC_CR_PLLON 0x01000000U
5753 #define RCC_CR_PLLRDY 0x02000000U
5754 #define RCC_CR_PLLI2SON 0x04000000U
5755 #define RCC_CR_PLLI2SRDY 0x08000000U
5756 #define RCC_CR_PLLSAION 0x10000000U
5757 #define RCC_CR_PLLSAIRDY 0x20000000U
5758
5759 /******************** Bit definition for RCC_PLLCFGR register ***************/
5760 #define RCC_PLLCFGR_PLLM 0x0000003FU
5761 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5762 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5763 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5764 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5765 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5766 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5767 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5768 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5769 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5770 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5771 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5772 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5773 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5774 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5775 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5776 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5777 #define RCC_PLLCFGR_PLLP 0x00030000U
5778 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5779 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5780 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5781 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5782 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5783 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5784 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5785 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5786 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5787 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5788
5789 #define RCC_PLLCFGR_PLLR 0x70000000U
5790 #define RCC_PLLCFGR_PLLR_0 0x10000000U
5791 #define RCC_PLLCFGR_PLLR_1 0x20000000U
5792 #define RCC_PLLCFGR_PLLR_2 0x40000000U
5793
5794 /******************** Bit definition for RCC_CFGR register ******************/
5795 /*!< SW configuration */
5796 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
5797 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
5798 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
5799 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
5800 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
5801 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
5802
5803 /*!< SWS configuration */
5804 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
5805 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
5806 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
5807 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
5808 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
5809 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
5810
5811 /*!< HPRE configuration */
5812 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
5813 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
5814 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
5815 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
5816 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
5817
5818 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
5819 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
5820 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
5821 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
5822 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
5823 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
5824 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
5825 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
5826 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
5827
5828 /*!< PPRE1 configuration */
5829 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
5830 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
5831 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
5832 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
5833
5834 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
5835 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
5836 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
5837 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
5838 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
5839
5840 /*!< PPRE2 configuration */
5841 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
5842 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
5843 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
5844 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
5845
5846 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
5847 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
5848 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
5849 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
5850 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
5851
5852 /*!< RTCPRE configuration */
5853 #define RCC_CFGR_RTCPRE 0x001F0000U
5854 #define RCC_CFGR_RTCPRE_0 0x00010000U
5855 #define RCC_CFGR_RTCPRE_1 0x00020000U
5856 #define RCC_CFGR_RTCPRE_2 0x00040000U
5857 #define RCC_CFGR_RTCPRE_3 0x00080000U
5858 #define RCC_CFGR_RTCPRE_4 0x00100000U
5859
5860 /*!< MCO1 configuration */
5861 #define RCC_CFGR_MCO1 0x00600000U
5862 #define RCC_CFGR_MCO1_0 0x00200000U
5863 #define RCC_CFGR_MCO1_1 0x00400000U
5864
5865 #define RCC_CFGR_I2SSRC 0x00800000U
5866
5867 #define RCC_CFGR_MCO1PRE 0x07000000U
5868 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5869 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5870 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5871
5872 #define RCC_CFGR_MCO2PRE 0x38000000U
5873 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5874 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5875 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5876
5877 #define RCC_CFGR_MCO2 0xC0000000U
5878 #define RCC_CFGR_MCO2_0 0x40000000U
5879 #define RCC_CFGR_MCO2_1 0x80000000U
5880
5881 /******************** Bit definition for RCC_CIR register *******************/
5882 #define RCC_CIR_LSIRDYF 0x00000001U
5883 #define RCC_CIR_LSERDYF 0x00000002U
5884 #define RCC_CIR_HSIRDYF 0x00000004U
5885 #define RCC_CIR_HSERDYF 0x00000008U
5886 #define RCC_CIR_PLLRDYF 0x00000010U
5887 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5888 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5889 #define RCC_CIR_CSSF 0x00000080U
5890 #define RCC_CIR_LSIRDYIE 0x00000100U
5891 #define RCC_CIR_LSERDYIE 0x00000200U
5892 #define RCC_CIR_HSIRDYIE 0x00000400U
5893 #define RCC_CIR_HSERDYIE 0x00000800U
5894 #define RCC_CIR_PLLRDYIE 0x00001000U
5895 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5896 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5897 #define RCC_CIR_LSIRDYC 0x00010000U
5898 #define RCC_CIR_LSERDYC 0x00020000U
5899 #define RCC_CIR_HSIRDYC 0x00040000U
5900 #define RCC_CIR_HSERDYC 0x00080000U
5901 #define RCC_CIR_PLLRDYC 0x00100000U
5902 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5903 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5904 #define RCC_CIR_CSSC 0x00800000U
5905
5906 /******************** Bit definition for RCC_AHB1RSTR register **************/
5907 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5908 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5909 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5910 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5911 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5912 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5913 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5914 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5915 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5916 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5917 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5918 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5919 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5920 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5921 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5922 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5923 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5924
5925 /******************** Bit definition for RCC_AHB2RSTR register **************/
5926 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5927 #define RCC_AHB2RSTR_JPEGRST 0x00000002U
5928 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5929 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5930
5931 /******************** Bit definition for RCC_AHB3RSTR register **************/
5932
5933 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5934 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
5935
5936 /******************** Bit definition for RCC_APB1RSTR register **************/
5937 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5938 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5939 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5940 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5941 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5942 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5943 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5944 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5945 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5946 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
5947 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5948 #define RCC_APB1RSTR_CAN3RST 0x00002000U
5949 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5950 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5951 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
5952 #define RCC_APB1RSTR_USART2RST 0x00020000U
5953 #define RCC_APB1RSTR_USART3RST 0x00040000U
5954 #define RCC_APB1RSTR_UART4RST 0x00080000U
5955 #define RCC_APB1RSTR_UART5RST 0x00100000U
5956 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5957 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5958 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5959 #define RCC_APB1RSTR_I2C4RST 0x01000000U
5960 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5961 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5962 #define RCC_APB1RSTR_CECRST 0x08000000U
5963 #define RCC_APB1RSTR_PWRRST 0x10000000U
5964 #define RCC_APB1RSTR_DACRST 0x20000000U
5965 #define RCC_APB1RSTR_UART7RST 0x40000000U
5966 #define RCC_APB1RSTR_UART8RST 0x80000000U
5967
5968 /******************** Bit definition for RCC_APB2RSTR register **************/
5969 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5970 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5971 #define RCC_APB2RSTR_USART1RST 0x00000010U
5972 #define RCC_APB2RSTR_USART6RST 0x00000020U
5973 #define RCC_APB2RSTR_SDMMC2RST 0x00000080U
5974 #define RCC_APB2RSTR_ADCRST 0x00000100U
5975 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
5976 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5977 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5978 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5979 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5980 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5981 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5982 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5983 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5984 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5985 #define RCC_APB2RSTR_SAI2RST 0x00800000U
5986 #define RCC_APB2RSTR_LTDCRST 0x04000000U
5987 #define RCC_APB2RSTR_DFSDM1RST 0x20000000U
5988 #define RCC_APB2RSTR_MDIORST 0x40000000U
5989
5990 /******************** Bit definition for RCC_AHB1ENR register ***************/
5991 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5992 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5993 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5994 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5995 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5996 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5997 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5998 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5999 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
6000 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
6001 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
6002 #define RCC_AHB1ENR_CRCEN 0x00001000U
6003 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
6004 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
6005 #define RCC_AHB1ENR_DMA1EN 0x00200000U
6006 #define RCC_AHB1ENR_DMA2EN 0x00400000U
6007 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
6008 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
6009 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
6010 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
6011 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
6012 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
6013 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
6014
6015 /******************** Bit definition for RCC_AHB2ENR register ***************/
6016 #define RCC_AHB2ENR_DCMIEN 0x00000001U
6017 #define RCC_AHB2ENR_JPEGEN 0x00000002U
6018 #define RCC_AHB2ENR_RNGEN 0x00000040U
6019 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
6020
6021 /******************** Bit definition for RCC_AHB3ENR register ***************/
6022 #define RCC_AHB3ENR_FMCEN 0x00000001U
6023 #define RCC_AHB3ENR_QSPIEN 0x00000002U
6024
6025 /******************** Bit definition for RCC_APB1ENR register ***************/
6026 #define RCC_APB1ENR_TIM2EN 0x00000001U
6027 #define RCC_APB1ENR_TIM3EN 0x00000002U
6028 #define RCC_APB1ENR_TIM4EN 0x00000004U
6029 #define RCC_APB1ENR_TIM5EN 0x00000008U
6030 #define RCC_APB1ENR_TIM6EN 0x00000010U
6031 #define RCC_APB1ENR_TIM7EN 0x00000020U
6032 #define RCC_APB1ENR_TIM12EN 0x00000040U
6033 #define RCC_APB1ENR_TIM13EN 0x00000080U
6034 #define RCC_APB1ENR_TIM14EN 0x00000100U
6035 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
6036 #define RCC_APB1ENR_RTCEN 0x00000400U
6037 #define RCC_APB1ENR_WWDGEN 0x00000800U
6038 #define RCC_APB1ENR_CAN3EN 0x00002000U
6039 #define RCC_APB1ENR_SPI2EN 0x00004000U
6040 #define RCC_APB1ENR_SPI3EN 0x00008000U
6041 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
6042 #define RCC_APB1ENR_USART2EN 0x00020000U
6043 #define RCC_APB1ENR_USART3EN 0x00040000U
6044 #define RCC_APB1ENR_UART4EN 0x00080000U
6045 #define RCC_APB1ENR_UART5EN 0x00100000U
6046 #define RCC_APB1ENR_I2C1EN 0x00200000U
6047 #define RCC_APB1ENR_I2C2EN 0x00400000U
6048 #define RCC_APB1ENR_I2C3EN 0x00800000U
6049 #define RCC_APB1ENR_I2C4EN 0x01000000U
6050 #define RCC_APB1ENR_CAN1EN 0x02000000U
6051 #define RCC_APB1ENR_CAN2EN 0x04000000U
6052 #define RCC_APB1ENR_CECEN 0x08000000U
6053 #define RCC_APB1ENR_PWREN 0x10000000U
6054 #define RCC_APB1ENR_DACEN 0x20000000U
6055 #define RCC_APB1ENR_UART7EN 0x40000000U
6056 #define RCC_APB1ENR_UART8EN 0x80000000U
6057
6058 /******************** Bit definition for RCC_APB2ENR register ***************/
6059 #define RCC_APB2ENR_TIM1EN 0x00000001U
6060 #define RCC_APB2ENR_TIM8EN 0x00000002U
6061 #define RCC_APB2ENR_USART1EN 0x00000010U
6062 #define RCC_APB2ENR_USART6EN 0x00000020U
6063 #define RCC_APB2ENR_SDMMC2EN 0x00000080U
6064 #define RCC_APB2ENR_ADC1EN 0x00000100U
6065 #define RCC_APB2ENR_ADC2EN 0x00000200U
6066 #define RCC_APB2ENR_ADC3EN 0x00000400U
6067 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
6068 #define RCC_APB2ENR_SPI1EN 0x00001000U
6069 #define RCC_APB2ENR_SPI4EN 0x00002000U
6070 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
6071 #define RCC_APB2ENR_TIM9EN 0x00010000U
6072 #define RCC_APB2ENR_TIM10EN 0x00020000U
6073 #define RCC_APB2ENR_TIM11EN 0x00040000U
6074 #define RCC_APB2ENR_SPI5EN 0x00100000U
6075 #define RCC_APB2ENR_SPI6EN 0x00200000U
6076 #define RCC_APB2ENR_SAI1EN 0x00400000U
6077 #define RCC_APB2ENR_SAI2EN 0x00800000U
6078 #define RCC_APB2ENR_LTDCEN 0x04000000U
6079 #define RCC_APB2ENR_DFSDM1EN 0x20000000U
6080 #define RCC_APB2ENR_MDIOEN 0x40000000U
6081
6082 /******************** Bit definition for RCC_AHB1LPENR register *************/
6083 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
6084 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
6085 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
6086 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
6087 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
6088 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
6089 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
6090 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
6091 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
6092 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
6093 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
6094 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
6095 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
6096 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
6097 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
6098 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
6099 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
6100 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
6101 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
6102 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
6103 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
6104 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
6105 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
6106 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
6107 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
6108 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
6109 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
6110
6111 /******************** Bit definition for RCC_AHB2LPENR register *************/
6112 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
6113 #define RCC_AHB2LPENR_JPEGLPEN 0x00000002U
6114 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
6115 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
6116
6117 /******************** Bit definition for RCC_AHB3LPENR register *************/
6118 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
6119 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
6120 /******************** Bit definition for RCC_APB1LPENR register *************/
6121 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
6122 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
6123 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
6124 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
6125 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
6126 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
6127 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
6128 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
6129 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
6130 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
6131 #define RCC_APB1LPENR_RTCLPEN 0x00000400U
6132 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
6133 #define RCC_APB1LPENR_CAN3LPEN 0x00002000U
6134 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
6135 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
6136 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
6137 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
6138 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
6139 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
6140 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
6141 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
6142 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
6143 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
6144 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
6145 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
6146 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
6147 #define RCC_APB1LPENR_CECLPEN 0x08000000U
6148 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
6149 #define RCC_APB1LPENR_DACLPEN 0x20000000U
6150 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
6151 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
6152
6153 /******************** Bit definition for RCC_APB2LPENR register *************/
6154 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
6155 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
6156 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
6157 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
6158 #define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U
6159 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
6160 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
6161 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
6162 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
6163 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
6164 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
6165 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
6166 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
6167 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
6168 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
6169 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
6170 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
6171 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
6172 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
6173 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
6174 #define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U
6175 #define RCC_APB2LPENR_MDIOLPEN 0x40000000U
6176
6177 /******************** Bit definition for RCC_BDCR register ******************/
6178 #define RCC_BDCR_LSEON 0x00000001U
6179 #define RCC_BDCR_LSERDY 0x00000002U
6180 #define RCC_BDCR_LSEBYP 0x00000004U
6181 #define RCC_BDCR_LSEDRV 0x00000018U
6182 #define RCC_BDCR_LSEDRV_0 0x00000008U
6183 #define RCC_BDCR_LSEDRV_1 0x00000010U
6184 #define RCC_BDCR_RTCSEL 0x00000300U
6185 #define RCC_BDCR_RTCSEL_0 0x00000100U
6186 #define RCC_BDCR_RTCSEL_1 0x00000200U
6187 #define RCC_BDCR_RTCEN 0x00008000U
6188 #define RCC_BDCR_BDRST 0x00010000U
6189
6190 /******************** Bit definition for RCC_CSR register *******************/
6191 #define RCC_CSR_LSION 0x00000001U
6192 #define RCC_CSR_LSIRDY 0x00000002U
6193 #define RCC_CSR_RMVF 0x01000000U
6194 #define RCC_CSR_BORRSTF 0x02000000U
6195 #define RCC_CSR_PINRSTF 0x04000000U
6196 #define RCC_CSR_PORRSTF 0x08000000U
6197 #define RCC_CSR_SFTRSTF 0x10000000U
6198 #define RCC_CSR_IWDGRSTF 0x20000000U
6199 #define RCC_CSR_WWDGRSTF 0x40000000U
6200 #define RCC_CSR_LPWRRSTF 0x80000000U
6201
6202 /******************** Bit definition for RCC_SSCGR register *****************/
6203 #define RCC_SSCGR_MODPER 0x00001FFFU
6204 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
6205 #define RCC_SSCGR_SPREADSEL 0x40000000U
6206 #define RCC_SSCGR_SSCGEN 0x80000000U
6207
6208 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
6209 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
6210 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
6211 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
6212 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
6213 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
6214 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
6215 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
6216 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
6217 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
6218 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
6219 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
6220 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
6221 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
6222 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
6223 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
6224 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
6225 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
6226 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
6227 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
6228 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
6229 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
6230 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
6231
6232 /******************** Bit definition for RCC_PLLSAICFGR register ************/
6233 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
6234 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
6235 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
6236 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
6237 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
6238 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
6239 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
6240 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
6241 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
6242 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
6243 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
6244 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
6245 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
6246 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
6247 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
6248 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
6249 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
6250 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
6251 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
6252 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
6253 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
6254 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
6255
6256 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
6257 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
6258 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
6259 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
6260 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
6261 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
6262 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
6263
6264 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
6265 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
6266 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
6267 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
6268 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
6269 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
6270
6271 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
6272 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
6273 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
6274
6275 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
6276 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
6277 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
6278
6279 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
6280 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
6281 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
6282
6283 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
6284 #define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U
6285 #define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U
6286
6287 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
6288 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
6289 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
6290 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
6291 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
6292 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
6293 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
6294 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
6295 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
6296 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
6297 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
6298 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
6299 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
6300 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
6301 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
6302 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
6303 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
6304 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
6305 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
6306 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
6307 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
6308 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
6309 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
6310 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
6311 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
6312 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
6313 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
6314 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
6315 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
6316 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
6317 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
6318 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
6319 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
6320 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
6321 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
6322 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
6323 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
6324 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
6325 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
6326 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
6327 #define RCC_DCKCFGR2_CECSEL 0x04000000U
6328 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
6329 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
6330 #define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U
6331
6332 /******************************************************************************/
6333 /* */
6334 /* RNG */
6335 /* */
6336 /******************************************************************************/
6337 /******************** Bits definition for RNG_CR register *******************/
6338 #define RNG_CR_RNGEN 0x00000004U
6339 #define RNG_CR_IE 0x00000008U
6340
6341 /******************** Bits definition for RNG_SR register *******************/
6342 #define RNG_SR_DRDY 0x00000001U
6343 #define RNG_SR_CECS 0x00000002U
6344 #define RNG_SR_SECS 0x00000004U
6345 #define RNG_SR_CEIS 0x00000020U
6346 #define RNG_SR_SEIS 0x00000040U
6347
6348 /******************************************************************************/
6349 /* */
6350 /* Real-Time Clock (RTC) */
6351 /* */
6352 /******************************************************************************/
6353 /******************** Bits definition for RTC_TR register *******************/
6354 #define RTC_TR_PM 0x00400000U
6355 #define RTC_TR_HT 0x00300000U
6356 #define RTC_TR_HT_0 0x00100000U
6357 #define RTC_TR_HT_1 0x00200000U
6358 #define RTC_TR_HU 0x000F0000U
6359 #define RTC_TR_HU_0 0x00010000U
6360 #define RTC_TR_HU_1 0x00020000U
6361 #define RTC_TR_HU_2 0x00040000U
6362 #define RTC_TR_HU_3 0x00080000U
6363 #define RTC_TR_MNT 0x00007000U
6364 #define RTC_TR_MNT_0 0x00001000U
6365 #define RTC_TR_MNT_1 0x00002000U
6366 #define RTC_TR_MNT_2 0x00004000U
6367 #define RTC_TR_MNU 0x00000F00U
6368 #define RTC_TR_MNU_0 0x00000100U
6369 #define RTC_TR_MNU_1 0x00000200U
6370 #define RTC_TR_MNU_2 0x00000400U
6371 #define RTC_TR_MNU_3 0x00000800U
6372 #define RTC_TR_ST 0x00000070U
6373 #define RTC_TR_ST_0 0x00000010U
6374 #define RTC_TR_ST_1 0x00000020U
6375 #define RTC_TR_ST_2 0x00000040U
6376 #define RTC_TR_SU 0x0000000FU
6377 #define RTC_TR_SU_0 0x00000001U
6378 #define RTC_TR_SU_1 0x00000002U
6379 #define RTC_TR_SU_2 0x00000004U
6380 #define RTC_TR_SU_3 0x00000008U
6381
6382 /******************** Bits definition for RTC_DR register *******************/
6383 #define RTC_DR_YT 0x00F00000U
6384 #define RTC_DR_YT_0 0x00100000U
6385 #define RTC_DR_YT_1 0x00200000U
6386 #define RTC_DR_YT_2 0x00400000U
6387 #define RTC_DR_YT_3 0x00800000U
6388 #define RTC_DR_YU 0x000F0000U
6389 #define RTC_DR_YU_0 0x00010000U
6390 #define RTC_DR_YU_1 0x00020000U
6391 #define RTC_DR_YU_2 0x00040000U
6392 #define RTC_DR_YU_3 0x00080000U
6393 #define RTC_DR_WDU 0x0000E000U
6394 #define RTC_DR_WDU_0 0x00002000U
6395 #define RTC_DR_WDU_1 0x00004000U
6396 #define RTC_DR_WDU_2 0x00008000U
6397 #define RTC_DR_MT 0x00001000U
6398 #define RTC_DR_MU 0x00000F00U
6399 #define RTC_DR_MU_0 0x00000100U
6400 #define RTC_DR_MU_1 0x00000200U
6401 #define RTC_DR_MU_2 0x00000400U
6402 #define RTC_DR_MU_3 0x00000800U
6403 #define RTC_DR_DT 0x00000030U
6404 #define RTC_DR_DT_0 0x00000010U
6405 #define RTC_DR_DT_1 0x00000020U
6406 #define RTC_DR_DU 0x0000000FU
6407 #define RTC_DR_DU_0 0x00000001U
6408 #define RTC_DR_DU_1 0x00000002U
6409 #define RTC_DR_DU_2 0x00000004U
6410 #define RTC_DR_DU_3 0x00000008U
6411
6412 /******************** Bits definition for RTC_CR register *******************/
6413 #define RTC_CR_ITSE 0x01000000U
6414 #define RTC_CR_COE 0x00800000U
6415 #define RTC_CR_OSEL 0x00600000U
6416 #define RTC_CR_OSEL_0 0x00200000U
6417 #define RTC_CR_OSEL_1 0x00400000U
6418 #define RTC_CR_POL 0x00100000U
6419 #define RTC_CR_COSEL 0x00080000U
6420 #define RTC_CR_BCK 0x00040000U
6421 #define RTC_CR_SUB1H 0x00020000U
6422 #define RTC_CR_ADD1H 0x00010000U
6423 #define RTC_CR_TSIE 0x00008000U
6424 #define RTC_CR_WUTIE 0x00004000U
6425 #define RTC_CR_ALRBIE 0x00002000U
6426 #define RTC_CR_ALRAIE 0x00001000U
6427 #define RTC_CR_TSE 0x00000800U
6428 #define RTC_CR_WUTE 0x00000400U
6429 #define RTC_CR_ALRBE 0x00000200U
6430 #define RTC_CR_ALRAE 0x00000100U
6431 #define RTC_CR_FMT 0x00000040U
6432 #define RTC_CR_BYPSHAD 0x00000020U
6433 #define RTC_CR_REFCKON 0x00000010U
6434 #define RTC_CR_TSEDGE 0x00000008U
6435 #define RTC_CR_WUCKSEL 0x00000007U
6436 #define RTC_CR_WUCKSEL_0 0x00000001U
6437 #define RTC_CR_WUCKSEL_1 0x00000002U
6438 #define RTC_CR_WUCKSEL_2 0x00000004U
6439
6440 /******************** Bits definition for RTC_ISR register ******************/
6441 #define RTC_ISR_ITSF 0x00020000U
6442 #define RTC_ISR_RECALPF 0x00010000U
6443 #define RTC_ISR_TAMP3F 0x00008000U
6444 #define RTC_ISR_TAMP2F 0x00004000U
6445 #define RTC_ISR_TAMP1F 0x00002000U
6446 #define RTC_ISR_TSOVF 0x00001000U
6447 #define RTC_ISR_TSF 0x00000800U
6448 #define RTC_ISR_WUTF 0x00000400U
6449 #define RTC_ISR_ALRBF 0x00000200U
6450 #define RTC_ISR_ALRAF 0x00000100U
6451 #define RTC_ISR_INIT 0x00000080U
6452 #define RTC_ISR_INITF 0x00000040U
6453 #define RTC_ISR_RSF 0x00000020U
6454 #define RTC_ISR_INITS 0x00000010U
6455 #define RTC_ISR_SHPF 0x00000008U
6456 #define RTC_ISR_WUTWF 0x00000004U
6457 #define RTC_ISR_ALRBWF 0x00000002U
6458 #define RTC_ISR_ALRAWF 0x00000001U
6459
6460 /******************** Bits definition for RTC_PRER register *****************/
6461 #define RTC_PRER_PREDIV_A 0x007F0000U
6462 #define RTC_PRER_PREDIV_S 0x00007FFFU
6463
6464 /******************** Bits definition for RTC_WUTR register *****************/
6465 #define RTC_WUTR_WUT 0x0000FFFFU
6466
6467 /******************** Bits definition for RTC_ALRMAR register ***************/
6468 #define RTC_ALRMAR_MSK4 0x80000000U
6469 #define RTC_ALRMAR_WDSEL 0x40000000U
6470 #define RTC_ALRMAR_DT 0x30000000U
6471 #define RTC_ALRMAR_DT_0 0x10000000U
6472 #define RTC_ALRMAR_DT_1 0x20000000U
6473 #define RTC_ALRMAR_DU 0x0F000000U
6474 #define RTC_ALRMAR_DU_0 0x01000000U
6475 #define RTC_ALRMAR_DU_1 0x02000000U
6476 #define RTC_ALRMAR_DU_2 0x04000000U
6477 #define RTC_ALRMAR_DU_3 0x08000000U
6478 #define RTC_ALRMAR_MSK3 0x00800000U
6479 #define RTC_ALRMAR_PM 0x00400000U
6480 #define RTC_ALRMAR_HT 0x00300000U
6481 #define RTC_ALRMAR_HT_0 0x00100000U
6482 #define RTC_ALRMAR_HT_1 0x00200000U
6483 #define RTC_ALRMAR_HU 0x000F0000U
6484 #define RTC_ALRMAR_HU_0 0x00010000U
6485 #define RTC_ALRMAR_HU_1 0x00020000U
6486 #define RTC_ALRMAR_HU_2 0x00040000U
6487 #define RTC_ALRMAR_HU_3 0x00080000U
6488 #define RTC_ALRMAR_MSK2 0x00008000U
6489 #define RTC_ALRMAR_MNT 0x00007000U
6490 #define RTC_ALRMAR_MNT_0 0x00001000U
6491 #define RTC_ALRMAR_MNT_1 0x00002000U
6492 #define RTC_ALRMAR_MNT_2 0x00004000U
6493 #define RTC_ALRMAR_MNU 0x00000F00U
6494 #define RTC_ALRMAR_MNU_0 0x00000100U
6495 #define RTC_ALRMAR_MNU_1 0x00000200U
6496 #define RTC_ALRMAR_MNU_2 0x00000400U
6497 #define RTC_ALRMAR_MNU_3 0x00000800U
6498 #define RTC_ALRMAR_MSK1 0x00000080U
6499 #define RTC_ALRMAR_ST 0x00000070U
6500 #define RTC_ALRMAR_ST_0 0x00000010U
6501 #define RTC_ALRMAR_ST_1 0x00000020U
6502 #define RTC_ALRMAR_ST_2 0x00000040U
6503 #define RTC_ALRMAR_SU 0x0000000FU
6504 #define RTC_ALRMAR_SU_0 0x00000001U
6505 #define RTC_ALRMAR_SU_1 0x00000002U
6506 #define RTC_ALRMAR_SU_2 0x00000004U
6507 #define RTC_ALRMAR_SU_3 0x00000008U
6508
6509 /******************** Bits definition for RTC_ALRMBR register ***************/
6510 #define RTC_ALRMBR_MSK4 0x80000000U
6511 #define RTC_ALRMBR_WDSEL 0x40000000U
6512 #define RTC_ALRMBR_DT 0x30000000U
6513 #define RTC_ALRMBR_DT_0 0x10000000U
6514 #define RTC_ALRMBR_DT_1 0x20000000U
6515 #define RTC_ALRMBR_DU 0x0F000000U
6516 #define RTC_ALRMBR_DU_0 0x01000000U
6517 #define RTC_ALRMBR_DU_1 0x02000000U
6518 #define RTC_ALRMBR_DU_2 0x04000000U
6519 #define RTC_ALRMBR_DU_3 0x08000000U
6520 #define RTC_ALRMBR_MSK3 0x00800000U
6521 #define RTC_ALRMBR_PM 0x00400000U
6522 #define RTC_ALRMBR_HT 0x00300000U
6523 #define RTC_ALRMBR_HT_0 0x00100000U
6524 #define RTC_ALRMBR_HT_1 0x00200000U
6525 #define RTC_ALRMBR_HU 0x000F0000U
6526 #define RTC_ALRMBR_HU_0 0x00010000U
6527 #define RTC_ALRMBR_HU_1 0x00020000U
6528 #define RTC_ALRMBR_HU_2 0x00040000U
6529 #define RTC_ALRMBR_HU_3 0x00080000U
6530 #define RTC_ALRMBR_MSK2 0x00008000U
6531 #define RTC_ALRMBR_MNT 0x00007000U
6532 #define RTC_ALRMBR_MNT_0 0x00001000U
6533 #define RTC_ALRMBR_MNT_1 0x00002000U
6534 #define RTC_ALRMBR_MNT_2 0x00004000U
6535 #define RTC_ALRMBR_MNU 0x00000F00U
6536 #define RTC_ALRMBR_MNU_0 0x00000100U
6537 #define RTC_ALRMBR_MNU_1 0x00000200U
6538 #define RTC_ALRMBR_MNU_2 0x00000400U
6539 #define RTC_ALRMBR_MNU_3 0x00000800U
6540 #define RTC_ALRMBR_MSK1 0x00000080U
6541 #define RTC_ALRMBR_ST 0x00000070U
6542 #define RTC_ALRMBR_ST_0 0x00000010U
6543 #define RTC_ALRMBR_ST_1 0x00000020U
6544 #define RTC_ALRMBR_ST_2 0x00000040U
6545 #define RTC_ALRMBR_SU 0x0000000FU
6546 #define RTC_ALRMBR_SU_0 0x00000001U
6547 #define RTC_ALRMBR_SU_1 0x00000002U
6548 #define RTC_ALRMBR_SU_2 0x00000004U
6549 #define RTC_ALRMBR_SU_3 0x00000008U
6550
6551 /******************** Bits definition for RTC_WPR register ******************/
6552 #define RTC_WPR_KEY 0x000000FFU
6553
6554 /******************** Bits definition for RTC_SSR register ******************/
6555 #define RTC_SSR_SS 0x0000FFFFU
6556
6557 /******************** Bits definition for RTC_SHIFTR register ***************/
6558 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6559 #define RTC_SHIFTR_ADD1S 0x80000000U
6560
6561 /******************** Bits definition for RTC_TSTR register *****************/
6562 #define RTC_TSTR_PM 0x00400000U
6563 #define RTC_TSTR_HT 0x00300000U
6564 #define RTC_TSTR_HT_0 0x00100000U
6565 #define RTC_TSTR_HT_1 0x00200000U
6566 #define RTC_TSTR_HU 0x000F0000U
6567 #define RTC_TSTR_HU_0 0x00010000U
6568 #define RTC_TSTR_HU_1 0x00020000U
6569 #define RTC_TSTR_HU_2 0x00040000U
6570 #define RTC_TSTR_HU_3 0x00080000U
6571 #define RTC_TSTR_MNT 0x00007000U
6572 #define RTC_TSTR_MNT_0 0x00001000U
6573 #define RTC_TSTR_MNT_1 0x00002000U
6574 #define RTC_TSTR_MNT_2 0x00004000U
6575 #define RTC_TSTR_MNU 0x00000F00U
6576 #define RTC_TSTR_MNU_0 0x00000100U
6577 #define RTC_TSTR_MNU_1 0x00000200U
6578 #define RTC_TSTR_MNU_2 0x00000400U
6579 #define RTC_TSTR_MNU_3 0x00000800U
6580 #define RTC_TSTR_ST 0x00000070U
6581 #define RTC_TSTR_ST_0 0x00000010U
6582 #define RTC_TSTR_ST_1 0x00000020U
6583 #define RTC_TSTR_ST_2 0x00000040U
6584 #define RTC_TSTR_SU 0x0000000FU
6585 #define RTC_TSTR_SU_0 0x00000001U
6586 #define RTC_TSTR_SU_1 0x00000002U
6587 #define RTC_TSTR_SU_2 0x00000004U
6588 #define RTC_TSTR_SU_3 0x00000008U
6589
6590 /******************** Bits definition for RTC_TSDR register *****************/
6591 #define RTC_TSDR_WDU 0x0000E000U
6592 #define RTC_TSDR_WDU_0 0x00002000U
6593 #define RTC_TSDR_WDU_1 0x00004000U
6594 #define RTC_TSDR_WDU_2 0x00008000U
6595 #define RTC_TSDR_MT 0x00001000U
6596 #define RTC_TSDR_MU 0x00000F00U
6597 #define RTC_TSDR_MU_0 0x00000100U
6598 #define RTC_TSDR_MU_1 0x00000200U
6599 #define RTC_TSDR_MU_2 0x00000400U
6600 #define RTC_TSDR_MU_3 0x00000800U
6601 #define RTC_TSDR_DT 0x00000030U
6602 #define RTC_TSDR_DT_0 0x00000010U
6603 #define RTC_TSDR_DT_1 0x00000020U
6604 #define RTC_TSDR_DU 0x0000000FU
6605 #define RTC_TSDR_DU_0 0x00000001U
6606 #define RTC_TSDR_DU_1 0x00000002U
6607 #define RTC_TSDR_DU_2 0x00000004U
6608 #define RTC_TSDR_DU_3 0x00000008U
6609
6610 /******************** Bits definition for RTC_TSSSR register ****************/
6611 #define RTC_TSSSR_SS 0x0000FFFFU
6612
6613 /******************** Bits definition for RTC_CAL register *****************/
6614 #define RTC_CALR_CALP 0x00008000U
6615 #define RTC_CALR_CALW8 0x00004000U
6616 #define RTC_CALR_CALW16 0x00002000U
6617 #define RTC_CALR_CALM 0x000001FFU
6618 #define RTC_CALR_CALM_0 0x00000001U
6619 #define RTC_CALR_CALM_1 0x00000002U
6620 #define RTC_CALR_CALM_2 0x00000004U
6621 #define RTC_CALR_CALM_3 0x00000008U
6622 #define RTC_CALR_CALM_4 0x00000010U
6623 #define RTC_CALR_CALM_5 0x00000020U
6624 #define RTC_CALR_CALM_6 0x00000040U
6625 #define RTC_CALR_CALM_7 0x00000080U
6626 #define RTC_CALR_CALM_8 0x00000100U
6627
6628 /******************** Bits definition for RTC_TAMPCR register ****************/
6629 #define RTC_TAMPCR_TAMP3MF 0x01000000U
6630 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
6631 #define RTC_TAMPCR_TAMP3IE 0x00400000U
6632 #define RTC_TAMPCR_TAMP2MF 0x00200000U
6633 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
6634 #define RTC_TAMPCR_TAMP2IE 0x00080000U
6635 #define RTC_TAMPCR_TAMP1MF 0x00040000U
6636 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
6637 #define RTC_TAMPCR_TAMP1IE 0x00010000U
6638 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
6639 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
6640 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
6641 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
6642 #define RTC_TAMPCR_TAMPFLT 0x00001800U
6643 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
6644 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
6645 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
6646 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
6647 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
6648 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
6649 #define RTC_TAMPCR_TAMPTS 0x00000080U
6650 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
6651 #define RTC_TAMPCR_TAMP3E 0x00000020U
6652 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
6653 #define RTC_TAMPCR_TAMP2E 0x00000008U
6654 #define RTC_TAMPCR_TAMPIE 0x00000004U
6655 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
6656 #define RTC_TAMPCR_TAMP1E 0x00000001U
6657
6658
6659 /******************** Bits definition for RTC_ALRMASSR register *************/
6660 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6661 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6662 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6663 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6664 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6665 #define RTC_ALRMASSR_SS 0x00007FFFU
6666
6667 /******************** Bits definition for RTC_ALRMBSSR register *************/
6668 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6669 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6670 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6671 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6672 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6673 #define RTC_ALRMBSSR_SS 0x00007FFFU
6674
6675 /******************** Bits definition for RTC_OR register ****************/
6676 #define RTC_OR_TSINSEL 0x00000006U
6677 #define RTC_OR_TSINSEL_0 0x00000002U
6678 #define RTC_OR_TSINSEL_1 0x00000004U
6679 #define RTC_OR_ALARMTYPE 0x00000008U
6680
6681 /******************** Bits definition for RTC_BKP0R register ****************/
6682 #define RTC_BKP0R 0xFFFFFFFFU
6683
6684 /******************** Bits definition for RTC_BKP1R register ****************/
6685 #define RTC_BKP1R 0xFFFFFFFFU
6686
6687 /******************** Bits definition for RTC_BKP2R register ****************/
6688 #define RTC_BKP2R 0xFFFFFFFFU
6689
6690 /******************** Bits definition for RTC_BKP3R register ****************/
6691 #define RTC_BKP3R 0xFFFFFFFFU
6692
6693 /******************** Bits definition for RTC_BKP4R register ****************/
6694 #define RTC_BKP4R 0xFFFFFFFFU
6695
6696 /******************** Bits definition for RTC_BKP5R register ****************/
6697 #define RTC_BKP5R 0xFFFFFFFFU
6698
6699 /******************** Bits definition for RTC_BKP6R register ****************/
6700 #define RTC_BKP6R 0xFFFFFFFFU
6701
6702 /******************** Bits definition for RTC_BKP7R register ****************/
6703 #define RTC_BKP7R 0xFFFFFFFFU
6704
6705 /******************** Bits definition for RTC_BKP8R register ****************/
6706 #define RTC_BKP8R 0xFFFFFFFFU
6707
6708 /******************** Bits definition for RTC_BKP9R register ****************/
6709 #define RTC_BKP9R 0xFFFFFFFFU
6710
6711 /******************** Bits definition for RTC_BKP10R register ***************/
6712 #define RTC_BKP10R 0xFFFFFFFFU
6713
6714 /******************** Bits definition for RTC_BKP11R register ***************/
6715 #define RTC_BKP11R 0xFFFFFFFFU
6716
6717 /******************** Bits definition for RTC_BKP12R register ***************/
6718 #define RTC_BKP12R 0xFFFFFFFFU
6719
6720 /******************** Bits definition for RTC_BKP13R register ***************/
6721 #define RTC_BKP13R 0xFFFFFFFFU
6722
6723 /******************** Bits definition for RTC_BKP14R register ***************/
6724 #define RTC_BKP14R 0xFFFFFFFFU
6725
6726 /******************** Bits definition for RTC_BKP15R register ***************/
6727 #define RTC_BKP15R 0xFFFFFFFFU
6728
6729 /******************** Bits definition for RTC_BKP16R register ***************/
6730 #define RTC_BKP16R 0xFFFFFFFFU
6731
6732 /******************** Bits definition for RTC_BKP17R register ***************/
6733 #define RTC_BKP17R 0xFFFFFFFFU
6734
6735 /******************** Bits definition for RTC_BKP18R register ***************/
6736 #define RTC_BKP18R 0xFFFFFFFFU
6737
6738 /******************** Bits definition for RTC_BKP19R register ***************/
6739 #define RTC_BKP19R 0xFFFFFFFFU
6740
6741 /******************** Bits definition for RTC_BKP20R register ***************/
6742 #define RTC_BKP20R 0xFFFFFFFFU
6743
6744 /******************** Bits definition for RTC_BKP21R register ***************/
6745 #define RTC_BKP21R 0xFFFFFFFFU
6746
6747 /******************** Bits definition for RTC_BKP22R register ***************/
6748 #define RTC_BKP22R 0xFFFFFFFFU
6749
6750 /******************** Bits definition for RTC_BKP23R register ***************/
6751 #define RTC_BKP23R 0xFFFFFFFFU
6752
6753 /******************** Bits definition for RTC_BKP24R register ***************/
6754 #define RTC_BKP24R 0xFFFFFFFFU
6755
6756 /******************** Bits definition for RTC_BKP25R register ***************/
6757 #define RTC_BKP25R 0xFFFFFFFFU
6758
6759 /******************** Bits definition for RTC_BKP26R register ***************/
6760 #define RTC_BKP26R 0xFFFFFFFFU
6761
6762 /******************** Bits definition for RTC_BKP27R register ***************/
6763 #define RTC_BKP27R 0xFFFFFFFFU
6764
6765 /******************** Bits definition for RTC_BKP28R register ***************/
6766 #define RTC_BKP28R 0xFFFFFFFFU
6767
6768 /******************** Bits definition for RTC_BKP29R register ***************/
6769 #define RTC_BKP29R 0xFFFFFFFFU
6770
6771 /******************** Bits definition for RTC_BKP30R register ***************/
6772 #define RTC_BKP30R 0xFFFFFFFFU
6773
6774 /******************** Bits definition for RTC_BKP31R register ***************/
6775 #define RTC_BKP31R 0xFFFFFFFFU
6776
6777 /******************** Number of backup registers ******************************/
6778 #define RTC_BKP_NUMBER 0x00000020U
6779
6780
6781 /******************************************************************************/
6782 /* */
6783 /* Serial Audio Interface */
6784 /* */
6785 /******************************************************************************/
6786 /******************** Bit definition for SAI_GCR register *******************/
6787 #define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
6788 #define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
6789 #define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
6790
6791 #define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
6792 #define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
6793 #define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
6794
6795 /******************* Bit definition for SAI_xCR1 register *******************/
6796 #define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
6797 #define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
6798 #define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
6799
6800 #define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
6801 #define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
6802 #define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
6803
6804 #define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
6805 #define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
6806 #define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
6807 #define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
6808
6809 #define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
6810 #define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
6811
6812 #define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
6813 #define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
6814 #define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
6815
6816 #define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
6817 #define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
6818 #define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
6819 #define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
6820 #define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
6821
6822 #define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
6823 #define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
6824 #define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
6825 #define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
6826 #define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
6827
6828 /******************* Bit definition for SAI_xCR2 register *******************/
6829 #define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
6830 #define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
6831 #define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
6832 #define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
6833
6834 #define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
6835 #define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
6836 #define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
6837 #define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
6838
6839 #define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
6840 #define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
6841 #define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
6842 #define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
6843 #define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
6844 #define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
6845 #define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
6846
6847 #define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
6848
6849 #define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
6850 #define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
6851 #define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
6852
6853 /****************** Bit definition for SAI_xFRCR register *******************/
6854 #define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
6855 #define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
6856 #define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
6857 #define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
6858 #define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
6859 #define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
6860 #define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
6861 #define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
6862 #define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
6863
6864 #define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
6865 #define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
6866 #define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
6867 #define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
6868 #define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
6869 #define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
6870 #define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
6871 #define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
6872
6873 #define SAI_xFRCR_FSDEF 0x00010000U /*!<Frame Synchronization Definition */
6874 #define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
6875 #define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
6876
6877 /* Legacy define */
6878 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6879
6880 /****************** Bit definition for SAI_xSLOTR register *******************/
6881 #define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
6882 #define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
6883 #define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
6884 #define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
6885 #define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
6886 #define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
6887
6888 #define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
6889 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
6890 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
6891
6892 #define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
6893 #define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
6894 #define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
6895 #define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
6896 #define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
6897
6898 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
6899
6900 /******************* Bit definition for SAI_xIMR register *******************/
6901 #define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
6902 #define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
6903 #define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
6904 #define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
6905 #define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
6906 #define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
6907 #define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
6908
6909 /******************** Bit definition for SAI_xSR register *******************/
6910 #define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
6911 #define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
6912 #define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
6913 #define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
6914 #define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
6915 #define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
6916 #define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
6917
6918 #define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
6919 #define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
6920 #define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
6921 #define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
6922
6923 /****************** Bit definition for SAI_xCLRFR register ******************/
6924 #define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
6925 #define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
6926 #define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
6927 #define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
6928 #define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
6929 #define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
6930 #define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
6931
6932 /****************** Bit definition for SAI_xDR register *********************/
6933 #define SAI_xDR_DATA 0xFFFFFFFFU
6934
6935 /******************************************************************************/
6936 /* */
6937 /* SPDIF-RX Interface */
6938 /* */
6939 /******************************************************************************/
6940 /******************** Bit definition for SPDIF_CR register *******************/
6941 #define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */
6942 #define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */
6943 #define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */
6944 #define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */
6945 #define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */
6946 #define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */
6947 #define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */
6948 #define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */
6949 #define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */
6950 #define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */
6951 #define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */
6952 #define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */
6953 #define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIF input selection */
6954
6955 /******************* Bit definition for SPDIFRX_IMR register *******************/
6956 #define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */
6957 #define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */
6958 #define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */
6959 #define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */
6960 #define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */
6961 #define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */
6962 #define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */
6963
6964 /******************* Bit definition for SPDIFRX_SR register *******************/
6965 #define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */
6966 #define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */
6967 #define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */
6968 #define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */
6969 #define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */
6970 #define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */
6971 #define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */
6972 #define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */
6973 #define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */
6974 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with spdif_clk */
6975
6976 /******************* Bit definition for SPDIFRX_IFCR register *******************/
6977 #define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */
6978 #define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */
6979 #define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */
6980 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */
6981
6982 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6983 #define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */
6984 #define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */
6985 #define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */
6986 #define SPDIFRX_DR0_U 0x04000000U /*!<User bit */
6987 #define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */
6988 #define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */
6989
6990 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6991 #define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */
6992 #define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */
6993 #define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */
6994 #define SPDIFRX_DR1_U 0x00000004U /*!<User bit */
6995 #define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */
6996 #define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */
6997
6998 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6999 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */
7000 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */
7001
7002 /******************* Bit definition for SPDIFRX_CSR register *******************/
7003 #define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */
7004 #define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */
7005 #define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */
7006
7007 /******************* Bit definition for SPDIFRX_DIR register *******************/
7008 #define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
7009 #define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
7010
7011
7012 /******************************************************************************/
7013 /* */
7014 /* SD host Interface */
7015 /* */
7016 /******************************************************************************/
7017 /****************** Bit definition for SDMMC_POWER register ******************/
7018 #define SDMMC_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
7019 #define SDMMC_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
7020 #define SDMMC_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
7021
7022 /****************** Bit definition for SDMMC_CLKCR register ******************/
7023 #define SDMMC_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
7024 #define SDMMC_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
7025 #define SDMMC_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
7026 #define SDMMC_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
7027
7028 #define SDMMC_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
7029 #define SDMMC_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
7030 #define SDMMC_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
7031
7032 #define SDMMC_CLKCR_NEGEDGE 0x2000U /*!<SDMMC_CK dephasing selection bit */
7033 #define SDMMC_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
7034
7035 /******************* Bit definition for SDMMC_ARG register *******************/
7036 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
7037
7038 /******************* Bit definition for SDMMC_CMD register *******************/
7039 #define SDMMC_CMD_CMDINDEX 0x003FU /*!<Command Index */
7040
7041 #define SDMMC_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
7042 #define SDMMC_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
7043 #define SDMMC_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
7044
7045 #define SDMMC_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
7046 #define SDMMC_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
7047 #define SDMMC_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
7048 #define SDMMC_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
7049
7050 /***************** Bit definition for SDMMC_RESPCMD register *****************/
7051 #define SDMMC_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
7052
7053 /****************** Bit definition for SDMMC_RESP0 register ******************/
7054 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
7055
7056 /****************** Bit definition for SDMMC_RESP1 register ******************/
7057 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
7058
7059 /****************** Bit definition for SDMMC_RESP2 register ******************/
7060 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
7061
7062 /****************** Bit definition for SDMMC_RESP3 register ******************/
7063 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
7064
7065 /****************** Bit definition for SDMMC_RESP4 register ******************/
7066 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
7067
7068 /****************** Bit definition for SDMMC_DTIMER register *****************/
7069 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
7070
7071 /****************** Bit definition for SDMMC_DLEN register *******************/
7072 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
7073
7074 /****************** Bit definition for SDMMC_DCTRL register ******************/
7075 #define SDMMC_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
7076 #define SDMMC_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
7077 #define SDMMC_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
7078 #define SDMMC_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
7079
7080 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
7081 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
7082 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
7083 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
7084 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
7085
7086 #define SDMMC_DCTRL_RWSTART 0x0100U /*!<Read wait start */
7087 #define SDMMC_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
7088 #define SDMMC_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
7089 #define SDMMC_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
7090
7091 /****************** Bit definition for SDMMC_DCOUNT register *****************/
7092 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
7093
7094 /****************** Bit definition for SDMMC_STA registe ********************/
7095 #define SDMMC_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
7096 #define SDMMC_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
7097 #define SDMMC_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
7098 #define SDMMC_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
7099 #define SDMMC_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
7100 #define SDMMC_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
7101 #define SDMMC_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
7102 #define SDMMC_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
7103 #define SDMMC_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
7104 #define SDMMC_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
7105 #define SDMMC_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
7106 #define SDMMC_STA_TXACT 0x00001000U /*!<Data transmit in progress */
7107 #define SDMMC_STA_RXACT 0x00002000U /*!<Data receive in progress */
7108 #define SDMMC_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
7109 #define SDMMC_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
7110 #define SDMMC_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
7111 #define SDMMC_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
7112 #define SDMMC_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
7113 #define SDMMC_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
7114 #define SDMMC_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
7115 #define SDMMC_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
7116 #define SDMMC_STA_SDIOIT 0x00400000U /*!<SDMMC interrupt received */
7117
7118 /******************* Bit definition for SDMMC_ICR register *******************/
7119 #define SDMMC_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
7120 #define SDMMC_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
7121 #define SDMMC_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
7122 #define SDMMC_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
7123 #define SDMMC_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
7124 #define SDMMC_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
7125 #define SDMMC_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
7126 #define SDMMC_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
7127 #define SDMMC_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
7128 #define SDMMC_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
7129 #define SDMMC_ICR_SDIOITC 0x00400000U /*!<SDMMCIT flag clear bit */
7130
7131 /****************** Bit definition for SDMMC_MASK register *******************/
7132 #define SDMMC_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
7133 #define SDMMC_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
7134 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
7135 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
7136 #define SDMMC_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
7137 #define SDMMC_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
7138 #define SDMMC_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
7139 #define SDMMC_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
7140 #define SDMMC_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
7141 #define SDMMC_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
7142 #define SDMMC_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
7143 #define SDMMC_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
7144 #define SDMMC_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
7145 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
7146 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
7147 #define SDMMC_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
7148 #define SDMMC_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
7149 #define SDMMC_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
7150 #define SDMMC_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
7151 #define SDMMC_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
7152 #define SDMMC_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
7153 #define SDMMC_MASK_SDIOITIE 0x00400000U /*!<SDMMC Mode Interrupt Received interrupt Enable */
7154
7155 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
7156 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
7157
7158 /****************** Bit definition for SDMMC_FIFO register *******************/
7159 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
7160
7161 /******************************************************************************/
7162 /* */
7163 /* Serial Peripheral Interface (SPI) */
7164 /* */
7165 /******************************************************************************/
7166 /******************* Bit definition for SPI_CR1 register ********************/
7167 #define SPI_CR1_CPHA 0x00000001U /*!< Clock Phase */
7168 #define SPI_CR1_CPOL 0x00000002U /*!< Clock Polarity */
7169 #define SPI_CR1_MSTR 0x00000004U /*!< Master Selection */
7170 #define SPI_CR1_BR 0x00000038U /*!< BR[2:0] bits (Baud Rate Control) */
7171 #define SPI_CR1_BR_0 0x00000008U /*!< Bit 0 */
7172 #define SPI_CR1_BR_1 0x00000010U /*!< Bit 1 */
7173 #define SPI_CR1_BR_2 0x00000020U /*!< Bit 2 */
7174 #define SPI_CR1_SPE 0x00000040U /*!< SPI Enable */
7175 #define SPI_CR1_LSBFIRST 0x00000080U /*!< Frame Format */
7176 #define SPI_CR1_SSI 0x00000100U /*!< Internal slave select */
7177 #define SPI_CR1_SSM 0x00000200U /*!< Software slave management */
7178 #define SPI_CR1_RXONLY 0x00000400U /*!< Receive only */
7179 #define SPI_CR1_CRCL 0x00000800U /*!< CRC Length */
7180 #define SPI_CR1_CRCNEXT 0x00001000U /*!< Transmit CRC next */
7181 #define SPI_CR1_CRCEN 0x00002000U /*!< Hardware CRC calculation enable */
7182 #define SPI_CR1_BIDIOE 0x00004000U /*!< Output enable in bidirectional mode */
7183 #define SPI_CR1_BIDIMODE 0x00008000U /*!< Bidirectional data mode enable */
7184
7185 /******************* Bit definition for SPI_CR2 register ********************/
7186 #define SPI_CR2_RXDMAEN 0x00000001U /*!< Rx Buffer DMA Enable */
7187 #define SPI_CR2_TXDMAEN 0x00000002U /*!< Tx Buffer DMA Enable */
7188 #define SPI_CR2_SSOE 0x00000004U /*!< SS Output Enable */
7189 #define SPI_CR2_NSSP 0x00000008U /*!< NSS pulse management Enable */
7190 #define SPI_CR2_FRF 0x00000010U /*!< Frame Format Enable */
7191 #define SPI_CR2_ERRIE 0x00000020U /*!< Error Interrupt Enable */
7192 #define SPI_CR2_RXNEIE 0x00000040U /*!< RX buffer Not Empty Interrupt Enable */
7193 #define SPI_CR2_TXEIE 0x00000080U /*!< Tx buffer Empty Interrupt Enable */
7194 #define SPI_CR2_DS 0x00000F00U /*!< DS[3:0] Data Size */
7195 #define SPI_CR2_DS_0 0x00000100U /*!< Bit 0 */
7196 #define SPI_CR2_DS_1 0x00000200U /*!< Bit 1 */
7197 #define SPI_CR2_DS_2 0x00000400U /*!< Bit 2 */
7198 #define SPI_CR2_DS_3 0x00000800U /*!< Bit 3 */
7199 #define SPI_CR2_FRXTH 0x00001000U /*!< FIFO reception Threshold */
7200 #define SPI_CR2_LDMARX 0x00002000U /*!< Last DMA transfer for reception */
7201 #define SPI_CR2_LDMATX 0x00004000U /*!< Last DMA transfer for transmission */
7202
7203 /******************** Bit definition for SPI_SR register ********************/
7204 #define SPI_SR_RXNE 0x00000001U /*!< Receive buffer Not Empty */
7205 #define SPI_SR_TXE 0x00000002U /*!< Transmit buffer Empty */
7206 #define SPI_SR_CHSIDE 0x00000004U /*!< Channel side */
7207 #define SPI_SR_UDR 0x00000008U /*!< Underrun flag */
7208 #define SPI_SR_CRCERR 0x00000010U /*!< CRC Error flag */
7209 #define SPI_SR_MODF 0x00000020U /*!< Mode fault */
7210 #define SPI_SR_OVR 0x00000040U /*!< Overrun flag */
7211 #define SPI_SR_BSY 0x00000080U /*!< Busy flag */
7212 #define SPI_SR_FRE 0x00000100U /*!< TI frame format error */
7213 #define SPI_SR_FRLVL 0x00000600U /*!< FIFO Reception Level */
7214 #define SPI_SR_FRLVL_0 0x00000200U /*!< Bit 0 */
7215 #define SPI_SR_FRLVL_1 0x00000400U /*!< Bit 1 */
7216 #define SPI_SR_FTLVL 0x00001800U /*!< FIFO Transmission Level */
7217 #define SPI_SR_FTLVL_0 0x00000800U /*!< Bit 0 */
7218 #define SPI_SR_FTLVL_1 0x00001000U /*!< Bit 1 */
7219
7220 /******************** Bit definition for SPI_DR register ********************/
7221 #define SPI_DR_DR 0xFFFFU /*!< Data Register */
7222
7223 /******************* Bit definition for SPI_CRCPR register ******************/
7224 #define SPI_CRCPR_CRCPOLY 0xFFFFU /*!< CRC polynomial register */
7225
7226 /****************** Bit definition for SPI_RXCRCR register ******************/
7227 #define SPI_RXCRCR_RXCRC 0xFFFFU /*!< Rx CRC Register */
7228
7229 /****************** Bit definition for SPI_TXCRCR register ******************/
7230 #define SPI_TXCRCR_TXCRC 0xFFFFU /*!< Tx CRC Register */
7231
7232 /****************** Bit definition for SPI_I2SCFGR register *****************/
7233 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
7234 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
7235 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
7236 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
7237 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
7238 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
7239 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
7240 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
7241 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
7242 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
7243 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
7244 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
7245 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
7246 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
7247 #define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
7248
7249 /****************** Bit definition for SPI_I2SPR register *******************/
7250 #define SPI_I2SPR_I2SDIV 0x00FFU /*!<I2S Linear prescaler */
7251 #define SPI_I2SPR_ODD 0x0100U /*!<Odd factor for the prescaler */
7252 #define SPI_I2SPR_MCKOE 0x0200U /*!<Master Clock Output Enable */
7253
7254
7255 /******************************************************************************/
7256 /* */
7257 /* SYSCFG */
7258 /* */
7259 /******************************************************************************/
7260 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7261 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U /*!< Boot information after Reset */
7262
7263 #define SYSCFG_MEMRMP_SWP_FB 0x00000100U /*!< User Flash Bank swap */
7264
7265 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U /*!< FMC Memory Mapping swapping */
7266 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
7267 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
7268
7269 /****************** Bit definition for SYSCFG_PMC register ******************/
7270 #define SYSCFG_PMC_I2C1_FMP 0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */
7271 #define SYSCFG_PMC_I2C2_FMP 0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */
7272 #define SYSCFG_PMC_I2C3_FMP 0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */
7273 #define SYSCFG_PMC_I2C4_FMP 0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */
7274 #define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U /*!< PB6_FMP Fast Mode + Enable */
7275 #define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U /*!< PB7_FMP Fast Mode + Enable */
7276 #define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U /*!< PB8_FMP Fast Mode + Enable */
7277 #define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U /*!< PB9_FMP Fast Mode + Enable */
7278
7279 #define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
7280 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
7281 #define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
7282 #define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
7283
7284 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
7285
7286 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7287 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
7288 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
7289 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
7290 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
7291 /**
7292 * @brief EXTI0 configuration
7293 */
7294 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
7295 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
7296 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
7297 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
7298 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
7299 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
7300 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
7301 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
7302 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
7303 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
7304 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
7305
7306 /**
7307 * @brief EXTI1 configuration
7308 */
7309 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
7310 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
7311 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
7312 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
7313 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
7314 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
7315 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
7316 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
7317 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
7318 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
7319 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
7320
7321 /**
7322 * @brief EXTI2 configuration
7323 */
7324 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
7325 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
7326 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
7327 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
7328 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
7329 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
7330 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
7331 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
7332 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
7333 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
7334 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
7335
7336 /**
7337 * @brief EXTI3 configuration
7338 */
7339 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
7340 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
7341 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
7342 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
7343 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
7344 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
7345 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
7346 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
7347 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
7348 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
7349 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
7350
7351 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
7352 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
7353 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
7354 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
7355 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
7356 /**
7357 * @brief EXTI4 configuration
7358 */
7359 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
7360 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
7361 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
7362 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
7363 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
7364 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
7365 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
7366 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
7367 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
7368 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
7369 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
7370
7371 /**
7372 * @brief EXTI5 configuration
7373 */
7374 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
7375 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
7376 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
7377 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
7378 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
7379 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
7380 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
7381 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
7382 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
7383 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
7384 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
7385
7386 /**
7387 * @brief EXTI6 configuration
7388 */
7389 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
7390 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
7391 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
7392 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
7393 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
7394 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
7395 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
7396 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
7397 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
7398 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
7399 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
7400
7401 /**
7402 * @brief EXTI7 configuration
7403 */
7404 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
7405 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
7406 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
7407 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
7408 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
7409 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
7410 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
7411 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
7412 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
7413 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
7414 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
7415
7416 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7417 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
7418 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
7419 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
7420 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
7421
7422 /**
7423 * @brief EXTI8 configuration
7424 */
7425 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
7426 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
7427 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
7428 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
7429 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
7430 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
7431 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
7432 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
7433 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
7434 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
7435
7436 /**
7437 * @brief EXTI9 configuration
7438 */
7439 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
7440 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
7441 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
7442 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
7443 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
7444 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
7445 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
7446 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
7447 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
7448 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
7449
7450 /**
7451 * @brief EXTI10 configuration
7452 */
7453 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
7454 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
7455 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
7456 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
7457 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
7458 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
7459 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
7460 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
7461 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
7462 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
7463
7464 /**
7465 * @brief EXTI11 configuration
7466 */
7467 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
7468 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
7469 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
7470 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
7471 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
7472 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
7473 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
7474 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
7475 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
7476 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
7477
7478
7479 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7480 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
7481 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
7482 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
7483 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
7484 /**
7485 * @brief EXTI12 configuration
7486 */
7487 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
7488 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
7489 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
7490 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
7491 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
7492 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
7493 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
7494 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
7495 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
7496 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
7497
7498 /**
7499 * @brief EXTI13 configuration
7500 */
7501 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
7502 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
7503 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
7504 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
7505 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
7506 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
7507 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
7508 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
7509 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
7510 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
7511
7512 /**
7513 * @brief EXTI14 configuration
7514 */
7515 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
7516 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
7517 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
7518 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
7519 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
7520 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
7521 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
7522 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
7523 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
7524 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
7525
7526 /**
7527 * @brief EXTI15 configuration
7528 */
7529 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
7530 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
7531 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
7532 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
7533 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
7534 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
7535 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
7536 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
7537 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
7538 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
7539
7540 /****************** Bit definition for SYSCFG_CBR register ******************/
7541 #define SYSCFG_CBR_CLL 0x00000001U /*!<Core Lockup Lock */
7542 #define SYSCFG_CBR_PVDL 0x00000004U /*!<PVD Lock */
7543
7544 /****************** Bit definition for SYSCFG_CMPCR register ****************/
7545 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell power-down */
7546 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell ready flag */
7547
7548 /******************************************************************************/
7549 /* */
7550 /* TIM */
7551 /* */
7552 /******************************************************************************/
7553 /******************* Bit definition for TIM_CR1 register ********************/
7554 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
7555 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
7556 #define TIM_CR1_URS 0x0004U /*!<Update request source */
7557 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
7558 #define TIM_CR1_DIR 0x0010U /*!<Direction */
7559
7560 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
7561 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
7562 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
7563
7564 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
7565
7566 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
7567 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
7568 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
7569 #define TIM_CR1_UIFREMAP 0x0800U /*!<UIF status bit */
7570
7571 /******************* Bit definition for TIM_CR2 register ********************/
7572 #define TIM_CR2_CCPC 0x00000001U /*!<Capture/Compare Preloaded Control */
7573 #define TIM_CR2_CCUS 0x00000004U /*!<Capture/Compare Control Update Selection */
7574 #define TIM_CR2_CCDS 0x00000008U /*!<Capture/Compare DMA Selection */
7575
7576 #define TIM_CR2_OIS5 0x00010000U /*!<Output Idle state 4 (OC4 output) */
7577 #define TIM_CR2_OIS6 0x00040000U /*!<Output Idle state 4 (OC4 output) */
7578
7579 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
7580 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
7581 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
7582 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
7583
7584 #define TIM_CR2_MMS2 0x00F00000U /*!<MMS[2:0] bits (Master Mode Selection) */
7585 #define TIM_CR2_MMS2_0 0x00100000U /*!<Bit 0 */
7586 #define TIM_CR2_MMS2_1 0x00200000U /*!<Bit 1 */
7587 #define TIM_CR2_MMS2_2 0x00400000U /*!<Bit 2 */
7588 #define TIM_CR2_MMS2_3 0x00800000U /*!<Bit 2 */
7589
7590 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
7591 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
7592 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
7593 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
7594 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
7595 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
7596 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
7597 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
7598
7599 /******************* Bit definition for TIM_SMCR register *******************/
7600 #define TIM_SMCR_SMS 0x00010007U /*!<SMS[2:0] bits (Slave mode selection) */
7601 #define TIM_SMCR_SMS_0 0x00000001U /*!<Bit 0 */
7602 #define TIM_SMCR_SMS_1 0x00000002U /*!<Bit 1 */
7603 #define TIM_SMCR_SMS_2 0x00000004U /*!<Bit 2 */
7604 #define TIM_SMCR_SMS_3 0x00010000U /*!<Bit 3 */
7605 #define TIM_SMCR_OCCS 0x00000008U /*!< OCREF clear selection */
7606
7607 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
7608 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
7609 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
7610 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
7611
7612 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
7613
7614 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
7615 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
7616 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
7617 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
7618 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
7619
7620 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
7621 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
7622 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
7623
7624 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
7625 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
7626
7627 /******************* Bit definition for TIM_DIER register *******************/
7628 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
7629 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
7630 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
7631 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
7632 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
7633 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
7634 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
7635 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
7636 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
7637 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
7638 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
7639 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
7640 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
7641 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
7642 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
7643
7644 /******************** Bit definition for TIM_SR register ********************/
7645 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
7646 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
7647 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
7648 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
7649 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
7650 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
7651 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
7652 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
7653 #define TIM_SR_B2IF 0x0100U /*!<Break2 interrupt Flag */
7654 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
7655 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
7656 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
7657 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
7658
7659 /******************* Bit definition for TIM_EGR register ********************/
7660 #define TIM_EGR_UG 0x00000001U /*!<Update Generation */
7661 #define TIM_EGR_CC1G 0x00000002U /*!<Capture/Compare 1 Generation */
7662 #define TIM_EGR_CC2G 0x00000004U /*!<Capture/Compare 2 Generation */
7663 #define TIM_EGR_CC3G 0x00000008U /*!<Capture/Compare 3 Generation */
7664 #define TIM_EGR_CC4G 0x00000010U /*!<Capture/Compare 4 Generation */
7665 #define TIM_EGR_COMG 0x00000020U /*!<Capture/Compare Control Update Generation */
7666 #define TIM_EGR_TG 0x00000040U /*!<Trigger Generation */
7667 #define TIM_EGR_BG 0x00000080U /*!<Break Generation */
7668 #define TIM_EGR_B2G 0x00000100U /*!<Break2 Generation */
7669
7670 /****************** Bit definition for TIM_CCMR1 register *******************/
7671 #define TIM_CCMR1_CC1S 0x00000003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7672 #define TIM_CCMR1_CC1S_0 0x00000001U /*!<Bit 0 */
7673 #define TIM_CCMR1_CC1S_1 0x00000002U /*!<Bit 1 */
7674
7675 #define TIM_CCMR1_OC1FE 0x00000004U /*!<Output Compare 1 Fast enable */
7676 #define TIM_CCMR1_OC1PE 0x00000008U /*!<Output Compare 1 Preload enable */
7677
7678 #define TIM_CCMR1_OC1M 0x00010070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7679 #define TIM_CCMR1_OC1M_0 0x00000010U /*!<Bit 0 */
7680 #define TIM_CCMR1_OC1M_1 0x00000020U /*!<Bit 1 */
7681 #define TIM_CCMR1_OC1M_2 0x00000040U /*!<Bit 2 */
7682 #define TIM_CCMR1_OC1M_3 0x00010000U /*!<Bit 3 */
7683
7684 #define TIM_CCMR1_OC1CE 0x00000080U /*!<Output Compare 1Clear Enable */
7685
7686 #define TIM_CCMR1_CC2S 0x00000300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7687 #define TIM_CCMR1_CC2S_0 0x00000100U /*!<Bit 0 */
7688 #define TIM_CCMR1_CC2S_1 0x00000200U /*!<Bit 1 */
7689
7690 #define TIM_CCMR1_OC2FE 0x00000400U /*!<Output Compare 2 Fast enable */
7691 #define TIM_CCMR1_OC2PE 0x00000800U /*!<Output Compare 2 Preload enable */
7692
7693 #define TIM_CCMR1_OC2M 0x01007000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7694 #define TIM_CCMR1_OC2M_0 0x00001000U /*!<Bit 0 */
7695 #define TIM_CCMR1_OC2M_1 0x00002000U /*!<Bit 1 */
7696 #define TIM_CCMR1_OC2M_2 0x00004000U /*!<Bit 2 */
7697 #define TIM_CCMR1_OC2M_3 0x01000000U /*!<Bit 3 */
7698
7699 #define TIM_CCMR1_OC2CE 0x00008000U /*!<Output Compare 2 Clear Enable */
7700
7701 /*----------------------------------------------------------------------------*/
7702
7703 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7704 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
7705 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
7706
7707 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7708 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
7709 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
7710 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
7711 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
7712
7713 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7714 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
7715 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
7716
7717 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7718 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
7719 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
7720 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
7721 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
7722
7723 /****************** Bit definition for TIM_CCMR2 register *******************/
7724 #define TIM_CCMR2_CC3S 0x00000003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7725 #define TIM_CCMR2_CC3S_0 0x00000001U /*!<Bit 0 */
7726 #define TIM_CCMR2_CC3S_1 0x00000002U /*!<Bit 1 */
7727
7728 #define TIM_CCMR2_OC3FE 0x00000004U /*!<Output Compare 3 Fast enable */
7729 #define TIM_CCMR2_OC3PE 0x00000008U /*!<Output Compare 3 Preload enable */
7730
7731 #define TIM_CCMR2_OC3M 0x00010070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7732 #define TIM_CCMR2_OC3M_0 0x00000010U /*!<Bit 0 */
7733 #define TIM_CCMR2_OC3M_1 0x00000020U /*!<Bit 1 */
7734 #define TIM_CCMR2_OC3M_2 0x00000040U /*!<Bit 2 */
7735 #define TIM_CCMR2_OC3M_3 0x00010000U /*!<Bit 3 */
7736
7737
7738
7739 #define TIM_CCMR2_OC3CE 0x00000080U /*!<Output Compare 3 Clear Enable */
7740
7741 #define TIM_CCMR2_CC4S 0x00000300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7742 #define TIM_CCMR2_CC4S_0 0x00000100U /*!<Bit 0 */
7743 #define TIM_CCMR2_CC4S_1 0x00000200U /*!<Bit 1 */
7744
7745 #define TIM_CCMR2_OC4FE 0x00000400U /*!<Output Compare 4 Fast enable */
7746 #define TIM_CCMR2_OC4PE 0x00000800U /*!<Output Compare 4 Preload enable */
7747
7748 #define TIM_CCMR2_OC4M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7749 #define TIM_CCMR2_OC4M_0 0x00001000U /*!<Bit 0 */
7750 #define TIM_CCMR2_OC4M_1 0x00002000U /*!<Bit 1 */
7751 #define TIM_CCMR2_OC4M_2 0x00004000U /*!<Bit 2 */
7752 #define TIM_CCMR2_OC4M_3 0x01000000U /*!<Bit 3 */
7753
7754 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
7755
7756 /*----------------------------------------------------------------------------*/
7757
7758 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7759 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
7760 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
7761
7762 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7763 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
7764 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
7765 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
7766 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
7767
7768 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7769 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
7770 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
7771
7772 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7773 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
7774 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
7775 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
7776 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
7777
7778 /******************* Bit definition for TIM_CCER register *******************/
7779 #define TIM_CCER_CC1E 0x00000001U /*!<Capture/Compare 1 output enable */
7780 #define TIM_CCER_CC1P 0x00000002U /*!<Capture/Compare 1 output Polarity */
7781 #define TIM_CCER_CC1NE 0x00000004U /*!<Capture/Compare 1 Complementary output enable */
7782 #define TIM_CCER_CC1NP 0x00000008U /*!<Capture/Compare 1 Complementary output Polarity */
7783 #define TIM_CCER_CC2E 0x00000010U /*!<Capture/Compare 2 output enable */
7784 #define TIM_CCER_CC2P 0x00000020U /*!<Capture/Compare 2 output Polarity */
7785 #define TIM_CCER_CC2NE 0x00000040U /*!<Capture/Compare 2 Complementary output enable */
7786 #define TIM_CCER_CC2NP 0x00000080U /*!<Capture/Compare 2 Complementary output Polarity */
7787 #define TIM_CCER_CC3E 0x00000100U /*!<Capture/Compare 3 output enable */
7788 #define TIM_CCER_CC3P 0x00000200U /*!<Capture/Compare 3 output Polarity */
7789 #define TIM_CCER_CC3NE 0x00000400U /*!<Capture/Compare 3 Complementary output enable */
7790 #define TIM_CCER_CC3NP 0x00000800U /*!<Capture/Compare 3 Complementary output Polarity */
7791 #define TIM_CCER_CC4E 0x00001000U /*!<Capture/Compare 4 output enable */
7792 #define TIM_CCER_CC4P 0x00002000U /*!<Capture/Compare 4 output Polarity */
7793 #define TIM_CCER_CC4NP 0x00008000U /*!<Capture/Compare 4 Complementary output Polarity */
7794 #define TIM_CCER_CC5E 0x00010000U /*!<Capture/Compare 5 output enable */
7795 #define TIM_CCER_CC5P 0x00020000U /*!<Capture/Compare 5 output Polarity */
7796 #define TIM_CCER_CC6E 0x00100000U /*!<Capture/Compare 6 output enable */
7797 #define TIM_CCER_CC6P 0x00200000U /*!<Capture/Compare 6 output Polarity */
7798
7799
7800 /******************* Bit definition for TIM_CNT register ********************/
7801 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
7802
7803 /******************* Bit definition for TIM_PSC register ********************/
7804 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
7805
7806 /******************* Bit definition for TIM_ARR register ********************/
7807 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
7808
7809 /******************* Bit definition for TIM_RCR register ********************/
7810 #define TIM_RCR_REP ((uint8_t)0xFFU) /*!<Repetition Counter Value */
7811
7812 /******************* Bit definition for TIM_CCR1 register *******************/
7813 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
7814
7815 /******************* Bit definition for TIM_CCR2 register *******************/
7816 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
7817
7818 /******************* Bit definition for TIM_CCR3 register *******************/
7819 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
7820
7821 /******************* Bit definition for TIM_CCR4 register *******************/
7822 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
7823
7824 /******************* Bit definition for TIM_BDTR register *******************/
7825 #define TIM_BDTR_DTG 0x000000FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7826 #define TIM_BDTR_DTG_0 0x00000001U /*!<Bit 0 */
7827 #define TIM_BDTR_DTG_1 0x00000002U /*!<Bit 1 */
7828 #define TIM_BDTR_DTG_2 0x00000004U /*!<Bit 2 */
7829 #define TIM_BDTR_DTG_3 0x00000008U /*!<Bit 3 */
7830 #define TIM_BDTR_DTG_4 0x00000010U /*!<Bit 4 */
7831 #define TIM_BDTR_DTG_5 0x00000020U /*!<Bit 5 */
7832 #define TIM_BDTR_DTG_6 0x00000040U /*!<Bit 6 */
7833 #define TIM_BDTR_DTG_7 0x00000080U /*!<Bit 7 */
7834
7835 #define TIM_BDTR_LOCK 0x00000300U /*!<LOCK[1:0] bits (Lock Configuration) */
7836 #define TIM_BDTR_LOCK_0 0x00000100U /*!<Bit 0 */
7837 #define TIM_BDTR_LOCK_1 0x00000200U /*!<Bit 1 */
7838
7839 #define TIM_BDTR_OSSI 0x00000400U /*!<Off-State Selection for Idle mode */
7840 #define TIM_BDTR_OSSR 0x00000800U /*!<Off-State Selection for Run mode */
7841 #define TIM_BDTR_BKE 0x00001000U /*!<Break enable */
7842 #define TIM_BDTR_BKP 0x00002000U /*!<Break Polarity */
7843 #define TIM_BDTR_AOE 0x00004000U /*!<Automatic Output enable */
7844 #define TIM_BDTR_MOE 0x00008000U /*!<Main Output enable */
7845 #define TIM_BDTR_BKF 0x000F0000U /*!<Break Filter for Break1 */
7846 #define TIM_BDTR_BK2F 0x00F00000U /*!<Break Filter for Break2 */
7847 #define TIM_BDTR_BK2E 0x01000000U /*!<Break enable for Break2 */
7848 #define TIM_BDTR_BK2P 0x02000000U /*!<Break Polarity for Break2 */
7849
7850 /******************* Bit definition for TIM_DCR register ********************/
7851 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
7852 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
7853 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
7854 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
7855 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
7856 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
7857
7858 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
7859 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
7860 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
7861 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
7862 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
7863 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
7864
7865 /******************* Bit definition for TIM_DMAR register *******************/
7866 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
7867
7868 /******************* Bit definition for TIM_OR regiter *********************/
7869 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
7870 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
7871 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
7872 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
7873 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
7874 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
7875
7876 /****************** Bit definition for TIM_CCMR3 register *******************/
7877 #define TIM_CCMR3_OC5FE 0x00000004U /*!<Output Compare 5 Fast enable */
7878 #define TIM_CCMR3_OC5PE 0x00000008U /*!<Output Compare 5 Preload enable */
7879
7880 #define TIM_CCMR3_OC5M 0x00010070U /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
7881 #define TIM_CCMR3_OC5M_0 0x00000010U /*!<Bit 0 */
7882 #define TIM_CCMR3_OC5M_1 0x00000020U /*!<Bit 1 */
7883 #define TIM_CCMR3_OC5M_2 0x00000040U /*!<Bit 2 */
7884 #define TIM_CCMR3_OC5M_3 0x00010000U /*!<Bit 3 */
7885
7886 #define TIM_CCMR3_OC5CE 0x00000080U /*!<Output Compare 5 Clear Enable */
7887
7888 #define TIM_CCMR3_OC6FE 0x00000400U /*!<Output Compare 4 Fast enable */
7889 #define TIM_CCMR3_OC6PE 0x00000800U /*!<Output Compare 4 Preload enable */
7890
7891 #define TIM_CCMR3_OC6M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7892 #define TIM_CCMR3_OC6M_0 0x00001000U /*!<Bit 0 */
7893 #define TIM_CCMR3_OC6M_1 0x00002000U /*!<Bit 1 */
7894 #define TIM_CCMR3_OC6M_2 0x00004000U /*!<Bit 2 */
7895 #define TIM_CCMR3_OC6M_3 0x01000000U /*!<Bit 3 */
7896
7897 #define TIM_CCMR3_OC6CE 0x00008000U /*!<Output Compare 4 Clear Enable */
7898
7899 /******************* Bit definition for TIM_CCR5 register *******************/
7900 #define TIM_CCR5_CCR5 0xFFFFFFFFU /*!<Capture/Compare 5 Value */
7901 #define TIM_CCR5_GC5C1 0x20000000U /*!<Group Channel 5 and Channel 1 */
7902 #define TIM_CCR5_GC5C2 0x40000000U /*!<Group Channel 5 and Channel 2 */
7903 #define TIM_CCR5_GC5C3 0x80000000U /*!<Group Channel 5 and Channel 3 */
7904
7905 /******************* Bit definition for TIM_CCR6 register *******************/
7906 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
7907
7908 /******************* Bit definition for TIM1_AF1 register *******************/
7909 #define TIM1_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
7910 #define TIM1_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
7911
7912 /******************* Bit definition for TIM1_AF2 register *******************/
7913 #define TIM1_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN input enable */
7914 #define TIM1_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
7915
7916 /******************* Bit definition for TIM8_AF1 register *******************/
7917 #define TIM8_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
7918 #define TIM8_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
7919
7920 /******************* Bit definition for TIM8_AF2 register *******************/
7921 #define TIM8_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN2 input enable */
7922 #define TIM8_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
7923
7924 /******************************************************************************/
7925 /* */
7926 /* Low Power Timer (LPTIM) */
7927 /* */
7928 /******************************************************************************/
7929 /****************** Bit definition for LPTIM_ISR register *******************/
7930 #define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
7931 #define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
7932 #define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
7933 #define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
7934 #define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
7935 #define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
7936 #define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
7937
7938 /****************** Bit definition for LPTIM_ICR register *******************/
7939 #define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
7940 #define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
7941 #define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
7942 #define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
7943 #define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
7944 #define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
7945 #define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
7946
7947 /****************** Bit definition for LPTIM_IER register *******************/
7948 #define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
7949 #define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
7950 #define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
7951 #define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
7952 #define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
7953 #define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
7954 #define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
7955
7956 /****************** Bit definition for LPTIM_CFGR register*******************/
7957 #define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
7958
7959 #define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
7960 #define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
7961 #define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
7962
7963 #define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7964 #define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
7965 #define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
7966
7967 #define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7968 #define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
7969 #define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
7970
7971 #define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
7972 #define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
7973 #define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
7974 #define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
7975
7976 #define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7977 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
7978 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
7979 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
7980
7981 #define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7982 #define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
7983 #define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
7984
7985 #define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
7986 #define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
7987 #define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
7988 #define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
7989 #define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
7990 #define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
7991
7992 /****************** Bit definition for LPTIM_CR register ********************/
7993 #define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
7994 #define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
7995 #define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
7996
7997 /****************** Bit definition for LPTIM_CMP register *******************/
7998 #define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
7999
8000 /****************** Bit definition for LPTIM_ARR register *******************/
8001 #define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
8002
8003 /****************** Bit definition for LPTIM_CNT register *******************/
8004 #define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
8005 /******************************************************************************/
8006 /* */
8007 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
8008 /* */
8009 /******************************************************************************/
8010 /****************** Bit definition for USART_CR1 register *******************/
8011 #define USART_CR1_UE 0x00000001U /*!< USART Enable */
8012 #define USART_CR1_RE 0x00000004U /*!< Receiver Enable */
8013 #define USART_CR1_TE 0x00000008U /*!< Transmitter Enable */
8014 #define USART_CR1_IDLEIE 0x00000010U /*!< IDLE Interrupt Enable */
8015 #define USART_CR1_RXNEIE 0x00000020U /*!< RXNE Interrupt Enable */
8016 #define USART_CR1_TCIE 0x00000040U /*!< Transmission Complete Interrupt Enable */
8017 #define USART_CR1_TXEIE 0x00000080U /*!< TXE Interrupt Enable */
8018 #define USART_CR1_PEIE 0x00000100U /*!< PE Interrupt Enable */
8019 #define USART_CR1_PS 0x00000200U /*!< Parity Selection */
8020 #define USART_CR1_PCE 0x00000400U /*!< Parity Control Enable */
8021 #define USART_CR1_WAKE 0x00000800U /*!< Receiver Wakeup method */
8022 #define USART_CR1_M 0x10001000U /*!< Word length */
8023 #define USART_CR1_M_0 0x00001000U /*!< Word length - Bit 0 */
8024 #define USART_CR1_MME 0x00002000U /*!< Mute Mode Enable */
8025 #define USART_CR1_CMIE 0x00004000U /*!< Character match interrupt enable */
8026 #define USART_CR1_OVER8 0x00008000U /*!< Oversampling by 8-bit or 16-bit mode */
8027 #define USART_CR1_DEDT 0x001F0000U /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
8028 #define USART_CR1_DEDT_0 0x00010000U /*!< Bit 0 */
8029 #define USART_CR1_DEDT_1 0x00020000U /*!< Bit 1 */
8030 #define USART_CR1_DEDT_2 0x00040000U /*!< Bit 2 */
8031 #define USART_CR1_DEDT_3 0x00080000U /*!< Bit 3 */
8032 #define USART_CR1_DEDT_4 0x00100000U /*!< Bit 4 */
8033 #define USART_CR1_DEAT 0x03E00000U /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
8034 #define USART_CR1_DEAT_0 0x00200000U /*!< Bit 0 */
8035 #define USART_CR1_DEAT_1 0x00400000U /*!< Bit 1 */
8036 #define USART_CR1_DEAT_2 0x00800000U /*!< Bit 2 */
8037 #define USART_CR1_DEAT_3 0x01000000U /*!< Bit 3 */
8038 #define USART_CR1_DEAT_4 0x02000000U /*!< Bit 4 */
8039 #define USART_CR1_RTOIE 0x04000000U /*!< Receive Time Out interrupt enable */
8040 #define USART_CR1_EOBIE 0x08000000U /*!< End of Block interrupt enable */
8041 #define USART_CR1_M_1 0x10000000U /*!< Word length - Bit 1 */
8042
8043 /****************** Bit definition for USART_CR2 register *******************/
8044 #define USART_CR2_ADDM7 0x00000010U /*!< 7-bit or 4-bit Address Detection */
8045 #define USART_CR2_LBDL 0x00000020U /*!< LIN Break Detection Length */
8046 #define USART_CR2_LBDIE 0x00000040U /*!< LIN Break Detection Interrupt Enable */
8047 #define USART_CR2_LBCL 0x00000100U /*!< Last Bit Clock pulse */
8048 #define USART_CR2_CPHA 0x00000200U /*!< Clock Phase */
8049 #define USART_CR2_CPOL 0x00000400U /*!< Clock Polarity */
8050 #define USART_CR2_CLKEN 0x00000800U /*!< Clock Enable */
8051 #define USART_CR2_STOP 0x00003000U /*!< STOP[1:0] bits (STOP bits) */
8052 #define USART_CR2_STOP_0 0x00001000U /*!< Bit 0 */
8053 #define USART_CR2_STOP_1 0x00002000U /*!< Bit 1 */
8054 #define USART_CR2_LINEN 0x00004000U /*!< LIN mode enable */
8055 #define USART_CR2_SWAP 0x00008000U /*!< SWAP TX/RX pins */
8056 #define USART_CR2_RXINV 0x00010000U /*!< RX pin active level inversion */
8057 #define USART_CR2_TXINV 0x00020000U /*!< TX pin active level inversion */
8058 #define USART_CR2_DATAINV 0x00040000U /*!< Binary data inversion */
8059 #define USART_CR2_MSBFIRST 0x00080000U /*!< Most Significant Bit First */
8060 #define USART_CR2_ABREN 0x00100000U /*!< Auto Baud-Rate Enable */
8061 #define USART_CR2_ABRMODE 0x00600000U /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
8062 #define USART_CR2_ABRMODE_0 0x00200000U /*!< Bit 0 */
8063 #define USART_CR2_ABRMODE_1 0x00400000U /*!< Bit 1 */
8064 #define USART_CR2_RTOEN 0x00800000U /*!< Receiver Time-Out enable */
8065 #define USART_CR2_ADD 0xFF000000U /*!< Address of the USART node */
8066
8067 /****************** Bit definition for USART_CR3 register *******************/
8068 #define USART_CR3_EIE 0x00000001U /*!< Error Interrupt Enable */
8069 #define USART_CR3_IREN 0x00000002U /*!< IrDA mode Enable */
8070 #define USART_CR3_IRLP 0x00000004U /*!< IrDA Low-Power */
8071 #define USART_CR3_HDSEL 0x00000008U /*!< Half-Duplex Selection */
8072 #define USART_CR3_NACK 0x00000010U /*!< SmartCard NACK enable */
8073 #define USART_CR3_SCEN 0x00000020U /*!< SmartCard mode enable */
8074 #define USART_CR3_DMAR 0x00000040U /*!< DMA Enable Receiver */
8075 #define USART_CR3_DMAT 0x00000080U /*!< DMA Enable Transmitter */
8076 #define USART_CR3_RTSE 0x00000100U /*!< RTS Enable */
8077 #define USART_CR3_CTSE 0x00000200U /*!< CTS Enable */
8078 #define USART_CR3_CTSIE 0x00000400U /*!< CTS Interrupt Enable */
8079 #define USART_CR3_ONEBIT 0x00000800U /*!< One sample bit method enable */
8080 #define USART_CR3_OVRDIS 0x00001000U /*!< Overrun Disable */
8081 #define USART_CR3_DDRE 0x00002000U /*!< DMA Disable on Reception Error */
8082 #define USART_CR3_DEM 0x00004000U /*!< Driver Enable Mode */
8083 #define USART_CR3_DEP 0x00008000U /*!< Driver Enable Polarity Selection */
8084 #define USART_CR3_SCARCNT 0x000E0000U /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
8085 #define USART_CR3_SCARCNT_0 0x00020000U /*!< Bit 0 */
8086 #define USART_CR3_SCARCNT_1 0x00040000U /*!< Bit 1 */
8087 #define USART_CR3_SCARCNT_2 0x00080000U /*!< Bit 2 */
8088
8089
8090 /****************** Bit definition for USART_BRR register *******************/
8091 #define USART_BRR_DIV_FRACTION 0x000FU /*!< Fraction of USARTDIV */
8092 #define USART_BRR_DIV_MANTISSA 0xFFF0U /*!< Mantissa of USARTDIV */
8093
8094 /****************** Bit definition for USART_GTPR register ******************/
8095 #define USART_GTPR_PSC 0x00FFU /*!< PSC[7:0] bits (Prescaler value) */
8096 #define USART_GTPR_GT 0xFF00U /*!< GT[7:0] bits (Guard time value) */
8097
8098
8099 /******************* Bit definition for USART_RTOR register *****************/
8100 #define USART_RTOR_RTO 0x00FFFFFFU /*!< Receiver Time Out Value */
8101 #define USART_RTOR_BLEN 0xFF000000U /*!< Block Length */
8102
8103 /******************* Bit definition for USART_RQR register ******************/
8104 #define USART_RQR_ABRRQ 0x0001U /*!< Auto-Baud Rate Request */
8105 #define USART_RQR_SBKRQ 0x0002U /*!< Send Break Request */
8106 #define USART_RQR_MMRQ 0x0004U /*!< Mute Mode Request */
8107 #define USART_RQR_RXFRQ 0x0008U /*!< Receive Data flush Request */
8108 #define USART_RQR_TXFRQ 0x0010U /*!< Transmit data flush Request */
8109
8110 /******************* Bit definition for USART_ISR register ******************/
8111 #define USART_ISR_PE 0x00000001U /*!< Parity Error */
8112 #define USART_ISR_FE 0x00000002U /*!< Framing Error */
8113 #define USART_ISR_NE 0x00000004U /*!< Noise detected Flag */
8114 #define USART_ISR_ORE 0x00000008U /*!< OverRun Error */
8115 #define USART_ISR_IDLE 0x00000010U /*!< IDLE line detected */
8116 #define USART_ISR_RXNE 0x00000020U /*!< Read Data Register Not Empty */
8117 #define USART_ISR_TC 0x00000040U /*!< Transmission Complete */
8118 #define USART_ISR_TXE 0x00000080U /*!< Transmit Data Register Empty */
8119 #define USART_ISR_LBDF 0x00000100U /*!< LIN Break Detection Flag */
8120 #define USART_ISR_CTSIF 0x00000200U /*!< CTS interrupt flag */
8121 #define USART_ISR_CTS 0x00000400U /*!< CTS flag */
8122 #define USART_ISR_RTOF 0x00000800U /*!< Receiver Time Out */
8123 #define USART_ISR_EOBF 0x00001000U /*!< End Of Block Flag */
8124 #define USART_ISR_ABRE 0x00004000U /*!< Auto-Baud Rate Error */
8125 #define USART_ISR_ABRF 0x00008000U /*!< Auto-Baud Rate Flag */
8126 #define USART_ISR_BUSY 0x00010000U /*!< Busy Flag */
8127 #define USART_ISR_CMF 0x00020000U /*!< Character Match Flag */
8128 #define USART_ISR_SBKF 0x00040000U /*!< Send Break Flag */
8129 #define USART_ISR_RWU 0x00080000U /*!< Receive Wake Up from mute mode Flag */
8130 #define USART_ISR_WUF 0x00100000U /*!< Wake Up from stop mode Flag */
8131 #define USART_ISR_TEACK 0x00200000U /*!< Transmit Enable Acknowledge Flag */
8132 #define USART_ISR_REACK 0x00400000U /*!< Receive Enable Acknowledge Flag */
8133
8134
8135 /******************* Bit definition for USART_ICR register ******************/
8136 #define USART_ICR_PECF 0x00000001U /*!< Parity Error Clear Flag */
8137 #define USART_ICR_FECF 0x00000002U /*!< Framing Error Clear Flag */
8138 #define USART_ICR_NCF 0x00000004U /*!< Noise detected Clear Flag */
8139 #define USART_ICR_ORECF 0x00000008U /*!< OverRun Error Clear Flag */
8140 #define USART_ICR_IDLECF 0x00000010U /*!< IDLE line detected Clear Flag */
8141 #define USART_ICR_TCCF 0x00000040U /*!< Transmission Complete Clear Flag */
8142 #define USART_ICR_LBDCF 0x00000100U /*!< LIN Break Detection Clear Flag */
8143 #define USART_ICR_CTSCF 0x00000200U /*!< CTS Interrupt Clear Flag */
8144 #define USART_ICR_RTOCF 0x00000800U /*!< Receiver Time Out Clear Flag */
8145 #define USART_ICR_EOBCF 0x00001000U /*!< End Of Block Clear Flag */
8146 #define USART_ICR_CMCF 0x00020000U /*!< Character Match Clear Flag */
8147 #define USART_ICR_WUCF 0x00100000U /*!< Wake Up from stop mode Clear Flag */
8148
8149 /******************* Bit definition for USART_RDR register ******************/
8150 #define USART_RDR_RDR 0x01FFU /*!< RDR[8:0] bits (Receive Data value) */
8151
8152 /******************* Bit definition for USART_TDR register ******************/
8153 #define USART_TDR_TDR 0x01FFU /*!< TDR[8:0] bits (Transmit Data value) */
8154
8155 /******************************************************************************/
8156 /* */
8157 /* Window WATCHDOG */
8158 /* */
8159 /******************************************************************************/
8160 /******************* Bit definition for WWDG_CR register ********************/
8161 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
8162 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
8163 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
8164 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
8165 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
8166 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
8167 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
8168 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
8169
8170
8171 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
8172
8173 /******************* Bit definition for WWDG_CFR register *******************/
8174 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
8175 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
8176 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
8177 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
8178 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
8179 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
8180 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
8181 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
8182
8183
8184 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
8185 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
8186 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
8187
8188
8189 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
8190
8191 /******************* Bit definition for WWDG_SR register ********************/
8192 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
8193
8194 /******************************************************************************/
8195 /* */
8196 /* DBG */
8197 /* */
8198 /******************************************************************************/
8199 /******************** Bit definition for DBGMCU_IDCODE register *************/
8200 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
8201 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
8202
8203 /******************** Bit definition for DBGMCU_CR register *****************/
8204 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
8205 #define DBGMCU_CR_DBG_STOP 0x00000002U
8206 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
8207 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
8208
8209 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
8210 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U /*!<Bit 0 */
8211 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U /*!<Bit 1 */
8212
8213 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
8214 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
8215 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
8216 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
8217 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
8218 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
8219 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
8220 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
8221 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
8222 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
8223 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
8224 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
8225 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
8226 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U
8227 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
8228 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
8229 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
8230 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
8231 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
8232
8233 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
8234 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
8235 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
8236 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
8237 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
8238 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
8239
8240 /******************************************************************************/
8241 /* */
8242 /* Ethernet MAC Registers bits definitions */
8243 /* */
8244 /******************************************************************************/
8245 /* Bit definition for Ethernet MAC Control Register register */
8246 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
8247 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
8248 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
8249 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
8250 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
8251 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
8252 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
8253 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
8254 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
8255 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
8256 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
8257 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
8258 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
8259 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
8260 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
8261 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
8262 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
8263 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
8264 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
8265 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8266 a transmission attempt during retries after a collision: 0 =< r <2^k */
8267 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
8268 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
8269 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
8270 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
8271 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
8272 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
8273 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
8274
8275 /* Bit definition for Ethernet MAC Frame Filter Register */
8276 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
8277 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
8278 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
8279 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
8280 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
8281 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
8282 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
8283 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
8284 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
8285 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
8286 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
8287 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
8288 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
8289 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
8290
8291 /* Bit definition for Ethernet MAC Hash Table High Register */
8292 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
8293
8294 /* Bit definition for Ethernet MAC Hash Table Low Register */
8295 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
8296
8297 /* Bit definition for Ethernet MAC MII Address Register */
8298 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
8299 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
8300 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
8301 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8302 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8303 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8304 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8305 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8306 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
8307 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
8308
8309 /* Bit definition for Ethernet MAC MII Data Register */
8310 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
8311
8312 /* Bit definition for Ethernet MAC Flow Control Register */
8313 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
8314 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
8315 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
8316 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
8317 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
8318 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
8319 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
8320 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
8321 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
8322 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
8323 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
8324
8325 /* Bit definition for Ethernet MAC VLAN Tag Register */
8326 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
8327 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
8328
8329 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
8330 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
8331 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
8332 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
8333 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
8334 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
8335 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
8336 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
8337 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
8338 RSVD - Filter1 Command - RSVD - Filter0 Command
8339 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
8340 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
8341 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
8342
8343 /* Bit definition for Ethernet MAC PMT Control and Status Register */
8344 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
8345 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
8346 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
8347 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
8348 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
8349 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
8350 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
8351
8352 /* Bit definition for Ethernet MAC Status Register */
8353 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
8354 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
8355 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
8356 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
8357 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
8358
8359 /* Bit definition for Ethernet MAC Interrupt Mask Register */
8360 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
8361 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
8362
8363 /* Bit definition for Ethernet MAC Address0 High Register */
8364 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
8365
8366 /* Bit definition for Ethernet MAC Address0 Low Register */
8367 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
8368
8369 /* Bit definition for Ethernet MAC Address1 High Register */
8370 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
8371 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
8372 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8373 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8374 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8375 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8376 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8377 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8378 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
8379 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
8380
8381 /* Bit definition for Ethernet MAC Address1 Low Register */
8382 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
8383
8384 /* Bit definition for Ethernet MAC Address2 High Register */
8385 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
8386 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
8387 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
8388 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8389 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8390 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8391 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8392 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8393 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8394 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
8395
8396 /* Bit definition for Ethernet MAC Address2 Low Register */
8397 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
8398
8399 /* Bit definition for Ethernet MAC Address3 High Register */
8400 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
8401 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
8402 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
8403 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8404 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8405 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8406 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8407 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8408 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8409 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
8410
8411 /* Bit definition for Ethernet MAC Address3 Low Register */
8412 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
8413
8414 /******************************************************************************/
8415 /* Ethernet MMC Registers bits definition */
8416 /******************************************************************************/
8417
8418 /* Bit definition for Ethernet MMC Contol Register */
8419 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
8420 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
8421 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
8422 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
8423 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
8424 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
8425
8426 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8427 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
8428 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
8429 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
8430
8431 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8432 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
8433 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
8434 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
8435
8436 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8437 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8438 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8439 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8440
8441 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8442 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8443 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8444 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8445
8446 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8447 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8448
8449 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8450 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8451
8452 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8453 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
8454
8455 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8456 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
8457
8458 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8459 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
8460
8461 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8462 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
8463
8464 /******************************************************************************/
8465 /* Ethernet PTP Registers bits definition */
8466 /******************************************************************************/
8467
8468 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8469 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
8470 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
8471 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
8472 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
8473 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
8474 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
8475 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
8476 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
8477 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
8478
8479 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
8480 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
8481 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
8482 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
8483 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
8484 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
8485
8486 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8487 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
8488
8489 /* Bit definition for Ethernet PTP Time Stamp High Register */
8490 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
8491
8492 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8493 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
8494 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
8495
8496 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8497 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
8498
8499 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8500 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
8501 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
8502
8503 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8504 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
8505
8506 /* Bit definition for Ethernet PTP Target Time High Register */
8507 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
8508
8509 /* Bit definition for Ethernet PTP Target Time Low Register */
8510 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
8511
8512 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8513 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
8514 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
8515
8516 /******************************************************************************/
8517 /* Ethernet DMA Registers bits definition */
8518 /******************************************************************************/
8519
8520 /* Bit definition for Ethernet DMA Bus Mode Register */
8521 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
8522 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
8523 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
8524 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
8525 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8526 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8527 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8528 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8529 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8530 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8531 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8532 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8533 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8534 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8535 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8536 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8537 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
8538 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
8539 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
8540 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
8541 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
8542 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
8543 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
8544 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8545 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8546 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8547 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8548 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8549 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8550 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8551 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8552 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8553 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8554 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8555 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8556 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
8557 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
8558 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
8559 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
8560
8561 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8562 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
8563
8564 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
8565 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
8566
8567 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8568 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
8569
8570 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8571 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
8572
8573 /* Bit definition for Ethernet DMA Status Register */
8574 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
8575 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
8576 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
8577 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
8578 /* combination with EBS[2:0] for GetFlagStatus function */
8579 #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
8580 #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
8581 #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
8582 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
8583 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
8584 #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
8585 #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
8586 #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
8587 #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
8588 #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
8589 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
8590 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
8591 #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
8592 #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
8593 #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
8594 #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
8595 #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
8596 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
8597 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
8598 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
8599 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
8600 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
8601 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
8602 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
8603 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
8604 #define ETH_DMASR_RS 0x00000040U /* Receive status */
8605 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
8606 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
8607 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
8608 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
8609 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
8610 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
8611
8612 /* Bit definition for Ethernet DMA Operation Mode Register */
8613 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
8614 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
8615 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
8616 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
8617 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
8618 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
8619 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8620 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8621 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8622 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8623 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8624 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8625 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8626 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8627 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
8628 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
8629 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
8630 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
8631 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
8632 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
8633 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
8634 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
8635 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
8636 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
8637
8638 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8639 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
8640 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
8641 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
8642 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
8643 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
8644 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
8645 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
8646 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
8647 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
8648 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
8649 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
8650 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
8651 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
8652 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
8653 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
8654
8655 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8656 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8657 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8658 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8659 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8660
8661 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8662 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8663
8664 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8665 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8666
8667 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8668 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8669
8670 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8671 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8672
8673 /******************************************************************************/
8674 /* */
8675 /* USB_OTG */
8676 /* */
8677 /******************************************************************************/
8678 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8679 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
8680 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
8681 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
8682 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
8683 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
8684 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
8685 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
8686 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
8687 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
8688 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
8689 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
8690 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
8691 #define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
8692 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
8693 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
8694 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
8695 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
8696 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
8697
8698 /******************** Bit definition for USB_OTG_HCFG register ********************/
8699 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
8700 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
8701 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
8702 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
8703
8704 /******************** Bit definition for USB_OTG_DCFG register ********************/
8705 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
8706 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
8707 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
8708 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
8709
8710 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
8711 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
8712 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
8713 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
8714 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
8715 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
8716 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
8717 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
8718
8719 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
8720 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
8721 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
8722
8723 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
8724 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
8725 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
8726
8727 /******************** Bit definition for USB_OTG_PCGCR register ********************/
8728 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
8729 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
8730 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
8731
8732 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
8733 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
8734 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
8735 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
8736 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
8737 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
8738 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
8739 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
8740
8741 /******************** Bit definition for USB_OTG_DCTL register ********************/
8742 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
8743 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
8744 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
8745 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
8746
8747 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
8748 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
8749 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
8750 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
8751 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
8752 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
8753 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
8754 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
8755 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
8756
8757 /******************** Bit definition for USB_OTG_HFIR register ********************/
8758 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
8759
8760 /******************** Bit definition for USB_OTG_HFNUM register ********************/
8761 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
8762 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
8763
8764 /******************** Bit definition for USB_OTG_DSTS register ********************/
8765 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
8766
8767 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
8768 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
8769 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
8770 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
8771 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
8772
8773 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8774 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
8775 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
8776 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
8777 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
8778 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
8779 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
8780 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
8781 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
8782 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
8783
8784 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8785 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
8786 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
8787 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
8788 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
8789 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
8790 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
8791 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
8792 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
8793 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
8794 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
8795 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
8796 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
8797 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
8798 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
8799 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
8800 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
8801 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
8802 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
8803 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
8804 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
8805 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
8806 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
8807 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
8808 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
8809 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
8810
8811 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8812 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
8813 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
8814 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
8815 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
8816 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
8817 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
8818 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
8819 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
8820 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
8821 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
8822 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
8823 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
8824 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
8825
8826 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8827 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
8828 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
8829 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
8830 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
8831 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
8832 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
8833 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
8834 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
8835
8836 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8837 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
8838 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
8839 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
8840 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
8841 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
8842 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
8843 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
8844 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
8845 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
8846 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
8847
8848 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
8849 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
8850 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
8851 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
8852 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
8853 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
8854 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
8855 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
8856 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
8857
8858 /******************** Bit definition for USB_OTG_HAINT register ********************/
8859 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
8860
8861 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8862 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
8863 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
8864 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
8865 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
8866 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
8867 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
8868 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
8869 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
8870
8871 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
8872 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
8873 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
8874 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
8875 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
8876 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
8877 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
8878 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
8879 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
8880 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
8881 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
8882 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
8883 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
8884 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
8885 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
8886 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
8887 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
8888 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
8889 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
8890 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
8891 #define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
8892 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
8893 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
8894 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
8895 #define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
8896 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
8897 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
8898 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
8899 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
8900
8901 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
8902 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
8903 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
8904 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
8905 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
8906 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
8907 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
8908 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
8909 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
8910 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
8911 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
8912 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
8913 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
8914 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
8915 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
8916 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
8917 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
8918 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
8919 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
8920 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
8921 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
8922 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
8923 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
8924 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
8925 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
8926 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
8927 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
8928 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
8929 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
8930
8931 /******************** Bit definition for USB_OTG_DAINT register ********************/
8932 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
8933 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
8934
8935 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
8936 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
8937
8938 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8939 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
8940 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
8941 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
8942 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
8943
8944 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
8945 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
8946 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
8947
8948 /******************** Bit definition for OTG register ********************/
8949
8950 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
8951 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
8952 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
8953 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
8954 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
8955 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
8956
8957 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
8958 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
8959 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
8960
8961 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
8962 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
8963 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
8964 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
8965 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
8966
8967 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
8968 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
8969 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
8970 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
8971 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
8972
8973 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
8974 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
8975 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
8976 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
8977 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
8978
8979 /******************** Bit definition for OTG register ********************/
8980
8981 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
8982 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
8983 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
8984 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
8985 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
8986 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
8987
8988 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
8989 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
8990 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
8991
8992 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
8993 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
8994 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
8995 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
8996 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
8997
8998 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
8999 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
9000 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
9001 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
9002 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
9003
9004 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
9005 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
9006 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
9007 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
9008 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
9009
9010 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
9011 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
9012
9013 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
9014 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
9015
9016 /******************** Bit definition for OTG register ********************/
9017 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
9018 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
9019 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
9020 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
9021
9022 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
9023 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
9024
9025 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
9026 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
9027
9028 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
9029 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
9030 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
9031 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
9032 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
9033 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
9034 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
9035 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
9036 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
9037
9038 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
9039 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
9040 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
9041 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
9042 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
9043 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
9044 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
9045 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
9046
9047 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
9048 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
9049 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
9050
9051 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
9052 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
9053 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
9054 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
9055 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
9056 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
9057 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
9058 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
9059 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
9060 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
9061 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
9062
9063 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
9064 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
9065 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
9066 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
9067 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
9068 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
9069 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
9070 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
9071 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
9072 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
9073 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
9074
9075 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
9076 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
9077
9078 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
9079 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
9080 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
9081
9082 /******************** Bit definition for USB_OTG_GCCFG register ********************/
9083 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
9084 #define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
9085
9086 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
9087 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U /*!< ADP module enable */
9088 #define USB_OTG_GPWRDN_ADPIF 0x00800000U /*!< ADP Interrupt flag */
9089
9090 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
9091 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
9092 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
9093
9094 /******************** Bit definition for USB_OTG_CID register ********************/
9095 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
9096
9097 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
9098 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
9099 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
9100 #define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
9101 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
9102 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
9103 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
9104 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
9105 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
9106 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
9107 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
9108 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
9109 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
9110 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
9111 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
9112 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
9113
9114 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
9115 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
9116 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
9117 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
9118 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
9119 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
9120 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
9121 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
9122 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
9123 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
9124
9125 /******************** Bit definition for USB_OTG_HPRT register ********************/
9126 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
9127 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
9128 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
9129 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
9130 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
9131 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
9132 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
9133 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
9134 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
9135
9136 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
9137 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
9138 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
9139 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
9140
9141 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
9142 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
9143 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
9144 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
9145 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
9146
9147 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
9148 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
9149 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
9150
9151 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
9152 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
9153 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
9154 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
9155 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
9156 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
9157 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
9158 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
9159 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
9160 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
9161 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
9162 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
9163
9164 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
9165 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
9166 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
9167
9168 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
9169 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
9170 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
9171 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
9172 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
9173
9174 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
9175 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
9176 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
9177 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
9178
9179 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
9180 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
9181 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
9182 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
9183 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
9184 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
9185 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
9186 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
9187 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
9188 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
9189 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
9190
9191 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
9192 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
9193
9194 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
9195 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
9196 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
9197 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
9198 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
9199 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
9200 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
9201
9202 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
9203 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
9204 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
9205
9206 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
9207 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
9208 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
9209
9210 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
9211 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
9212 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
9213 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
9214 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
9215 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
9216 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
9217 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
9218 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
9219 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
9220 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
9221
9222 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
9223
9224 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
9225 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
9226 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
9227 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
9228 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
9229 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
9230 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
9231 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
9232
9233 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
9234 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
9235 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
9236 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
9237 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
9238 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
9239 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
9240 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
9241
9242 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
9243 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
9244 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
9245 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
9246 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
9247
9248 /******************** Bit definition for USB_OTG_HCINT register ********************/
9249 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
9250 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
9251 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
9252 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
9253 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
9254 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
9255 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
9256 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
9257 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
9258 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
9259 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
9260
9261 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
9262 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
9263 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
9264 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
9265 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
9266 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
9267 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
9268 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
9269 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
9270 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
9271 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
9272 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
9273
9274 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
9275 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
9276 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
9277 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
9278 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
9279 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
9280 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
9281 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
9282 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
9283 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
9284 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
9285 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
9286
9287 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
9288
9289 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
9290 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
9291 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
9292 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
9293 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
9294 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
9295 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
9296 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
9297 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
9298 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
9299
9300 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
9301 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
9302
9303 /******************** Bit definition for USB_OTG_HCDMA register ********************/
9304 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
9305
9306 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
9307 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
9308
9309 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
9310 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
9311 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
9312
9313 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
9314 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
9315 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
9316 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
9317 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
9318 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
9319 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
9320 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
9321 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
9322 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
9323 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
9324 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
9325 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
9326 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
9327 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
9328
9329 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
9330 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
9331 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
9332 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
9333 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
9334 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
9335 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
9336 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
9337
9338 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
9339 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
9340 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
9341
9342 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
9343 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
9344 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
9345
9346 /******************** Bit definition for PCGCCTL register ********************/
9347 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
9348 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
9349 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
9350
9351 /******************************************************************************/
9352 /* */
9353 /* JPEG Encoder/Decoder */
9354 /* */
9355 /******************************************************************************/
9356 /******************** Bit definition for CONFR0 register ********************/
9357 #define JPEG_CONFR0_START 0x00000001U /*!<Start/Stop bit */
9358
9359 /******************** Bit definition for CONFR1 register *******************/
9360 #define JPEG_CONFR1_NF 0x00000003U /*!<Number of color components */
9361 #define JPEG_CONFR1_NF_0 0x00000001U /*!<Bit 0 */
9362 #define JPEG_CONFR1_NF_1 0x00000002U /*!<Bit 1 */
9363 #define JPEG_CONFR1_RE 0x00000004U /*!<Restart maker Enable */
9364 #define JPEG_CONFR1_DE 0x00000008U /*!<Decoding Enable */
9365 #define JPEG_CONFR1_COLORSPACE 0x00000030U /*!<Color Space */
9366 #define JPEG_CONFR1_COLORSPACE_0 0x00000010U /*!<Bit 0 */
9367 #define JPEG_CONFR1_COLORSPACE_1 0x00000020U /*!<Bit 1 */
9368 #define JPEG_CONFR1_NS 0x000000C0U /*!<Number of components for Scan */
9369 #define JPEG_CONFR1_NS_0 0x00000040U /*!<Bit 0 */
9370 #define JPEG_CONFR1_NS_1 0x00000080U /*!<Bit 1 */
9371 #define JPEG_CONFR1_HDR 0x00000100U /*!<Header Processing On/Off */
9372 #define JPEG_CONFR1_YSIZE 0xFFFF0000U /*!<Number of lines in source image */
9373
9374 /******************** Bit definition for CONFR2 register *******************/
9375 #define JPEG_CONFR2_NMCU 0x03FFFFFFU /*!<Number of MCU units minus 1 to encode */
9376
9377 /******************** Bit definition for CONFR3 register *******************/
9378 #define JPEG_CONFR3_NRST 0x0000FFFFU /*!<Number of MCU between two restart makers minus 1 */
9379 #define JPEG_CONFR3_XSIZE 0xFFFF0000U /*!<Number of pixels per line */
9380
9381 /******************** Bit definition for CONFR4 register *******************/
9382 #define JPEG_CONFR4_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
9383 #define JPEG_CONFR4_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
9384 #define JPEG_CONFR4_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
9385 #define JPEG_CONFR4_QT_0 0x00000004U /*!<Bit 0 */
9386 #define JPEG_CONFR4_QT_1 0x00000008U /*!<Bit 1 */
9387 #define JPEG_CONFR4_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
9388 #define JPEG_CONFR4_NB_0 0x00000010U /*!<Bit 0 */
9389 #define JPEG_CONFR4_NB_1 0x00000020U /*!<Bit 1 */
9390 #define JPEG_CONFR4_NB_2 0x00000040U /*!<Bit 2 */
9391 #define JPEG_CONFR4_NB_3 0x00000080U /*!<Bit 3 */
9392 #define JPEG_CONFR4_VSF 0x00000F00U /*!<Vertical sampling factor for component 1 */
9393 #define JPEG_CONFR4_VSF_0 0x00000100U /*!<Bit 0 */
9394 #define JPEG_CONFR4_VSF_1 0x00000200U /*!<Bit 1 */
9395 #define JPEG_CONFR4_VSF_2 0x00000400U /*!<Bit 2 */
9396 #define JPEG_CONFR4_VSF_3 0x00000800U /*!<Bit 3 */
9397 #define JPEG_CONFR4_HSF 0x0000F000U /*!<Horizontal sampling factor for component 1 */
9398 #define JPEG_CONFR4_HSF_0 0x00001000U /*!<Bit 0 */
9399 #define JPEG_CONFR4_HSF_1 0x00002000U /*!<Bit 1 */
9400 #define JPEG_CONFR4_HSF_2 0x00004000U /*!<Bit 2 */
9401 #define JPEG_CONFR4_HSF_3 0x00008000U /*!<Bit 3 */
9402
9403 /******************** Bit definition for CONFR5 register *******************/
9404 #define JPEG_CONFR5_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
9405 #define JPEG_CONFR5_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
9406 #define JPEG_CONFR5_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
9407 #define JPEG_CONFR5_QT_0 0x00000004U /*!<Bit 0 */
9408 #define JPEG_CONFR5_QT_1 0x00000008U /*!<Bit 1 */
9409 #define JPEG_CONFR5_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
9410 #define JPEG_CONFR5_NB_0 0x00000010U /*!<Bit 0 */
9411 #define JPEG_CONFR5_NB_1 0x00000020U /*!<Bit 1 */
9412 #define JPEG_CONFR5_NB_2 0x00000040U /*!<Bit 2 */
9413 #define JPEG_CONFR5_NB_3 0x00000080U /*!<Bit 3 */
9414 #define JPEG_CONFR5_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
9415 #define JPEG_CONFR5_VSF_0 0x00000100U /*!<Bit 0 */
9416 #define JPEG_CONFR5_VSF_1 0x00000200U /*!<Bit 1 */
9417 #define JPEG_CONFR5_VSF_2 0x00000400U /*!<Bit 2 */
9418 #define JPEG_CONFR5_VSF_3 0x00000800U /*!<Bit 3 */
9419 #define JPEG_CONFR5_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
9420 #define JPEG_CONFR5_HSF_0 0x00001000U /*!<Bit 0 */
9421 #define JPEG_CONFR5_HSF_1 0x00002000U /*!<Bit 1 */
9422 #define JPEG_CONFR5_HSF_2 0x00004000U /*!<Bit 2 */
9423 #define JPEG_CONFR5_HSF_3 0x00008000U /*!<Bit 3 */
9424
9425 /******************** Bit definition for CONFR6 register *******************/
9426 #define JPEG_CONFR6_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
9427 #define JPEG_CONFR6_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
9428 #define JPEG_CONFR6_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
9429 #define JPEG_CONFR6_QT_0 0x00000004U /*!<Bit 0 */
9430 #define JPEG_CONFR6_QT_1 0x00000008U /*!<Bit 1 */
9431 #define JPEG_CONFR6_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
9432 #define JPEG_CONFR6_NB_0 0x00000010U /*!<Bit 0 */
9433 #define JPEG_CONFR6_NB_1 0x00000020U /*!<Bit 1 */
9434 #define JPEG_CONFR6_NB_2 0x00000040U /*!<Bit 2 */
9435 #define JPEG_CONFR6_NB_3 0x00000080U /*!<Bit 3 */
9436 #define JPEG_CONFR6_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
9437 #define JPEG_CONFR6_VSF_0 0x00000100U /*!<Bit 0 */
9438 #define JPEG_CONFR6_VSF_1 0x00000200U /*!<Bit 1 */
9439 #define JPEG_CONFR6_VSF_2 0x00000400U /*!<Bit 2 */
9440 #define JPEG_CONFR6_VSF_3 0x00000800U /*!<Bit 3 */
9441 #define JPEG_CONFR6_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
9442 #define JPEG_CONFR6_HSF_0 0x00001000U /*!<Bit 0 */
9443 #define JPEG_CONFR6_HSF_1 0x00002000U /*!<Bit 1 */
9444 #define JPEG_CONFR6_HSF_2 0x00004000U /*!<Bit 2 */
9445 #define JPEG_CONFR6_HSF_3 0x00008000U /*!<Bit 3 */
9446
9447 /******************** Bit definition for CONFR7 register *******************/
9448 #define JPEG_CONFR7_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
9449 #define JPEG_CONFR7_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
9450 #define JPEG_CONFR7_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
9451 #define JPEG_CONFR7_QT_0 0x00000004U /*!<Bit 0 */
9452 #define JPEG_CONFR7_QT_1 0x00000008U /*!<Bit 1 */
9453 #define JPEG_CONFR7_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
9454 #define JPEG_CONFR7_NB_0 0x00000010U /*!<Bit 0 */
9455 #define JPEG_CONFR7_NB_1 0x00000020U /*!<Bit 1 */
9456 #define JPEG_CONFR7_NB_2 0x00000040U /*!<Bit 2 */
9457 #define JPEG_CONFR7_NB_3 0x00000080U /*!<Bit 3 */
9458 #define JPEG_CONFR7_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
9459 #define JPEG_CONFR7_VSF_0 0x00000100U /*!<Bit 0 */
9460 #define JPEG_CONFR7_VSF_1 0x00000200U /*!<Bit 1 */
9461 #define JPEG_CONFR7_VSF_2 0x00000400U /*!<Bit 2 */
9462 #define JPEG_CONFR7_VSF_3 0x00000800U /*!<Bit 3 */
9463 #define JPEG_CONFR7_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
9464 #define JPEG_CONFR7_HSF_0 0x00001000U /*!<Bit 0 */
9465 #define JPEG_CONFR7_HSF_1 0x00002000U /*!<Bit 1 */
9466 #define JPEG_CONFR7_HSF_2 0x00004000U /*!<Bit 2 */
9467 #define JPEG_CONFR7_HSF_3 0x00008000U /*!<Bit 3 */
9468
9469 /******************** Bit definition for CR register *******************/
9470 #define JPEG_CR_JCEN 0x00000001U /*!<Enable the JPEG Codec Core */
9471 #define JPEG_CR_IFTIE 0x00000002U /*!<Input FIFO Threshold Interrupt Enable */
9472 #define JPEG_CR_IFNFIE 0x00000004U /*!<Input FIFO Not Full Interrupt Enable */
9473 #define JPEG_CR_OFTIE 0x00000008U /*!<Output FIFO Threshold Interrupt Enable */
9474 #define JPEG_CR_OFNEIE 0x00000010U /*!<Output FIFO Not Empty Interrupt Enable */
9475 #define JPEG_CR_EOCIE 0x00000020U /*!<End of Conversion Interrupt Enable */
9476 #define JPEG_CR_HPDIE 0x00000040U /*!<Header Parsing Done Interrupt Enable */
9477 #define JPEG_CR_IDMAEN 0x00000800U /*!<Enable the DMA request generation for the input FIFO */
9478 #define JPEG_CR_ODMAEN 0x00001000U /*!<Enable the DMA request generation for the output FIFO */
9479 #define JPEG_CR_IFF 0x00002000U /*!<Flush the input FIFO */
9480 #define JPEG_CR_OFF 0x00004000U /*!<Flush the output FIFO */
9481
9482 /******************** Bit definition for SR register *******************/
9483 #define JPEG_SR_IFTF 0x00000002U /*!<Input FIFO is not full and is bellow its threshold flag */
9484 #define JPEG_SR_IFNFF 0x00000004U /*!<Input FIFO Not Full Flag, a data can be written */
9485 #define JPEG_SR_OFTF 0x00000008U /*!<Output FIFO is not empty and has reach its threshold */
9486 #define JPEG_SR_OFNEF 0x000000010U /*!<Output FIFO is not empty, a data is available */
9487 #define JPEG_SR_EOCF 0x000000020U /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
9488 #define JPEG_SR_HPDF 0x000000040U /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
9489 #define JPEG_SR_COF 0x000000080U /*!<JPEG Codec operation on going flag */
9490
9491 /******************** Bit definition for CFR register *******************/
9492 #define JPEG_CFR_CEOCF 0x00000020U /*!<Clear End of Conversion Flag */
9493 #define JPEG_CFR_CHPDF 0x00000040U /*!<Clear Header Parsing Done Flag */
9494
9495 /******************** Bit definition for DIR register ********************/
9496 #define JPEG_DIR_DATAIN 0xFFFFFFFFU /*!<Data Input FIFO */
9497
9498 /******************** Bit definition for DOR register ********************/
9499 #define JPEG_DOR_DATAOUT 0xFFFFFFFFU /*!<Data Output FIFO */
9500
9501 /******************************************************************************/
9502 /* */
9503 /* MDIOS */
9504 /* */
9505 /******************************************************************************/
9506 /******************** Bit definition for MDIOS_CR register *******************/
9507 #define MDIOS_CR_EN 0x00000001U /*!<Peripheral enable */
9508 #define MDIOS_CR_WRIE 0x00000002U /*!<Register write interrupt enable */
9509 #define MDIOS_CR_RDIE 0x00000004U /*!<Register Read Interrupt Enable */
9510 #define MDIOS_CR_EIE 0x00000008U /*!<Error interrupt enable */
9511 #define MDIOS_CR_DPC 0x00000080U /*!<Disable Preamble Check */
9512 #define MDIOS_CR_PORT_ADDRESS 0x00001F00U /*!<PORT_ADDRESS[4:0] bits */
9513 #define MDIOS_CR_PORT_ADDRESS_0 0x00000100U /*!<Bit 0 */
9514 #define MDIOS_CR_PORT_ADDRESS_1 0x00000200U /*!<Bit 1 */
9515 #define MDIOS_CR_PORT_ADDRESS_2 0x00000400U /*!<Bit 2 */
9516 #define MDIOS_CR_PORT_ADDRESS_3 0x00000800U /*!<Bit 3 */
9517 #define MDIOS_CR_PORT_ADDRESS_4 0x00001000U /*!<Bit 4 */
9518
9519 /******************** Bit definition for MDIOS_WRFR register *******************/
9520 #define MDIOS_WRFR_WRF 0xFFFFFFFFU /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
9521
9522 /******************** Bit definition for MDIOS_CWRFR register *******************/
9523 #define MDIOS_CWRFR_CWRF 0xFFFFFFFFU /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
9524
9525 /******************** Bit definition for MDIOS_RDFR register *******************/
9526 #define MDIOS_RDFR_RDF 0xFFFFFFFFU /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
9527
9528 /******************** Bit definition for MDIOS_CRDFR register *******************/
9529 #define MDIOS_CRDFR_CRDF 0xFFFFFFFFU /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
9530
9531 /******************** Bit definition for MDIOS_SR register *******************/
9532 #define MDIOS_SR_PERF 0x00000001U /*!< Preamble error flag */
9533 #define MDIOS_SR_SERF 0x00000002U /*!< Start error flag */
9534 #define MDIOS_SR_TERF 0x00000004U /*!< Turnaround error flag */
9535
9536 /******************** Bit definition for MDIOS_CLRFR register *******************/
9537 #define MDIOS_CLRFR_CPERF 0x00000001U /*!< Clear the preamble error flag */
9538 #define MDIOS_CLRFR_CSERF 0x00000002U /*!< Clear the start error flag */
9539 #define MDIOS_CLRFR_CTERF 0x00000004U /*!< Clear the turnaround error flag */
9540
9541 /**
9542 * @}
9543 */
9544
9545 /**
9546 * @}
9547 */
9548
9549 /** @addtogroup Exported_macros
9550 * @{
9551 */
9552
9553 /******************************* ADC Instances ********************************/
9554 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
9555 ((__INSTANCE__) == ADC2) || \
9556 ((__INSTANCE__) == ADC3))
9557
9558 /******************************* CAN Instances ********************************/
9559 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
9560 ((__INSTANCE__) == CAN2) || \
9561 ((__INSTANCE__) == CAN3))
9562 /******************************* CRC Instances ********************************/
9563 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
9564
9565 /******************************* DAC Instances ********************************/
9566 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
9567
9568 /******************************* DCMI Instances *******************************/
9569 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
9570
9571 /****************************** DFSDM Instances *******************************/
9572 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
9573 ((INSTANCE) == DFSDM1_Filter1) || \
9574 ((INSTANCE) == DFSDM1_Filter2) || \
9575 ((INSTANCE) == DFSDM1_Filter3))
9576
9577 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
9578 ((INSTANCE) == DFSDM1_Channel1) || \
9579 ((INSTANCE) == DFSDM1_Channel2) || \
9580 ((INSTANCE) == DFSDM1_Channel3) || \
9581 ((INSTANCE) == DFSDM1_Channel4) || \
9582 ((INSTANCE) == DFSDM1_Channel5) || \
9583 ((INSTANCE) == DFSDM1_Channel6) || \
9584 ((INSTANCE) == DFSDM1_Channel7))
9585
9586 /******************************* DMA2D Instances *******************************/
9587 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
9588
9589 /******************************** DMA Instances *******************************/
9590 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
9591 ((__INSTANCE__) == DMA1_Stream1) || \
9592 ((__INSTANCE__) == DMA1_Stream2) || \
9593 ((__INSTANCE__) == DMA1_Stream3) || \
9594 ((__INSTANCE__) == DMA1_Stream4) || \
9595 ((__INSTANCE__) == DMA1_Stream5) || \
9596 ((__INSTANCE__) == DMA1_Stream6) || \
9597 ((__INSTANCE__) == DMA1_Stream7) || \
9598 ((__INSTANCE__) == DMA2_Stream0) || \
9599 ((__INSTANCE__) == DMA2_Stream1) || \
9600 ((__INSTANCE__) == DMA2_Stream2) || \
9601 ((__INSTANCE__) == DMA2_Stream3) || \
9602 ((__INSTANCE__) == DMA2_Stream4) || \
9603 ((__INSTANCE__) == DMA2_Stream5) || \
9604 ((__INSTANCE__) == DMA2_Stream6) || \
9605 ((__INSTANCE__) == DMA2_Stream7))
9606
9607 /******************************* GPIO Instances *******************************/
9608 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9609 ((__INSTANCE__) == GPIOB) || \
9610 ((__INSTANCE__) == GPIOC) || \
9611 ((__INSTANCE__) == GPIOD) || \
9612 ((__INSTANCE__) == GPIOE) || \
9613 ((__INSTANCE__) == GPIOF) || \
9614 ((__INSTANCE__) == GPIOG) || \
9615 ((__INSTANCE__) == GPIOH) || \
9616 ((__INSTANCE__) == GPIOI) || \
9617 ((__INSTANCE__) == GPIOJ) || \
9618 ((__INSTANCE__) == GPIOK))
9619
9620 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9621 ((__INSTANCE__) == GPIOB) || \
9622 ((__INSTANCE__) == GPIOC) || \
9623 ((__INSTANCE__) == GPIOD) || \
9624 ((__INSTANCE__) == GPIOE) || \
9625 ((__INSTANCE__) == GPIOF) || \
9626 ((__INSTANCE__) == GPIOG) || \
9627 ((__INSTANCE__) == GPIOH) || \
9628 ((__INSTANCE__) == GPIOI) || \
9629 ((__INSTANCE__) == GPIOJ) || \
9630 ((__INSTANCE__) == GPIOK))
9631
9632 /****************************** CEC Instances *********************************/
9633 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
9634
9635 /****************************** QSPI Instances *********************************/
9636 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
9637
9638
9639 /******************************** I2C Instances *******************************/
9640 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
9641 ((__INSTANCE__) == I2C2) || \
9642 ((__INSTANCE__) == I2C3) || \
9643 ((__INSTANCE__) == I2C4))
9644
9645 /******************************** I2S Instances *******************************/
9646 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9647 ((__INSTANCE__) == SPI2) || \
9648 ((__INSTANCE__) == SPI3))
9649
9650 /******************************* LPTIM Instances ********************************/
9651 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
9652
9653 /****************************** LTDC Instances ********************************/
9654 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
9655
9656 /****************************** MDIOS Instances ********************************/
9657 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
9658
9659 /****************************** MDIOS Instances ********************************/
9660 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
9661
9662 /******************************* RNG Instances ********************************/
9663 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
9664
9665 /****************************** RTC Instances *********************************/
9666 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
9667
9668 /******************************* SAI Instances ********************************/
9669 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
9670 ((__PERIPH__) == SAI1_Block_B) || \
9671 ((__PERIPH__) == SAI2_Block_A) || \
9672 ((__PERIPH__) == SAI2_Block_B))
9673 /* Legacy define */
9674 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
9675
9676 /******************************** SDMMC Instances *******************************/
9677 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
9678 ((__INSTANCE__) == SDMMC2))
9679
9680 /****************************** SPDIFRX Instances *********************************/
9681 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
9682
9683 /******************************** SPI Instances *******************************/
9684 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9685 ((__INSTANCE__) == SPI2) || \
9686 ((__INSTANCE__) == SPI3) || \
9687 ((__INSTANCE__) == SPI4) || \
9688 ((__INSTANCE__) == SPI5) || \
9689 ((__INSTANCE__) == SPI6))
9690
9691 /****************** TIM Instances : All supported instances *******************/
9692 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9693 ((__INSTANCE__) == TIM2) || \
9694 ((__INSTANCE__) == TIM3) || \
9695 ((__INSTANCE__) == TIM4) || \
9696 ((__INSTANCE__) == TIM5) || \
9697 ((__INSTANCE__) == TIM6) || \
9698 ((__INSTANCE__) == TIM7) || \
9699 ((__INSTANCE__) == TIM8) || \
9700 ((__INSTANCE__) == TIM9) || \
9701 ((__INSTANCE__) == TIM10) || \
9702 ((__INSTANCE__) == TIM11) || \
9703 ((__INSTANCE__) == TIM12) || \
9704 ((__INSTANCE__) == TIM13) || \
9705 ((__INSTANCE__) == TIM14))
9706
9707 /************* TIM Instances : at least 1 capture/compare channel *************/
9708 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9709 ((__INSTANCE__) == TIM2) || \
9710 ((__INSTANCE__) == TIM3) || \
9711 ((__INSTANCE__) == TIM4) || \
9712 ((__INSTANCE__) == TIM5) || \
9713 ((__INSTANCE__) == TIM8) || \
9714 ((__INSTANCE__) == TIM9) || \
9715 ((__INSTANCE__) == TIM10) || \
9716 ((__INSTANCE__) == TIM11) || \
9717 ((__INSTANCE__) == TIM12) || \
9718 ((__INSTANCE__) == TIM13) || \
9719 ((__INSTANCE__) == TIM14))
9720
9721 /************ TIM Instances : at least 2 capture/compare channels *************/
9722 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9723 ((__INSTANCE__) == TIM2) || \
9724 ((__INSTANCE__) == TIM3) || \
9725 ((__INSTANCE__) == TIM4) || \
9726 ((__INSTANCE__) == TIM5) || \
9727 ((__INSTANCE__) == TIM8) || \
9728 ((__INSTANCE__) == TIM9) || \
9729 ((__INSTANCE__) == TIM12))
9730
9731 /************ TIM Instances : at least 3 capture/compare channels *************/
9732 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9733 ((__INSTANCE__) == TIM2) || \
9734 ((__INSTANCE__) == TIM3) || \
9735 ((__INSTANCE__) == TIM4) || \
9736 ((__INSTANCE__) == TIM5) || \
9737 ((__INSTANCE__) == TIM8))
9738
9739 /************ TIM Instances : at least 4 capture/compare channels *************/
9740 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9741 ((__INSTANCE__) == TIM2) || \
9742 ((__INSTANCE__) == TIM3) || \
9743 ((__INSTANCE__) == TIM4) || \
9744 ((__INSTANCE__) == TIM5) || \
9745 ((__INSTANCE__) == TIM8))
9746
9747 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9748 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
9749 (((__INSTANCE__) == TIM1) || \
9750 ((__INSTANCE__) == TIM8))
9751
9752 /****************** TIM Instances : supporting OCxREF clear *******************/
9753 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
9754 (((__INSTANCE__) == TIM1) || \
9755 ((__INSTANCE__) == TIM2) || \
9756 ((__INSTANCE__) == TIM3) || \
9757 ((__INSTANCE__) == TIM4) || \
9758 ((__INSTANCE__) == TIM8))
9759
9760 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
9761 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
9762 (((__INSTANCE__) == TIM1) || \
9763 ((__INSTANCE__) == TIM2) || \
9764 ((__INSTANCE__) == TIM3) || \
9765 ((__INSTANCE__) == TIM4) || \
9766 ((__INSTANCE__) == TIM5) || \
9767 ((__INSTANCE__) == TIM8))
9768
9769 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
9770 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
9771 (((__INSTANCE__) == TIM1) || \
9772 ((__INSTANCE__) == TIM2) || \
9773 ((__INSTANCE__) == TIM3) || \
9774 ((__INSTANCE__) == TIM4) || \
9775 ((__INSTANCE__) == TIM5) || \
9776 ((__INSTANCE__) == TIM8))
9777 /****************** TIM Instances : at least 5 capture/compare channels *******/
9778 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
9779 (((__INSTANCE__) == TIM1) || \
9780 ((__INSTANCE__) == TIM8) )
9781
9782 /****************** TIM Instances : at least 6 capture/compare channels *******/
9783 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
9784 (((__INSTANCE__) == TIM1) || \
9785 ((__INSTANCE__) == TIM8))
9786
9787
9788 /******************** TIM Instances : Advanced-control timers *****************/
9789 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9790 ((__INSTANCE__) == TIM8))
9791
9792 /****************** TIM Instances : supporting 2 break inputs *****************/
9793 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
9794 (((__INSTANCE__) == TIM1) || \
9795 ((__INSTANCE__) == TIM8))
9796
9797 /******************* TIM Instances : Timer input XOR function *****************/
9798 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9799 ((__INSTANCE__) == TIM2) || \
9800 ((__INSTANCE__) == TIM3) || \
9801 ((__INSTANCE__) == TIM4) || \
9802 ((__INSTANCE__) == TIM5) || \
9803 ((__INSTANCE__) == TIM8))
9804
9805 /****************** TIM Instances : DMA requests generation (UDE) *************/
9806 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9807 ((__INSTANCE__) == TIM2) || \
9808 ((__INSTANCE__) == TIM3) || \
9809 ((__INSTANCE__) == TIM4) || \
9810 ((__INSTANCE__) == TIM5) || \
9811 ((__INSTANCE__) == TIM6) || \
9812 ((__INSTANCE__) == TIM7) || \
9813 ((__INSTANCE__) == TIM8))
9814
9815 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
9816 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9817 ((__INSTANCE__) == TIM2) || \
9818 ((__INSTANCE__) == TIM3) || \
9819 ((__INSTANCE__) == TIM4) || \
9820 ((__INSTANCE__) == TIM5) || \
9821 ((__INSTANCE__) == TIM8))
9822
9823 /************ TIM Instances : DMA requests generation (COMDE) *****************/
9824 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9825 ((__INSTANCE__) == TIM2) || \
9826 ((__INSTANCE__) == TIM3) || \
9827 ((__INSTANCE__) == TIM4) || \
9828 ((__INSTANCE__) == TIM5) || \
9829 ((__INSTANCE__) == TIM8))
9830
9831 /******************** TIM Instances : DMA burst feature ***********************/
9832 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9833 ((__INSTANCE__) == TIM2) || \
9834 ((__INSTANCE__) == TIM3) || \
9835 ((__INSTANCE__) == TIM4) || \
9836 ((__INSTANCE__) == TIM5) || \
9837 ((__INSTANCE__) == TIM8))
9838
9839 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
9840 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9841 ((__INSTANCE__) == TIM2) || \
9842 ((__INSTANCE__) == TIM3) || \
9843 ((__INSTANCE__) == TIM4) || \
9844 ((__INSTANCE__) == TIM5) || \
9845 ((__INSTANCE__) == TIM6) || \
9846 ((__INSTANCE__) == TIM7) || \
9847 ((__INSTANCE__) == TIM8) || \
9848 ((__INSTANCE__) == TIM13) || \
9849 ((__INSTANCE__) == TIM14))
9850
9851 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9852 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9853 ((__INSTANCE__) == TIM2) || \
9854 ((__INSTANCE__) == TIM3) || \
9855 ((__INSTANCE__) == TIM4) || \
9856 ((__INSTANCE__) == TIM5) || \
9857 ((__INSTANCE__) == TIM8) || \
9858 ((__INSTANCE__) == TIM9) || \
9859 ((__INSTANCE__) == TIM12))
9860
9861 /********************** TIM Instances : 32 bit Counter ************************/
9862 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
9863 ((__INSTANCE__) == TIM5))
9864
9865 /***************** TIM Instances : external trigger input available ************/
9866 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9867 ((__INSTANCE__) == TIM2) || \
9868 ((__INSTANCE__) == TIM3) || \
9869 ((__INSTANCE__) == TIM4) || \
9870 ((__INSTANCE__) == TIM5) || \
9871 ((__INSTANCE__) == TIM8))
9872
9873 /****************** TIM Instances : remapping capability **********************/
9874 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
9875 ((__INSTANCE__) == TIM5) || \
9876 ((__INSTANCE__) == TIM11))
9877
9878 /******************* TIM Instances : output(s) available **********************/
9879 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
9880 ((((__INSTANCE__) == TIM1) && \
9881 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9882 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9883 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9884 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9885 || \
9886 (((__INSTANCE__) == TIM2) && \
9887 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9888 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9889 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9890 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9891 || \
9892 (((__INSTANCE__) == TIM3) && \
9893 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9894 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9895 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9896 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9897 || \
9898 (((__INSTANCE__) == TIM4) && \
9899 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9900 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9901 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9902 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9903 || \
9904 (((__INSTANCE__) == TIM5) && \
9905 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9906 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9907 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9908 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9909 || \
9910 (((__INSTANCE__) == TIM8) && \
9911 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9912 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9913 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9914 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9915 || \
9916 (((__INSTANCE__) == TIM9) && \
9917 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9918 ((__CHANNEL__) == TIM_CHANNEL_2))) \
9919 || \
9920 (((__INSTANCE__) == TIM10) && \
9921 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9922 || \
9923 (((__INSTANCE__) == TIM11) && \
9924 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9925 || \
9926 (((__INSTANCE__) == TIM12) && \
9927 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9928 ((__CHANNEL__) == TIM_CHANNEL_2))) \
9929 || \
9930 (((__INSTANCE__) == TIM13) && \
9931 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9932 || \
9933 (((__INSTANCE__) == TIM14) && \
9934 (((__CHANNEL__) == TIM_CHANNEL_1))))
9935
9936 /************ TIM Instances : complementary output(s) available ***************/
9937 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
9938 ((((__INSTANCE__) == TIM1) && \
9939 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9940 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9941 ((__CHANNEL__) == TIM_CHANNEL_3))) \
9942 || \
9943 (((__INSTANCE__) == TIM8) && \
9944 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9945 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9946 ((__CHANNEL__) == TIM_CHANNEL_3))))
9947
9948 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9949 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
9950 (((__INSTANCE__) == TIM1) || \
9951 ((__INSTANCE__) == TIM8) )
9952
9953 /****************** TIM Instances : supporting synchronization ****************/
9954 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
9955 (((__INSTANCE__) == TIM1) || \
9956 ((__INSTANCE__) == TIM2) || \
9957 ((__INSTANCE__) == TIM3) || \
9958 ((__INSTANCE__) == TIM4) || \
9959 ((__INSTANCE__) == TIM5) || \
9960 ((__INSTANCE__) == TIM6) || \
9961 ((__INSTANCE__) == TIM7) || \
9962 ((__INSTANCE__) == TIM8))
9963
9964 /******************** USART Instances : Synchronous mode **********************/
9965 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9966 ((__INSTANCE__) == USART2) || \
9967 ((__INSTANCE__) == USART3) || \
9968 ((__INSTANCE__) == USART6))
9969
9970 /******************** UART Instances : Asynchronous mode **********************/
9971 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9972 ((__INSTANCE__) == USART2) || \
9973 ((__INSTANCE__) == USART3) || \
9974 ((__INSTANCE__) == UART4) || \
9975 ((__INSTANCE__) == UART5) || \
9976 ((__INSTANCE__) == USART6) || \
9977 ((__INSTANCE__) == UART7) || \
9978 ((__INSTANCE__) == UART8))
9979
9980 /****************** UART Instances : Driver Enable *****************/
9981 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9982 ((__INSTANCE__) == USART2) || \
9983 ((__INSTANCE__) == USART3) || \
9984 ((__INSTANCE__) == UART4) || \
9985 ((__INSTANCE__) == UART5) || \
9986 ((__INSTANCE__) == USART6) || \
9987 ((__INSTANCE__) == UART7) || \
9988 ((__INSTANCE__) == UART8))
9989
9990 /****************** UART Instances : Hardware Flow control ********************/
9991 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9992 ((__INSTANCE__) == USART2) || \
9993 ((__INSTANCE__) == USART3) || \
9994 ((__INSTANCE__) == UART4) || \
9995 ((__INSTANCE__) == UART5) || \
9996 ((__INSTANCE__) == USART6) || \
9997 ((__INSTANCE__) == UART7) || \
9998 ((__INSTANCE__) == UART8))
9999
10000 /********************* UART Instances : Smart card mode ***********************/
10001 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
10002 ((__INSTANCE__) == USART2) || \
10003 ((__INSTANCE__) == USART3) || \
10004 ((__INSTANCE__) == USART6))
10005
10006 /*********************** UART Instances : IRDA mode ***************************/
10007 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
10008 ((__INSTANCE__) == USART2) || \
10009 ((__INSTANCE__) == USART3) || \
10010 ((__INSTANCE__) == UART4) || \
10011 ((__INSTANCE__) == UART5) || \
10012 ((__INSTANCE__) == USART6) || \
10013 ((__INSTANCE__) == UART7) || \
10014 ((__INSTANCE__) == UART8))
10015
10016 /****************************** IWDG Instances ********************************/
10017 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
10018
10019 /****************************** WWDG Instances ********************************/
10020 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
10021
10022
10023 /******************************************************************************/
10024 /* For a painless codes migration between the STM32F7xx device product */
10025 /* lines, the aliases defined below are put in place to overcome the */
10026 /* differences in the interrupt handlers and IRQn definitions. */
10027 /* No need to update developed interrupt code when moving across */
10028 /* product lines within the same STM32F7 Family */
10029 /******************************************************************************/
10030
10031 /* Aliases for __IRQn */
10032 #define HASH_RNG_IRQn RNG_IRQn
10033
10034 /* Aliases for __IRQHandler */
10035 #define HASH_RNG_IRQHandler RNG_IRQHandler
10036
10037 /**
10038 * @}
10039 */
10040
10041 /**
10042 * @}
10043 */
10044
10045 /**
10046 * @}
10047 */
10048
10049 #ifdef __cplusplus
10050 }
10051 #endif /* __cplusplus */
10052
10053 #endif /* __STM32F767xx_H */
10054
10055
10056 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)