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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_cortex.h
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_cortex.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief Header file of CORTEX HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_CORTEX_H
40 #define __STM32F7xx_HAL_CORTEX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup CORTEX
54 * @{
55 */
56 /* Exported types ------------------------------------------------------------*/
57 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
58 * @{
59 */
60
61 #if (__MPU_PRESENT == 1)
62 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
63 * @brief MPU Region initialization structure
64 * @{
65 */
66 typedef struct
67 {
68 uint8_t Enable; /*!< Specifies the status of the region.
69 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
70 uint8_t Number; /*!< Specifies the number of the region to protect.
71 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
72 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
73 uint8_t Size; /*!< Specifies the size of the region to protect.
74 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
75 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
77 uint8_t TypeExtField; /*!< Specifies the TEX field level.
78 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
79 uint8_t AccessPermission; /*!< Specifies the region access permission type.
80 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
81 uint8_t DisableExec; /*!< Specifies the instruction access status.
82 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
83 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
84 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
85 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
86 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
87 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
88 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
89 }MPU_Region_InitTypeDef;
90 /**
91 * @}
92 */
93 #endif /* __MPU_PRESENT */
94
95 /**
96 * @}
97 */
98
99 /* Exported constants --------------------------------------------------------*/
100
101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
102 * @{
103 */
104
105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
106 * @{
107 */
108 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
109 4 bits for subpriority */
110 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
111 3 bits for subpriority */
112 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
113 2 bits for subpriority */
114 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
115 1 bits for subpriority */
116 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
117 0 bits for subpriority */
118 /**
119 * @}
120 */
121
122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
123 * @{
124 */
125 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
126 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
127
128 /**
129 * @}
130 */
131
132 #if (__MPU_PRESENT == 1)
133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
134 * @{
135 */
136 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
137 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
138 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
139 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
140 /**
141 * @}
142 */
143
144 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
145 * @{
146 */
147 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
148 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
149 /**
150 * @}
151 */
152
153 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
154 * @{
155 */
156 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
157 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
158 /**
159 * @}
160 */
161
162 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
163 * @{
164 */
165 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
166 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
167 /**
168 * @}
169 */
170
171 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
172 * @{
173 */
174 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
175 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
176 /**
177 * @}
178 */
179
180 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
181 * @{
182 */
183 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
184 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
185 /**
186 * @}
187 */
188
189 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
190 * @{
191 */
192 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
193 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
194 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
195 /**
196 * @}
197 */
198
199 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
200 * @{
201 */
202 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
203 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
204 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
205 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
206 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
207 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
208 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
209 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
210 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
211 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
212 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
213 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
214 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
215 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
216 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
217 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
218 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
219 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
220 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
221 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
222 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
223 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
224 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
225 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
226 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
227 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
228 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
229 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
230 /**
231 * @}
232 */
233
234 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
235 * @{
236 */
237 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
238 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
239 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
240 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
241 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
242 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
243 /**
244 * @}
245 */
246
247 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
248 * @{
249 */
250 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
251 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
252 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
253 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
254 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
255 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
256 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
257 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
258 /**
259 * @}
260 */
261 #endif /* __MPU_PRESENT */
262
263 /**
264 * @}
265 */
266
267
268 /* Exported Macros -----------------------------------------------------------*/
269
270 /* Exported functions --------------------------------------------------------*/
271 /** @addtogroup CORTEX_Exported_Functions
272 * @{
273 */
274
275 /** @addtogroup CORTEX_Exported_Functions_Group1
276 * @{
277 */
278 /* Initialization and de-initialization functions *****************************/
279 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
280 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
281 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
282 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
283 void HAL_NVIC_SystemReset(void);
284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
285 /**
286 * @}
287 */
288
289 /** @addtogroup CORTEX_Exported_Functions_Group2
290 * @{
291 */
292 /* Peripheral Control functions ***********************************************/
293 #if (__MPU_PRESENT == 1)
294 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
295 #endif /* __MPU_PRESENT */
296 uint32_t HAL_NVIC_GetPriorityGrouping(void);
297 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
298 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
299 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
300 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
301 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
302 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
303 void HAL_SYSTICK_IRQHandler(void);
304 void HAL_SYSTICK_Callback(void);
305 /**
306 * @}
307 */
308
309 /**
310 * @}
311 */
312
313 /* Private types -------------------------------------------------------------*/
314 /* Private variables ---------------------------------------------------------*/
315 /* Private constants ---------------------------------------------------------*/
316 /* Private macros ------------------------------------------------------------*/
317 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
318 * @{
319 */
320 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
321 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
322 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
323 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
324 ((GROUP) == NVIC_PRIORITYGROUP_4))
325
326 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
327
328 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
329
330 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
331
332 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
333 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
334
335 #if (__MPU_PRESENT == 1)
336 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
337 ((STATE) == MPU_REGION_DISABLE))
338
339 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
340 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
341
342 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
343 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
344
345 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
346 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
347
348 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
349 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
350
351 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
352 ((TYPE) == MPU_TEX_LEVEL1) || \
353 ((TYPE) == MPU_TEX_LEVEL2))
354
355 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
356 ((TYPE) == MPU_REGION_PRIV_RW) || \
357 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
358 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
359 ((TYPE) == MPU_REGION_PRIV_RO) || \
360 ((TYPE) == MPU_REGION_PRIV_RO_URO))
361
362 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
363 ((NUMBER) == MPU_REGION_NUMBER1) || \
364 ((NUMBER) == MPU_REGION_NUMBER2) || \
365 ((NUMBER) == MPU_REGION_NUMBER3) || \
366 ((NUMBER) == MPU_REGION_NUMBER4) || \
367 ((NUMBER) == MPU_REGION_NUMBER5) || \
368 ((NUMBER) == MPU_REGION_NUMBER6) || \
369 ((NUMBER) == MPU_REGION_NUMBER7))
370
371 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
372 ((SIZE) == MPU_REGION_SIZE_64B) || \
373 ((SIZE) == MPU_REGION_SIZE_128B) || \
374 ((SIZE) == MPU_REGION_SIZE_256B) || \
375 ((SIZE) == MPU_REGION_SIZE_512B) || \
376 ((SIZE) == MPU_REGION_SIZE_1KB) || \
377 ((SIZE) == MPU_REGION_SIZE_2KB) || \
378 ((SIZE) == MPU_REGION_SIZE_4KB) || \
379 ((SIZE) == MPU_REGION_SIZE_8KB) || \
380 ((SIZE) == MPU_REGION_SIZE_16KB) || \
381 ((SIZE) == MPU_REGION_SIZE_32KB) || \
382 ((SIZE) == MPU_REGION_SIZE_64KB) || \
383 ((SIZE) == MPU_REGION_SIZE_128KB) || \
384 ((SIZE) == MPU_REGION_SIZE_256KB) || \
385 ((SIZE) == MPU_REGION_SIZE_512KB) || \
386 ((SIZE) == MPU_REGION_SIZE_1MB) || \
387 ((SIZE) == MPU_REGION_SIZE_2MB) || \
388 ((SIZE) == MPU_REGION_SIZE_4MB) || \
389 ((SIZE) == MPU_REGION_SIZE_8MB) || \
390 ((SIZE) == MPU_REGION_SIZE_16MB) || \
391 ((SIZE) == MPU_REGION_SIZE_32MB) || \
392 ((SIZE) == MPU_REGION_SIZE_64MB) || \
393 ((SIZE) == MPU_REGION_SIZE_128MB) || \
394 ((SIZE) == MPU_REGION_SIZE_256MB) || \
395 ((SIZE) == MPU_REGION_SIZE_512MB) || \
396 ((SIZE) == MPU_REGION_SIZE_1GB) || \
397 ((SIZE) == MPU_REGION_SIZE_2GB) || \
398 ((SIZE) == MPU_REGION_SIZE_4GB))
399
400 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
401 #endif /* __MPU_PRESENT */
402
403 /**
404 * @}
405 */
406
407 /* Private functions ---------------------------------------------------------*/
408 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
409 * @brief CORTEX private functions
410 * @{
411 */
412
413 #if (__MPU_PRESENT == 1)
414 /**
415 * @brief Disables the MPU
416 * @retval None
417 */
418 __STATIC_INLINE void HAL_MPU_Disable(void)
419 {
420 /* Disable fault exceptions */
421 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
422
423 /* Disable the MPU */
424 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
425 }
426
427 /**
428 * @brief Enables the MPU
429 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
430 * NMI, FAULTMASK and privileged access to the default memory
431 * This parameter can be one of the following values:
432 * @arg MPU_HFNMI_PRIVDEF_NONE
433 * @arg MPU_HARDFAULT_NMI
434 * @arg MPU_PRIVILEGED_DEFAULT
435 * @arg MPU_HFNMI_PRIVDEF
436 * @retval None
437 */
438 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
439 {
440 /* Enable the MPU */
441 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
442
443 /* Enable fault exceptions */
444 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
445 }
446 #endif /* __MPU_PRESENT */
447
448 /**
449 * @}
450 */
451
452 /**
453 * @}
454 */
455
456 /**
457 * @}
458 */
459
460 #ifdef __cplusplus
461 }
462 #endif
463
464 #endif /* __STM32F7xx_HAL_CORTEX_H */
465
466
467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)