int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    22-April-2016
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F7xx_HAL_DMA_H
  40 #define __STM32F7xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f7xx_hal_def.h"
  48
  49 /** @addtogroup STM32F7xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup DMA
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /** @defgroup DMA_Exported_Types DMA Exported Types
  60   * @brief    DMA Exported Types
  61   * @{
  62   */
  63
  64 /**
  65   * @brief  DMA Configuration Structure definition
  66   */
  67 typedef struct
  68 {
  69   uint32_t Channel;              /*!< Specifies the channel used for the specified stream.
  70                                       This parameter can be a value of @ref DMAEx_Channel_selection                  */
  71
  72   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
  73                                       from memory to memory or from peripheral to memory.
  74                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
  75
  76   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
  77                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
  78
  79   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
  80                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
  81
  82   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
  83                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
  84
  85   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
  86                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
  87
  88   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
  89                                       This parameter can be a value of @ref DMA_mode
  90                                       @note The circular buffer mode cannot be used if the memory-to-memory
  91                                             data transfer is configured on the selected Stream                        */
  92
  93   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
  94                                       This parameter can be a value of @ref DMA_Priority_level                       */
  95
  96   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
  97                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
  98                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
  99                                             memory-to-memory data transfer is configured on the selected stream       */
 100
 101   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
 102                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
 103
 104   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
 105                                       It specifies the amount of data to be transferred in a single non interruptible
 106                                       transaction.
 107                                       This parameter can be a value of @ref DMA_Memory_burst
 108                                       @note The burst mode is possible only if the address Increment mode is enabled. */
 109
 110   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
 111                                       It specifies the amount of data to be transferred in a single non interruptible
 112                                       transaction.
 113                                       This parameter can be a value of @ref DMA_Peripheral_burst
 114                                       @note The burst mode is possible only if the address Increment mode is enabled. */
 115 }DMA_InitTypeDef;
 116
 117 /**
 118   * @brief  HAL DMA State structures definition
 119   */
 120 typedef enum
 121 {
 122   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
 123   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
 124   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
 125   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
 126   HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
 127   HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
 128 }HAL_DMA_StateTypeDef;
 129
 130 /**
 131   * @brief  HAL DMA Error Code structure definition
 132   */
 133 typedef enum
 134 {
 135   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
 136   HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
 137 }HAL_DMA_LevelCompleteTypeDef;
 138
 139 /**
 140   * @brief  HAL DMA Error Code structure definition
 141   */
 142 typedef enum
 143 {
 144   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
 145   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
 146   HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
 147   HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
 148   HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
 149   HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
 150   HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
 151 }HAL_DMA_CallbackIDTypeDef;
 152
 153 /**
 154   * @brief  DMA handle Structure definition
 155   */
 156 typedef struct __DMA_HandleTypeDef
 157 {
 158   DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
 159
 160   DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */
 161
 162   HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */
 163
 164   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 165
 166   void                       *Parent;                                                      /*!< Parent object state                    */
 167
 168   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 169
 170   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 171
 172   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
 173
 174   void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
 175
 176   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 177
 178   void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */
 179
 180  __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
 181
 182  uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
 183
 184  uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
 185
 186 }DMA_HandleTypeDef;
 187
 188 /**
 189   * @}
 190   */
 191
 192
 193 /* Exported constants --------------------------------------------------------*/
 194
 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 196   * @brief    DMA Exported constants
 197   * @{
 198   */
 199
 200 /** @defgroup DMA_Error_Code DMA Error Code
 201   * @brief    DMA Error Code
 202   * @{
 203   */
 204 #define HAL_DMA_ERROR_NONE            ((uint32_t)0x00000000U)    /*!< No error                               */
 205 #define HAL_DMA_ERROR_TE              ((uint32_t)0x00000001U)    /*!< Transfer error                         */
 206 #define HAL_DMA_ERROR_FE              ((uint32_t)0x00000002U)    /*!< FIFO error                             */
 207 #define HAL_DMA_ERROR_DME             ((uint32_t)0x00000004U)    /*!< Direct Mode error                      */
 208 #define HAL_DMA_ERROR_TIMEOUT         ((uint32_t)0x00000020U)    /*!< Timeout error                          */
 209 #define HAL_DMA_ERROR_PARAM           ((uint32_t)0x00000040U)    /*!< Parameter error                        */
 210 #define HAL_DMA_ERROR_NO_XFER         ((uint32_t)0x00000080U)    /*!< Abort requested with no Xfer ongoing   */
 211 #define HAL_DMA_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000100U)    /*!< Not supported mode                     */
 212 /**
 213   * @}
 214   */
 215
 216 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 217   * @brief    DMA data transfer direction
 218   * @{
 219   */
 220 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
 221 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
 222 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
 223 /**
 224   * @}
 225   */
 226
 227 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 228   * @brief    DMA peripheral incremented mode
 229   * @{
 230   */
 231 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
 232 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
 233 /**
 234   * @}
 235   */
 236
 237 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 238   * @brief    DMA memory incremented mode
 239   * @{
 240   */
 241 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
 242 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
 243 /**
 244   * @}
 245   */
 246
 247 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 248   * @brief    DMA peripheral data size
 249   * @{
 250   */
 251 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Peripheral data alignment: Byte     */
 252 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
 253 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
 254 /**
 255   * @}
 256   */
 257
 258 /** @defgroup DMA_Memory_data_size DMA Memory data size
 259   * @brief    DMA memory data size
 260   * @{
 261   */
 262 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Memory data alignment: Byte     */
 263 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
 264 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
 265 /**
 266   * @}
 267   */
 268
 269 /** @defgroup DMA_mode DMA mode
 270   * @brief    DMA mode
 271   * @{
 272   */
 273 #define DMA_NORMAL         ((uint32_t)0x00000000U)       /*!< Normal mode                  */
 274 #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
 275 #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
 276 /**
 277   * @}
 278   */
 279
 280 /** @defgroup DMA_Priority_level DMA Priority level
 281   * @brief    DMA priority levels
 282   * @{
 283   */
 284 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low       */
 285 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
 286 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
 287 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
 288 /**
 289   * @}
 290   */
 291
 292 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
 293   * @brief    DMA FIFO direct mode
 294   * @{
 295   */
 296 #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
 297 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
 298 /**
 299   * @}
 300   */
 301
 302 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
 303   * @brief    DMA FIFO level
 304   * @{
 305   */
 306 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
 307 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
 308 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
 309 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
 310 /**
 311   * @}
 312   */
 313
 314 /** @defgroup DMA_Memory_burst DMA Memory burst
 315   * @brief    DMA memory burst
 316   * @{
 317   */
 318 #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
 319 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
 320 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
 321 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
 322 /**
 323   * @}
 324   */
 325
 326 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
 327   * @brief    DMA peripheral burst
 328   * @{
 329   */
 330 #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
 331 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
 332 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
 333 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
 334 /**
 335   * @}
 336   */
 337
 338 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 339   * @brief    DMA interrupts definition
 340   * @{
 341   */
 342 #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
 343 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
 344 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
 345 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
 346 #define DMA_IT_FE                         ((uint32_t)0x00000080U)
 347 /**
 348   * @}
 349   */
 350
 351 /** @defgroup DMA_flag_definitions DMA flag definitions
 352   * @brief    DMA flag definitions
 353   * @{
 354   */
 355 #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001U)
 356 #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004U)
 357 #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
 358 #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
 359 #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
 360 #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
 361 #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
 362 #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
 363 #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
 364 #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
 365 #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
 366 #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
 367 #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
 368 #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
 369 #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
 370 #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
 371 #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
 372 #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
 373 #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
 374 #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
 375 /**
 376   * @}
 377   */
 378
 379 /**
 380   * @}
 381   */
 382
 383 /* Exported macro ------------------------------------------------------------*/
 384
 385 /** @brief Reset DMA handle state
 386   * @param  __HANDLE__: specifies the DMA handle.
 387   * @retval None
 388   */
 389 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 390
 391 /**
 392   * @brief  Return the current DMA Stream FIFO filled level.
 393   * @param  __HANDLE__: DMA handle
 394   * @retval The FIFO filling state.
 395   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
 396   *                                              and not empty.
 397   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
 398   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
 399   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
 400   *           - DMA_FIFOStatus_Empty: when FIFO is empty
 401   *           - DMA_FIFOStatus_Full: when FIFO is full
 402   */
 403 #define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
 404
 405 /**
 406   * @brief  Enable the specified DMA Stream.
 407   * @param  __HANDLE__: DMA handle
 408   * @retval None
 409   */
 410 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
 411
 412 /**
 413   * @brief  Disable the specified DMA Stream.
 414   * @param  __HANDLE__: DMA handle
 415   * @retval None
 416   */
 417 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
 418
 419 /* Interrupt & Flag management */
 420
 421 /**
 422   * @brief  Return the current DMA Stream transfer complete flag.
 423   * @param  __HANDLE__: DMA handle
 424   * @retval The specified transfer complete flag index.
 425   */
 426 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 427 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 428  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 429  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 430  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 431  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 432  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 433  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 434  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 435  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 436  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 437  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 438  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
 439    DMA_FLAG_TCIF3_7)
 440
 441 /**
 442   * @brief  Return the current DMA Stream half transfer complete flag.
 443   * @param  __HANDLE__: DMA handle
 444   * @retval The specified half transfer complete flag index.
 445   */
 446 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 447 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 448  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 449  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 450  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 451  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 452  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 453  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 454  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 455  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 456  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 457  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 458  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
 459    DMA_FLAG_HTIF3_7)
 460
 461 /**
 462   * @brief  Return the current DMA Stream transfer error flag.
 463   * @param  __HANDLE__: DMA handle
 464   * @retval The specified transfer error flag index.
 465   */
 466 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 467 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 468  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 469  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 471  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 472  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 473  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 474  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 475  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
 479    DMA_FLAG_TEIF3_7)
 480
 481 /**
 482   * @brief  Return the current DMA Stream FIFO error flag.
 483   * @param  __HANDLE__: DMA handle
 484   * @retval The specified FIFO error flag index.
 485   */
 486 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
 487 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 488  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 489  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 491  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 492  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 495  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
 499    DMA_FLAG_FEIF3_7)
 500
 501 /**
 502   * @brief  Return the current DMA Stream direct mode error flag.
 503   * @param  __HANDLE__: DMA handle
 504   * @retval The specified direct mode error flag index.
 505   */
 506 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
 507 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 508  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 509  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 510  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 511  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 512  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 513  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 514  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 515  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 516  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 517  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 518  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
 519    DMA_FLAG_DMEIF3_7)
 520
 521 /**
 522   * @brief  Get the DMA Stream pending flags.
 523   * @param  __HANDLE__: DMA handle
 524   * @param  __FLAG__: Get the specified flag.
 525   *          This parameter can be any combination of the following values:
 526   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 527   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 528   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 529   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 530   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 531   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 532   * @retval The state of FLAG (SET or RESET).
 533   */
 534 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
 535 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
 536  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
 537  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
 538
 539 /**
 540   * @brief  Clear the DMA Stream pending flags.
 541   * @param  __HANDLE__: DMA handle
 542   * @param  __FLAG__: specifies the flag to clear.
 543   *          This parameter can be any combination of the following values:
 544   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 545   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 546   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 547   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 548   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 549   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 550   * @retval None
 551   */
 552 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
 553 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
 554  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
 555  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
 556
 557 /**
 558   * @brief  Enable the specified DMA Stream interrupts.
 559   * @param  __HANDLE__: DMA handle
 560   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 561   *        This parameter can be one of the following values:
 562   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
 563   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
 564   *           @arg DMA_IT_TE: Transfer error interrupt mask.
 565   *           @arg DMA_IT_FE: FIFO error interrupt mask.
 566   *           @arg DMA_IT_DME: Direct mode error interrupt.
 567   * @retval None
 568   */
 569 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
 570 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
 571
 572 /**
 573   * @brief  Disable the specified DMA Stream interrupts.
 574   * @param  __HANDLE__: DMA handle
 575   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 576   *         This parameter can be one of the following values:
 577   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 578   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 579   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 580   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 581   *            @arg DMA_IT_DME: Direct mode error interrupt.
 582   * @retval None
 583   */
 584 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 585 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
 586
 587 /**
 588   * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
 589   * @param  __HANDLE__: DMA handle
 590   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 591   *         This parameter can be one of the following values:
 592   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 593   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 594   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 595   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 596   *            @arg DMA_IT_DME: Direct mode error interrupt.
 597   * @retval The state of DMA_IT.
 598   */
 599 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 600                                                         ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
 601                                                         ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
 602
 603 /**
 604   * @brief  Writes the number of data units to be transferred on the DMA Stream.
 605   * @param  __HANDLE__: DMA handle
 606   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
 607   *          Number of data items depends only on the Peripheral data format.
 608   *
 609   * @note   If Peripheral data format is Bytes: number of data units is equal
 610   *         to total number of bytes to be transferred.
 611   *
 612   * @note   If Peripheral data format is Half-Word: number of data units is
 613   *         equal to total number of bytes to be transferred / 2.
 614   *
 615   * @note   If Peripheral data format is Word: number of data units is equal
 616   *         to total  number of bytes to be transferred / 4.
 617   *
 618   * @retval The number of remaining data units in the current DMAy Streamx transfer.
 619   */
 620 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
 621
 622 /**
 623   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
 624   * @param  __HANDLE__: DMA handle
 625   *
 626   * @retval The number of remaining data units in the current DMA Stream transfer.
 627   */
 628 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
 629
 630
 631 /* Include DMA HAL Extension module */
 632 #include "stm32f7xx_hal_dma_ex.h"
 633
 634 /* Exported functions --------------------------------------------------------*/
 635
 636 /** @defgroup DMA_Exported_Functions DMA Exported Functions
 637   * @brief    DMA Exported functions
 638   * @{
 639   */
 640
 641 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
 642   * @brief   Initialization and de-initialization functions
 643   * @{
 644   */
 645 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 646 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 647 /**
 648   * @}
 649   */
 650
 651 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
 652   * @brief   I/O operation functions
 653   * @{
 654   */
 655 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 656 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 657 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 658 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
 659 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
 660 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 661 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
 662 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
 663 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
 664
 665 /**
 666   * @}
 667   */
 668
 669 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
 670   * @brief    Peripheral State functions
 671   * @{
 672   */
 673 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 674 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 675 /**
 676   * @}
 677   */
 678 /**
 679   * @}
 680   */
 681 /* Private Constants -------------------------------------------------------------*/
 682 /** @defgroup DMA_Private_Constants DMA Private Constants
 683   * @brief    DMA private defines and constants
 684   * @{
 685   */
 686 /**
 687   * @}
 688   */
 689
 690 /* Private macros ------------------------------------------------------------*/
 691 /** @defgroup DMA_Private_Macros DMA Private Macros
 692   * @brief    DMA private macros
 693   * @{
 694   */
 695 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 696                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 697                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 698
 699 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
 700
 701 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 702                                             ((STATE) == DMA_PINC_DISABLE))
 703
 704 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 705                                         ((STATE) == DMA_MINC_DISABLE))
 706
 707 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 708                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 709                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 710
 711 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 712                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 713                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 714
 715 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 716                            ((MODE) == DMA_CIRCULAR) || \
 717                            ((MODE) == DMA_PFCTRL))
 718
 719 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 720                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 721                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 722                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 723
 724 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
 725                                        ((STATE) == DMA_FIFOMODE_ENABLE))
 726
 727 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
 728                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
 729                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
 730                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
 731
 732 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
 733                                     ((BURST) == DMA_MBURST_INC4)   || \
 734                                     ((BURST) == DMA_MBURST_INC8)   || \
 735                                     ((BURST) == DMA_MBURST_INC16))
 736
 737 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
 738                                         ((BURST) == DMA_PBURST_INC4)   || \
 739                                         ((BURST) == DMA_PBURST_INC8)   || \
 740                                         ((BURST) == DMA_PBURST_INC16))
 741 /**
 742   * @}
 743   */
 744
 745 /* Private functions ---------------------------------------------------------*/
 746 /** @defgroup DMA_Private_Functions DMA Private Functions
 747   * @brief    DMA private  functions
 748   * @{
 749   */
 750 /**
 751   * @}
 752   */
 753
 754 /**
 755   * @}
 756   */
 757
 758 /**
 759   * @}
 760   */
 761
 762 #ifdef __cplusplus
 763 }
 764 #endif
 765
 766 #endif /* __STM32F7xx_HAL_DMA_H */
 767
 768 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/