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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_flash_ex.h
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_flash_ex.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief Header file of FLASH HAL Extension module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_FLASH_EX_H
40 #define __STM32F7xx_HAL_FLASH_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup FLASHEx
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types
59 * @{
60 */
61
62 /**
63 * @brief FLASH Erase structure definition
64 */
65 typedef struct
66 {
67 uint32_t TypeErase; /*!< Mass erase or sector Erase.
68 This parameter can be a value of @ref FLASHEx_Type_Erase */
69
70 #if defined (FLASH_OPTCR_nDBANK)
71 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
72 This parameter must be a value of @ref FLASHEx_Banks */
73 #endif /* FLASH_OPTCR_nDBANK */
74
75 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
76 This parameter must be a value of @ref FLASHEx_Sectors */
77
78 uint32_t NbSectors; /*!< Number of sectors to be erased.
79 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
80
81 uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
82 This parameter must be a value of @ref FLASHEx_Voltage_Range */
83
84 } FLASH_EraseInitTypeDef;
85
86 /**
87 * @brief FLASH Option Bytes Program structure definition
88 */
89 typedef struct
90 {
91 uint32_t OptionType; /*!< Option byte to be configured.
92 This parameter can be a value of @ref FLASHEx_Option_Type */
93
94 uint32_t WRPState; /*!< Write protection activation or deactivation.
95 This parameter can be a value of @ref FLASHEx_WRP_State */
96
97 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
98 The value of this parameter depend on device used within the same series */
99
100 uint32_t RDPLevel; /*!< Set the read protection level.
101 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
102
103 uint32_t BORLevel; /*!< Set the BOR Level.
104 This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
105
106 uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
107 IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.
108 nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */
109
110 uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.
111 This parameter can be a value of @ref FLASHEx_Boot_Address */
112
113 uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.
114 This parameter can be a value of @ref FLASHEx_Boot_Address */
115
116 } FLASH_OBProgramInitTypeDef;
117
118 /**
119 * @}
120 */
121 /* Exported constants --------------------------------------------------------*/
122
123 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
124 * @{
125 */
126
127 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
128 * @{
129 */
130 #define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
131 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
132 /**
133 * @}
134 */
135
136 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
137 * @{
138 */
139 #define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */
140 #define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */
141 #define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */
142 #define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
143 /**
144 * @}
145 */
146
147 /** @defgroup FLASHEx_WRP_State FLASH WRP State
148 * @{
149 */
150 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
151 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
152 /**
153 * @}
154 */
155
156 /** @defgroup FLASHEx_Option_Type FLASH Option Type
157 * @{
158 */
159 #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
160 #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
161 #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
162 #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
163 #define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */
164 #define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */
165 /**
166 * @}
167 */
168
169 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
170 * @{
171 */
172 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
173 #define OB_RDP_LEVEL_1 ((uint8_t)0x55U)
174 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
175 it s no more possible to go back to level 1 or 0 */
176 /**
177 * @}
178 */
179
180 /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
181 * @{
182 */
183 #define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */
184 #define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */
185 /**
186 * @}
187 */
188
189
190 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
191 * @{
192 */
193 #define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */
194 #define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */
195 /**
196 * @}
197 */
198
199 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
200 * @{
201 */
202 #define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
203 #define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */
204 /**
205 * @}
206 */
207
208 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
209 * @{
210 */
211 #define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
212 #define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */
213 /**
214 * @}
215 */
216
217 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
218 * @{
219 */
220 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
221 #define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */
222 /**
223 * @}
224 */
225
226 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
227 * @{
228 */
229 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
230 #define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */
231 /**
232 * @}
233 */
234
235 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
236 * @{
237 */
238 #define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
239 #define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
240 #define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
241 #define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
242 /**
243 * @}
244 */
245
246 #if defined (FLASH_OPTCR_nDBOOT)
247 /** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT
248 * @{
249 */
250 #define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */
251 #define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash
252 (Dual bank Boot mode), or RAM if Boot address option in RAM */
253 /**
254 * @}
255 */
256 #endif /* FLASH_OPTCR_nDBOOT */
257
258 #if defined (FLASH_OPTCR_nDBANK)
259 /** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank
260 * @{
261 */
262 #define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */
263 #define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */
264 /**
265 * @}
266 */
267 #endif /* FLASH_OPTCR_nDBANK */
268
269 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address
270 * @{
271 */
272 #define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */
273 #define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */
274 #define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */
275 #define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
276 #define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
277 #define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
278 #define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
279 /**
280 * @}
281 */
282
283 /** @defgroup FLASH_Latency FLASH Latency
284 * @{
285 */
286 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
287 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
288 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
289 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
290 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
291 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
292 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
293 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
294 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
295 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
296 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
297 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
298 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
299 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
300 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
301 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
302 /**
303 * @}
304 */
305
306 #if defined (FLASH_OPTCR_nDBANK)
307 /** @defgroup FLASHEx_Banks FLASH Banks
308 * @{
309 */
310 #define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */
311 #define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */
312 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
313 /**
314 * @}
315 */
316 #endif /* FLASH_OPTCR_nDBANK */
317
318 /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
319 * @{
320 */
321 #if defined (FLASH_OPTCR_nDBANK)
322 #define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */
323 #else
324 #define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */
325 #endif /* FLASH_OPTCR_nDBANK */
326 /**
327 * @}
328 */
329
330 /** @defgroup FLASHEx_Sectors FLASH Sectors
331 * @{
332 */
333 #if (FLASH_SECTOR_TOTAL == 24)
334 #define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */
335 #define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */
336 #define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */
337 #define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */
338 #define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */
339 #define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */
340 #define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */
341 #define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */
342 #define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */
343 #define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */
344 #define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */
345 #define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */
346 #define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */
347 #define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */
348 #define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */
349 #define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */
350 #endif /* FLASH_SECTOR_TOTAL == 24 */
351 /**
352 * @}
353 */
354
355 #if (FLASH_SECTOR_TOTAL == 24)
356 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
357 * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,
358 * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.
359 * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,
360 * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and
361 * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).
362 * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.
363 * @{
364 */
365 /* Single Bank Sectors */
366 #define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */
367 #define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */
368 #define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */
369 #define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */
370 #define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */
371 #define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */
372 #define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */
373 #define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */
374 #define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */
375 #define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */
376 #define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */
377 #define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */
378 #define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */
379
380 /* Dual Bank Sectors */
381 #define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */
382 #define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */
383 #define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */
384 #define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */
385 #define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */
386 #define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */
387 #define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */
388 #define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */
389 #define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */
390 #define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */
391 #define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */
392 #define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */
393 #define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */
394 #define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */
395 #define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */
396 #define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */
397 #define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */
398 #define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */
399 #define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */
400 #define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */
401 #define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */
402 #define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */
403 #define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */
404 #define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */
405 #define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */
406 /**
407 * @}
408 */
409 #endif /* FLASH_SECTOR_TOTAL == 24 */
410
411 #if (FLASH_SECTOR_TOTAL == 8)
412 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
413 * @{
414 */
415 #define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
416 #define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
417 #define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */
418 #define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */
419 #define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */
420 #define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */
421 #define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */
422 #define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */
423 #define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */
424 /**
425 * @}
426 */
427 #endif /* FLASH_SECTOR_TOTAL == 8 */
428
429 /**
430 * @}
431 */
432
433 /* Exported macro ------------------------------------------------------------*/
434 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
435 * @{
436 */
437 /**
438 * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
439 * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
440 * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
441 * @retval The FLASH Boot Base Adress
442 */
443 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
444 /**
445 * @}
446 */
447
448 /* Exported functions --------------------------------------------------------*/
449 /** @addtogroup FLASHEx_Exported_Functions
450 * @{
451 */
452
453 /** @addtogroup FLASHEx_Exported_Functions_Group1
454 * @{
455 */
456 /* Extension Program operation functions *************************************/
457 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
458 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
459 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
460 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
461
462 /**
463 * @}
464 */
465
466 /**
467 * @}
468 */
469 /* Private types -------------------------------------------------------------*/
470 /* Private variables ---------------------------------------------------------*/
471 /* Private constants ---------------------------------------------------------*/
472 /* Private macros ------------------------------------------------------------*/
473 /** @defgroup FLASHEx_Private_Macros FLASH Private Macros
474 * @{
475 */
476
477 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
478 * @{
479 */
480
481 #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
482 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
483
484 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
485 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
486 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
487 ((RANGE) == FLASH_VOLTAGE_RANGE_4))
488
489 #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
490 ((VALUE) == OB_WRPSTATE_ENABLE))
491
492 #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
493 OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
494
495 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
496
497 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
498 ((LEVEL) == OB_RDP_LEVEL_1) ||\
499 ((LEVEL) == OB_RDP_LEVEL_2))
500
501 #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
502
503 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
504
505 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
506
507 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
508
509 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
510
511 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
512
513 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
514 ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
515
516 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
517 ((LATENCY) == FLASH_LATENCY_1) || \
518 ((LATENCY) == FLASH_LATENCY_2) || \
519 ((LATENCY) == FLASH_LATENCY_3) || \
520 ((LATENCY) == FLASH_LATENCY_4) || \
521 ((LATENCY) == FLASH_LATENCY_5) || \
522 ((LATENCY) == FLASH_LATENCY_6) || \
523 ((LATENCY) == FLASH_LATENCY_7) || \
524 ((LATENCY) == FLASH_LATENCY_8) || \
525 ((LATENCY) == FLASH_LATENCY_9) || \
526 ((LATENCY) == FLASH_LATENCY_10) || \
527 ((LATENCY) == FLASH_LATENCY_11) || \
528 ((LATENCY) == FLASH_LATENCY_12) || \
529 ((LATENCY) == FLASH_LATENCY_13) || \
530 ((LATENCY) == FLASH_LATENCY_14) || \
531 ((LATENCY) == FLASH_LATENCY_15))
532
533 #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
534
535 #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
536
537 #if (FLASH_SECTOR_TOTAL == 8)
538 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
539 ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
540 ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
541 ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
542
543 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U))
544 #endif /* FLASH_SECTOR_TOTAL == 8 */
545
546 #if (FLASH_SECTOR_TOTAL == 24)
547 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
548 ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
549 ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
550 ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
551 ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
552 ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
553 ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
554 ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
555 ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
556 ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
557 ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
558 ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
559
560 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
561 #endif /* FLASH_SECTOR_TOTAL == 24 */
562
563 #if defined (FLASH_OPTCR_nDBANK)
564 #define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
565 ((VALUE) == OB_NDBANK_DUAL_BANK))
566
567 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
568 ((BANK) == FLASH_BANK_2) || \
569 ((BANK) == FLASH_BANK_BOTH))
570 #endif /* FLASH_OPTCR_nDBANK */
571
572 #if defined (FLASH_OPTCR_nDBOOT)
573 #define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \
574 ((VALUE) == OB_DUAL_BOOT_ENABLE))
575 #endif /* FLASH_OPTCR_nDBOOT */
576
577 /**
578 * @}
579 */
580
581 /**
582 * @}
583 */
584
585 /* Private functions ---------------------------------------------------------*/
586 /** @defgroup FLASHEx_Private_Functions FLASH Private Functions
587 * @{
588 */
589 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
590 /**
591 * @}
592 */
593
594 /**
595 * @}
596 */
597
598 /**
599 * @}
600 */
601
602 #ifdef __cplusplus
603 }
604 #endif
605
606 #endif /* __STM32F7xx_HAL_FLASH_EX_H */
607
608 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)