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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_rcc_ex.h
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_rcc_ex.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief Header file of RCC HAL Extension module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_RCC_EX_H
40 #define __STM32F7xx_HAL_RCC_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup RCCEx
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
59 * @{
60 */
61
62 /**
63 * @brief RCC PLL configuration structure definition
64 */
65 typedef struct
66 {
67 uint32_t PLLState; /*!< The new state of the PLL.
68 This parameter can be a value of @ref RCC_PLL_Config */
69
70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
72
73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
74 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
75
76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
77 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
78
79 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
81
82 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
83 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
84 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
85 uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.
86 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
87 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
88
89 }RCC_PLLInitTypeDef;
90
91 /**
92 * @brief PLLI2S Clock structure definition
93 */
94 typedef struct
95 {
96 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
97 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
98 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
99
100 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
101 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
102 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
103
104 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
105 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
106 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
107
108 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
109 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
110 This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
111 }RCC_PLLI2SInitTypeDef;
112
113 /**
114 * @brief PLLSAI Clock structure definition
115 */
116 typedef struct
117 {
118 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
119 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
120 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
121
122 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
123 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
124 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
125
126 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
127 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
128 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
129
130 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
131 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
132 This parameter will be used only when PLLSAI is disabled */
133 }RCC_PLLSAIInitTypeDef;
134
135 /**
136 * @brief RCC extended clocks structure definition
137 */
138 typedef struct
139 {
140 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
141 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
142
143 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
144 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
145
146 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
147 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
148
149 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
150 This parameter must be a number between Min_Data = 1 and Max_Data = 32
151 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
152
153 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
154 This parameter must be a number between Min_Data = 1 and Max_Data = 32
155 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
156
157 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
158 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
159
160 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
161 This parameter can be a value of @ref RCC_RTC_Clock_Source */
162
163 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
164 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
165
166 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
167 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
168
169 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
170 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
171
172 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
173 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
174
175 uint32_t Usart1ClockSelection; /*!< USART1 clock source
176 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
177
178 uint32_t Usart2ClockSelection; /*!< USART2 clock source
179 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
180
181 uint32_t Usart3ClockSelection; /*!< USART3 clock source
182 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
183
184 uint32_t Uart4ClockSelection; /*!< UART4 clock source
185 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
186
187 uint32_t Uart5ClockSelection; /*!< UART5 clock source
188 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
189
190 uint32_t Usart6ClockSelection; /*!< USART6 clock source
191 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
192
193 uint32_t Uart7ClockSelection; /*!< UART7 clock source
194 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
195
196 uint32_t Uart8ClockSelection; /*!< UART8 clock source
197 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
198
199 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
200 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
201
202 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
203 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
204
205 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
206 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
207
208 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
209 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
210
211 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
212 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
213
214 uint32_t CecClockSelection; /*!< CEC clock source
215 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
216
217 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
218 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
219
220 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
221 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
222
223 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
224 uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source
225 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
226
227 uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source
228 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
229
230 uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
231 This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
232 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
233 }RCC_PeriphCLKInitTypeDef;
234 /**
235 * @}
236 */
237
238 /* Exported constants --------------------------------------------------------*/
239 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
240 * @{
241 */
242
243 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
244 * @{
245 */
246 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
247 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
248 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
249 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
250 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
251 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
252 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
253 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)
254 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)
255 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)
256 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)
257 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)
258 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)
259 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)
260 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)
261 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)
262 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)
263 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)
264 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)
265 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)
266 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)
267 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)
268 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)
269 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)
270 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
271 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
272 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
273 #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
274 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
275 #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
276 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
277
278 /**
279 * @}
280 */
281
282 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
283 * @{
284 */
285 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)
286 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)
287 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)
288 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)
289 /**
290 * @}
291 */
292
293 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
294 * @{
295 */
296 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)
297 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)
298 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)
299 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)
300 /**
301 * @}
302 */
303
304 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
305 * @{
306 */
307 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
308 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
309 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
310 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
311 /**
312 * @}
313 */
314
315 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
316 * @{
317 */
318 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
319 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
320
321 /**
322 * @}
323 */
324
325
326 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
327 * @{
328 */
329 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
330 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
331 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
332 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
333 #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL
334 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
335 /**
336 * @}
337 */
338
339 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
340 * @{
341 */
342 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
343 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
344 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
345 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
346 #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL
347 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
348 /**
349 * @}
350 */
351
352 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
353 * @{
354 */
355 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)
356 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
357 /**
358 * @}
359 */
360
361 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
362 * @{
363 */
364 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
365 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
366 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
367 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
368 /**
369 * @}
370 */
371
372 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
373 * @{
374 */
375 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
376 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
377 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
378 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
379 /**
380 * @}
381 */
382
383 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
384 * @{
385 */
386 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
387 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
388 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
389 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
390 /**
391 * @}
392 */
393
394 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
395 * @{
396 */
397 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
398 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
399 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
400 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
401 /**
402 * @}
403 */
404
405 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
406 * @{
407 */
408 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
409 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
410 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
411 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
412 /**
413 * @}
414 */
415
416 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
417 * @{
418 */
419 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
420 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
421 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
422 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
423 /**
424 * @}
425 */
426
427 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
428 * @{
429 */
430 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
431 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
432 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
433 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
434 /**
435 * @}
436 */
437
438 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
439 * @{
440 */
441 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
442 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
443 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
444 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
445 /**
446 * @}
447 */
448
449 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
450 * @{
451 */
452 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
453 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
454 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
455 /**
456 * @}
457 */
458
459 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
460 * @{
461 */
462 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
463 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
464 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
465
466 /**
467 * @}
468 */
469
470 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
471 * @{
472 */
473 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
474 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
475 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
476 /**
477 * @}
478 */
479
480 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
481 * @{
482 */
483 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
484 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
485 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
486 /**
487 * @}
488 */
489
490 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
491 * @{
492 */
493 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
494 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
495 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
496 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
497
498 /**
499 * @}
500 */
501
502 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
503 * @{
504 */
505 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)
506 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
507 /**
508 * @}
509 */
510
511 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
512 * @{
513 */
514 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
515 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
516 /**
517 * @}
518 */
519
520 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
521 * @{
522 */
523 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
524 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
525 /**
526 * @}
527 */
528
529 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
530 /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
531 * @{
532 */
533 #define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
534 #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL
535 /**
536 * @}
537 */
538
539 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source
540 * @{
541 */
542 #define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
543 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL
544 /**
545 * @}
546 */
547
548 /** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
549 * @{
550 */
551 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)
552 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL
553 /**
554 * @}
555 */
556 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
557
558 #if defined (STM32F769xx) || defined (STM32F779xx)
559 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
560 * @{
561 */
562 #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
563 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)
564 /**
565 * @}
566 */
567 #endif /* STM32F769xx || STM32F779xx */
568
569 /**
570 * @}
571 */
572
573 /* Exported macro ------------------------------------------------------------*/
574 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
575 * @{
576 */
577 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
578 * @brief Enables or disables the AHB/APB peripheral clock.
579 * @note After reset, the peripheral clock (used for registers read/write access)
580 * is disabled and the application software has to enable this clock before
581 * using it.
582 * @{
583 */
584
585 /** @brief Enables or disables the AHB1 peripheral clock.
586 * @note After reset, the peripheral clock (used for registers read/write access)
587 * is disabled and the application software has to enable this clock before
588 * using it.
589 */
590 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
591 __IO uint32_t tmpreg; \
592 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
593 /* Delay after an RCC peripheral clock enabling */ \
594 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
595 UNUSED(tmpreg); \
596 } while(0)
597
598 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
599 __IO uint32_t tmpreg; \
600 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
601 /* Delay after an RCC peripheral clock enabling */ \
602 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
603 UNUSED(tmpreg); \
604 } while(0)
605
606 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
607 __IO uint32_t tmpreg; \
608 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
609 /* Delay after an RCC peripheral clock enabling */ \
610 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
611 UNUSED(tmpreg); \
612 } while(0)
613
614 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
615 __IO uint32_t tmpreg; \
616 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
617 /* Delay after an RCC peripheral clock enabling */ \
618 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
619 UNUSED(tmpreg); \
620 } while(0)
621
622 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
623 __IO uint32_t tmpreg; \
624 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
625 /* Delay after an RCC peripheral clock enabling */ \
626 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
627 UNUSED(tmpreg); \
628 } while(0)
629
630 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
631 __IO uint32_t tmpreg; \
632 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
633 /* Delay after an RCC peripheral clock enabling */ \
634 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
635 UNUSED(tmpreg); \
636 } while(0)
637
638 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
639 __IO uint32_t tmpreg; \
640 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
641 /* Delay after an RCC peripheral clock enabling */ \
642 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
643 UNUSED(tmpreg); \
644 } while(0)
645
646 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
647 __IO uint32_t tmpreg; \
648 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
649 /* Delay after an RCC peripheral clock enabling */ \
650 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
651 UNUSED(tmpreg); \
652 } while(0)
653
654 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
655 __IO uint32_t tmpreg; \
656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
657 /* Delay after an RCC peripheral clock enabling */ \
658 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
659 UNUSED(tmpreg); \
660 } while(0)
661
662 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
663 __IO uint32_t tmpreg; \
664 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
665 /* Delay after an RCC peripheral clock enabling */ \
666 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
667 UNUSED(tmpreg); \
668 } while(0)
669
670 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
671 __IO uint32_t tmpreg; \
672 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
673 /* Delay after an RCC peripheral clock enabling */ \
674 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
675 UNUSED(tmpreg); \
676 } while(0)
677
678 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
679 __IO uint32_t tmpreg; \
680 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
681 /* Delay after an RCC peripheral clock enabling */ \
682 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
683 UNUSED(tmpreg); \
684 } while(0)
685
686 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
687 __IO uint32_t tmpreg; \
688 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
689 /* Delay after an RCC peripheral clock enabling */ \
690 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
691 UNUSED(tmpreg); \
692 } while(0)
693
694 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
695 __IO uint32_t tmpreg; \
696 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
697 /* Delay after an RCC peripheral clock enabling */ \
698 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
699 UNUSED(tmpreg); \
700 } while(0)
701
702 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
703 __IO uint32_t tmpreg; \
704 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
705 /* Delay after an RCC peripheral clock enabling */ \
706 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
707 UNUSED(tmpreg); \
708 } while(0)
709
710 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
711 __IO uint32_t tmpreg; \
712 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
713 /* Delay after an RCC peripheral clock enabling */ \
714 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
715 UNUSED(tmpreg); \
716 } while(0)
717
718 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
719 __IO uint32_t tmpreg; \
720 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
721 /* Delay after an RCC peripheral clock enabling */ \
722 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
723 UNUSED(tmpreg); \
724 } while(0)
725
726 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
727 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
728 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
729 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
730 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
731 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
732 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
733 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
734 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
735 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
736 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
737 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
738 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
739 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
740 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
741 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
742 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
743 /**
744 * @brief Enable ETHERNET clock.
745 */
746 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
747 __IO uint32_t tmpreg; \
748 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
749 /* Delay after an RCC peripheral clock enabling */ \
750 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
751 UNUSED(tmpreg); \
752 } while(0)
753
754 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
755 __IO uint32_t tmpreg; \
756 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
757 /* Delay after an RCC peripheral clock enabling */ \
758 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
759 UNUSED(tmpreg); \
760 } while(0)
761
762 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
763 __IO uint32_t tmpreg; \
764 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
765 /* Delay after an RCC peripheral clock enabling */ \
766 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
767 UNUSED(tmpreg); \
768 } while(0)
769
770 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
771 __IO uint32_t tmpreg; \
772 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
773 /* Delay after an RCC peripheral clock enabling */ \
774 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
775 UNUSED(tmpreg); \
776 } while(0)
777
778 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
779 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
780 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
781 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
782 } while(0)
783 /**
784 * @brief Disable ETHERNET clock.
785 */
786 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
787 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
788 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
789 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
790 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
791 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
792 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
793 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
794 } while(0)
795
796 /** @brief Enable or disable the AHB2 peripheral clock.
797 * @note After reset, the peripheral clock (used for registers read/write access)
798 * is disabled and the application software has to enable this clock before
799 * using it.
800 */
801 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
802 __IO uint32_t tmpreg; \
803 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
804 /* Delay after an RCC peripheral clock enabling */ \
805 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
806 UNUSED(tmpreg); \
807 } while(0)
808
809 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
810 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \
811 __IO uint32_t tmpreg; \
812 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
813 /* Delay after an RCC peripheral clock enabling */ \
814 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
815 UNUSED(tmpreg); \
816 } while(0)
817 #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
818 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
819
820 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
821 __IO uint32_t tmpreg; \
822 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
823 /* Delay after an RCC peripheral clock enabling */ \
824 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
825 UNUSED(tmpreg); \
826 } while(0)
827
828 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
829 __IO uint32_t tmpreg; \
830 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
831 /* Delay after an RCC peripheral clock enabling */ \
832 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
833 UNUSED(tmpreg); \
834 __HAL_RCC_SYSCFG_CLK_ENABLE();\
835 } while(0)
836
837 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
838 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
839
840 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
841 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
842 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
843 __IO uint32_t tmpreg; \
844 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
845 /* Delay after an RCC peripheral clock enabling */ \
846 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
847 UNUSED(tmpreg); \
848 } while(0)
849
850 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
851 __IO uint32_t tmpreg; \
852 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
853 /* Delay after an RCC peripheral clock enabling */ \
854 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
855 UNUSED(tmpreg); \
856 } while(0)
857
858 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
859 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
860 #endif /* STM32F756x || STM32F777xx || STM32F779xx */
861
862 /** @brief Enables or disables the AHB3 peripheral clock.
863 * @note After reset, the peripheral clock (used for registers read/write access)
864 * is disabled and the application software has to enable this clock before
865 * using it.
866 */
867 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
868 __IO uint32_t tmpreg; \
869 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
870 /* Delay after an RCC peripheral clock enabling */ \
871 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
872 UNUSED(tmpreg); \
873 } while(0)
874
875 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
876 __IO uint32_t tmpreg; \
877 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
878 /* Delay after an RCC peripheral clock enabling */ \
879 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
880 UNUSED(tmpreg); \
881 } while(0)
882
883 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
884 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
885
886 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
887 * @note After reset, the peripheral clock (used for registers read/write access)
888 * is disabled and the application software has to enable this clock before
889 * using it.
890 */
891 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
892 __IO uint32_t tmpreg; \
893 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
894 /* Delay after an RCC peripheral clock enabling */ \
895 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
896 UNUSED(tmpreg); \
897 } while(0)
898
899 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
900 __IO uint32_t tmpreg; \
901 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
902 /* Delay after an RCC peripheral clock enabling */ \
903 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
904 UNUSED(tmpreg); \
905 } while(0)
906
907 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
908 __IO uint32_t tmpreg; \
909 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
910 /* Delay after an RCC peripheral clock enabling */ \
911 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
912 UNUSED(tmpreg); \
913 } while(0)
914
915 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
916 __IO uint32_t tmpreg; \
917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
918 /* Delay after an RCC peripheral clock enabling */ \
919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
920 UNUSED(tmpreg); \
921 } while(0)
922
923 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
924 __IO uint32_t tmpreg; \
925 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
926 /* Delay after an RCC peripheral clock enabling */ \
927 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
928 UNUSED(tmpreg); \
929 } while(0)
930
931 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
932 __IO uint32_t tmpreg; \
933 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
934 /* Delay after an RCC peripheral clock enabling */ \
935 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
936 UNUSED(tmpreg); \
937 } while(0)
938
939 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
940 __IO uint32_t tmpreg; \
941 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
942 /* Delay after an RCC peripheral clock enabling */ \
943 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
944 UNUSED(tmpreg); \
945 } while(0)
946
947 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
948 __IO uint32_t tmpreg; \
949 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
950 /* Delay after an RCC peripheral clock enabling */ \
951 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
952 UNUSED(tmpreg); \
953 } while(0)
954
955 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
956 __IO uint32_t tmpreg; \
957 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
958 /* Delay after an RCC peripheral clock enabling */ \
959 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
960 UNUSED(tmpreg); \
961 } while(0)
962
963 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
964 __IO uint32_t tmpreg; \
965 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
966 /* Delay after an RCC peripheral clock enabling */ \
967 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
968 UNUSED(tmpreg); \
969 } while(0)
970
971 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
972 #define __HAL_RCC_RTC_CLK_ENABLE() do { \
973 __IO uint32_t tmpreg; \
974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
975 /* Delay after an RCC peripheral clock enabling */ \
976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
977 UNUSED(tmpreg); \
978 } while(0)
979
980 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
981 __IO uint32_t tmpreg; \
982 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
983 /* Delay after an RCC peripheral clock enabling */ \
984 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
985 UNUSED(tmpreg); \
986 } while(0)
987 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
988
989 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
990 __IO uint32_t tmpreg; \
991 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
992 /* Delay after an RCC peripheral clock enabling */ \
993 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
994 UNUSED(tmpreg); \
995 } while(0)
996
997 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
998 __IO uint32_t tmpreg; \
999 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1000 /* Delay after an RCC peripheral clock enabling */ \
1001 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1002 UNUSED(tmpreg); \
1003 } while(0)
1004
1005 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
1006 __IO uint32_t tmpreg; \
1007 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
1008 /* Delay after an RCC peripheral clock enabling */ \
1009 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
1010 UNUSED(tmpreg); \
1011 } while(0)
1012
1013 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
1014 __IO uint32_t tmpreg; \
1015 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1016 /* Delay after an RCC peripheral clock enabling */ \
1017 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1018 UNUSED(tmpreg); \
1019 } while(0)
1020
1021 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
1022 __IO uint32_t tmpreg; \
1023 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1024 /* Delay after an RCC peripheral clock enabling */ \
1025 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1026 UNUSED(tmpreg); \
1027 } while(0)
1028
1029 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1030 __IO uint32_t tmpreg; \
1031 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1032 /* Delay after an RCC peripheral clock enabling */ \
1033 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1034 UNUSED(tmpreg); \
1035 } while(0)
1036
1037 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1038 __IO uint32_t tmpreg; \
1039 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1040 /* Delay after an RCC peripheral clock enabling */ \
1041 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1042 UNUSED(tmpreg); \
1043 } while(0)
1044
1045 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
1046 __IO uint32_t tmpreg; \
1047 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
1048 /* Delay after an RCC peripheral clock enabling */ \
1049 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
1050 UNUSED(tmpreg); \
1051 } while(0)
1052
1053 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
1054 __IO uint32_t tmpreg; \
1055 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1056 /* Delay after an RCC peripheral clock enabling */ \
1057 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1058 UNUSED(tmpreg); \
1059 } while(0)
1060
1061 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1062 __IO uint32_t tmpreg; \
1063 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1064 /* Delay after an RCC peripheral clock enabling */ \
1065 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1066 UNUSED(tmpreg); \
1067 } while(0)
1068
1069 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
1070 __IO uint32_t tmpreg; \
1071 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
1072 /* Delay after an RCC peripheral clock enabling */ \
1073 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
1074 UNUSED(tmpreg); \
1075 } while(0)
1076
1077 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
1078 __IO uint32_t tmpreg; \
1079 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1080 /* Delay after an RCC peripheral clock enabling */ \
1081 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1082 UNUSED(tmpreg); \
1083 } while(0)
1084
1085 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1086 __IO uint32_t tmpreg; \
1087 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1088 /* Delay after an RCC peripheral clock enabling */ \
1089 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1090 UNUSED(tmpreg); \
1091 } while(0)
1092
1093 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
1094 __IO uint32_t tmpreg; \
1095 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1096 /* Delay after an RCC peripheral clock enabling */ \
1097 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1098 UNUSED(tmpreg); \
1099 } while(0)
1100
1101 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
1102 __IO uint32_t tmpreg; \
1103 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1104 /* Delay after an RCC peripheral clock enabling */ \
1105 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1106 UNUSED(tmpreg); \
1107 } while(0)
1108
1109 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
1110 __IO uint32_t tmpreg; \
1111 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1112 /* Delay after an RCC peripheral clock enabling */ \
1113 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1114 UNUSED(tmpreg); \
1115 } while(0)
1116
1117 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
1118 __IO uint32_t tmpreg; \
1119 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1120 /* Delay after an RCC peripheral clock enabling */ \
1121 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1122 UNUSED(tmpreg); \
1123 } while(0)
1124
1125 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1126 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
1127 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
1128 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
1129 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
1130 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
1131 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1132 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1133 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1134 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
1135 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1136 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
1137 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
1138 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1139 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
1140 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1141 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
1142 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
1143 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
1144 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1145 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1146 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
1147 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
1148 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
1149 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
1150 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
1151 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1152 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
1153 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
1154 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
1155 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
1156
1157 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
1158 * @note After reset, the peripheral clock (used for registers read/write access)
1159 * is disabled and the application software has to enable this clock before
1160 * using it.
1161 */
1162 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
1163 __IO uint32_t tmpreg; \
1164 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
1165 /* Delay after an RCC peripheral clock enabling */ \
1166 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
1167 UNUSED(tmpreg); \
1168 } while(0)
1169
1170 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1171 __IO uint32_t tmpreg; \
1172 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1173 /* Delay after an RCC peripheral clock enabling */ \
1174 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1175 UNUSED(tmpreg); \
1176 } while(0)
1177
1178 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
1179 __IO uint32_t tmpreg; \
1180 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
1181 /* Delay after an RCC peripheral clock enabling */ \
1182 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
1183 UNUSED(tmpreg); \
1184 } while(0)
1185
1186 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
1187 __IO uint32_t tmpreg; \
1188 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
1189 /* Delay after an RCC peripheral clock enabling */ \
1190 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
1191 UNUSED(tmpreg); \
1192 } while(0)
1193
1194 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1195 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
1196 __IO uint32_t tmpreg; \
1197 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
1198 /* Delay after an RCC peripheral clock enabling */ \
1199 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
1200 UNUSED(tmpreg); \
1201 } while(0)
1202 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1203
1204 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
1205 __IO uint32_t tmpreg; \
1206 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
1207 /* Delay after an RCC peripheral clock enabling */ \
1208 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
1209 UNUSED(tmpreg); \
1210 } while(0)
1211
1212 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1213 __IO uint32_t tmpreg; \
1214 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1215 /* Delay after an RCC peripheral clock enabling */ \
1216 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1217 UNUSED(tmpreg); \
1218 } while(0)
1219
1220 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1221 __IO uint32_t tmpreg; \
1222 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1223 /* Delay after an RCC peripheral clock enabling */ \
1224 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1225 UNUSED(tmpreg); \
1226 } while(0)
1227
1228 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
1229 __IO uint32_t tmpreg; \
1230 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
1231 /* Delay after an RCC peripheral clock enabling */ \
1232 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
1233 UNUSED(tmpreg); \
1234 } while(0)
1235
1236 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
1237 __IO uint32_t tmpreg; \
1238 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
1239 /* Delay after an RCC peripheral clock enabling */ \
1240 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
1241 UNUSED(tmpreg); \
1242 } while(0)
1243
1244 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
1245 __IO uint32_t tmpreg; \
1246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1247 /* Delay after an RCC peripheral clock enabling */ \
1248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1249 UNUSED(tmpreg); \
1250 } while(0)
1251
1252 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
1253 __IO uint32_t tmpreg; \
1254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1255 /* Delay after an RCC peripheral clock enabling */ \
1256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1257 UNUSED(tmpreg); \
1258 } while(0)
1259
1260 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1261 __IO uint32_t tmpreg; \
1262 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1263 /* Delay after an RCC peripheral clock enabling */ \
1264 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1265 UNUSED(tmpreg); \
1266 } while(0)
1267
1268 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
1269 __IO uint32_t tmpreg; \
1270 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1271 /* Delay after an RCC peripheral clock enabling */ \
1272 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1273 UNUSED(tmpreg); \
1274 } while(0)
1275
1276 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
1277 __IO uint32_t tmpreg; \
1278 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1279 /* Delay after an RCC peripheral clock enabling */ \
1280 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1281 UNUSED(tmpreg); \
1282 } while(0)
1283
1284 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
1285 __IO uint32_t tmpreg; \
1286 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1287 /* Delay after an RCC peripheral clock enabling */ \
1288 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1289 UNUSED(tmpreg); \
1290 } while(0)
1291
1292 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
1293 __IO uint32_t tmpreg; \
1294 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1295 /* Delay after an RCC peripheral clock enabling */ \
1296 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1297 UNUSED(tmpreg); \
1298 } while(0)
1299
1300 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
1301 __IO uint32_t tmpreg; \
1302 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
1303 /* Delay after an RCC peripheral clock enabling */ \
1304 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
1305 UNUSED(tmpreg); \
1306 } while(0)
1307
1308 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1309 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1310 __IO uint32_t tmpreg; \
1311 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1312 /* Delay after an RCC peripheral clock enabling */ \
1313 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1314 UNUSED(tmpreg); \
1315 } while(0)
1316 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1317
1318 #if defined (STM32F769xx) || defined (STM32F779xx)
1319 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
1320 __IO uint32_t tmpreg; \
1321 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1322 /* Delay after an RCC peripheral clock enabling */ \
1323 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1324 UNUSED(tmpreg); \
1325 } while(0)
1326 #endif /* STM32F769xx || STM32F779xx */
1327
1328 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1329 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
1330 __IO uint32_t tmpreg; \
1331 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
1332 /* Delay after an RCC peripheral clock enabling */ \
1333 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
1334 UNUSED(tmpreg); \
1335 } while(0)
1336
1337 #define __HAL_RCC_MDIO_CLK_ENABLE() do { \
1338 __IO uint32_t tmpreg; \
1339 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
1340 /* Delay after an RCC peripheral clock enabling */ \
1341 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
1342 UNUSED(tmpreg); \
1343 } while(0)
1344 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1345
1346 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
1347 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1348 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1349 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
1350 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1351 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
1352 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1353 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
1354 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1355 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1356 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
1357 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
1358 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
1359 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
1360 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1361 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
1362 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
1363 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
1364 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
1365 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
1366 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1367 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
1368 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1369 #if defined (STM32F769xx) || defined (STM32F779xx)
1370 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
1371 #endif /* STM32F769xx || STM32F779xx */
1372 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1373 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
1374 #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
1375 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1376
1377 /**
1378 * @}
1379 */
1380
1381
1382 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
1383 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
1384 * @note After reset, the peripheral clock (used for registers read/write access)
1385 * is disabled and the application software has to enable this clock before
1386 * using it.
1387 * @{
1388 */
1389
1390 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
1391 * @note After reset, the peripheral clock (used for registers read/write access)
1392 * is disabled and the application software has to enable this clock before
1393 * using it.
1394 */
1395 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
1396 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
1397 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
1398 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
1399 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
1400 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
1401 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
1402 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
1403 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
1404 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
1405 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
1406 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
1407 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
1408 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
1409 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
1410 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
1411 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
1412
1413 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
1414 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
1415 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
1416 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
1417 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
1418 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
1419 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
1420 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
1421 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
1422 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
1423 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
1424 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
1425 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
1426 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
1427 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
1428 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
1429 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
1430 /**
1431 * @brief Enable ETHERNET clock.
1432 */
1433 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
1434 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
1435 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
1436 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
1437 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
1438 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
1439 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
1440
1441 /**
1442 * @brief Disable ETHERNET clock.
1443 */
1444 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
1445 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
1446 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
1447 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
1448 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
1449 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
1450 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
1451
1452 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
1453 * @note After reset, the peripheral clock (used for registers read/write access)
1454 * is disabled and the application software has to enable this clock before
1455 * using it.
1456 */
1457 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
1458 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
1459 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
1460
1461 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
1462 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
1463 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
1464
1465 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
1466 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
1467 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
1468 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
1469 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
1470 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
1471
1472 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1473 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
1474 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
1475 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1476
1477 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
1478 * @note After reset, the peripheral clock (used for registers read/write access)
1479 * is disabled and the application software has to enable this clock before
1480 * using it.
1481 */
1482 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1483 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1484
1485 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
1486 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
1487
1488 /** @brief Get the enable or disable status of the APB1 peripheral clock.
1489 * @note After reset, the peripheral clock (used for registers read/write access)
1490 * is disabled and the application software has to enable this clock before
1491 * using it.
1492 */
1493 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1494 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
1495 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1496 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1497 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1498 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1499 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1500 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1501 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1502 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
1503 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1504 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
1505 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
1506 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1507 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
1508 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1509 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
1510 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
1511 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1512 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1513 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1514 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
1515 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1516 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
1517 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
1518 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1519 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1520 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1521 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1522 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
1523 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
1524
1525 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
1526 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
1527 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1528 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1529 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1530 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1531 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1532 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1533 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1534 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
1535 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1536 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
1537 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
1538 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1539 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
1540 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1541 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
1542 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
1543 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1544 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1545 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1546 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
1547 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
1548 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
1549 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
1550 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1551 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1552 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
1553 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1554 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
1555 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
1556
1557 /** @brief Get the enable or disable status of the APB2 peripheral clock.
1558 * @note After reset, the peripheral clock (used for registers read/write access)
1559 * is disabled and the application software has to enable this clock before
1560 * using it.
1561 */
1562 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
1563 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1564 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
1565 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
1566 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
1567 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1568 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1569 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
1570 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
1571 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
1572 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
1573 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
1574 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
1575 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
1576 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
1577 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
1578 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
1579 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1580 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
1581 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1582 #if defined (STM32F769xx) || defined (STM32F779xx)
1583 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
1584 #endif /* STM32F769xx || STM32F779xx */
1585 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1586 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
1587 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
1588 #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
1589 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1590 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
1591 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1592 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
1593 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
1594 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
1595 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1596 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1597 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
1598 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
1599 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
1600 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
1601 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
1602 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
1603 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
1604 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
1605 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
1606 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
1607 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1608 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
1609 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1610 #if defined (STM32F769xx) || defined (STM32F779xx)
1611 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
1612 #endif /* STM32F769xx || STM32F779xx */
1613 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1614 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
1615 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
1616 #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
1617 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1618 /**
1619 * @}
1620 */
1621
1622 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
1623 * @brief Forces or releases AHB/APB peripheral reset.
1624 * @{
1625 */
1626
1627 /** @brief Force or release AHB1 peripheral reset.
1628 */
1629 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
1630 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
1631 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
1632 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
1633 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
1634 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
1635 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
1636 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
1637 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
1638 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
1639 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
1640 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
1641 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
1642 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
1643 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
1644
1645 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
1646 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
1647 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
1648 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
1649 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
1650 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
1651 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
1652 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
1653 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
1654 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
1655 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
1656 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
1657 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
1658 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
1659 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
1660
1661 /** @brief Force or release AHB2 peripheral reset.
1662 */
1663 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
1664 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
1665 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
1666 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
1667
1668 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
1669 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
1670 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
1671 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
1672
1673 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1674 #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))
1675 #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
1676 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1677
1678 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
1679 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
1680 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
1681 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
1682 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
1683 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
1684
1685 /** @brief Force or release AHB3 peripheral reset
1686 */
1687 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
1688 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
1689 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
1690
1691 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
1692 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
1693 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
1694
1695 /** @brief Force or release APB1 peripheral reset.
1696 */
1697 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1698 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
1699 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1700 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1701 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1702 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1703 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1704 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1705 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1706 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
1707 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1708 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
1709 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1710 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
1711 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1712 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
1713 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
1714 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1715 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1716 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1717 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
1718 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
1719 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
1720 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
1721 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1722 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1723 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
1724 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1725 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
1726 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
1727
1728 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1729 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
1730 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1731 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1732 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1733 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1734 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1735 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1736 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1737 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
1738 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1739 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
1740 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1741 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
1742 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1743 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
1744 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
1745 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1746 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1747 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1748 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
1749 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
1750 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
1751 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
1752 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1753 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1754 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
1755 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1756 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
1757 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
1758
1759 /** @brief Force or release APB2 peripheral reset.
1760 */
1761 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
1762 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1763 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
1764 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
1765 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
1766 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
1767 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
1768 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
1769 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
1770 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1771 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
1772 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
1773 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
1774 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
1775 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
1776 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1777 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
1778 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1779
1780 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
1781 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1782 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
1783 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
1784 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
1785 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
1786 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
1787 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
1788 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
1789 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1790 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
1791 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
1792 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
1793 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
1794 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
1795 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1796 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
1797 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1798
1799 #if defined (STM32F769xx) || defined (STM32F779xx)
1800 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
1801 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
1802 #endif /* STM32F769xx || STM32F779xx */
1803
1804 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1805 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
1806 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
1807 #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))
1808
1809 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
1810 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
1811 #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
1812 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1813 /**
1814 * @}
1815 */
1816
1817 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
1818 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
1819 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1820 * power consumption.
1821 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1822 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1823 * @{
1824 */
1825
1826 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
1827 */
1828 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
1829 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
1830 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
1831 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
1832 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
1833 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
1834 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
1835 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
1836 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
1837 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
1838 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
1839 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
1840 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
1841 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
1842 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
1843 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
1844 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
1845 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
1846 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
1847 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
1848 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
1849 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
1850 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
1851 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
1852 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
1853
1854 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
1855 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
1856 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
1857 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
1858 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
1859 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
1860 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
1861 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
1862 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
1863 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
1864 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
1865 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
1866 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
1867 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
1868 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
1869 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
1870 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
1871 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
1872 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
1873 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
1874 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
1875 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
1876 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
1877 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
1878 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
1879
1880 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
1881 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1882 * power consumption.
1883 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1884 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1885 */
1886 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
1887 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
1888
1889 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1890 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
1891 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
1892 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1893
1894 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
1895 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
1896
1897 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
1898 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
1899
1900 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
1901 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
1902 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
1903
1904 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
1905 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
1906 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
1907
1908 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
1909 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1910 * power consumption.
1911 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1912 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1913 */
1914 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
1915 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
1916
1917 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
1918 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
1919
1920 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
1921 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1922 * power consumption.
1923 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1924 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1925 */
1926 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
1927 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
1928 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
1929 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
1930 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
1931 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
1932 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
1933 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
1934 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
1935 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
1936 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1937 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
1938 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
1939 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1940 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
1941 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
1942 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
1943 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
1944 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
1945 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
1946 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
1947 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
1948 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
1949 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
1950 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
1951 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
1952 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
1953 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
1954 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
1955 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
1956 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
1957
1958 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
1959 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
1960 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
1961 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
1962 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
1963 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
1964 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
1965 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
1966 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
1967 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
1968 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1969 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
1970 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
1971 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1972 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
1973 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
1974 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
1975 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
1976 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
1977 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
1978 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
1979 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
1980 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
1981 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
1982 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
1983 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
1984 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
1985 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
1986 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
1987 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
1988 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
1989
1990 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
1991 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1992 * power consumption.
1993 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1994 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1995 */
1996 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
1997 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
1998 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
1999 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
2000 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
2001 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
2002 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
2003 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
2004 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
2005 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
2006 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
2007 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
2008 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
2009 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
2010 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
2011 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
2012 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
2013 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2014 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
2015 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2016
2017 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
2018 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
2019 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
2020 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
2021 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
2022 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
2023 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
2024 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
2025 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
2026 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
2027 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
2028 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
2029 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
2030 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
2031 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
2032 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
2033 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
2034 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2035 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
2036 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2037 #if defined (STM32F769xx) || defined (STM32F779xx)
2038 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
2039 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
2040 #endif /* STM32F769xx || STM32F779xx */
2041 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2042 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
2043 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
2044 #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))
2045
2046 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
2047 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
2048 #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
2049 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2050 /**
2051 * @}
2052 */
2053
2054 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
2055 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
2056 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2057 * power consumption.
2058 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2059 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2060 * @{
2061 */
2062
2063 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
2064 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2065 * power consumption.
2066 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2067 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2068 */
2069 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
2070 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
2071 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
2072 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
2073 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
2074 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
2075 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
2076 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
2077 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
2078 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
2079 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
2080 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
2081 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
2082 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
2083 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
2084 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
2085 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
2086 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
2087 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
2088 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
2089 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
2090 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
2091 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
2092 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
2093 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
2094
2095 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
2096 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
2097 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
2098 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
2099 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
2100 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
2101 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
2102 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
2103 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
2104 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
2105 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
2106 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
2107 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
2108 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
2109 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
2110 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
2111 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
2112 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
2113 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
2114 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
2115 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
2116 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
2117 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
2118 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
2119 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
2120
2121 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
2122 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2123 * power consumption.
2124 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2125 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2126 */
2127 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
2128 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
2129
2130 #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2131 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
2132 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
2133 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2134
2135 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
2136 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
2137
2138 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
2139 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
2140
2141 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
2142 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
2143 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
2144
2145 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
2146 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
2147 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
2148
2149 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
2150 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2151 * power consumption.
2152 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2153 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2154 */
2155 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
2156 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
2157
2158 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
2159 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
2160
2161 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
2162 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2163 * power consumption.
2164 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2165 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2166 */
2167 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
2168 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
2169 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
2170 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
2171 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
2172 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
2173 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
2174 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
2175 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
2176 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
2177 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2178 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
2179 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
2180 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2181 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
2182 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
2183 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
2184 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
2185 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
2186 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
2187 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
2188 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
2189 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
2190 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
2191 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
2192 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
2193 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
2194 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
2195 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
2196 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
2197 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
2198
2199 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
2200 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
2201 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
2202 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
2203 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
2204 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
2205 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
2206 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
2207 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
2208 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
2209 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2210 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
2211 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
2212 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2213 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
2214 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
2215 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
2216 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
2217 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
2218 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
2219 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
2220 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
2221 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
2222 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
2223 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
2224 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
2225 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
2226 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
2227 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
2228 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
2229 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
2230
2231 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
2232 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2233 * power consumption.
2234 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2235 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2236 */
2237 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
2238 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
2239 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
2240 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
2241 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
2242 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
2243 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
2244 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
2245 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
2246 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
2247 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
2248 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
2249 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
2250 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
2251 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
2252 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
2253 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
2254 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2255 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
2256 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2257 #if defined (STM32F769xx) || defined (STM32F779xx)
2258 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
2259 #endif /* STM32F769xx || STM32F779xx */
2260 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2261 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
2262 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
2263 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
2264 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2265
2266 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
2267 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
2268 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
2269 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
2270 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
2271 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
2272 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
2273 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
2274 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
2275 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
2276 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
2277 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
2278 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
2279 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
2280 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
2281 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
2282 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
2283 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2284 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
2285 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2286 #if defined (STM32F769xx) || defined (STM32F779xx)
2287 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
2288 #endif /* STM32F769xx || STM32F779xx */
2289 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2290 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
2291 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
2292 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
2293 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2294 /**
2295 * @}
2296 */
2297
2298 /*------------------------------- PLL Configuration --------------------------*/
2299 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2300 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
2301 * @note This function must be used only when the main PLL is disabled.
2302 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
2303 * This parameter can be one of the following values:
2304 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
2305 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
2306 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
2307 * @param __PLLM__: specifies the division factor for PLL VCO input clock
2308 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
2309 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
2310 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
2311 * of 2 MHz to limit PLL jitter.
2312 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
2313 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
2314 * @note You have to set the PLLN parameter correctly to ensure that the VCO
2315 * output frequency is between 100 and 432 MHz.
2316 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
2317 * This parameter must be a number in the range {2, 4, 6, or 8}.
2318 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
2319 * the System clock frequency.
2320 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
2321 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
2322 * @note If the USB OTG FS is used in your application, you have to set the
2323 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
2324 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
2325 * correctly.
2326 * @param __PLLR__: specifies the division factor for DSI clock
2327 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
2328 */
2329 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
2330 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
2331 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
2332 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
2333 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
2334 ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
2335 #else
2336 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
2337 * @note This function must be used only when the main PLL is disabled.
2338 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
2339 * This parameter can be one of the following values:
2340 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
2341 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
2342 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
2343 * @param __PLLM__: specifies the division factor for PLL VCO input clock
2344 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
2345 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
2346 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
2347 * of 2 MHz to limit PLL jitter.
2348 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
2349 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
2350 * @note You have to set the PLLN parameter correctly to ensure that the VCO
2351 * output frequency is between 100 and 432 MHz.
2352 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
2353 * This parameter must be a number in the range {2, 4, 6, or 8}.
2354 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
2355 * the System clock frequency.
2356 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
2357 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
2358 * @note If the USB OTG FS is used in your application, you have to set the
2359 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
2360 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
2361 * correctly.
2362 */
2363 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
2364 (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
2365 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
2366 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
2367 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
2368 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2369 /*---------------------------------------------------------------------------------------------*/
2370
2371 /** @brief Macro to configure the Timers clocks prescalers
2372 * @param __PRESC__ : specifies the Timers clocks prescalers selection
2373 * This parameter can be one of the following values:
2374 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
2375 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
2376 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
2377 * division by 4 or more.
2378 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
2379 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
2380 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
2381 * to division by 8 or more.
2382 */
2383 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
2384 RCC->DCKCFGR1 |= (__PRESC__); \
2385 }while(0)
2386
2387 /** @brief Macros to Enable or Disable the PLLISAI.
2388 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
2389 */
2390 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
2391 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
2392
2393 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
2394 * @note This function must be used only when the PLLSAI is disabled.
2395 * @note PLLSAI clock source is common with the main PLL (configured in
2396 * RCC_PLLConfig function )
2397 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
2398 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
2399 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
2400 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
2401 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
2402 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
2403 * @param __PLLSAIQ__: specifies the division factor for SAI clock
2404 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
2405 * @param __PLLSAIR__: specifies the division factor for LTDC clock
2406 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
2407 */
2408 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
2409 (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
2410 ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
2411 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
2412 ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
2413
2414 /** @brief Macro to configure the PLLI2S clock multiplication and division factors.
2415 * @note This macro must be used only when the PLLI2S is disabled.
2416 * @note PLLI2S clock source is common with the main PLL (configured in
2417 * HAL_RCC_ClockConfig() API)
2418 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
2419 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
2420 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
2421 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
2422 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
2423 * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
2424 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
2425 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
2426 * @param __PLLI2SR__: specifies the division factor for I2S clock
2427 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
2428 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
2429 * on the I2S clock frequency.
2430 */
2431 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
2432 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
2433 ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
2434 ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
2435 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
2436
2437 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
2438 * @note This function must be called before enabling the PLLI2S.
2439 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
2440 * This parameter must be a number between 1 and 32.
2441 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
2442 */
2443 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
2444
2445 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
2446 * @note This function must be called before enabling the PLLSAI.
2447 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
2448 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
2449 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
2450 */
2451 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
2452
2453 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
2454 *
2455 * @note This function must be called before enabling the PLLSAI.
2456 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
2457 * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
2458 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
2459 */
2460 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
2461 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
2462
2463 /** @brief Macro to configure SAI1 clock source selection.
2464 * @note This function must be called before enabling PLLSAI, PLLI2S and
2465 * the SAI clock.
2466 * @param __SOURCE__: specifies the SAI1 clock source.
2467 * This parameter can be one of the following values:
2468 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
2469 * as SAI1 clock.
2470 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
2471 * as SAI1 clock.
2472 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
2473 * used as SAI1 clock.
2474 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
2475 * used as SAI1 clock.
2476 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
2477 */
2478 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
2479 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
2480
2481 /** @brief Macro to get the SAI1 clock source.
2482 * @retval The clock source can be one of the following values:
2483 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
2484 * as SAI1 clock.
2485 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
2486 * as SAI1 clock.
2487 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
2488 * used as SAI1 clock.
2489 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
2490 * used as SAI1 clock.
2491 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
2492 */
2493 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
2494
2495
2496 /** @brief Macro to configure SAI2 clock source selection.
2497 * @note This function must be called before enabling PLLSAI, PLLI2S and
2498 * the SAI clock.
2499 * @param __SOURCE__: specifies the SAI2 clock source.
2500 * This parameter can be one of the following values:
2501 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
2502 * as SAI2 clock.
2503 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
2504 * as SAI2 clock.
2505 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
2506 * used as SAI2 clock.
2507 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
2508 * used as SAI2 clock.
2509 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
2510 */
2511 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
2512 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
2513
2514
2515 /** @brief Macro to get the SAI2 clock source.
2516 * @retval The clock source can be one of the following values:
2517 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
2518 * as SAI2 clock.
2519 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
2520 * as SAI2 clock.
2521 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
2522 * used as SAI2 clock.
2523 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
2524 * used as SAI2 clock.
2525 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
2526 */
2527 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
2528
2529
2530 /** @brief Enable PLLSAI_RDY interrupt.
2531 */
2532 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
2533
2534 /** @brief Disable PLLSAI_RDY interrupt.
2535 */
2536 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
2537
2538 /** @brief Clear the PLLSAI RDY interrupt pending bits.
2539 */
2540 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
2541
2542 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
2543 * @retval The new state (TRUE or FALSE).
2544 */
2545 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
2546
2547 /** @brief Check PLLSAI RDY flag is set or not.
2548 * @retval The new state (TRUE or FALSE).
2549 */
2550 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
2551
2552 /** @brief Macro to Get I2S clock source selection.
2553 * @retval The clock source can be one of the following values:
2554 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
2555 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
2556 */
2557 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
2558
2559 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
2560 *
2561 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
2562 * This parameter can be one of the following values:
2563 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
2564 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
2565 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
2566 */
2567 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
2568 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
2569
2570 /** @brief Macro to get the I2C1 clock source.
2571 * @retval The clock source can be one of the following values:
2572 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
2573 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
2574 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
2575 */
2576 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
2577
2578 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
2579 *
2580 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
2581 * This parameter can be one of the following values:
2582 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
2583 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
2584 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
2585 */
2586 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
2587 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
2588
2589 /** @brief Macro to get the I2C2 clock source.
2590 * @retval The clock source can be one of the following values:
2591 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
2592 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
2593 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
2594 */
2595 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
2596
2597 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
2598 *
2599 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
2600 * This parameter can be one of the following values:
2601 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
2602 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
2603 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
2604 */
2605 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
2606 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
2607
2608 /** @brief macro to get the I2C3 clock source.
2609 * @retval The clock source can be one of the following values:
2610 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
2611 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
2612 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
2613 */
2614 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
2615
2616 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
2617 *
2618 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
2619 * This parameter can be one of the following values:
2620 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
2621 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
2622 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
2623 */
2624 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
2625 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
2626
2627 /** @brief macro to get the I2C4 clock source.
2628 * @retval The clock source can be one of the following values:
2629 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
2630 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
2631 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
2632 */
2633 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
2634
2635 /** @brief Macro to configure the USART1 clock (USART1CLK).
2636 *
2637 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
2638 * This parameter can be one of the following values:
2639 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
2640 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
2641 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
2642 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
2643 */
2644 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
2645 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
2646
2647 /** @brief macro to get the USART1 clock source.
2648 * @retval The clock source can be one of the following values:
2649 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
2650 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
2651 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
2652 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
2653 */
2654 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
2655
2656 /** @brief Macro to configure the USART2 clock (USART2CLK).
2657 *
2658 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
2659 * This parameter can be one of the following values:
2660 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
2661 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
2662 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
2663 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
2664 */
2665 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
2666 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
2667
2668 /** @brief macro to get the USART2 clock source.
2669 * @retval The clock source can be one of the following values:
2670 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
2671 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
2672 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
2673 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
2674 */
2675 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
2676
2677 /** @brief Macro to configure the USART3 clock (USART3CLK).
2678 *
2679 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
2680 * This parameter can be one of the following values:
2681 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
2682 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
2683 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
2684 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
2685 */
2686 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
2687 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
2688
2689 /** @brief macro to get the USART3 clock source.
2690 * @retval The clock source can be one of the following values:
2691 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
2692 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
2693 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
2694 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
2695 */
2696 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
2697
2698 /** @brief Macro to configure the UART4 clock (UART4CLK).
2699 *
2700 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
2701 * This parameter can be one of the following values:
2702 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
2703 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
2704 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
2705 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
2706 */
2707 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
2708 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
2709
2710 /** @brief macro to get the UART4 clock source.
2711 * @retval The clock source can be one of the following values:
2712 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
2713 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
2714 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
2715 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
2716 */
2717 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
2718
2719 /** @brief Macro to configure the UART5 clock (UART5CLK).
2720 *
2721 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
2722 * This parameter can be one of the following values:
2723 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
2724 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
2725 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
2726 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
2727 */
2728 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
2729 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
2730
2731 /** @brief macro to get the UART5 clock source.
2732 * @retval The clock source can be one of the following values:
2733 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
2734 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
2735 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
2736 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
2737 */
2738 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
2739
2740 /** @brief Macro to configure the USART6 clock (USART6CLK).
2741 *
2742 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
2743 * This parameter can be one of the following values:
2744 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
2745 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
2746 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
2747 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
2748 */
2749 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
2750 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
2751
2752 /** @brief macro to get the USART6 clock source.
2753 * @retval The clock source can be one of the following values:
2754 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
2755 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
2756 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
2757 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
2758 */
2759 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
2760
2761 /** @brief Macro to configure the UART7 clock (UART7CLK).
2762 *
2763 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
2764 * This parameter can be one of the following values:
2765 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
2766 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
2767 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
2768 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
2769 */
2770 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
2771 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
2772
2773 /** @brief macro to get the UART7 clock source.
2774 * @retval The clock source can be one of the following values:
2775 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
2776 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
2777 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
2778 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
2779 */
2780 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
2781
2782 /** @brief Macro to configure the UART8 clock (UART8CLK).
2783 *
2784 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
2785 * This parameter can be one of the following values:
2786 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
2787 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
2788 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
2789 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
2790 */
2791 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
2792 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
2793
2794 /** @brief macro to get the UART8 clock source.
2795 * @retval The clock source can be one of the following values:
2796 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
2797 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
2798 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
2799 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
2800 */
2801 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
2802
2803 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
2804 *
2805 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
2806 * This parameter can be one of the following values:
2807 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
2808 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
2809 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
2810 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
2811 */
2812 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
2813 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
2814
2815 /** @brief macro to get the LPTIM1 clock source.
2816 * @retval The clock source can be one of the following values:
2817 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
2818 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
2819 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
2820 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
2821 */
2822 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
2823
2824 /** @brief Macro to configure the CEC clock (CECCLK).
2825 *
2826 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
2827 * This parameter can be one of the following values:
2828 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
2829 * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
2830 */
2831 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
2832 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
2833
2834 /** @brief macro to get the CEC clock source.
2835 * @retval The clock source can be one of the following values:
2836 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
2837 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
2838 */
2839 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
2840
2841 /** @brief Macro to configure the CLK48 source (CLK48CLK).
2842 *
2843 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
2844 * This parameter can be one of the following values:
2845 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
2846 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
2847 */
2848 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
2849 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
2850
2851 /** @brief macro to get the CLK48 source.
2852 * @retval The clock source can be one of the following values:
2853 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
2854 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
2855 */
2856 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
2857
2858 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
2859 *
2860 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
2861 * This parameter can be one of the following values:
2862 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
2863 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
2864 */
2865 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
2866 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
2867
2868 /** @brief macro to get the SDMMC1 clock source.
2869 * @retval The clock source can be one of the following values:
2870 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
2871 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
2872 */
2873 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
2874
2875 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2876 /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
2877 * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
2878 * This parameter can be one of the following values:
2879 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
2880 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
2881 */
2882 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
2883 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
2884
2885 /** @brief macro to get the SDMMC2 clock source.
2886 * @retval The clock source can be one of the following values:
2887 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
2888 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
2889 */
2890 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
2891
2892 /** @brief Macro to configure the DFSDM1 clock
2893 * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
2894 * This parameter can be one of the following values:
2895 * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock
2896 * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
2897 */
2898 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
2899 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
2900
2901 /** @brief Macro to get the DFSDM1 clock source.
2902 * @retval The clock source can be one of the following values:
2903 * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock
2904 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock
2905 */
2906 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
2907
2908 /** @brief Macro to configure the DFSDM1 Audio clock
2909 * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
2910 * This parameter can be one of the following values:
2911 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
2912 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
2913 */
2914 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
2915 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
2916
2917 /** @brief Macro to get the DFSDM1 Audio clock source.
2918 * @retval The clock source can be one of the following values:
2919 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
2920 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
2921 */
2922 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
2923 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2924
2925 #if defined (STM32F769xx) || defined (STM32F779xx)
2926 /** @brief Macro to configure the DSI clock.
2927 * @param __DSI_CLKSOURCE__: specifies the DSI clock source.
2928 * This parameter can be one of the following values:
2929 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
2930 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
2931 */
2932 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
2933
2934 /** @brief Macro to Get the DSI clock.
2935 * @retval The clock source can be one of the following values:
2936 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
2937 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
2938 */
2939 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
2940 #endif /* STM32F769xx || STM32F779xx */
2941 /**
2942 * @}
2943 */
2944
2945 /* Exported functions --------------------------------------------------------*/
2946 /** @addtogroup RCCEx_Exported_Functions_Group1
2947 * @{
2948 */
2949 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
2950 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
2951 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
2952
2953 /**
2954 * @}
2955 */
2956 /* Private macros ------------------------------------------------------------*/
2957 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
2958 * @{
2959 */
2960 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
2961 * @{
2962 */
2963 #if defined(STM32F756xx) || defined(STM32F746xx)
2964 #define IS_RCC_PERIPHCLOCK(SELECTION) \
2965 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
2966 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
2967 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
2968 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2969 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2970 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2971 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2972 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2973 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
2974 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
2975 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
2976 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2977 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2978 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2979 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2980 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2981 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2982 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2983 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
2984 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
2985 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
2986 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
2987 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
2988 #elif defined(STM32F745xx)
2989 #define IS_RCC_PERIPHCLOCK(SELECTION) \
2990 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
2991 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
2992 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2993 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2994 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2995 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2996 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2997 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
2998 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
2999 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
3000 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
3001 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
3002 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
3003 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
3004 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
3005 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
3006 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
3007 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
3008 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
3009 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
3010 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
3011 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
3012 #elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
3013 #define IS_RCC_PERIPHCLOCK(SELECTION) \
3014 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
3015 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
3016 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
3017 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
3018 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
3019 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
3020 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
3021 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
3022 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
3023 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
3024 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
3025 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
3026 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
3027 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
3028 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
3029 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
3030 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
3031 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
3032 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
3033 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
3034 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
3035 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
3036 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
3037 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
3038 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
3039 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
3040 #elif defined (STM32F765xx)
3041 #define IS_RCC_PERIPHCLOCK(SELECTION) \
3042 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
3043 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
3044 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
3045 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
3046 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
3047 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
3048 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
3049 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
3050 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
3051 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
3052 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
3053 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
3054 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
3055 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
3056 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
3057 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
3058 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
3059 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
3060 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
3061 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
3062 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
3063 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
3064 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
3065 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
3066 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
3067 #endif /* STM32F746xx || STM32F756xx */
3068 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
3069 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
3070 ((VALUE) == RCC_PLLI2SP_DIV4) ||\
3071 ((VALUE) == RCC_PLLI2SP_DIV6) ||\
3072 ((VALUE) == RCC_PLLI2SP_DIV8))
3073 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
3074 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
3075
3076 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
3077 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
3078 ((VALUE) == RCC_PLLSAIP_DIV4) ||\
3079 ((VALUE) == RCC_PLLSAIP_DIV6) ||\
3080 ((VALUE) == RCC_PLLSAIP_DIV8))
3081 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
3082 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
3083
3084 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
3085
3086 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
3087
3088 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
3089 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
3090 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
3091 ((VALUE) == RCC_PLLSAIDIVR_16))
3092 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
3093 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
3094
3095 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
3096 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
3097
3098 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
3099 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
3100 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
3101 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
3102 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
3103 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
3104 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
3105
3106 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
3107 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
3108 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
3109 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
3110 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
3111 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
3112 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
3113 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
3114 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
3115 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
3116
3117 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
3118 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
3119 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
3120 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
3121 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
3122
3123 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
3124 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
3125 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
3126 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
3127 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
3128
3129 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
3130 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
3131 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
3132 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
3133 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
3134
3135 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
3136 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
3137 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
3138 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
3139 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
3140
3141 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
3142 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
3143 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
3144 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
3145 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
3146 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
3147 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
3148 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
3149 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
3150 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
3151 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
3152 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
3153 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
3154
3155 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
3156 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
3157 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
3158 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
3159 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
3160 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
3161 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
3162 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
3163 #define IS_RCC_LPTIM1CLK(SOURCE) \
3164 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
3165 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
3166 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
3167 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
3168 #define IS_RCC_CLK48SOURCE(SOURCE) \
3169 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
3170 ((SOURCE) == RCC_CLK48SOURCE_PLL))
3171 #define IS_RCC_TIMPRES(VALUE) \
3172 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
3173 ((VALUE) == RCC_TIMPRES_ACTIVATED))
3174
3175 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)
3176 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
3177 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
3178 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
3179 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
3180 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
3181 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
3182 #endif /* STM32F745xx || STM32F746xx || STM32F756xx */
3183
3184 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
3185 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
3186
3187 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
3188 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
3189 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \
3190 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
3191
3192 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
3193 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
3194 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \
3195 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
3196
3197 #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
3198 ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
3199
3200 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \
3201 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
3202
3203 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
3204 ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
3205 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
3206
3207 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
3208 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
3209 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
3210 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
3211
3212 /**
3213 * @}
3214 */
3215
3216 /**
3217 * @}
3218 */
3219
3220 /**
3221 * @}
3222 */
3223
3224 /**
3225 * @}
3226 */
3227 #ifdef __cplusplus
3228 }
3229 #endif
3230
3231 #endif /* __STM32F7xx_HAL_RCC_EX_H */
3232
3233 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)