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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_adc_ex.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the ADC extension peripheral:
9 * + Extended features functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
17 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
18 (##) ADC pins configuration
19 (+++) Enable the clock for the ADC GPIOs using the following function:
20 __HAL_RCC_GPIOx_CLK_ENABLE()
21 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
22 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
23 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
24 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
25 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
26 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
27 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
28 (+++) Configure and enable two DMA streams stream for managing data
29 transfer from peripheral to memory (output stream)
30 (+++) Associate the initialized DMA handle to the ADC DMA handle
31 using __HAL_LINKDMA()
32 (+++) Configure the priority and enable the NVIC for the transfer complete
33 interrupt on the two DMA Streams. The output stream should have higher
34 priority than the input stream.
35 (#) Configure the ADC Prescaler, conversion resolution and data alignment
36 using the HAL_ADC_Init() function.
37
38 (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
39 and HAL_ADC_ConfigChannel() functions.
40
41 (#) Three operation modes are available within this driver :
42
43 *** Polling mode IO operation ***
44 =================================
45 [..]
46 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
47 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
48 user can specify the value of timeout according to his end application
49 (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
50 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
51
52 *** Interrupt mode IO operation ***
53 ===================================
54 [..]
55 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
56 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
57 (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
58 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
59 (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
60 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
61 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
62
63
64 *** DMA mode IO operation ***
65 ==============================
66 [..]
67 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
68 of data to be transferred at each end of conversion
69 (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
70 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
71 (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
72 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
73 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
74
75 *** Multi mode ADCs Regular channels configuration ***
76 ======================================================
77 [..]
78 (+) Select the Multi mode ADC regular channels features (dual or triple mode)
79 and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
80 (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
81 of data to be transferred at each end of conversion
82 (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
83
84
85 @endverbatim
86 ******************************************************************************
87 * @attention
88 *
89 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
90 *
91 * Redistribution and use in source and binary forms, with or without modification,
92 * are permitted provided that the following conditions are met:
93 * 1. Redistributions of source code must retain the above copyright notice,
94 * this list of conditions and the following disclaimer.
95 * 2. Redistributions in binary form must reproduce the above copyright notice,
96 * this list of conditions and the following disclaimer in the documentation
97 * and/or other materials provided with the distribution.
98 * 3. Neither the name of STMicroelectronics nor the names of its contributors
99 * may be used to endorse or promote products derived from this software
100 * without specific prior written permission.
101 *
102 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
103 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
104 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
105 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
106 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
107 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
108 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
109 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
110 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
111 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
112 *
113 ******************************************************************************
114 */
115
116 /* Includes ------------------------------------------------------------------*/
117 #include "stm32f7xx_hal.h"
118
119 /** @addtogroup STM32F7xx_HAL_Driver
120 * @{
121 */
122
123 /** @defgroup ADCEx ADCEx
124 * @brief ADC Extended driver modules
125 * @{
126 */
127
128 #ifdef HAL_ADC_MODULE_ENABLED
129
130 /* Private typedef -----------------------------------------------------------*/
131 /* Private define ------------------------------------------------------------*/
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /** @addtogroup ADCEx_Private_Functions
135 * @{
136 */
137 /* Private function prototypes -----------------------------------------------*/
138 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
139 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
140 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
141 /**
142 * @}
143 */
144
145 /* Exported functions --------------------------------------------------------*/
146 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions
147 * @{
148 */
149
150 /** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
151 * @brief Extended features functions
152 *
153 @verbatim
154 ===============================================================================
155 ##### Extended features functions #####
156 ===============================================================================
157 [..] This section provides functions allowing to:
158 (+) Start conversion of injected channel.
159 (+) Stop conversion of injected channel.
160 (+) Start multimode and enable DMA transfer.
161 (+) Stop multimode and disable DMA transfer.
162 (+) Get result of injected channel conversion.
163 (+) Get result of multimode conversion.
164 (+) Configure injected channels.
165 (+) Configure multimode.
166
167 @endverbatim
168 * @{
169 */
170
171 /**
172 * @brief Enables the selected ADC software start conversion of the injected channels.
173 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
174 * the configuration information for the specified ADC.
175 * @retval HAL status
176 */
177 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
178 {
179 __IO uint32_t counter = 0;
180 uint32_t tmp1 = 0, tmp2 = 0;
181
182 /* Process locked */
183 __HAL_LOCK(hadc);
184
185 /* Enable the ADC peripheral */
186
187 /* Check if ADC peripheral is disabled in order to enable it and wait during
188 Tstab time the ADC's stabilization */
189 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
190 {
191 /* Enable the Peripheral */
192 __HAL_ADC_ENABLE(hadc);
193
194 /* Delay for ADC stabilization time */
195 /* Compute number of CPU cycles to wait for */
196 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
197 while(counter != 0)
198 {
199 counter--;
200 }
201 }
202
203 /* Start conversion if ADC is effectively enabled */
204 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
205 {
206 /* Set ADC state */
207 /* - Clear state bitfield related to injected group conversion results */
208 /* - Set state bitfield related to injected operation */
209 ADC_STATE_CLR_SET(hadc->State,
210 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
211 HAL_ADC_STATE_INJ_BUSY);
212
213 /* Check if a regular conversion is ongoing */
214 /* Note: On this device, there is no ADC error code fields related to */
215 /* conversions on group injected only. In case of conversion on */
216 /* going on group regular, no error code is reset. */
217 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
218 {
219 /* Reset ADC all error code fields */
220 ADC_CLEAR_ERRORCODE(hadc);
221 }
222
223 /* Process unlocked */
224 /* Unlock before starting ADC conversions: in case of potential */
225 /* interruption, to let the process to ADC IRQ Handler. */
226 __HAL_UNLOCK(hadc);
227
228 /* Clear injected group conversion flag */
229 /* (To ensure of no unknown state from potential previous ADC operations) */
230 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
231
232 /* Check if Multimode enabled */
233 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
234 {
235 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
236 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
237 if(tmp1 && tmp2)
238 {
239 /* Enable the selected ADC software conversion for injected group */
240 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
241 }
242 }
243 else
244 {
245 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
246 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
247 if((hadc->Instance == ADC1) && tmp1 && tmp2)
248 {
249 /* Enable the selected ADC software conversion for injected group */
250 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
251 }
252 }
253 }
254
255 /* Return function status */
256 return HAL_OK;
257 }
258
259 /**
260 * @brief Enables the interrupt and starts ADC conversion of injected channels.
261 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
262 * the configuration information for the specified ADC.
263 *
264 * @retval HAL status.
265 */
266 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
267 {
268 __IO uint32_t counter = 0;
269 uint32_t tmp1 = 0, tmp2 = 0;
270
271 /* Process locked */
272 __HAL_LOCK(hadc);
273
274 /* Enable the ADC peripheral */
275
276 /* Check if ADC peripheral is disabled in order to enable it and wait during
277 Tstab time the ADC's stabilization */
278 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
279 {
280 /* Enable the Peripheral */
281 __HAL_ADC_ENABLE(hadc);
282
283 /* Delay for ADC stabilization time */
284 /* Compute number of CPU cycles to wait for */
285 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
286 while(counter != 0)
287 {
288 counter--;
289 }
290 }
291
292 /* Start conversion if ADC is effectively enabled */
293 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
294 {
295 /* Set ADC state */
296 /* - Clear state bitfield related to injected group conversion results */
297 /* - Set state bitfield related to injected operation */
298 ADC_STATE_CLR_SET(hadc->State,
299 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
300 HAL_ADC_STATE_INJ_BUSY);
301
302 /* Check if a regular conversion is ongoing */
303 /* Note: On this device, there is no ADC error code fields related to */
304 /* conversions on group injected only. In case of conversion on */
305 /* going on group regular, no error code is reset. */
306 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
307 {
308 /* Reset ADC all error code fields */
309 ADC_CLEAR_ERRORCODE(hadc);
310 }
311
312 /* Process unlocked */
313 /* Unlock before starting ADC conversions: in case of potential */
314 /* interruption, to let the process to ADC IRQ Handler. */
315 __HAL_UNLOCK(hadc);
316
317 /* Clear injected group conversion flag */
318 /* (To ensure of no unknown state from potential previous ADC operations) */
319 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
320
321 /* Enable end of conversion interrupt for injected channels */
322 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
323
324 /* Check if Multimode enabled */
325 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
326 {
327 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
328 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
329 if(tmp1 && tmp2)
330 {
331 /* Enable the selected ADC software conversion for injected group */
332 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
333 }
334 }
335 else
336 {
337 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
338 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
339 if((hadc->Instance == ADC1) && tmp1 && tmp2)
340 {
341 /* Enable the selected ADC software conversion for injected group */
342 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
343 }
344 }
345 }
346
347 /* Return function status */
348 return HAL_OK;
349 }
350
351 /**
352 * @brief Stop conversion of injected channels. Disable ADC peripheral if
353 * no regular conversion is on going.
354 * @note If ADC must be disabled and if conversion is on going on
355 * regular group, function HAL_ADC_Stop must be used to stop both
356 * injected and regular groups, and disable the ADC.
357 * @note If injected group mode auto-injection is enabled,
358 * function HAL_ADC_Stop must be used.
359 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
360 * @param hadc: ADC handle
361 * @retval None
362 */
363 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
364 {
365 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
366
367 /* Check the parameters */
368 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
369
370 /* Process locked */
371 __HAL_LOCK(hadc);
372
373 /* Stop potential conversion and disable ADC peripheral */
374 /* Conditioned to: */
375 /* - No conversion on the other group (regular group) is intended to */
376 /* continue (injected and regular groups stop conversion and ADC disable */
377 /* are common) */
378 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
379 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
380 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
381 {
382 /* Stop potential conversion on going, on regular and injected groups */
383 /* Disable ADC peripheral */
384 __HAL_ADC_DISABLE(hadc);
385
386 /* Check if ADC is effectively disabled */
387 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
388 {
389 /* Set ADC state */
390 ADC_STATE_CLR_SET(hadc->State,
391 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
392 HAL_ADC_STATE_READY);
393 }
394 }
395 else
396 {
397 /* Update ADC state machine to error */
398 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
399
400 tmp_hal_status = HAL_ERROR;
401 }
402
403 /* Process unlocked */
404 __HAL_UNLOCK(hadc);
405
406 /* Return function status */
407 return tmp_hal_status;
408 }
409
410 /**
411 * @brief Poll for injected conversion complete
412 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
413 * the configuration information for the specified ADC.
414 * @param Timeout: Timeout value in millisecond.
415 * @retval HAL status
416 */
417 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
418 {
419 uint32_t tickstart = 0;
420
421 /* Get tick */
422 tickstart = HAL_GetTick();
423
424 /* Check End of conversion flag */
425 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
426 {
427 /* Check for the Timeout */
428 if(Timeout != HAL_MAX_DELAY)
429 {
430 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
431 {
432 hadc->State= HAL_ADC_STATE_TIMEOUT;
433 /* Process unlocked */
434 __HAL_UNLOCK(hadc);
435 return HAL_TIMEOUT;
436 }
437 }
438 }
439
440 /* Clear injected group conversion flag */
441 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
442
443 /* Update ADC state machine */
444 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
445
446 /* Determine whether any further conversion upcoming on group injected */
447 /* by external trigger, continuous mode or scan sequence on going. */
448 /* Note: On STM32F7, there is no independent flag of end of sequence. */
449 /* The test of scan sequence on going is done either with scan */
450 /* sequence disabled or with end of conversion flag set to */
451 /* of end of sequence. */
452 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
453 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
454 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
455 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
456 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
457 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
458 {
459 /* Set ADC state */
460 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
461
462 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
463 {
464 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
465 }
466 }
467
468 /* Return ADC state */
469 return HAL_OK;
470 }
471
472 /**
473 * @brief Stop conversion of injected channels, disable interruption of
474 * end-of-conversion. Disable ADC peripheral if no regular conversion
475 * is on going.
476 * @note If ADC must be disabled and if conversion is on going on
477 * regular group, function HAL_ADC_Stop must be used to stop both
478 * injected and regular groups, and disable the ADC.
479 * @note If injected group mode auto-injection is enabled,
480 * function HAL_ADC_Stop must be used.
481 * @param hadc: ADC handle
482 * @retval None
483 */
484 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
485 {
486 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
487
488 /* Check the parameters */
489 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
490
491 /* Process locked */
492 __HAL_LOCK(hadc);
493
494 /* Stop potential conversion and disable ADC peripheral */
495 /* Conditioned to: */
496 /* - No conversion on the other group (regular group) is intended to */
497 /* continue (injected and regular groups stop conversion and ADC disable */
498 /* are common) */
499 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
500 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
501 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
502 {
503 /* Stop potential conversion on going, on regular and injected groups */
504 /* Disable ADC peripheral */
505 __HAL_ADC_DISABLE(hadc);
506
507 /* Check if ADC is effectively disabled */
508 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
509 {
510 /* Disable ADC end of conversion interrupt for injected channels */
511 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
512
513 /* Set ADC state */
514 ADC_STATE_CLR_SET(hadc->State,
515 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
516 HAL_ADC_STATE_READY);
517 }
518 }
519 else
520 {
521 /* Update ADC state machine to error */
522 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
523
524 tmp_hal_status = HAL_ERROR;
525 }
526
527 /* Process unlocked */
528 __HAL_UNLOCK(hadc);
529
530 /* Return function status */
531 return tmp_hal_status;
532 }
533
534 /**
535 * @brief Gets the converted value from data register of injected channel.
536 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
537 * the configuration information for the specified ADC.
538 * @param InjectedRank: the ADC injected rank.
539 * This parameter can be one of the following values:
540 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
541 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
542 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
543 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
544 * @retval None
545 */
546 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
547 {
548 __IO uint32_t tmp = 0;
549
550 /* Check the parameters */
551 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
552
553 /* Clear injected group conversion flag to have similar behaviour as */
554 /* regular group: reading data register also clears end of conversion flag. */
555 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
556
557 /* Return the selected ADC converted value */
558 switch(InjectedRank)
559 {
560 case ADC_INJECTED_RANK_4:
561 {
562 tmp = hadc->Instance->JDR4;
563 }
564 break;
565 case ADC_INJECTED_RANK_3:
566 {
567 tmp = hadc->Instance->JDR3;
568 }
569 break;
570 case ADC_INJECTED_RANK_2:
571 {
572 tmp = hadc->Instance->JDR2;
573 }
574 break;
575 case ADC_INJECTED_RANK_1:
576 {
577 tmp = hadc->Instance->JDR1;
578 }
579 break;
580 default:
581 break;
582 }
583 return tmp;
584 }
585
586 /**
587 * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
588 *
589 * @note Caution: This function must be used only with the ADC master.
590 *
591 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
592 * the configuration information for the specified ADC.
593 * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
594 * @param Length: The length of data to be transferred from ADC peripheral to memory.
595 * @retval HAL status
596 */
597 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
598 {
599 __IO uint32_t counter = 0;
600
601 /* Check the parameters */
602 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
603 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
604 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
605
606 /* Process locked */
607 __HAL_LOCK(hadc);
608
609 /* Check if ADC peripheral is disabled in order to enable it and wait during
610 Tstab time the ADC's stabilization */
611 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
612 {
613 /* Enable the Peripheral */
614 __HAL_ADC_ENABLE(hadc);
615
616 /* Delay for temperature sensor stabilization time */
617 /* Compute number of CPU cycles to wait for */
618 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
619 while(counter != 0)
620 {
621 counter--;
622 }
623 }
624
625 /* Start conversion if ADC is effectively enabled */
626 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
627 {
628 /* Set ADC state */
629 /* - Clear state bitfield related to regular group conversion results */
630 /* - Set state bitfield related to regular group operation */
631 ADC_STATE_CLR_SET(hadc->State,
632 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
633 HAL_ADC_STATE_REG_BUSY);
634
635 /* If conversions on group regular are also triggering group injected, */
636 /* update ADC state. */
637 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
638 {
639 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
640 }
641
642 /* State machine update: Check if an injected conversion is ongoing */
643 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
644 {
645 /* Reset ADC error code fields related to conversions on group regular */
646 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
647 }
648 else
649 {
650 /* Reset ADC all error code fields */
651 ADC_CLEAR_ERRORCODE(hadc);
652 }
653
654 /* Process unlocked */
655 /* Unlock before starting ADC conversions: in case of potential */
656 /* interruption, to let the process to ADC IRQ Handler. */
657 __HAL_UNLOCK(hadc);
658
659 /* Set the DMA transfer complete callback */
660 hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
661
662 /* Set the DMA half transfer complete callback */
663 hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
664
665 /* Set the DMA error callback */
666 hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
667
668 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
669 /* start (in case of SW start): */
670
671 /* Clear regular group conversion flag and overrun flag */
672 /* (To ensure of no unknown state from potential previous ADC operations) */
673 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
674
675 /* Enable ADC overrun interrupt */
676 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
677
678 if (hadc->Init.DMAContinuousRequests != DISABLE)
679 {
680 /* Enable the selected ADC DMA request after last transfer */
681 ADC->CCR |= ADC_CCR_DDS;
682 }
683 else
684 {
685 /* Disable the selected ADC EOC rising on each regular channel conversion */
686 ADC->CCR &= ~ADC_CCR_DDS;
687 }
688
689 /* Enable the DMA Stream */
690 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
691
692 /* if no external trigger present enable software conversion of regular channels */
693 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
694 {
695 /* Enable the selected ADC software conversion for regular group */
696 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
697 }
698 }
699
700 /* Return function status */
701 return HAL_OK;
702 }
703
704 /**
705 * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
706 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
707 * the configuration information for the specified ADC.
708 * @retval HAL status
709 */
710 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
711 {
712 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
713
714 /* Check the parameters */
715 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
716
717 /* Process locked */
718 __HAL_LOCK(hadc);
719
720 /* Stop potential conversion on going, on regular and injected groups */
721 /* Disable ADC peripheral */
722 __HAL_ADC_DISABLE(hadc);
723
724 /* Check if ADC is effectively disabled */
725 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
726 {
727 /* Disable the selected ADC DMA mode for multimode */
728 ADC->CCR &= ~ADC_CCR_DDS;
729
730 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
731 /* DMA transfer is on going) */
732 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
733
734 /* Disable ADC overrun interrupt */
735 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
736
737 /* Set ADC state */
738 ADC_STATE_CLR_SET(hadc->State,
739 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
740 HAL_ADC_STATE_READY);
741 }
742
743 /* Process unlocked */
744 __HAL_UNLOCK(hadc);
745
746 /* Return function status */
747 return tmp_hal_status;
748 }
749
750 /**
751 * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
752 * data in the selected multi mode.
753 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
754 * the configuration information for the specified ADC.
755 * @retval The converted data value.
756 */
757 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
758 {
759 /* Return the multi mode conversion value */
760 return ADC->CDR;
761 }
762
763 /**
764 * @brief Injected conversion complete callback in non blocking mode
765 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
766 * the configuration information for the specified ADC.
767 * @retval None
768 */
769 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
770 {
771 /* Prevent unused argument(s) compilation warning */
772 UNUSED(hadc);
773 /* NOTE : This function Should not be modified, when the callback is needed,
774 the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
775 */
776 }
777
778 /**
779 * @brief Configures for the selected ADC injected channel its corresponding
780 * rank in the sequencer and its sample time.
781 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
782 * the configuration information for the specified ADC.
783 * @param sConfigInjected: ADC configuration structure for injected channel.
784 * @retval None
785 */
786 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
787 {
788
789 #ifdef USE_FULL_ASSERT
790 uint32_t tmp = 0;
791 #endif /* USE_FULL_ASSERT */
792
793 /* Check the parameters */
794 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
795 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
796 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
797 assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
798 assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
799 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
800 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
801
802 #ifdef USE_FULL_ASSERT
803 tmp = ADC_GET_RESOLUTION(hadc);
804 assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
805 #endif /* USE_FULL_ASSERT */
806
807 if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
808 {
809 assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
810 }
811
812 /* Process locked */
813 __HAL_LOCK(hadc);
814
815 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
816 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
817 {
818 /* Clear the old sample time */
819 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
820
821 /* Set the new sample time */
822 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
823 }
824 else /* ADC_Channel include in ADC_Channel_[0..9] */
825 {
826 /* Clear the old sample time */
827 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
828
829 /* Set the new sample time */
830 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
831 }
832
833 /*---------------------------- ADCx JSQR Configuration -----------------*/
834 hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
835 hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
836
837 /* Rank configuration */
838
839 /* Clear the old SQx bits for the selected rank */
840 hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
841
842 /* Set the SQx bits for the selected rank */
843 hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
844
845 /* Enable external trigger if trigger selection is different of software */
846 /* start. */
847 /* Note: This configuration keeps the hardware feature of parameter */
848 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
849 /* software start. */
850 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
851 {
852 /* Select external trigger to start conversion */
853 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
854 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
855
856 /* Select external trigger polarity */
857 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
858 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
859 }
860 else
861 {
862 /* Reset the external trigger */
863 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
864 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
865 }
866
867 if (sConfigInjected->AutoInjectedConv != DISABLE)
868 {
869 /* Enable the selected ADC automatic injected group conversion */
870 hadc->Instance->CR1 |= ADC_CR1_JAUTO;
871 }
872 else
873 {
874 /* Disable the selected ADC automatic injected group conversion */
875 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
876 }
877
878 if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
879 {
880 /* Enable the selected ADC injected discontinuous mode */
881 hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
882 }
883 else
884 {
885 /* Disable the selected ADC injected discontinuous mode */
886 hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
887 }
888
889 switch(sConfigInjected->InjectedRank)
890 {
891 case 1:
892 /* Set injected channel 1 offset */
893 hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
894 hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
895 break;
896 case 2:
897 /* Set injected channel 2 offset */
898 hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
899 hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
900 break;
901 case 3:
902 /* Set injected channel 3 offset */
903 hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
904 hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
905 break;
906 default:
907 /* Set injected channel 4 offset */
908 hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
909 hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
910 break;
911 }
912
913 /* if ADC1 Channel_18 is selected enable VBAT Channel */
914 if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
915 {
916 /* Enable the VBAT channel*/
917 ADC->CCR |= ADC_CCR_VBATE;
918 }
919
920 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
921 if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
922 {
923 /* Enable the TSVREFE channel*/
924 ADC->CCR |= ADC_CCR_TSVREFE;
925 }
926
927 /* Process unlocked */
928 __HAL_UNLOCK(hadc);
929
930 /* Return function status */
931 return HAL_OK;
932 }
933
934 /**
935 * @brief Configures the ADC multi-mode
936 * @param hadc : pointer to a ADC_HandleTypeDef structure that contains
937 * the configuration information for the specified ADC.
938 * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains
939 * the configuration information for multimode.
940 * @retval HAL status
941 */
942 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
943 {
944 /* Check the parameters */
945 assert_param(IS_ADC_MODE(multimode->Mode));
946 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
947 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
948
949 /* Process locked */
950 __HAL_LOCK(hadc);
951
952 /* Set ADC mode */
953 ADC->CCR &= ~(ADC_CCR_MULTI);
954 ADC->CCR |= multimode->Mode;
955
956 /* Set the ADC DMA access mode */
957 ADC->CCR &= ~(ADC_CCR_DMA);
958 ADC->CCR |= multimode->DMAAccessMode;
959
960 /* Set delay between two sampling phases */
961 ADC->CCR &= ~(ADC_CCR_DELAY);
962 ADC->CCR |= multimode->TwoSamplingDelay;
963
964 /* Process unlocked */
965 __HAL_UNLOCK(hadc);
966
967 /* Return function status */
968 return HAL_OK;
969 }
970
971 /**
972 * @}
973 */
974
975 /**
976 * @brief DMA transfer complete callback.
977 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
978 * the configuration information for the specified DMA module.
979 * @retval None
980 */
981 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
982 {
983 /* Retrieve ADC handle corresponding to current DMA handle */
984 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
985
986 /* Update state machine on conversion status if not in error state */
987 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
988 {
989 /* Update ADC state machine */
990 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
991
992 /* Determine whether any further conversion upcoming on group regular */
993 /* by external trigger, continuous mode or scan sequence on going. */
994 /* Note: On STM32F7, there is no independent flag of end of sequence. */
995 /* The test of scan sequence on going is done either with scan */
996 /* sequence disabled or with end of conversion flag set to */
997 /* of end of sequence. */
998 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
999 (hadc->Init.ContinuousConvMode == DISABLE) &&
1000 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1001 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1002 {
1003 /* Disable ADC end of single conversion interrupt on group regular */
1004 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1005 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1006 /* by overrun IRQ process below. */
1007 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1008
1009 /* Set ADC state */
1010 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1011
1012 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1013 {
1014 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1015 }
1016 }
1017
1018 /* Conversion complete callback */
1019 HAL_ADC_ConvCpltCallback(hadc);
1020 }
1021 else
1022 {
1023 /* Call DMA error callback */
1024 hadc->DMA_Handle->XferErrorCallback(hdma);
1025 }
1026 }
1027
1028 /**
1029 * @brief DMA half transfer complete callback.
1030 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
1031 * the configuration information for the specified DMA module.
1032 * @retval None
1033 */
1034 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
1035 {
1036 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1037 /* Conversion complete callback */
1038 HAL_ADC_ConvHalfCpltCallback(hadc);
1039 }
1040
1041 /**
1042 * @brief DMA error callback
1043 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
1044 * the configuration information for the specified DMA module.
1045 * @retval None
1046 */
1047 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
1048 {
1049 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1050 hadc->State= HAL_ADC_STATE_ERROR_DMA;
1051 /* Set ADC error code to DMA error */
1052 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
1053 HAL_ADC_ErrorCallback(hadc);
1054 }
1055
1056 /**
1057 * @}
1058 */
1059
1060 #endif /* HAL_ADC_MODULE_ENABLED */
1061 /**
1062 * @}
1063 */
1064
1065 /**
1066 * @}
1067 */
1068
1069 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)