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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_dma2d.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief DMA2D HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the DMA2D peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 (#) Program the required configuration through the following parameters:
21 the transfer mode, the output color mode and the output offset using
22 HAL_DMA2D_Init() function.
23
24 (#) Program the required configuration through the following parameters:
25 the input color mode, the input color, the input alpha value, the alpha mode,
26 the red/blue swap mode, the inverted alpha mode and the input offset using
27 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
28
29 *** Polling mode IO operation ***
30 =================================
31 [..]
32 (#) Configure pdata parameter (explained hereafter), destination and data length
33 and enable the transfer using HAL_DMA2D_Start().
34 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
35 user can specify the value of timeout according to his end application.
36
37 *** Interrupt mode IO operation ***
38 ===================================
39 [..]
40 (#) Configure pdata parameter, destination and data length and enable
41 the transfer using HAL_DMA2D_Start_IT().
42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
44 add his own function by customization of function pointer XferCpltCallback (member
45 of DMA2D handle structure).
46 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
47 XferErrorCallback.
48
49 -@- In Register-to-Memory transfer mode, pdata parameter is the register
50 color, in Memory-to-memory or Memory-to-Memory with pixel format
51 conversion pdata is the source address.
52
53 -@- Configure the foreground source address, the background source address,
54 the destination and data length then Enable the transfer using
55 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
56 in interrupt mode.
57
58 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
59 are used if the memory to memory with blending transfer mode is selected.
60
61 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
62 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
63
64 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
65
66 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
67 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
68 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
69 HAL_DMA2D_DisableDeadTime().
70
71 (#) The transfer can be suspended, resumed and aborted using the following
72 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
73
74 (#) The CLUT loading can be suspended, resumed and aborted using the following
75 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
76 HAL_DMA2D_CLUTLoading_Abort().
77
78 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
79
80 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
81
82 *** DMA2D HAL driver macros list ***
83 =============================================
84 [..]
85 Below the list of most used macros in DMA2D HAL driver :
86
87 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
88 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
89 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
90 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
91 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
92 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
93
94 [..]
95 (@) You can refer to the DMA2D HAL driver header file for more useful macros
96
97 @endverbatim
98 ******************************************************************************
99 * @attention
100 *
101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
102 *
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
113 *
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
124 *
125 ******************************************************************************
126 */
127
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f7xx_hal.h"
130
131 /** @addtogroup STM32F7xx_HAL_Driver
132 * @{
133 */
134
135 /** @defgroup DMA2D DMA2D
136 * @brief DMA2D HAL module driver
137 * @{
138 */
139
140 #ifdef HAL_DMA2D_MODULE_ENABLED
141
142 /* Private types -------------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
145 * @{
146 */
147
148 /** @defgroup DMA2D_TimeOut DMA2D Time Out
149 * @{
150 */
151 #define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */
152 #define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */
153 /**
154 * @}
155 */
156
157 /** @defgroup DMA2D_Shifts DMA2D Shifts
158 * @{
159 */
160 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
161 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
162
163 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
164 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
165
166 #define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */
167 #define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */
168 #define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */
169
170 #define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */
171 #define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */
172 #define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */
173
174 #define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
175
176 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
177 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
178
179 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
180 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
181
182 #define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
183 /**
184 * @}
185 */
186
187 /**
188 * @}
189 */
190
191 /* Private variables ---------------------------------------------------------*/
192 /* Private constants ---------------------------------------------------------*/
193 /* Private macro -------------------------------------------------------------*/
194 /* Private function prototypes -----------------------------------------------*/
195 /** @addtogroup DMA2D_Private_Functions_Prototypes
196 * @{
197 */
198 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
199 /**
200 * @}
201 */
202
203 /* Private functions ---------------------------------------------------------*/
204 /* Exported functions --------------------------------------------------------*/
205 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
206 * @{
207 */
208
209 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
210 * @brief Initialization and Configuration functions
211 *
212 @verbatim
213 ===============================================================================
214 ##### Initialization and Configuration functions #####
215 ===============================================================================
216 [..] This section provides functions allowing to:
217 (+) Initialize and configure the DMA2D
218 (+) De-initialize the DMA2D
219
220 @endverbatim
221 * @{
222 */
223
224 /**
225 * @brief Initialize the DMA2D according to the specified
226 * parameters in the DMA2D_InitTypeDef and create the associated handle.
227 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
228 * the configuration information for the DMA2D.
229 * @retval HAL status
230 */
231 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
232 {
233 /* Check the DMA2D peripheral state */
234 if(hdma2d == NULL)
235 {
236 return HAL_ERROR;
237 }
238
239 /* Check the parameters */
240 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
241 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
242 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
243 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
244
245 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
246 {
247 /* Allocate lock resource and initialize it */
248 hdma2d->Lock = HAL_UNLOCKED;
249 /* Init the low level hardware */
250 HAL_DMA2D_MspInit(hdma2d);
251 }
252
253 /* Change DMA2D peripheral state */
254 hdma2d->State = HAL_DMA2D_STATE_BUSY;
255
256 /* DMA2D CR register configuration -------------------------------------------*/
257 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
258
259 /* DMA2D OPFCCR register configuration ---------------------------------------*/
260 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
261
262 /* DMA2D OOR register configuration ------------------------------------------*/
263 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
264
265 #if defined (DMA2D_OPFCCR_AI)
266 /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
267 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));
268 #endif /* DMA2D_OPFCCR_AI */
269
270 #if defined (DMA2D_OPFCCR_RBS)
271 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));
272 #endif /* DMA2D_OPFCCR_RBS */
273
274
275 /* Update error code */
276 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
277
278 /* Initialize the DMA2D state*/
279 hdma2d->State = HAL_DMA2D_STATE_READY;
280
281 return HAL_OK;
282 }
283
284 /**
285 * @brief Deinitializes the DMA2D peripheral registers to their default reset
286 * values.
287 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
288 * the configuration information for the DMA2D.
289 * @retval None
290 */
291
292 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
293 {
294
295 /* Check the DMA2D peripheral state */
296 if(hdma2d == NULL)
297 {
298 return HAL_ERROR;
299 }
300
301 /* Before aborting any DMA2D transfer or CLUT loading, check
302 first whether or not DMA2D clock is enabled */
303 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
304 {
305 /* Abort DMA2D transfer if any */
306 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
307 {
308 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
309 {
310 /* Issue when aborting DMA2D transfer */
311 return HAL_ERROR;
312 }
313 }
314 else
315 {
316 /* Abort background CLUT loading if any */
317 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
318 {
319 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)
320 {
321 /* Issue when aborting background CLUT loading */
322 return HAL_ERROR;
323 }
324 }
325 else
326 {
327 /* Abort foreground CLUT loading if any */
328 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
329 {
330 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)
331 {
332 /* Issue when aborting foreground CLUT loading */
333 return HAL_ERROR;
334 }
335 }
336 }
337 }
338 }
339
340
341 /* Carry on with de-initialization of low level hardware */
342 HAL_DMA2D_MspDeInit(hdma2d);
343
344 /* Reset DMA2D control registers*/
345 hdma2d->Instance->CR = 0;
346 hdma2d->Instance->FGOR = 0;
347 hdma2d->Instance->BGOR = 0;
348 hdma2d->Instance->FGPFCCR = 0;
349 hdma2d->Instance->BGPFCCR = 0;
350 hdma2d->Instance->OPFCCR = 0;
351
352 /* Update error code */
353 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
354
355 /* Initialize the DMA2D state*/
356 hdma2d->State = HAL_DMA2D_STATE_RESET;
357
358 /* Release Lock */
359 __HAL_UNLOCK(hdma2d);
360
361 return HAL_OK;
362 }
363
364 /**
365 * @brief Initializes the DMA2D MSP.
366 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
367 * the configuration information for the DMA2D.
368 * @retval None
369 */
370 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
371 {
372 /* Prevent unused argument(s) compilation warning */
373 UNUSED(hdma2d);
374
375 /* NOTE : This function should not be modified; when the callback is needed,
376 the HAL_DMA2D_MspInit can be implemented in the user file.
377 */
378 }
379
380 /**
381 * @brief DeInitializes the DMA2D MSP.
382 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
383 * the configuration information for the DMA2D.
384 * @retval None
385 */
386 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
387 {
388 /* Prevent unused argument(s) compilation warning */
389 UNUSED(hdma2d);
390
391 /* NOTE : This function should not be modified; when the callback is needed,
392 the HAL_DMA2D_MspDeInit can be implemented in the user file.
393 */
394 }
395
396 /**
397 * @}
398 */
399
400
401 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
402 * @brief IO operation functions
403 *
404 @verbatim
405 ===============================================================================
406 ##### IO operation functions #####
407 ===============================================================================
408 [..] This section provides functions allowing to:
409 (+) Configure the pdata, destination address and data size then
410 start the DMA2D transfer.
411 (+) Configure the source for foreground and background, destination address
412 and data size then start a MultiBuffer DMA2D transfer.
413 (+) Configure the pdata, destination address and data size then
414 start the DMA2D transfer with interrupt.
415 (+) Configure the source for foreground and background, destination address
416 and data size then start a MultiBuffer DMA2D transfer with interrupt.
417 (+) Abort DMA2D transfer.
418 (+) Suspend DMA2D transfer.
419 (+) Resume DMA2D transfer.
420 (+) Enable CLUT transfer.
421 (+) Configure CLUT loading then start transfer in polling mode.
422 (+) Configure CLUT loading then start transfer in interrupt mode.
423 (+) Abort DMA2D CLUT loading.
424 (+) Suspend DMA2D CLUT loading.
425 (+) Resume DMA2D CLUT loading.
426 (+) Poll for transfer complete.
427 (+) handle DMA2D interrupt request.
428 (+) Transfer watermark callback.
429 (+) CLUT Transfer Complete callback.
430
431
432 @endverbatim
433 * @{
434 */
435
436 /**
437 * @brief Start the DMA2D Transfer.
438 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
439 * the configuration information for the DMA2D.
440 * @param pdata: Configure the source memory Buffer address if
441 * Memory-to-Memory or Memory-to-Memory with pixel format
442 * conversion mode is selected, or configure
443 * the color value if Register-to-Memory mode is selected.
444 * @param DstAddress: The destination memory Buffer address.
445 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
446 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
447 * @retval HAL status
448 */
449 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
450 {
451 /* Check the parameters */
452 assert_param(IS_DMA2D_LINE(Height));
453 assert_param(IS_DMA2D_PIXEL(Width));
454
455 /* Process locked */
456 __HAL_LOCK(hdma2d);
457
458 /* Change DMA2D peripheral state */
459 hdma2d->State = HAL_DMA2D_STATE_BUSY;
460
461 /* Configure the source, destination address and the data size */
462 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
463
464 /* Enable the Peripheral */
465 __HAL_DMA2D_ENABLE(hdma2d);
466
467 return HAL_OK;
468 }
469
470 /**
471 * @brief Start the DMA2D Transfer with interrupt enabled.
472 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
473 * the configuration information for the DMA2D.
474 * @param pdata: Configure the source memory Buffer address if
475 * the Memory-to-Memory or Memory-to-Memory with pixel format
476 * conversion mode is selected, or configure
477 * the color value if Register-to-Memory mode is selected.
478 * @param DstAddress: The destination memory Buffer address.
479 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
480 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
481 * @retval HAL status
482 */
483 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
484 {
485 /* Check the parameters */
486 assert_param(IS_DMA2D_LINE(Height));
487 assert_param(IS_DMA2D_PIXEL(Width));
488
489 /* Process locked */
490 __HAL_LOCK(hdma2d);
491
492 /* Change DMA2D peripheral state */
493 hdma2d->State = HAL_DMA2D_STATE_BUSY;
494
495 /* Configure the source, destination address and the data size */
496 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
497
498 /* Enable the transfer complete, transfer error and configuration error interrupts */
499 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
500
501 /* Enable the Peripheral */
502 __HAL_DMA2D_ENABLE(hdma2d);
503
504 return HAL_OK;
505 }
506
507 /**
508 * @brief Start the multi-source DMA2D Transfer.
509 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
510 * the configuration information for the DMA2D.
511 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
512 * @param SrcAddress2: The source memory Buffer address for the background layer.
513 * @param DstAddress: The destination memory Buffer address.
514 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
515 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
516 * @retval HAL status
517 */
518 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
519 {
520 /* Check the parameters */
521 assert_param(IS_DMA2D_LINE(Height));
522 assert_param(IS_DMA2D_PIXEL(Width));
523
524 /* Process locked */
525 __HAL_LOCK(hdma2d);
526
527 /* Change DMA2D peripheral state */
528 hdma2d->State = HAL_DMA2D_STATE_BUSY;
529
530 /* Configure DMA2D Stream source2 address */
531 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
532
533 /* Configure the source, destination address and the data size */
534 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
535
536 /* Enable the Peripheral */
537 __HAL_DMA2D_ENABLE(hdma2d);
538
539 return HAL_OK;
540 }
541
542 /**
543 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
544 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
545 * the configuration information for the DMA2D.
546 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
547 * @param SrcAddress2: The source memory Buffer address for the background layer.
548 * @param DstAddress: The destination memory Buffer address.
549 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
550 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
551 * @retval HAL status
552 */
553 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
554 {
555 /* Check the parameters */
556 assert_param(IS_DMA2D_LINE(Height));
557 assert_param(IS_DMA2D_PIXEL(Width));
558
559 /* Process locked */
560 __HAL_LOCK(hdma2d);
561
562 /* Change DMA2D peripheral state */
563 hdma2d->State = HAL_DMA2D_STATE_BUSY;
564
565 /* Configure DMA2D Stream source2 address */
566 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
567
568 /* Configure the source, destination address and the data size */
569 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
570
571 /* Enable the transfer complete, transfer error and configuration error interrupts */
572 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
573
574 /* Enable the Peripheral */
575 __HAL_DMA2D_ENABLE(hdma2d);
576
577 return HAL_OK;
578 }
579
580 /**
581 * @brief Abort the DMA2D Transfer.
582 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
583 * the configuration information for the DMA2D.
584 * @retval HAL status
585 */
586 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
587 {
588 uint32_t tickstart = 0;
589
590 /* Abort the DMA2D transfer */
591 /* START bit is reset to make sure not to set it again, in the event the HW clears it
592 between the register read and the register write by the CPU (writing \910\92 has no
593 effect on START bitvalue). */
594 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
595
596 /* Get tick */
597 tickstart = HAL_GetTick();
598
599 /* Check if the DMA2D is effectively disabled */
600 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
601 {
602 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
603 {
604 /* Update error code */
605 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
606
607 /* Change the DMA2D state */
608 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
609
610 /* Process Unlocked */
611 __HAL_UNLOCK(hdma2d);
612
613 return HAL_TIMEOUT;
614 }
615 }
616
617 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
618 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
619
620 /* Change the DMA2D state*/
621 hdma2d->State = HAL_DMA2D_STATE_READY;
622
623 /* Process Unlocked */
624 __HAL_UNLOCK(hdma2d);
625
626 return HAL_OK;
627 }
628
629 /**
630 * @brief Suspend the DMA2D Transfer.
631 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
632 * the configuration information for the DMA2D.
633 * @retval HAL status
634 */
635 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
636 {
637 uint32_t tickstart = 0;
638
639 /* Suspend the DMA2D transfer */
640 /* START bit is reset to make sure not to set it again, in the event the HW clears it
641 between the register read and the register write by the CPU (writing \910\92 has no
642 effect on START bitvalue). */
643 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
644
645 /* Get tick */
646 tickstart = HAL_GetTick();
647
648 /* Check if the DMA2D is effectively suspended */
649 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
650 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
651 {
652 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
653 {
654 /* Update error code */
655 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
656
657 /* Change the DMA2D state */
658 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
659
660 return HAL_TIMEOUT;
661 }
662 }
663
664 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
665 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
666 {
667 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
668 }
669 else
670 {
671 /* Make sure SUSP bit is cleared since it is meaningless
672 when no tranfer is on-going */
673 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
674 }
675
676 return HAL_OK;
677 }
678
679 /**
680 * @brief Resume the DMA2D Transfer.
681 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
682 * the configuration information for the DMA2D.
683 * @retval HAL status
684 */
685 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
686 {
687 /* Check the SUSP and START bits */
688 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
689 {
690 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
691 hdma2d->State = HAL_DMA2D_STATE_BUSY;
692 }
693
694 /* Resume the DMA2D transfer */
695 /* START bit is reset to make sure not to set it again, in the event the HW clears it
696 between the register read and the register write by the CPU (writing \910\92 has no
697 effect on START bitvalue). */
698 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
699
700 return HAL_OK;
701 }
702
703
704 /**
705 * @brief Enable the DMA2D CLUT Transfer.
706 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
707 * the configuration information for the DMA2D.
708 * @param LayerIdx: DMA2D Layer index.
709 * This parameter can be one of the following values:
710 * 0(background) / 1(foreground)
711 * @retval HAL status
712 */
713 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
714 {
715 /* Check the parameters */
716 assert_param(IS_DMA2D_LAYER(LayerIdx));
717
718 /* Process locked */
719 __HAL_LOCK(hdma2d);
720
721 /* Change DMA2D peripheral state */
722 hdma2d->State = HAL_DMA2D_STATE_BUSY;
723
724 if(LayerIdx == 0)
725 {
726 /* Enable the background CLUT loading */
727 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
728 }
729 else
730 {
731 /* Enable the foreground CLUT loading */
732 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
733 }
734
735 return HAL_OK;
736 }
737
738
739 /**
740 * @brief Start DMA2D CLUT Loading.
741 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
742 * the configuration information for the DMA2D.
743 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
744 * the configuration information for the color look up table.
745 * @param LayerIdx: DMA2D Layer index.
746 * This parameter can be one of the following values:
747 * 0(background) / 1(foreground)
748 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
749 * @retval HAL status
750 */
751 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
752 {
753 /* Check the parameters */
754 assert_param(IS_DMA2D_LAYER(LayerIdx));
755 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
756 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
757
758 /* Process locked */
759 __HAL_LOCK(hdma2d);
760
761 /* Change DMA2D peripheral state */
762 hdma2d->State = HAL_DMA2D_STATE_BUSY;
763
764 /* Configure the CLUT of the background DMA2D layer */
765 if(LayerIdx == 0)
766 {
767 /* Write background CLUT memory address */
768 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
769
770 /* Write background CLUT size and CLUT color mode */
771 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
772 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
773
774 /* Enable the CLUT loading for the background */
775 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
776 }
777 /* Configure the CLUT of the foreground DMA2D layer */
778 else
779 {
780 /* Write foreground CLUT memory address */
781 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
782
783 /* Write foreground CLUT size and CLUT color mode */
784 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
785 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
786
787 /* Enable the CLUT loading for the foreground */
788 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
789 }
790
791 return HAL_OK;
792 }
793
794 /**
795 * @brief Start DMA2D CLUT Loading with interrupt enabled.
796 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
797 * the configuration information for the DMA2D.
798 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
799 * the configuration information for the color look up table.
800 * @param LayerIdx: DMA2D Layer index.
801 * This parameter can be one of the following values:
802 * 0(background) / 1(foreground)
803 * @retval HAL status
804 */
805 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
806 {
807 /* Check the parameters */
808 assert_param(IS_DMA2D_LAYER(LayerIdx));
809 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
810 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
811
812 /* Process locked */
813 __HAL_LOCK(hdma2d);
814
815 /* Change DMA2D peripheral state */
816 hdma2d->State = HAL_DMA2D_STATE_BUSY;
817
818 /* Configure the CLUT of the background DMA2D layer */
819 if(LayerIdx == 0)
820 {
821 /* Write background CLUT memory address */
822 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
823
824 /* Write background CLUT size and CLUT color mode */
825 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
826 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
827
828 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
829 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
830
831 /* Enable the CLUT loading for the background */
832 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
833 }
834 /* Configure the CLUT of the foreground DMA2D layer */
835 else
836 {
837 /* Write foreground CLUT memory address */
838 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
839
840 /* Write foreground CLUT size and CLUT color mode */
841 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
842 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
843
844 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
845 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
846
847 /* Enable the CLUT loading for the foreground */
848 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
849 }
850
851 return HAL_OK;
852 }
853
854 /**
855 * @brief Abort the DMA2D CLUT loading.
856 * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
857 * the configuration information for the DMA2D.
858 * @param LayerIdx: DMA2D Layer index.
859 * This parameter can be one of the following values:
860 * 0(background) / 1(foreground)
861 * @retval HAL status
862 */
863 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
864 {
865 uint32_t tickstart = 0;
866 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
867
868 /* Abort the CLUT loading */
869 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
870
871 /* If foreground CLUT loading is considered, update local variables */
872 if(LayerIdx == 1)
873 {
874 reg = &(hdma2d->Instance->FGPFCCR);
875 }
876
877
878 /* Get tick */
879 tickstart = HAL_GetTick();
880
881 /* Check if the CLUT loading is aborted */
882 while((*reg & DMA2D_BGPFCCR_START) != RESET)
883 {
884 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
885 {
886 /* Update error code */
887 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
888
889 /* Change the DMA2D state */
890 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
891
892 /* Process Unlocked */
893 __HAL_UNLOCK(hdma2d);
894
895 return HAL_TIMEOUT;
896 }
897 }
898
899 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
900 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
901
902 /* Change the DMA2D state*/
903 hdma2d->State = HAL_DMA2D_STATE_READY;
904
905 /* Process Unlocked */
906 __HAL_UNLOCK(hdma2d);
907
908 return HAL_OK;
909 }
910
911 /**
912 * @brief Suspend the DMA2D CLUT loading.
913 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
914 * the configuration information for the DMA2D.
915 * @param LayerIdx: DMA2D Layer index.
916 * This parameter can be one of the following values:
917 * 0(background) / 1(foreground)
918 * @retval HAL status
919 */
920 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
921 {
922 uint32_t tickstart = 0;
923 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
924
925 /* Suspend the CLUT loading */
926 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
927
928 /* If foreground CLUT loading is considered, update local variables */
929 if(LayerIdx == 1)
930 {
931 reg = &(hdma2d->Instance->FGPFCCR);
932 }
933
934 /* Get tick */
935 tickstart = HAL_GetTick();
936
937 /* Check if the CLUT loading is suspended */
938 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
939 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
940 {
941 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
942 {
943 /* Update error code */
944 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
945
946 /* Change the DMA2D state */
947 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
948
949 return HAL_TIMEOUT;
950 }
951 }
952
953 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
954 if ((*reg & DMA2D_BGPFCCR_START) != RESET)
955 {
956 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
957 }
958 else
959 {
960 /* Make sure SUSP bit is cleared since it is meaningless
961 when no tranfer is on-going */
962 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
963 }
964
965 return HAL_OK;
966 }
967
968 /**
969 * @brief Resume the DMA2D CLUT loading.
970 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
971 * the configuration information for the DMA2D.
972 * @param LayerIdx: DMA2D Layer index.
973 * This parameter can be one of the following values:
974 * 0(background) / 1(foreground)
975 * @retval HAL status
976 */
977 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
978 {
979 /* Check the SUSP and START bits for background or foreground CLUT loading */
980 if(LayerIdx == 0)
981 {
982 /* Background CLUT loading suspension check */
983 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
984 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
985 {
986 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
987 hdma2d->State = HAL_DMA2D_STATE_BUSY;
988 }
989 }
990 else
991 {
992 /* Foreground CLUT loading suspension check */
993 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
994 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
995 {
996 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
997 hdma2d->State = HAL_DMA2D_STATE_BUSY;
998 }
999 }
1000
1001 /* Resume the CLUT loading */
1002 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1003
1004 return HAL_OK;
1005 }
1006
1007
1008 /**
1009
1010 * @brief Polling for transfer complete or CLUT loading.
1011 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1012 * the configuration information for the DMA2D.
1013 * @param Timeout: Timeout duration
1014 * @retval HAL status
1015 */
1016 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1017 {
1018 uint32_t tickstart = 0;
1019 __IO uint32_t isrflags = 0x0;
1020
1021 /* Polling for DMA2D transfer */
1022 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
1023 {
1024 /* Get tick */
1025 tickstart = HAL_GetTick();
1026
1027 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
1028 {
1029 isrflags = READ_REG(hdma2d->Instance->ISR);
1030 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
1031 {
1032 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1033 {
1034 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1035 }
1036 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1037 {
1038 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1039 }
1040 /* Clear the transfer and configuration error flags */
1041 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1042
1043 /* Change DMA2D state */
1044 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1045
1046 /* Process unlocked */
1047 __HAL_UNLOCK(hdma2d);
1048
1049 return HAL_ERROR;
1050 }
1051 /* Check for the Timeout */
1052 if(Timeout != HAL_MAX_DELAY)
1053 {
1054 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1055 {
1056 /* Update error code */
1057 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1058
1059 /* Change the DMA2D state */
1060 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1061
1062 /* Process unlocked */
1063 __HAL_UNLOCK(hdma2d);
1064
1065 return HAL_TIMEOUT;
1066 }
1067 }
1068 }
1069 }
1070 /* Polling for CLUT loading (foreground or background) */
1071 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
1072 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
1073 {
1074 /* Get tick */
1075 tickstart = HAL_GetTick();
1076
1077 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
1078 {
1079 isrflags = READ_REG(hdma2d->Instance->ISR);
1080 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
1081 {
1082 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
1083 {
1084 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1085 }
1086 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1087 {
1088 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1089 }
1090 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1091 {
1092 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1093 }
1094 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1095 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1096
1097 /* Change DMA2D state */
1098 hdma2d->State= HAL_DMA2D_STATE_ERROR;
1099
1100 /* Process unlocked */
1101 __HAL_UNLOCK(hdma2d);
1102
1103 return HAL_ERROR;
1104 }
1105 /* Check for the Timeout */
1106 if(Timeout != HAL_MAX_DELAY)
1107 {
1108 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1109 {
1110 /* Update error code */
1111 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1112
1113 /* Change the DMA2D state */
1114 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1115
1116 /* Process unlocked */
1117 __HAL_UNLOCK(hdma2d);
1118
1119 return HAL_TIMEOUT;
1120 }
1121 }
1122 }
1123 }
1124
1125 /* Clear the transfer complete and CLUT loading flags */
1126 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1127
1128 /* Change DMA2D state */
1129 hdma2d->State = HAL_DMA2D_STATE_READY;
1130
1131 /* Process unlocked */
1132 __HAL_UNLOCK(hdma2d);
1133
1134 return HAL_OK;
1135 }
1136 /**
1137 * @brief Handle DMA2D interrupt request.
1138 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1139 * the configuration information for the DMA2D.
1140 * @retval HAL status
1141 */
1142 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1143 {
1144 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1145 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1146
1147 /* Transfer Error Interrupt management ***************************************/
1148 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1149 {
1150 if ((crflags & DMA2D_IT_TE) != RESET)
1151 {
1152 /* Disable the transfer Error interrupt */
1153 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1154
1155 /* Update error code */
1156 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1157
1158 /* Clear the transfer error flag */
1159 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1160
1161 /* Change DMA2D state */
1162 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1163
1164 /* Process Unlocked */
1165 __HAL_UNLOCK(hdma2d);
1166
1167 if(hdma2d->XferErrorCallback != NULL)
1168 {
1169 /* Transfer error Callback */
1170 hdma2d->XferErrorCallback(hdma2d);
1171 }
1172 }
1173 }
1174 /* Configuration Error Interrupt management **********************************/
1175 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1176 {
1177 if ((crflags & DMA2D_IT_CE) != RESET)
1178 {
1179 /* Disable the Configuration Error interrupt */
1180 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1181
1182 /* Clear the Configuration error flag */
1183 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1184
1185 /* Update error code */
1186 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1187
1188 /* Change DMA2D state */
1189 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1190
1191 /* Process Unlocked */
1192 __HAL_UNLOCK(hdma2d);
1193
1194 if(hdma2d->XferErrorCallback != NULL)
1195 {
1196 /* Transfer error Callback */
1197 hdma2d->XferErrorCallback(hdma2d);
1198 }
1199 }
1200 }
1201 /* CLUT access Error Interrupt management ***********************************/
1202 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
1203 {
1204 if ((crflags & DMA2D_IT_CAE) != RESET)
1205 {
1206 /* Disable the CLUT access error interrupt */
1207 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1208
1209 /* Clear the CLUT access error flag */
1210 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1211
1212 /* Update error code */
1213 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1214
1215 /* Change DMA2D state */
1216 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1217
1218 /* Process Unlocked */
1219 __HAL_UNLOCK(hdma2d);
1220
1221 if(hdma2d->XferErrorCallback != NULL)
1222 {
1223 /* Transfer error Callback */
1224 hdma2d->XferErrorCallback(hdma2d);
1225 }
1226 }
1227 }
1228 /* Transfer watermark Interrupt management **********************************/
1229 if ((isrflags & DMA2D_FLAG_TW) != RESET)
1230 {
1231 if ((crflags & DMA2D_IT_TW) != RESET)
1232 {
1233 /* Disable the transfer watermark interrupt */
1234 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1235
1236 /* Clear the transfer watermark flag */
1237 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1238
1239 /* Transfer watermark Callback */
1240 HAL_DMA2D_LineEventCallback(hdma2d);
1241 }
1242 }
1243 /* Transfer Complete Interrupt management ************************************/
1244 if ((isrflags & DMA2D_FLAG_TC) != RESET)
1245 {
1246 if ((crflags & DMA2D_IT_TC) != RESET)
1247 {
1248 /* Disable the transfer complete interrupt */
1249 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1250
1251 /* Clear the transfer complete flag */
1252 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1253
1254 /* Update error code */
1255 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1256
1257 /* Change DMA2D state */
1258 hdma2d->State = HAL_DMA2D_STATE_READY;
1259
1260 /* Process Unlocked */
1261 __HAL_UNLOCK(hdma2d);
1262
1263 if(hdma2d->XferCpltCallback != NULL)
1264 {
1265 /* Transfer complete Callback */
1266 hdma2d->XferCpltCallback(hdma2d);
1267 }
1268 }
1269 }
1270 /* CLUT Transfer Complete Interrupt management ******************************/
1271 if ((isrflags & DMA2D_FLAG_CTC) != RESET)
1272 {
1273 if ((crflags & DMA2D_IT_CTC) != RESET)
1274 {
1275 /* Disable the CLUT transfer complete interrupt */
1276 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1277
1278 /* Clear the CLUT transfer complete flag */
1279 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1280
1281 /* Update error code */
1282 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1283
1284 /* Change DMA2D state */
1285 hdma2d->State = HAL_DMA2D_STATE_READY;
1286
1287 /* Process Unlocked */
1288 __HAL_UNLOCK(hdma2d);
1289
1290 /* CLUT Transfer complete Callback */
1291 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1292 }
1293 }
1294
1295 }
1296
1297 /**
1298 * @brief Transfer watermark callback.
1299 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1300 * the configuration information for the DMA2D.
1301 * @retval None
1302 */
1303 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1304 {
1305 /* Prevent unused argument(s) compilation warning */
1306 UNUSED(hdma2d);
1307
1308 /* NOTE : This function should not be modified; when the callback is needed,
1309 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1310 */
1311 }
1312
1313 /**
1314 * @brief CLUT Transfer Complete callback.
1315 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1316 * the configuration information for the DMA2D.
1317 * @retval None
1318 */
1319 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1320 {
1321 /* Prevent unused argument(s) compilation warning */
1322 UNUSED(hdma2d);
1323
1324 /* NOTE : This function should not be modified; when the callback is needed,
1325 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1326 */
1327 }
1328
1329 /**
1330 * @}
1331 */
1332
1333 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1334 * @brief Peripheral Control functions
1335 *
1336 @verbatim
1337 ===============================================================================
1338 ##### Peripheral Control functions #####
1339 ===============================================================================
1340 [..] This section provides functions allowing to:
1341 (+) Configure the DMA2D foreground or background layer parameters.
1342 (+) Configure the DMA2D CLUT transfer.
1343 (+) Configure the line watermark
1344 (+) Configure the dead time value.
1345 (+) Enable or disable the dead time value functionality.
1346
1347
1348 @endverbatim
1349 * @{
1350 */
1351
1352 /**
1353 * @brief Configure the DMA2D Layer according to the specified
1354 * parameters in the DMA2D_InitTypeDef and create the associated handle.
1355 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1356 * the configuration information for the DMA2D.
1357 * @param LayerIdx: DMA2D Layer index.
1358 * This parameter can be one of the following values:
1359 * 0(background) / 1(foreground)
1360 * @retval HAL status
1361 */
1362 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1363 {
1364 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1365
1366 uint32_t regMask = 0, regValue = 0;
1367
1368 /* Check the parameters */
1369 assert_param(IS_DMA2D_LAYER(LayerIdx));
1370 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
1371 if(hdma2d->Init.Mode != DMA2D_R2M)
1372 {
1373 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
1374 if(hdma2d->Init.Mode != DMA2D_M2M)
1375 {
1376 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
1377 }
1378 }
1379
1380 /* Process locked */
1381 __HAL_LOCK(hdma2d);
1382
1383 /* Change DMA2D peripheral state */
1384 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1385
1386 /* DMA2D BGPFCR register configuration -----------------------------------*/
1387 /* Prepare the value to be written to the BGPFCCR register */
1388
1389 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM);
1390 regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
1391
1392 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
1393 regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI);
1394 regMask |= DMA2D_BGPFCCR_AI;
1395 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
1396
1397 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
1398 regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);
1399 regMask |= DMA2D_BGPFCCR_RBS;
1400 #endif
1401
1402 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1403 {
1404 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1405 }
1406 else
1407 {
1408 regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
1409 }
1410
1411 /* Configure the background DMA2D layer */
1412 if(LayerIdx == 0)
1413 {
1414 /* Write DMA2D BGPFCCR register */
1415 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1416
1417 /* DMA2D BGOR register configuration -------------------------------------*/
1418 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1419
1420 /* DMA2D BGCOLR register configuration -------------------------------------*/
1421 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1422 {
1423 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1424 }
1425 }
1426 /* Configure the foreground DMA2D layer */
1427 else
1428 {
1429 /* Write DMA2D FGPFCCR register */
1430 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1431
1432 /* DMA2D FGOR register configuration -------------------------------------*/
1433 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1434
1435 /* DMA2D FGCOLR register configuration -------------------------------------*/
1436 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1437 {
1438 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1439 }
1440 }
1441 /* Initialize the DMA2D state*/
1442 hdma2d->State = HAL_DMA2D_STATE_READY;
1443
1444 /* Process unlocked */
1445 __HAL_UNLOCK(hdma2d);
1446
1447 return HAL_OK;
1448 }
1449
1450 /**
1451 * @brief Configure the DMA2D CLUT Transfer.
1452 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1453 * the configuration information for the DMA2D.
1454 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1455 * the configuration information for the color look up table.
1456 * @param LayerIdx: DMA2D Layer index.
1457 * This parameter can be one of the following values:
1458 * 0(background) / 1(foreground)
1459 * @retval HAL status
1460 */
1461 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1462 {
1463 /* Check the parameters */
1464 assert_param(IS_DMA2D_LAYER(LayerIdx));
1465 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1466 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1467
1468 /* Process locked */
1469 __HAL_LOCK(hdma2d);
1470
1471 /* Change DMA2D peripheral state */
1472 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1473
1474 /* Configure the CLUT of the background DMA2D layer */
1475 if(LayerIdx == 0)
1476 {
1477 /* Write background CLUT memory address */
1478 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1479
1480 /* Write background CLUT size and CLUT color mode */
1481 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1482 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
1483 }
1484 /* Configure the CLUT of the foreground DMA2D layer */
1485 else
1486 {
1487 /* Write foreground CLUT memory address */
1488 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1489
1490 /* Write foreground CLUT size and CLUT color mode */
1491 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1492 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
1493 }
1494
1495 /* Set the DMA2D state to Ready*/
1496 hdma2d->State = HAL_DMA2D_STATE_READY;
1497
1498 /* Process unlocked */
1499 __HAL_UNLOCK(hdma2d);
1500
1501 return HAL_OK;
1502 }
1503
1504
1505 /**
1506 * @brief Configure the line watermark.
1507 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1508 * the configuration information for the DMA2D.
1509 * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
1510 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1511 * @note The transfer watermark interrupt is disabled once it has occurred.
1512 * @retval HAL status
1513 */
1514
1515 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1516 {
1517 /* Check the parameters */
1518 assert_param(IS_DMA2D_LINEWATERMARK(Line));
1519
1520 if (Line > DMA2D_LWR_LW)
1521 {
1522 return HAL_ERROR;
1523 }
1524 else
1525 {
1526 /* Process locked */
1527 __HAL_LOCK(hdma2d);
1528
1529 /* Change DMA2D peripheral state */
1530 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1531
1532 /* Sets the Line watermark configuration */
1533 WRITE_REG(hdma2d->Instance->LWR, Line);
1534
1535 /* Enable the Line interrupt */
1536 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1537
1538 /* Initialize the DMA2D state*/
1539 hdma2d->State = HAL_DMA2D_STATE_READY;
1540
1541 /* Process unlocked */
1542 __HAL_UNLOCK(hdma2d);
1543
1544 return HAL_OK;
1545 }
1546 }
1547
1548 /**
1549 * @brief Enable DMA2D dead time feature.
1550 * @param hdma2d: DMA2D handle.
1551 * @retval HAL status
1552 */
1553 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1554 {
1555 /* Process Locked */
1556 __HAL_LOCK(hdma2d);
1557
1558 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1559
1560 /* Set DMA2D_AMTCR EN bit */
1561 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1562
1563 hdma2d->State = HAL_DMA2D_STATE_READY;
1564
1565 /* Process Unlocked */
1566 __HAL_UNLOCK(hdma2d);
1567
1568 return HAL_OK;
1569 }
1570
1571 /**
1572 * @brief Disable DMA2D dead time feature.
1573 * @param hdma2d: DMA2D handle.
1574 * @retval HAL status
1575 */
1576 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1577 {
1578 /* Process Locked */
1579 __HAL_LOCK(hdma2d);
1580
1581 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1582
1583 /* Clear DMA2D_AMTCR EN bit */
1584 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1585
1586 hdma2d->State = HAL_DMA2D_STATE_READY;
1587
1588 /* Process Unlocked */
1589 __HAL_UNLOCK(hdma2d);
1590
1591 return HAL_OK;
1592 }
1593
1594 /**
1595 * @brief Configure dead time.
1596 * @note The dead time value represents the guaranteed minimum number of cycles between
1597 * two consecutive transactions on the AHB bus.
1598 * @param hdma2d: DMA2D handle.
1599 * @param DeadTime: dead time value.
1600 * @retval HAL status
1601 */
1602 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
1603 {
1604 /* Process Locked */
1605 __HAL_LOCK(hdma2d);
1606
1607 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1608
1609 /* Set DMA2D_AMTCR DT field */
1610 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
1611
1612 hdma2d->State = HAL_DMA2D_STATE_READY;
1613
1614 /* Process Unlocked */
1615 __HAL_UNLOCK(hdma2d);
1616
1617 return HAL_OK;
1618 }
1619
1620 /**
1621 * @}
1622 */
1623
1624
1625 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
1626 * @brief Peripheral State functions
1627 *
1628 @verbatim
1629 ===============================================================================
1630 ##### Peripheral State and Errors functions #####
1631 ===============================================================================
1632 [..]
1633 This subsection provides functions allowing to :
1634 (+) Get the DMA2D state
1635 (+) Get the DMA2D error code
1636
1637 @endverbatim
1638 * @{
1639 */
1640
1641 /**
1642 * @brief Return the DMA2D state
1643 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1644 * the configuration information for the DMA2D.
1645 * @retval HAL state
1646 */
1647 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
1648 {
1649 return hdma2d->State;
1650 }
1651
1652 /**
1653 * @brief Return the DMA2D error code
1654 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
1655 * the configuration information for DMA2D.
1656 * @retval DMA2D Error Code
1657 */
1658 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
1659 {
1660 return hdma2d->ErrorCode;
1661 }
1662
1663 /**
1664 * @}
1665 */
1666
1667 /**
1668 * @}
1669 */
1670
1671
1672 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
1673 * @{
1674 */
1675
1676 /**
1677 * @brief Set the DMA2D transfer parameters.
1678 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1679 * the configuration information for the specified DMA2D.
1680 * @param pdata: The source memory Buffer address
1681 * @param DstAddress: The destination memory Buffer address
1682 * @param Width: The width of data to be transferred from source to destination.
1683 * @param Height: The height of data to be transferred from source to destination.
1684 * @retval HAL status
1685 */
1686 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
1687 {
1688 uint32_t tmp = 0;
1689 uint32_t tmp1 = 0;
1690 uint32_t tmp2 = 0;
1691 uint32_t tmp3 = 0;
1692 uint32_t tmp4 = 0;
1693
1694 /* Configure DMA2D data size */
1695 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
1696
1697 /* Configure DMA2D destination address */
1698 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
1699
1700 /* Register to memory DMA2D mode selected */
1701 if (hdma2d->Init.Mode == DMA2D_R2M)
1702 {
1703 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
1704 tmp2 = pdata & DMA2D_OCOLR_RED_1;
1705 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
1706 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
1707
1708 /* Prepare the value to be written to the OCOLR register according to the color mode */
1709 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
1710 {
1711 tmp = (tmp3 | tmp2 | tmp1| tmp4);
1712 }
1713 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
1714 {
1715 tmp = (tmp3 | tmp2 | tmp4);
1716 }
1717 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
1718 {
1719 tmp2 = (tmp2 >> 19);
1720 tmp3 = (tmp3 >> 10);
1721 tmp4 = (tmp4 >> 3 );
1722 tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
1723 }
1724 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
1725 {
1726 tmp1 = (tmp1 >> 31);
1727 tmp2 = (tmp2 >> 19);
1728 tmp3 = (tmp3 >> 11);
1729 tmp4 = (tmp4 >> 3 );
1730 tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
1731 }
1732 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
1733 {
1734 tmp1 = (tmp1 >> 28);
1735 tmp2 = (tmp2 >> 20);
1736 tmp3 = (tmp3 >> 12);
1737 tmp4 = (tmp4 >> 4 );
1738 tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
1739 }
1740 /* Write to DMA2D OCOLR register */
1741 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
1742 }
1743 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
1744 {
1745 /* Configure DMA2D source address */
1746 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
1747 }
1748 }
1749
1750 /**
1751 * @}
1752 */
1753 #endif /* HAL_DMA2D_MODULE_ENABLED */
1754 /**
1755 * @}
1756 */
1757
1758 /**
1759 * @}
1760 */
1761
1762 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)