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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_dsi.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_dsi.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief DSI HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the DSI peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f7xx_hal.h"
46
47 /** @addtogroup STM32F7xx_HAL_Driver
48 * @{
49 */
50 /** @addtogroup DSI
51 * @{
52 */
53
54 #ifdef HAL_DSI_MODULE_ENABLED
55
56 #if defined (STM32F769xx) || defined (STM32F779xx)
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private defines -----------------------------------------------------------*/
60 /** @addtogroup DSI_Private_Constants
61 * @{
62 */
63 #define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
64
65 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
66 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
67 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
68 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
69 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
70 #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
71 #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
72 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
73 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
74 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
75 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
76 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
77 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
78 /**
79 * @}
80 */
81
82 /* Private variables ---------------------------------------------------------*/
83 /* Private constants ---------------------------------------------------------*/
84 /* Private macros ------------------------------------------------------------*/
85 /* Private function prototypes -----------------------------------------------*/
86 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
87
88 /* Private functions ---------------------------------------------------------*/
89 /**
90 * @brief Generic DSI packet header configuration
91 * @param DSIx: Pointer to DSI register base
92 * @param ChannelID: Virtual channel ID of the header packet
93 * @param DataType: Packet data type of the header packet
94 * This parameter can be any value of :
95 * @ref DSI_SHORT_WRITE_PKT_Data_Type
96 * or @ref DSI_LONG_WRITE_PKT_Data_Type
97 * or @ref DSI_SHORT_READ_PKT_Data_Type
98 * or DSI_MAX_RETURN_PKT_SIZE
99 * @param Data0: Word count LSB
100 * @param Data1: Word count MSB
101 * @retval None
102 */
103 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
104 uint32_t ChannelID,
105 uint32_t DataType,
106 uint32_t Data0,
107 uint32_t Data1)
108 {
109 /* Update the DSI packet header with new information */
110 DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));
111 }
112
113 /* Exported functions --------------------------------------------------------*/
114 /** @addtogroup DSI_Exported_Functions
115 * @{
116 */
117
118 /** @defgroup DSI_Group1 Initialization and Configuration functions
119 * @brief Initialization and Configuration functions
120 *
121 @verbatim
122 ===============================================================================
123 ##### Initialization and Configuration functions #####
124 ===============================================================================
125 [..] This section provides functions allowing to:
126 (+) Initialize and configure the DSI
127 (+) De-initialize the DSI
128
129 @endverbatim
130 * @{
131 */
132
133 /**
134 * @brief Initializes the DSI according to the specified
135 * parameters in the DSI_InitTypeDef and create the associated handle.
136 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
137 * the configuration information for the DSI.
138 * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
139 * the PLL Clock structure definition for the DSI.
140 * @retval HAL status
141 */
142 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
143 {
144 uint32_t tickstart = 0;
145 uint32_t unitIntervalx4 = 0;
146 uint32_t tempIDF = 0;
147
148 /* Check the DSI handle allocation */
149 if(hdsi == NULL)
150 {
151 return HAL_ERROR;
152 }
153
154 /* Check function parameters */
155 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
156 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
157 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
158 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
159 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
160
161 if(hdsi->State == HAL_DSI_STATE_RESET)
162 {
163 /* Initialize the low level hardware */
164 HAL_DSI_MspInit(hdsi);
165 }
166
167 /* Change DSI peripheral state */
168 hdsi->State = HAL_DSI_STATE_BUSY;
169
170 /**************** Turn on the regulator and enable the DSI PLL ****************/
171
172 /* Enable the regulator */
173 __HAL_DSI_REG_ENABLE(hdsi);
174
175 /* Get tick */
176 tickstart = HAL_GetTick();
177
178 /* Wait until the regulator is ready */
179 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
180 {
181 /* Check for the Timeout */
182 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
183 {
184 return HAL_TIMEOUT;
185 }
186 }
187
188 /* Set the PLL division factors */
189 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
190 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));
191
192 /* Enable the DSI PLL */
193 __HAL_DSI_PLL_ENABLE(hdsi);
194
195 /* Get tick */
196 tickstart = HAL_GetTick();
197
198 /* Wait for the lock of the PLL */
199 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
200 {
201 /* Check for the Timeout */
202 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
203 {
204 return HAL_TIMEOUT;
205 }
206 }
207
208 /*************************** Set the PHY parameters ***************************/
209
210 /* D-PHY clock and digital enable*/
211 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
212
213 /* Clock lane configuration */
214 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
215 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
216
217 /* Configure the number of active data lanes */
218 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
219 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
220
221 /************************ Set the DSI clock parameters ************************/
222
223 /* Set the TX escape clock division factor */
224 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
225 hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;
226
227 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
228 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
229 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
230 tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;
231 unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);
232
233 /* Set the bit period in high-speed mode */
234 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;
235 hdsi->Instance->WPCR[0] |= unitIntervalx4;
236
237 /****************************** Error management *****************************/
238
239 /* Disable all error interrupts and reset the Error Mask */
240 hdsi->Instance->IER[0] = 0;
241 hdsi->Instance->IER[1] = 0;
242 hdsi->ErrorMsk = 0;
243
244 /* Initialise the error code */
245 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
246
247 /* Initialize the DSI state*/
248 hdsi->State = HAL_DSI_STATE_READY;
249
250 return HAL_OK;
251 }
252
253 /**
254 * @brief De-initializes the DSI peripheral registers to their default reset
255 * values.
256 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
257 * the configuration information for the DSI.
258 * @retval HAL status
259 */
260 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
261 {
262 /* Check the DSI handle allocation */
263 if(hdsi == NULL)
264 {
265 return HAL_ERROR;
266 }
267
268 /* Change DSI peripheral state */
269 hdsi->State = HAL_DSI_STATE_BUSY;
270
271 /* Disable the DSI wrapper */
272 __HAL_DSI_WRAPPER_DISABLE(hdsi);
273
274 /* Disable the DSI host */
275 __HAL_DSI_DISABLE(hdsi);
276
277 /* D-PHY clock and digital disable */
278 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
279
280 /* Turn off the DSI PLL */
281 __HAL_DSI_PLL_DISABLE(hdsi);
282
283 /* Disable the regulator */
284 __HAL_DSI_REG_DISABLE(hdsi);
285
286 /* DeInit the low level hardware */
287 HAL_DSI_MspDeInit(hdsi);
288
289 /* Initialise the error code */
290 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
291
292 /* Initialize the DSI state*/
293 hdsi->State = HAL_DSI_STATE_RESET;
294
295 /* Release Lock */
296 __HAL_UNLOCK(hdsi);
297
298 return HAL_OK;
299 }
300
301 /**
302 * @brief Return the DSI error code
303 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
304 * the configuration information for the DSI.
305 * @retval DSI Error Code
306 */
307 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
308 {
309 /* Get the error code */
310 return hdsi->ErrorCode;
311 }
312
313 /**
314 * @brief Enable the error monitor flags
315 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
316 * the configuration information for the DSI.
317 * @param ActiveErrors: indicates which error interrupts will be enabled.
318 * This parameter can be any combination of @ref DSI_Error_Data_Type.
319 * @retval HAL status
320 */
321 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
322 {
323 /* Process locked */
324 __HAL_LOCK(hdsi);
325
326 hdsi->Instance->IER[0] = 0;
327 hdsi->Instance->IER[1] = 0;
328
329 /* Store active errors to the handle */
330 hdsi->ErrorMsk = ActiveErrors;
331
332 if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
333 {
334 /* Enable the interrupt generation on selected errors */
335 hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;
336 }
337
338 if((ActiveErrors & HAL_DSI_ERROR_PHY ) != RESET)
339 {
340 /* Enable the interrupt generation on selected errors */
341 hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;
342 }
343
344 if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
345 {
346 /* Enable the interrupt generation on selected errors */
347 hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;
348 }
349
350 if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
351 {
352 /* Enable the interrupt generation on selected errors */
353 hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;
354 }
355
356 if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
357 {
358 /* Enable the interrupt generation on selected errors */
359 hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;
360 }
361
362 if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
363 {
364 /* Enable the interrupt generation on selected errors */
365 hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;
366 }
367
368 if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
369 {
370 /* Enable the interrupt generation on selected errors */
371 hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;
372 }
373
374 if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
375 {
376 /* Enable the interrupt generation on selected errors */
377 hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;
378 }
379
380 if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
381 {
382 /* Enable the interrupt generation on selected errors */
383 hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;
384 }
385
386 if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
387 {
388 /* Enable the interrupt generation on selected errors */
389 hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;
390 }
391
392 /* Process Unlocked */
393 __HAL_UNLOCK(hdsi);
394
395 return HAL_OK;
396 }
397
398 /**
399 * @brief Initializes the DSI MSP.
400 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
401 * the configuration information for the DSI.
402 * @retval None
403 */
404 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
405 {
406 /* Prevent unused argument(s) compilation warning */
407 UNUSED(hdsi);
408
409 /* NOTE : This function Should not be modified, when the callback is needed,
410 the HAL_DSI_MspInit could be implemented in the user file
411 */
412 }
413
414 /**
415 * @brief De-initializes the DSI MSP.
416 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
417 * the configuration information for the DSI.
418 * @retval None
419 */
420 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
421 {
422 /* Prevent unused argument(s) compilation warning */
423 UNUSED(hdsi);
424
425 /* NOTE : This function Should not be modified, when the callback is needed,
426 the HAL_DSI_MspDeInit could be implemented in the user file
427 */
428 }
429
430 /**
431 * @}
432 */
433
434 /** @defgroup DSI_Group2 IO operation functions
435 * @brief IO operation functions
436 *
437 @verbatim
438 ===============================================================================
439 ##### IO operation functions #####
440 ===============================================================================
441 [..] This section provides function allowing to:
442 (+) Handle DSI interrupt request
443
444 @endverbatim
445 * @{
446 */
447 /**
448 * @brief Handles DSI interrupt request.
449 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
450 * the configuration information for the DSI.
451 * @retval HAL status
452 */
453 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
454 {
455 uint32_t ErrorStatus0, ErrorStatus1;
456
457 /* Tearing Effect Interrupt management ***************************************/
458 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
459 {
460 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
461 {
462 /* Clear the Tearing Effect Interrupt Flag */
463 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
464
465 /* Tearing Effect Callback */
466 HAL_DSI_TearingEffectCallback(hdsi);
467 }
468 }
469
470 /* End of Refresh Interrupt management ***************************************/
471 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
472 {
473 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
474 {
475 /* Clear the End of Refresh Interrupt Flag */
476 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
477
478 /* End of Refresh Callback */
479 HAL_DSI_EndOfRefreshCallback(hdsi);
480 }
481 }
482
483 /* Error Interrupts management ***********************************************/
484 if(hdsi->ErrorMsk != 0)
485 {
486 ErrorStatus0 = hdsi->Instance->ISR[0];
487 ErrorStatus0 &= hdsi->Instance->IER[0];
488 ErrorStatus1 = hdsi->Instance->ISR[1];
489 ErrorStatus1 &= hdsi->Instance->IER[1];
490
491 if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
492 {
493 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
494 }
495
496 if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
497 {
498 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
499 }
500
501 if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
502 {
503 hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
504 }
505
506 if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
507 {
508 hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
509 }
510
511 if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
512 {
513 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
514 }
515
516 if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
517 {
518 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
519 }
520
521 if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
522 {
523 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
524 }
525
526 if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
527 {
528 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
529 }
530
531 if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
532 {
533 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
534 }
535
536 if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
537 {
538 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
539 }
540
541 /* Check only selected errors */
542 if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
543 {
544 /* DSI error interrupt user callback */
545 HAL_DSI_ErrorCallback(hdsi);
546 }
547 }
548 }
549
550 /**
551 * @brief Tearing Effect DSI callback.
552 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
553 * the configuration information for the DSI.
554 * @retval None
555 */
556 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
557 {
558 /* Prevent unused argument(s) compilation warning */
559 UNUSED(hdsi);
560
561 /* NOTE : This function Should not be modified, when the callback is needed,
562 the HAL_DSI_TearingEffectCallback could be implemented in the user file
563 */
564 }
565
566 /**
567 * @brief End of Refresh DSI callback.
568 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
569 * the configuration information for the DSI.
570 * @retval None
571 */
572 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
573 {
574 /* Prevent unused argument(s) compilation warning */
575 UNUSED(hdsi);
576
577 /* NOTE : This function Should not be modified, when the callback is needed,
578 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
579 */
580 }
581
582 /**
583 * @brief Operation Error DSI callback.
584 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
585 * the configuration information for the DSI.
586 * @retval None
587 */
588 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
589 {
590 /* Prevent unused argument(s) compilation warning */
591 UNUSED(hdsi);
592
593 /* NOTE : This function Should not be modified, when the callback is needed,
594 the HAL_DSI_ErrorCallback could be implemented in the user file
595 */
596 }
597
598 /**
599 * @}
600 */
601
602 /** @defgroup DSI_Group3 Peripheral Control functions
603 * @brief Peripheral Control functions
604 *
605 @verbatim
606 ===============================================================================
607 ##### Peripheral Control functions #####
608 ===============================================================================
609 [..] This section provides functions allowing to:
610 (+)
611 (+)
612 (+)
613
614 @endverbatim
615 * @{
616 */
617
618 /**
619 * @brief Configure the Generic interface read-back Virtual Channel ID.
620 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
621 * the configuration information for the DSI.
622 * @param VirtualChannelID: Virtual channel ID
623 * @retval HAL status
624 */
625 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
626 {
627 /* Process locked */
628 __HAL_LOCK(hdsi);
629
630 /* Update the GVCID register */
631 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
632 hdsi->Instance->GVCIDR |= VirtualChannelID;
633
634 /* Process unlocked */
635 __HAL_UNLOCK(hdsi);
636
637 return HAL_OK;
638 }
639
640 /**
641 * @brief Select video mode and configure the corresponding parameters
642 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
643 * the configuration information for the DSI.
644 * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
645 * the DSI video mode configuration parameters
646 * @retval HAL status
647 */
648 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
649 {
650 /* Process locked */
651 __HAL_LOCK(hdsi);
652
653 /* Check the parameters */
654 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
655 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
656 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
657 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
658 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
659 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
660 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
661 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
662 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
663 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
664 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
665 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
666 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
667 /* Check the LooselyPacked variant only in 18-bit mode */
668 if(VidCfg->ColorCoding == DSI_RGB666)
669 {
670 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
671 }
672
673 /* Select video mode by resetting CMDM and DSIM bits */
674 hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
675 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
676
677 /* Configure the video mode transmission type */
678 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
679 hdsi->Instance->VMCR |= VidCfg->Mode;
680
681 /* Configure the video packet size */
682 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
683 hdsi->Instance->VPCR |= VidCfg->PacketSize;
684
685 /* Set the chunks number to be transmitted through the DSI link */
686 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
687 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
688
689 /* Set the size of the null packet */
690 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
691 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
692
693 /* Select the virtual channel for the LTDC interface traffic */
694 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
695 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
696
697 /* Configure the polarity of control signals */
698 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
699 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
700
701 /* Select the color coding for the host */
702 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
703 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
704
705 /* Select the color coding for the wrapper */
706 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
707 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);
708
709 /* Enable/disable the loosely packed variant to 18-bit configuration */
710 if(VidCfg->ColorCoding == DSI_RGB666)
711 {
712 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
713 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
714 }
715
716 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
717 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
718 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
719
720 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
721 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
722 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
723
724 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
725 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
726 hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
727
728 /* Set the Vertical Synchronization Active (VSA) */
729 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
730 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
731
732 /* Set the Vertical Back Porch (VBP)*/
733 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
734 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
735
736 /* Set the Vertical Front Porch (VFP)*/
737 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
738 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
739
740 /* Set the Vertical Active period*/
741 hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
742 hdsi->Instance->VVACR |= VidCfg->VerticalActive;
743
744 /* Configure the command transmission mode */
745 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
746 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
747
748 /* Low power largest packet size */
749 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
750 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);
751
752 /* Low power VACT largest packet size */
753 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
754 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
755
756 /* Enable LP transition in HFP period */
757 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
758 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
759
760 /* Enable LP transition in HBP period */
761 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
762 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
763
764 /* Enable LP transition in VACT period */
765 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
766 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
767
768 /* Enable LP transition in VFP period */
769 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
770 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
771
772 /* Enable LP transition in VBP period */
773 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
774 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
775
776 /* Enable LP transition in vertical sync period */
777 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
778 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
779
780 /* Enable the request for an acknowledge response at the end of a frame */
781 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
782 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
783
784 /* Process unlocked */
785 __HAL_UNLOCK(hdsi);
786
787 return HAL_OK;
788 }
789
790 /**
791 * @brief Select adapted command mode and configure the corresponding parameters
792 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
793 * the configuration information for the DSI.
794 * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
795 * the DSI command mode configuration parameters
796 * @retval HAL status
797 */
798 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
799 {
800 /* Process locked */
801 __HAL_LOCK(hdsi);
802
803 /* Check the parameters */
804 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
805 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
806 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
807 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
808 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
809 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
810 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
811 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
812 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
813
814 /* Select command mode by setting CMDM and DSIM bits */
815 hdsi->Instance->MCR |= DSI_MCR_CMDM;
816 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
817 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
818
819 /* Select the virtual channel for the LTDC interface traffic */
820 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
821 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
822
823 /* Configure the polarity of control signals */
824 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
825 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
826
827 /* Select the color coding for the host */
828 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
829 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
830
831 /* Select the color coding for the wrapper */
832 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
833 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);
834
835 /* Configure the maximum allowed size for write memory command */
836 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
837 hdsi->Instance->LCCR |= CmdCfg->CommandSize;
838
839 /* Configure the tearing effect source and polarity and select the refresh mode */
840 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
841 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
842
843 /* Configure the tearing effect acknowledge request */
844 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
845 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
846
847 /* Enable the Tearing Effect interrupt */
848 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
849
850 /* Enable the End of Refresh interrupt */
851 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
852
853 /* Process unlocked */
854 __HAL_UNLOCK(hdsi);
855
856 return HAL_OK;
857 }
858
859 /**
860 * @brief Configure command transmission mode: High-speed or Low-power
861 * and enable/disable acknowledge request after packet transmission
862 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
863 * the configuration information for the DSI.
864 * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
865 * the DSI command transmission mode configuration parameters
866 * @retval HAL status
867 */
868 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
869 {
870 /* Process locked */
871 __HAL_LOCK(hdsi);
872
873 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
874 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
875 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
876 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
877 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
878 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
879 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
880 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
881 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
882 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
883 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
884 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
885 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
886
887 /* Select High-speed or Low-power for command transmission */
888 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
889 DSI_CMCR_GSW1TX |\
890 DSI_CMCR_GSW2TX |\
891 DSI_CMCR_GSR0TX |\
892 DSI_CMCR_GSR1TX |\
893 DSI_CMCR_GSR2TX |\
894 DSI_CMCR_GLWTX |\
895 DSI_CMCR_DSW0TX |\
896 DSI_CMCR_DSW1TX |\
897 DSI_CMCR_DSR0TX |\
898 DSI_CMCR_DLWTX |\
899 DSI_CMCR_MRDPS);
900 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
901 LPCmd->LPGenShortWriteOneP |\
902 LPCmd->LPGenShortWriteTwoP |\
903 LPCmd->LPGenShortReadNoP |\
904 LPCmd->LPGenShortReadOneP |\
905 LPCmd->LPGenShortReadTwoP |\
906 LPCmd->LPGenLongWrite |\
907 LPCmd->LPDcsShortWriteNoP |\
908 LPCmd->LPDcsShortWriteOneP |\
909 LPCmd->LPDcsShortReadNoP |\
910 LPCmd->LPDcsLongWrite |\
911 LPCmd->LPMaxReadPacket);
912
913 /* Configure the acknowledge request after each packet transmission */
914 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
915 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
916
917 /* Process unlocked */
918 __HAL_UNLOCK(hdsi);
919
920 return HAL_OK;
921 }
922
923 /**
924 * @brief Configure the flow control parameters
925 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
926 * the configuration information for the DSI.
927 * @param FlowControl: flow control feature(s) to be enabled.
928 * This parameter can be any combination of @ref DSI_FlowControl.
929 * @retval HAL status
930 */
931 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
932 {
933 /* Process locked */
934 __HAL_LOCK(hdsi);
935
936 /* Check the parameters */
937 assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
938
939 /* Set the DSI Host Protocol Configuration Register */
940 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
941 hdsi->Instance->PCR |= FlowControl;
942
943 /* Process unlocked */
944 __HAL_UNLOCK(hdsi);
945
946 return HAL_OK;
947 }
948
949 /**
950 * @brief Configure the DSI PHY timer parameters
951 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
952 * the configuration information for the DSI.
953 * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
954 * the DSI PHY timing parameters
955 * @retval HAL status
956 */
957 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
958 {
959 uint32_t maxTime;
960 /* Process locked */
961 __HAL_LOCK(hdsi);
962
963 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
964
965 /* Clock lane timer configuration */
966
967 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
968 High-Speed transmission.
969 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
970 to Low-Power and from Low-Power to High-Speed.
971 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
972 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
973
974 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
975 */
976 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
977 hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));
978
979 /* Data lane timer configuration */
980 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
981 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));
982
983 /* Configure the wait period to request HS transmission after a stop state */
984 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
985 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);
986
987 /* Process unlocked */
988 __HAL_UNLOCK(hdsi);
989
990 return HAL_OK;
991 }
992
993 /**
994 * @brief Configure the DSI HOST timeout parameters
995 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
996 * the configuration information for the DSI.
997 * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
998 * the DSI host timeout parameters
999 * @retval HAL status
1000 */
1001 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
1002 {
1003 /* Process locked */
1004 __HAL_LOCK(hdsi);
1005
1006 /* Set the timeout clock division factor */
1007 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
1008 hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);
1009
1010 /* High-speed transmission timeout */
1011 hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
1012 hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);
1013
1014 /* Low-power reception timeout */
1015 hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;
1016 hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;
1017
1018 /* High-speed read timeout */
1019 hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;
1020 hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;
1021
1022 /* Low-power read timeout */
1023 hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;
1024 hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;
1025
1026 /* High-speed write timeout */
1027 hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;
1028 hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;
1029
1030 /* High-speed write presp mode */
1031 hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;
1032 hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;
1033
1034 /* Low-speed write timeout */
1035 hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;
1036 hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;
1037
1038 /* BTA timeout */
1039 hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;
1040 hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;
1041
1042 /* Process unlocked */
1043 __HAL_UNLOCK(hdsi);
1044
1045 return HAL_OK;
1046 }
1047
1048 /**
1049 * @brief Start the DSI module
1050 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1051 * the configuration information for the DSI.
1052 * @retval HAL status
1053 */
1054 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
1055 {
1056 /* Process locked */
1057 __HAL_LOCK(hdsi);
1058
1059 /* Enable the DSI host */
1060 __HAL_DSI_ENABLE(hdsi);
1061
1062 /* Enable the DSI wrapper */
1063 __HAL_DSI_WRAPPER_ENABLE(hdsi);
1064
1065 /* Process unlocked */
1066 __HAL_UNLOCK(hdsi);
1067
1068 return HAL_OK;
1069 }
1070
1071 /**
1072 * @brief Stop the DSI module
1073 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1074 * the configuration information for the DSI.
1075 * @retval HAL status
1076 */
1077 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
1078 {
1079 /* Process locked */
1080 __HAL_LOCK(hdsi);
1081
1082 /* Disable the DSI host */
1083 __HAL_DSI_DISABLE(hdsi);
1084
1085 /* Disable the DSI wrapper */
1086 __HAL_DSI_WRAPPER_DISABLE(hdsi);
1087
1088 /* Process unlocked */
1089 __HAL_UNLOCK(hdsi);
1090
1091 return HAL_OK;
1092 }
1093
1094 /**
1095 * @brief Refresh the display in command mode
1096 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1097 * the configuration information for the DSI.
1098 * @retval HAL status
1099 */
1100 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
1101 {
1102 /* Process locked */
1103 __HAL_LOCK(hdsi);
1104
1105 /* Update the display */
1106 hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
1107
1108 /* Process unlocked */
1109 __HAL_UNLOCK(hdsi);
1110
1111 return HAL_OK;
1112 }
1113
1114 /**
1115 * @brief Controls the display color mode in Video mode
1116 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1117 * the configuration information for the DSI.
1118 * @param ColorMode: Color mode (full or 8-colors).
1119 * This parameter can be any value of @ref DSI_Color_Mode
1120 * @retval HAL status
1121 */
1122 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
1123 {
1124 /* Process locked */
1125 __HAL_LOCK(hdsi);
1126
1127 /* Check the parameters */
1128 assert_param(IS_DSI_COLOR_MODE(ColorMode));
1129
1130 /* Update the display color mode */
1131 hdsi->Instance->WCR &= ~DSI_WCR_COLM;
1132 hdsi->Instance->WCR |= ColorMode;
1133
1134 /* Process unlocked */
1135 __HAL_UNLOCK(hdsi);
1136
1137 return HAL_OK;
1138 }
1139
1140 /**
1141 * @brief Control the display shutdown in Video mode
1142 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1143 * the configuration information for the DSI.
1144 * @param Shutdown: Shut-down (Display-ON or Display-OFF).
1145 * This parameter can be any value of @ref DSI_ShutDown
1146 * @retval HAL status
1147 */
1148 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
1149 {
1150 /* Process locked */
1151 __HAL_LOCK(hdsi);
1152
1153 /* Check the parameters */
1154 assert_param(IS_DSI_SHUT_DOWN(Shutdown));
1155
1156 /* Update the display Shutdown */
1157 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
1158 hdsi->Instance->WCR |= Shutdown;
1159
1160 /* Process unlocked */
1161 __HAL_UNLOCK(hdsi);
1162
1163 return HAL_OK;
1164 }
1165
1166 /**
1167 * @brief DCS or Generic short write command
1168 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1169 * the configuration information for the DSI.
1170 * @param ChannelID: Virtual channel ID.
1171 * @param Mode: DSI short packet data type.
1172 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
1173 * @param Param1: DSC command or first generic parameter.
1174 * This parameter can be any value of @ref DSI_DCS_Command or a
1175 * generic command code.
1176 * @param Param2: DSC parameter or second generic parameter.
1177 * @retval HAL status
1178 */
1179 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1180 uint32_t ChannelID,
1181 uint32_t Mode,
1182 uint32_t Param1,
1183 uint32_t Param2)
1184 {
1185 uint32_t tickstart = 0;
1186
1187 /* Process locked */
1188 __HAL_LOCK(hdsi);
1189
1190 /* Check the parameters */
1191 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
1192
1193 /* Get tick */
1194 tickstart = HAL_GetTick();
1195
1196 /* Wait for Command FIFO Empty */
1197 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)
1198 {
1199 /* Check for the Timeout */
1200 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1201 {
1202 /* Process Unlocked */
1203 __HAL_UNLOCK(hdsi);
1204
1205 return HAL_TIMEOUT;
1206 }
1207 }
1208
1209 /* Configure the packet to send a short DCS command with 0 or 1 parameter */
1210 DSI_ConfigPacketHeader(hdsi->Instance,
1211 ChannelID,
1212 Mode,
1213 Param1,
1214 Param2);
1215
1216 /* Process unlocked */
1217 __HAL_UNLOCK(hdsi);
1218
1219 return HAL_OK;
1220 }
1221
1222 /**
1223 * @brief DCS or Generic long write command
1224 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1225 * the configuration information for the DSI.
1226 * @param ChannelID: Virtual channel ID.
1227 * @param Mode: DSI long packet data type.
1228 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
1229 * @param NbParams: Number of parameters.
1230 * @param Param1: DSC command or first generic parameter.
1231 * This parameter can be any value of @ref DSI_DCS_Command or a
1232 * generic command code
1233 * @param ParametersTable: Pointer to parameter values table.
1234 * @retval HAL status
1235 */
1236 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1237 uint32_t ChannelID,
1238 uint32_t Mode,
1239 uint32_t NbParams,
1240 uint32_t Param1,
1241 uint8_t* ParametersTable)
1242 {
1243 uint32_t uicounter = 0;
1244 uint32_t tickstart = 0;
1245
1246 /* Process locked */
1247 __HAL_LOCK(hdsi);
1248
1249 /* Check the parameters */
1250 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
1251
1252 /* Get tick */
1253 tickstart = HAL_GetTick();
1254
1255 /* Wait for Command FIFO Empty */
1256 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
1257 {
1258 /* Check for the Timeout */
1259 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1260 {
1261 /* Process Unlocked */
1262 __HAL_UNLOCK(hdsi);
1263
1264 return HAL_TIMEOUT;
1265 }
1266 }
1267
1268 /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
1269 while(uicounter < NbParams)
1270 {
1271 if(uicounter == 0x00)
1272 {
1273 hdsi->Instance->GPDR=(Param1 | \
1274 ((uint32_t)(*(ParametersTable + uicounter)) << 8) | \
1275 ((uint32_t)(*(ParametersTable + uicounter+1))<<16) | \
1276 ((uint32_t)(*(ParametersTable + uicounter+2))<<24));
1277 uicounter += 3;
1278 }
1279 else
1280 {
1281 hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \
1282 ((uint32_t)(*(ParametersTable + uicounter+1)) << 8) | \
1283 ((uint32_t)(*(ParametersTable + uicounter+2)) << 16) | \
1284 ((uint32_t)(*(ParametersTable + uicounter+3)) << 24));
1285 uicounter+=4;
1286 }
1287 }
1288
1289 /* Configure the packet to send a long DCS command */
1290 DSI_ConfigPacketHeader(hdsi->Instance,
1291 ChannelID,
1292 Mode,
1293 ((NbParams+1)&0x00FF),
1294 (((NbParams+1)&0xFF00)>>8));
1295
1296 /* Process unlocked */
1297 __HAL_UNLOCK(hdsi);
1298
1299 return HAL_OK;
1300 }
1301
1302 /**
1303 * @brief Read command (DCS or generic)
1304 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1305 * the configuration information for the DSI.
1306 * @param ChannelNbr: Virtual channel ID
1307 * @param Array: pointer to a buffer to store the payload of a read back operation.
1308 * @param Size: Data size to be read (in byte).
1309 * @param Mode: DSI read packet data type.
1310 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
1311 * @param DCSCmd: DCS get/read command.
1312 * @param ParametersTable: Pointer to parameter values table.
1313 * @retval HAL status
1314 */
1315 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1316 uint32_t ChannelNbr,
1317 uint8_t* Array,
1318 uint32_t Size,
1319 uint32_t Mode,
1320 uint32_t DCSCmd,
1321 uint8_t* ParametersTable)
1322 {
1323 uint32_t tickstart = 0;
1324
1325 /* Process locked */
1326 __HAL_LOCK(hdsi);
1327
1328 /* Check the parameters */
1329 assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
1330
1331 if(Size > 2)
1332 {
1333 /* set max return packet size */
1334 HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));
1335 }
1336
1337 /* Configure the packet to read command */
1338 if (Mode == DSI_DCS_SHORT_PKT_READ)
1339 {
1340 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);
1341 }
1342 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
1343 {
1344 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);
1345 }
1346 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
1347 {
1348 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);
1349 }
1350 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
1351 {
1352 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);
1353 }
1354 else
1355 {
1356 /* Process Unlocked */
1357 __HAL_UNLOCK(hdsi);
1358
1359 return HAL_ERROR;
1360 }
1361
1362 /* Get tick */
1363 tickstart = HAL_GetTick();
1364
1365 /* Check that the payload read FIFO is not empty */
1366 while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
1367 {
1368 /* Check for the Timeout */
1369 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1370 {
1371 /* Process Unlocked */
1372 __HAL_UNLOCK(hdsi);
1373
1374 return HAL_TIMEOUT;
1375 }
1376 }
1377
1378 /* Get the first byte */
1379 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
1380 if (Size > 4)
1381 {
1382 Size -= 4;
1383 Array += 4;
1384 }
1385 else
1386 {
1387 /* Process unlocked */
1388 __HAL_UNLOCK(hdsi);
1389
1390 return HAL_OK;
1391 }
1392
1393 /* Get tick */
1394 tickstart = HAL_GetTick();
1395
1396 /* Get the remaining bytes if any */
1397 while(((int)(Size)) > 0)
1398 {
1399 if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)
1400 {
1401 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
1402 Size -= 4;
1403 Array += 4;
1404 }
1405
1406 /* Check for the Timeout */
1407 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1408 {
1409 /* Process Unlocked */
1410 __HAL_UNLOCK(hdsi);
1411
1412 return HAL_TIMEOUT;
1413 }
1414 }
1415
1416 /* Process unlocked */
1417 __HAL_UNLOCK(hdsi);
1418
1419 return HAL_OK;
1420 }
1421
1422 /**
1423 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1424 * (only data lanes are in ULPM)
1425 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1426 * the configuration information for the DSI.
1427 * @retval HAL status
1428 */
1429 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
1430 {
1431 uint32_t tickstart = 0;
1432
1433 /* Process locked */
1434 __HAL_LOCK(hdsi);
1435
1436 /* ULPS Request on Data Lanes */
1437 hdsi->Instance->PUCR |= DSI_PUCR_URDL;
1438
1439 /* Get tick */
1440 tickstart = HAL_GetTick();
1441
1442 /* Wait until the D-PHY active lanes enter into ULPM */
1443 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1444 {
1445 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
1446 {
1447 /* Check for the Timeout */
1448 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1449 {
1450 /* Process Unlocked */
1451 __HAL_UNLOCK(hdsi);
1452
1453 return HAL_TIMEOUT;
1454 }
1455 }
1456 }
1457 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1458 {
1459 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
1460 {
1461 /* Check for the Timeout */
1462 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1463 {
1464 /* Process Unlocked */
1465 __HAL_UNLOCK(hdsi);
1466
1467 return HAL_TIMEOUT;
1468 }
1469 }
1470 }
1471
1472 /* Process unlocked */
1473 __HAL_UNLOCK(hdsi);
1474
1475 return HAL_OK;
1476 }
1477
1478 /**
1479 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1480 * (only data lanes are in ULPM)
1481 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1482 * the configuration information for the DSI.
1483 * @retval HAL status
1484 */
1485 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
1486 {
1487 uint32_t tickstart = 0;
1488
1489 /* Process locked */
1490 __HAL_LOCK(hdsi);
1491
1492 /* Exit ULPS on Data Lanes */
1493 hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
1494
1495 /* Get tick */
1496 tickstart = HAL_GetTick();
1497
1498 /* Wait until all active lanes exit ULPM */
1499 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1500 {
1501 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
1502 {
1503 /* Check for the Timeout */
1504 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1505 {
1506 /* Process Unlocked */
1507 __HAL_UNLOCK(hdsi);
1508
1509 return HAL_TIMEOUT;
1510 }
1511 }
1512 }
1513 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1514 {
1515 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
1516 {
1517 /* Check for the Timeout */
1518 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1519 {
1520 /* Process Unlocked */
1521 __HAL_UNLOCK(hdsi);
1522
1523 return HAL_TIMEOUT;
1524 }
1525 }
1526 }
1527
1528 /* De-assert the ULPM requests and the ULPM exit bits */
1529 hdsi->Instance->PUCR = 0;
1530
1531 /* Process unlocked */
1532 __HAL_UNLOCK(hdsi);
1533
1534 return HAL_OK;
1535 }
1536
1537 /**
1538 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1539 * (both data and clock lanes are in ULPM)
1540 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1541 * the configuration information for the DSI.
1542 * @retval HAL status
1543 */
1544 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
1545 {
1546 uint32_t tickstart = 0;
1547
1548 /* Process locked */
1549 __HAL_LOCK(hdsi);
1550
1551 /* Clock lane configuration: no more HS request */
1552 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
1553
1554 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
1555 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
1556
1557 /* ULPS Request on Clock and Data Lanes */
1558 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
1559
1560 /* Get tick */
1561 tickstart = HAL_GetTick();
1562
1563 /* Wait until all active lanes exit ULPM */
1564 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1565 {
1566 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
1567 {
1568 /* Check for the Timeout */
1569 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1570 {
1571 /* Process Unlocked */
1572 __HAL_UNLOCK(hdsi);
1573
1574 return HAL_TIMEOUT;
1575 }
1576 }
1577 }
1578 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1579 {
1580 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
1581 {
1582 /* Check for the Timeout */
1583 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1584 {
1585 /* Process Unlocked */
1586 __HAL_UNLOCK(hdsi);
1587
1588 return HAL_TIMEOUT;
1589 }
1590 }
1591 }
1592
1593 /* Turn off the DSI PLL */
1594 __HAL_DSI_PLL_DISABLE(hdsi);
1595
1596 /* Process unlocked */
1597 __HAL_UNLOCK(hdsi);
1598
1599 return HAL_OK;
1600 }
1601
1602 /**
1603 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1604 * (both data and clock lanes are in ULPM)
1605 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1606 * the configuration information for the DSI.
1607 * @retval HAL status
1608 */
1609 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
1610 {
1611 uint32_t tickstart = 0;
1612
1613 /* Process locked */
1614 __HAL_LOCK(hdsi);
1615
1616 /* Turn on the DSI PLL */
1617 __HAL_DSI_PLL_ENABLE(hdsi);
1618
1619 /* Get tick */
1620 tickstart = HAL_GetTick();
1621
1622 /* Wait for the lock of the PLL */
1623 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
1624 {
1625 /* Check for the Timeout */
1626 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1627 {
1628 /* Process Unlocked */
1629 __HAL_UNLOCK(hdsi);
1630
1631 return HAL_TIMEOUT;
1632 }
1633 }
1634
1635 /* Exit ULPS on Clock and Data Lanes */
1636 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
1637
1638 /* Get tick */
1639 tickstart = HAL_GetTick();
1640
1641 /* Wait until all active lanes exit ULPM */
1642 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1643 {
1644 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
1645 {
1646 /* Check for the Timeout */
1647 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1648 {
1649 /* Process Unlocked */
1650 __HAL_UNLOCK(hdsi);
1651
1652 return HAL_TIMEOUT;
1653 }
1654 }
1655 }
1656 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1657 {
1658 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
1659 {
1660 /* Check for the Timeout */
1661 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1662 {
1663 /* Process Unlocked */
1664 __HAL_UNLOCK(hdsi);
1665
1666 return HAL_TIMEOUT;
1667 }
1668 }
1669 }
1670
1671 /* De-assert the ULPM requests and the ULPM exit bits */
1672 hdsi->Instance->PUCR = 0;
1673
1674 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
1675 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
1676
1677 /* Restore clock lane configuration to HS */
1678 hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
1679
1680 /* Process unlocked */
1681 __HAL_UNLOCK(hdsi);
1682
1683 return HAL_OK;
1684 }
1685
1686 /**
1687 * @brief Start test pattern generation
1688 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1689 * the configuration information for the DSI.
1690 * @param Mode: Pattern generator mode
1691 * This parameter can be one of the following values:
1692 * 0 : Color bars (horizontal or vertical)
1693 * 1 : BER pattern (vertical only)
1694 * @param Orientation: Pattern generator orientation
1695 * This parameter can be one of the following values:
1696 * 0 : Vertical color bars
1697 * 1 : Horizontal color bars
1698 * @retval HAL status
1699 */
1700 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
1701 {
1702 /* Process locked */
1703 __HAL_LOCK(hdsi);
1704
1705 /* Configure pattern generator mode and orientation */
1706 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
1707 hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));
1708
1709 /* Enable pattern generator by setting PGE bit */
1710 hdsi->Instance->VMCR |= DSI_VMCR_PGE;
1711
1712 /* Process unlocked */
1713 __HAL_UNLOCK(hdsi);
1714
1715 return HAL_OK;
1716 }
1717
1718 /**
1719 * @brief Stop test pattern generation
1720 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1721 * the configuration information for the DSI.
1722 * @retval HAL status
1723 */
1724 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
1725 {
1726 /* Process locked */
1727 __HAL_LOCK(hdsi);
1728
1729 /* Disable pattern generator by clearing PGE bit */
1730 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
1731
1732 /* Process unlocked */
1733 __HAL_UNLOCK(hdsi);
1734
1735 return HAL_OK;
1736 }
1737
1738 /**
1739 * @brief Set Slew-Rate And Delay Tuning
1740 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1741 * the configuration information for the DSI.
1742 * @param CommDelay: Communication delay to be adjusted.
1743 * This parameter can be any value of @ref DSI_Communication_Delay
1744 * @param Lane: select between clock or data lanes.
1745 * This parameter can be any value of @ref DSI_Lane_Group
1746 * @param Value: Custom value of the slew-rate or delay
1747 * @retval HAL status
1748 */
1749 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
1750 {
1751 /* Process locked */
1752 __HAL_LOCK(hdsi);
1753
1754 /* Check function parameters */
1755 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
1756 assert_param(IS_DSI_LANE_GROUP(Lane));
1757
1758 switch(CommDelay)
1759 {
1760 case DSI_SLEW_RATE_HSTX:
1761 if(Lane == DSI_CLOCK_LANE)
1762 {
1763 /* High-Speed Transmission Slew Rate Control on Clock Lane */
1764 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;
1765 hdsi->Instance->WPCR[1] |= Value<<16;
1766 }
1767 else if(Lane == DSI_DATA_LANES)
1768 {
1769 /* High-Speed Transmission Slew Rate Control on Data Lanes */
1770 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;
1771 hdsi->Instance->WPCR[1] |= Value<<18;
1772 }
1773 break;
1774 case DSI_SLEW_RATE_LPTX:
1775 if(Lane == DSI_CLOCK_LANE)
1776 {
1777 /* Low-Power transmission Slew Rate Compensation on Clock Lane */
1778 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;
1779 hdsi->Instance->WPCR[1] |= Value<<6;
1780 }
1781 else if(Lane == DSI_DATA_LANES)
1782 {
1783 /* Low-Power transmission Slew Rate Compensation on Data Lanes */
1784 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;
1785 hdsi->Instance->WPCR[1] |= Value<<8;
1786 }
1787 break;
1788 case DSI_HS_DELAY:
1789 if(Lane == DSI_CLOCK_LANE)
1790 {
1791 /* High-Speed Transmission Delay on Clock Lane */
1792 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;
1793 hdsi->Instance->WPCR[1] |= Value;
1794 }
1795 else if(Lane == DSI_DATA_LANES)
1796 {
1797 /* High-Speed Transmission Delay on Data Lanes */
1798 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;
1799 hdsi->Instance->WPCR[1] |= Value<<2;
1800 }
1801 break;
1802 default:
1803 break;
1804 }
1805
1806 /* Process unlocked */
1807 __HAL_UNLOCK(hdsi);
1808
1809 return HAL_OK;
1810 }
1811
1812 /**
1813 * @brief Low-Power Reception Filter Tuning
1814 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1815 * the configuration information for the DSI.
1816 * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
1817 * @retval HAL status
1818 */
1819 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
1820 {
1821 /* Process locked */
1822 __HAL_LOCK(hdsi);
1823
1824 /* Low-Power RX low-pass Filtering Tuning */
1825 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;
1826 hdsi->Instance->WPCR[1] |= Frequency<<25;
1827
1828 /* Process unlocked */
1829 __HAL_UNLOCK(hdsi);
1830
1831 return HAL_OK;
1832 }
1833
1834 /**
1835 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
1836 * defined in the MIPI D-PHY specification
1837 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1838 * the configuration information for the DSI.
1839 * @param State: ENABLE or DISABLE
1840 * @retval HAL status
1841 */
1842 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
1843 {
1844 /* Process locked */
1845 __HAL_LOCK(hdsi);
1846
1847 /* Check function parameters */
1848 assert_param(IS_FUNCTIONAL_STATE(State));
1849
1850 /* Activate/Disactivate additional current path on all lanes */
1851 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;
1852 hdsi->Instance->WPCR[1] |= ((uint32_t)State << 12);
1853
1854 /* Process unlocked */
1855 __HAL_UNLOCK(hdsi);
1856
1857 return HAL_OK;
1858 }
1859
1860 /**
1861 * @brief Custom lane pins configuration
1862 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1863 * the configuration information for the DSI.
1864 * @param CustomLane: Function to be applyed on selected lane.
1865 * This parameter can be any value of @ref DSI_CustomLane
1866 * @param Lane: select between clock or data lane 0 or data lane 1.
1867 * This parameter can be any value of @ref DSI_Lane_Select
1868 * @param State: ENABLE or DISABLE
1869 * @retval HAL status
1870 */
1871 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
1872 {
1873 /* Process locked */
1874 __HAL_LOCK(hdsi);
1875
1876 /* Check function parameters */
1877 assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
1878 assert_param(IS_DSI_LANE(Lane));
1879 assert_param(IS_FUNCTIONAL_STATE(State));
1880
1881 switch(CustomLane)
1882 {
1883 case DSI_SWAP_LANE_PINS:
1884 if(Lane == DSI_CLOCK_LANE)
1885 {
1886 /* Swap pins on clock lane */
1887 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;
1888 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 6);
1889 }
1890 else if(Lane == DSI_DATA_LANE0)
1891 {
1892 /* Swap pins on data lane 0 */
1893 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;
1894 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 7);
1895 }
1896 else if(Lane == DSI_DATA_LANE1)
1897 {
1898 /* Swap pins on data lane 1 */
1899 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;
1900 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 8);
1901 }
1902 break;
1903 case DSI_INVERT_HS_SIGNAL:
1904 if(Lane == DSI_CLOCK_LANE)
1905 {
1906 /* Invert HS signal on clock lane */
1907 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;
1908 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 9);
1909 }
1910 else if(Lane == DSI_DATA_LANE0)
1911 {
1912 /* Invert HS signal on data lane 0 */
1913 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;
1914 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 10);
1915 }
1916 else if(Lane == DSI_DATA_LANE1)
1917 {
1918 /* Invert HS signal on data lane 1 */
1919 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;
1920 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 11);
1921 }
1922 break;
1923 default:
1924 break;
1925 }
1926
1927 /* Process unlocked */
1928 __HAL_UNLOCK(hdsi);
1929
1930 return HAL_OK;
1931 }
1932
1933 /**
1934 * @brief Set custom timing for the PHY
1935 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1936 * the configuration information for the DSI.
1937 * @param Timing: PHY timing to be adjusted.
1938 * This parameter can be any value of @ref DSI_PHY_Timing
1939 * @param State: ENABLE or DISABLE
1940 * @param Value: Custom value of the timing
1941 * @retval HAL status
1942 */
1943 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
1944 {
1945 /* Process locked */
1946 __HAL_LOCK(hdsi);
1947
1948 /* Check function parameters */
1949 assert_param(IS_DSI_PHY_TIMING(Timing));
1950 assert_param(IS_FUNCTIONAL_STATE(State));
1951
1952 switch(Timing)
1953 {
1954 case DSI_TCLK_POST:
1955 /* Enable/Disable custom timing setting */
1956 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;
1957 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 27);
1958
1959 if(State)
1960 {
1961 /* Set custom value */
1962 hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;
1963 hdsi->Instance->WPCR[4] |= Value & DSI_WPCR4_TCLKPOST;
1964 }
1965
1966 break;
1967 case DSI_TLPX_CLK:
1968 /* Enable/Disable custom timing setting */
1969 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;
1970 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 26);
1971
1972 if(State)
1973 {
1974 /* Set custom value */
1975 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;
1976 hdsi->Instance->WPCR[3] |= (Value << 24) & DSI_WPCR3_TLPXC;
1977 }
1978
1979 break;
1980 case DSI_THS_EXIT:
1981 /* Enable/Disable custom timing setting */
1982 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;
1983 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 25);
1984
1985 if(State)
1986 {
1987 /* Set custom value */
1988 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;
1989 hdsi->Instance->WPCR[3] |= (Value << 16) & DSI_WPCR3_THSEXIT;
1990 }
1991
1992 break;
1993 case DSI_TLPX_DATA:
1994 /* Enable/Disable custom timing setting */
1995 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;
1996 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 24);
1997
1998 if(State)
1999 {
2000 /* Set custom value */
2001 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;
2002 hdsi->Instance->WPCR[3] |= (Value << 8) & DSI_WPCR3_TLPXD;
2003 }
2004
2005 break;
2006 case DSI_THS_ZERO:
2007 /* Enable/Disable custom timing setting */
2008 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;
2009 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 23);
2010
2011 if(State)
2012 {
2013 /* Set custom value */
2014 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;
2015 hdsi->Instance->WPCR[3] |= Value & DSI_WPCR3_THSZERO;
2016 }
2017
2018 break;
2019 case DSI_THS_TRAIL:
2020 /* Enable/Disable custom timing setting */
2021 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;
2022 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 22);
2023
2024 if(State)
2025 {
2026 /* Set custom value */
2027 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;
2028 hdsi->Instance->WPCR[2] |= (Value << 24) & DSI_WPCR2_THSTRAIL;
2029 }
2030
2031 break;
2032 case DSI_THS_PREPARE:
2033 /* Enable/Disable custom timing setting */
2034 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;
2035 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 21);
2036
2037 if(State)
2038 {
2039 /* Set custom value */
2040 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;
2041 hdsi->Instance->WPCR[2] |= (Value << 16) & DSI_WPCR2_THSPREP;
2042 }
2043
2044 break;
2045 case DSI_TCLK_ZERO:
2046 /* Enable/Disable custom timing setting */
2047 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;
2048 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 20);
2049
2050 if(State)
2051 {
2052 /* Set custom value */
2053 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;
2054 hdsi->Instance->WPCR[2] |= (Value << 8) & DSI_WPCR2_TCLKZERO;
2055 }
2056
2057 break;
2058 case DSI_TCLK_PREPARE:
2059 /* Enable/Disable custom timing setting */
2060 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;
2061 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 19);
2062
2063 if(State)
2064 {
2065 /* Set custom value */
2066 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;
2067 hdsi->Instance->WPCR[2] |= Value & DSI_WPCR2_TCLKPREP;
2068 }
2069
2070 break;
2071 default:
2072 break;
2073 }
2074
2075 /* Process unlocked */
2076 __HAL_UNLOCK(hdsi);
2077
2078 return HAL_OK;
2079 }
2080
2081 /**
2082 * @brief Force the Clock/Data Lane in TX Stop Mode
2083 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2084 * the configuration information for the DSI.
2085 * @param Lane: select between clock or data lanes.
2086 * This parameter can be any value of @ref DSI_Lane_Group
2087 * @param State: ENABLE or DISABLE
2088 * @retval HAL status
2089 */
2090 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
2091 {
2092 /* Process locked */
2093 __HAL_LOCK(hdsi);
2094
2095 /* Check function parameters */
2096 assert_param(IS_DSI_LANE_GROUP(Lane));
2097 assert_param(IS_FUNCTIONAL_STATE(State));
2098
2099 if(Lane == DSI_CLOCK_LANE)
2100 {
2101 /* Force/Unforce the Clock Lane in TX Stop Mode */
2102 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;
2103 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 12);
2104 }
2105 else if(Lane == DSI_DATA_LANES)
2106 {
2107 /* Force/Unforce the Data Lanes in TX Stop Mode */
2108 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;
2109 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 13);
2110 }
2111
2112 /* Process unlocked */
2113 __HAL_UNLOCK(hdsi);
2114
2115 return HAL_OK;
2116 }
2117
2118 /**
2119 * @brief Forces LP Receiver in Low-Power Mode
2120 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2121 * the configuration information for the DSI.
2122 * @param State: ENABLE or DISABLE
2123 * @retval HAL status
2124 */
2125 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
2126 {
2127 /* Process locked */
2128 __HAL_LOCK(hdsi);
2129
2130 /* Check function parameters */
2131 assert_param(IS_FUNCTIONAL_STATE(State));
2132
2133 /* Force/Unforce LP Receiver in Low-Power Mode */
2134 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;
2135 hdsi->Instance->WPCR[1] |= ((uint32_t)State << 22);
2136
2137 /* Process unlocked */
2138 __HAL_UNLOCK(hdsi);
2139
2140 return HAL_OK;
2141 }
2142
2143 /**
2144 * @brief Force Data Lanes in RX Mode after a BTA
2145 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2146 * the configuration information for the DSI.
2147 * @param State: ENABLE or DISABLE
2148 * @retval HAL status
2149 */
2150 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
2151 {
2152 /* Process locked */
2153 __HAL_LOCK(hdsi);
2154
2155 /* Check function parameters */
2156 assert_param(IS_FUNCTIONAL_STATE(State));
2157
2158 /* Force Data Lanes in RX Mode */
2159 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;
2160 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 16);
2161
2162 /* Process unlocked */
2163 __HAL_UNLOCK(hdsi);
2164
2165 return HAL_OK;
2166 }
2167
2168 /**
2169 * @brief Enable a pull-down on the lanes to prevent from floating states when unused
2170 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2171 * the configuration information for the DSI.
2172 * @param State: ENABLE or DISABLE
2173 * @retval HAL status
2174 */
2175 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
2176 {
2177 /* Process locked */
2178 __HAL_LOCK(hdsi);
2179
2180 /* Check function parameters */
2181 assert_param(IS_FUNCTIONAL_STATE(State));
2182
2183 /* Enable/Disable pull-down on lanes */
2184 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;
2185 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 18);
2186
2187 /* Process unlocked */
2188 __HAL_UNLOCK(hdsi);
2189
2190 return HAL_OK;
2191 }
2192
2193 /**
2194 * @brief Switch off the contention detection on data lanes
2195 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2196 * the configuration information for the DSI.
2197 * @param State: ENABLE or DISABLE
2198 * @retval HAL status
2199 */
2200 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
2201 {
2202 /* Process locked */
2203 __HAL_LOCK(hdsi);
2204
2205 /* Check function parameters */
2206 assert_param(IS_FUNCTIONAL_STATE(State));
2207
2208 /* Contention Detection on Data Lanes OFF */
2209 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;
2210 hdsi->Instance->WPCR[0] |= ((uint32_t)State << 14);
2211
2212 /* Process unlocked */
2213 __HAL_UNLOCK(hdsi);
2214
2215 return HAL_OK;
2216 }
2217
2218 /**
2219 * @}
2220 */
2221
2222 /** @defgroup DSI_Group4 Peripheral State and Errors functions
2223 * @brief Peripheral State and Errors functions
2224 *
2225 @verbatim
2226 ===============================================================================
2227 ##### Peripheral State and Errors functions #####
2228 ===============================================================================
2229 [..]
2230 This subsection provides functions allowing to
2231 (+) Check the DSI state.
2232 (+) Get error code.
2233
2234 @endverbatim
2235 * @{
2236 */
2237
2238 /**
2239 * @brief Return the DSI state
2240 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2241 * the configuration information for the DSI.
2242 * @retval HAL state
2243 */
2244 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
2245 {
2246 return hdsi->State;
2247 }
2248
2249 /**
2250 * @}
2251 */
2252
2253 /**
2254 * @}
2255 */
2256 #endif /*STM32F769xx | STM32F779xx */
2257 #endif /* HAL_DSI_MODULE_ENABLED */
2258 /**
2259 * @}
2260 */
2261
2262 /**
2263 * @}
2264 */
2265
2266 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)