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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_eth.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_eth.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief ETH HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Ethernet (ETH) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
21 ETH_HandleTypeDef heth;
22
23 (#)Fill parameters of Init structure in heth handle
24
25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
26
27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
28 (##) Enable the Ethernet interface clock using
29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
32
33 (##) Initialize the related GPIO clocks
34 (##) Configure Ethernet pin-out
35 (##) Configure Ethernet NVIC interrupt (IT mode)
36
37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
40
41 (#)Enable MAC and DMA transmission and reception:
42 (##) HAL_ETH_Start();
43
44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
45 the frame to MAC TX FIFO:
46 (##) HAL_ETH_TransmitFrame();
47
48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
49 frame parameters
50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
51
52 (#) Get a received frame when an ETH RX interrupt occurs:
53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
54
55 (#) Communicate with external PHY device:
56 (##) Read a specific register from the PHY
57 HAL_ETH_ReadPHYRegister();
58 (##) Write data to a specific RHY register:
59 HAL_ETH_WritePHYRegister();
60
61 (#) Configure the Ethernet MAC after ETH peripheral initialization
62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
63
64 (#) Configure the Ethernet DMA after ETH peripheral initialization
65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
66
67 @endverbatim
68 ******************************************************************************
69 * @attention
70 *
71 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
72 *
73 * Redistribution and use in source and binary forms, with or without modification,
74 * are permitted provided that the following conditions are met:
75 * 1. Redistributions of source code must retain the above copyright notice,
76 * this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright notice,
78 * this list of conditions and the following disclaimer in the documentation
79 * and/or other materials provided with the distribution.
80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
81 * may be used to endorse or promote products derived from this software
82 * without specific prior written permission.
83 *
84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
94 *
95 ******************************************************************************
96 */
97
98 /* Includes ------------------------------------------------------------------*/
99 #include "stm32f7xx_hal.h"
100
101 /** @addtogroup STM32F7xx_HAL_Driver
102 * @{
103 */
104
105 /** @defgroup ETH ETH
106 * @brief ETH HAL module driver
107 * @{
108 */
109
110 #ifdef HAL_ETH_MODULE_ENABLED
111
112 /* Private typedef -----------------------------------------------------------*/
113 /* Private define ------------------------------------------------------------*/
114 /** @defgroup ETH_Private_Constants ETH Private Constants
115 * @{
116 */
117 #define ETH_TIMEOUT_SWRESET ((uint32_t)500)
118 #define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000)
119 #define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000)
120
121 /**
122 * @}
123 */
124 /* Private macro -------------------------------------------------------------*/
125 /* Private variables ---------------------------------------------------------*/
126 /* Private function prototypes -----------------------------------------------*/
127 /** @defgroup ETH_Private_Functions ETH Private Functions
128 * @{
129 */
130 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
131 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
132 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
133 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
134 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
135 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
136 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
137 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
138 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
139 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
140 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
141
142 /**
143 * @}
144 */
145 /* Private functions ---------------------------------------------------------*/
146
147 /** @defgroup ETH_Exported_Functions ETH Exported Functions
148 * @{
149 */
150
151 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
152 * @brief Initialization and Configuration functions
153 *
154 @verbatim
155 ===============================================================================
156 ##### Initialization and de-initialization functions #####
157 ===============================================================================
158 [..] This section provides functions allowing to:
159 (+) Initialize and configure the Ethernet peripheral
160 (+) De-initialize the Ethernet peripheral
161
162 @endverbatim
163 * @{
164 */
165
166 /**
167 * @brief Initializes the Ethernet MAC and DMA according to default
168 * parameters.
169 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
170 * the configuration information for ETHERNET module
171 * @retval HAL status
172 */
173 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
174 {
175 uint32_t tempreg = 0, phyreg = 0;
176 uint32_t hclk = 60000000;
177 uint32_t tickstart = 0;
178 uint32_t err = ETH_SUCCESS;
179
180 /* Check the ETH peripheral state */
181 if(heth == NULL)
182 {
183 return HAL_ERROR;
184 }
185
186 /* Check parameters */
187 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
188 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
189 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
190 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
191
192 if(heth->State == HAL_ETH_STATE_RESET)
193 {
194 /* Allocate lock resource and initialize it */
195 heth->Lock = HAL_UNLOCKED;
196 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
197 HAL_ETH_MspInit(heth);
198 }
199
200 /* Enable SYSCFG Clock */
201 __HAL_RCC_SYSCFG_CLK_ENABLE();
202
203 /* Select MII or RMII Mode*/
204 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
205 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
206
207 /* Ethernet Software reset */
208 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
209 /* After reset all the registers holds their respective reset values */
210 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
211
212 /* Get tick */
213 tickstart = HAL_GetTick();
214
215 /* Wait for software reset */
216 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
217 {
218 /* Check for the Timeout */
219 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
220 {
221 heth->State= HAL_ETH_STATE_TIMEOUT;
222
223 /* Process Unlocked */
224 __HAL_UNLOCK(heth);
225
226 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
227 not available, please check your external PHY or the IO configuration */
228
229 return HAL_TIMEOUT;
230 }
231 }
232
233 /*-------------------------------- MAC Initialization ----------------------*/
234 /* Get the ETHERNET MACMIIAR value */
235 tempreg = (heth->Instance)->MACMIIAR;
236 /* Clear CSR Clock Range CR[2:0] bits */
237 tempreg &= ETH_MACMIIAR_CR_MASK;
238
239 /* Get hclk frequency value */
240 hclk = HAL_RCC_GetHCLKFreq();
241
242 /* Set CR bits depending on hclk value */
243 if((hclk >= 20000000)&&(hclk < 35000000))
244 {
245 /* CSR Clock Range between 20-35 MHz */
246 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
247 }
248 else if((hclk >= 35000000)&&(hclk < 60000000))
249 {
250 /* CSR Clock Range between 35-60 MHz */
251 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
252 }
253 else if((hclk >= 60000000)&&(hclk < 100000000))
254 {
255 /* CSR Clock Range between 60-100 MHz */
256 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
257 }
258 else if((hclk >= 100000000)&&(hclk < 150000000))
259 {
260 /* CSR Clock Range between 100-150 MHz */
261 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
262 }
263 else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
264 {
265 /* CSR Clock Range between 150-216 MHz */
266 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
267 }
268
269 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
270 (heth->Instance)->MACMIIAR = (uint32_t)tempreg;
271
272 /*-------------------- PHY initialization and configuration ----------------*/
273 /* Put the PHY in reset mode */
274 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
275 {
276 /* In case of write timeout */
277 err = ETH_ERROR;
278
279 /* Config MAC and DMA */
280 ETH_MACDMAConfig(heth, err);
281
282 /* Set the ETH peripheral state to READY */
283 heth->State = HAL_ETH_STATE_READY;
284
285 /* Return HAL_ERROR */
286 return HAL_ERROR;
287 }
288
289 /* Delay to assure PHY reset */
290 HAL_Delay(PHY_RESET_DELAY);
291
292 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
293 {
294 /* Get tick */
295 tickstart = HAL_GetTick();
296
297 /* We wait for linked status */
298 do
299 {
300 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
301
302 /* Check for the Timeout */
303 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
304 {
305 /* In case of write timeout */
306 err = ETH_ERROR;
307
308 /* Config MAC and DMA */
309 ETH_MACDMAConfig(heth, err);
310
311 heth->State= HAL_ETH_STATE_READY;
312
313 /* Process Unlocked */
314 __HAL_UNLOCK(heth);
315
316 return HAL_TIMEOUT;
317 }
318 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
319
320
321 /* Enable Auto-Negotiation */
322 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
323 {
324 /* In case of write timeout */
325 err = ETH_ERROR;
326
327 /* Config MAC and DMA */
328 ETH_MACDMAConfig(heth, err);
329
330 /* Set the ETH peripheral state to READY */
331 heth->State = HAL_ETH_STATE_READY;
332
333 /* Return HAL_ERROR */
334 return HAL_ERROR;
335 }
336
337 /* Get tick */
338 tickstart = HAL_GetTick();
339
340 /* Wait until the auto-negotiation will be completed */
341 do
342 {
343 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
344
345 /* Check for the Timeout */
346 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
347 {
348 /* In case of write timeout */
349 err = ETH_ERROR;
350
351 /* Config MAC and DMA */
352 ETH_MACDMAConfig(heth, err);
353
354 heth->State= HAL_ETH_STATE_READY;
355
356 /* Process Unlocked */
357 __HAL_UNLOCK(heth);
358
359 return HAL_TIMEOUT;
360 }
361
362 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
363
364 /* Read the result of the auto-negotiation */
365 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
366 {
367 /* In case of write timeout */
368 err = ETH_ERROR;
369
370 /* Config MAC and DMA */
371 ETH_MACDMAConfig(heth, err);
372
373 /* Set the ETH peripheral state to READY */
374 heth->State = HAL_ETH_STATE_READY;
375
376 /* Return HAL_ERROR */
377 return HAL_ERROR;
378 }
379
380 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
381 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
382 {
383 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
384 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
385 }
386 else
387 {
388 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
389 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
390 }
391 /* Configure the MAC with the speed fixed by the auto-negotiation process */
392 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
393 {
394 /* Set Ethernet speed to 10M following the auto-negotiation */
395 (heth->Init).Speed = ETH_SPEED_10M;
396 }
397 else
398 {
399 /* Set Ethernet speed to 100M following the auto-negotiation */
400 (heth->Init).Speed = ETH_SPEED_100M;
401 }
402 }
403 else /* AutoNegotiation Disable */
404 {
405 /* Check parameters */
406 assert_param(IS_ETH_SPEED(heth->Init.Speed));
407 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
408
409 /* Set MAC Speed and Duplex Mode */
410 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
411 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
412 {
413 /* In case of write timeout */
414 err = ETH_ERROR;
415
416 /* Config MAC and DMA */
417 ETH_MACDMAConfig(heth, err);
418
419 /* Set the ETH peripheral state to READY */
420 heth->State = HAL_ETH_STATE_READY;
421
422 /* Return HAL_ERROR */
423 return HAL_ERROR;
424 }
425
426 /* Delay to assure PHY configuration */
427 HAL_Delay(PHY_CONFIG_DELAY);
428 }
429
430 /* Config MAC and DMA */
431 ETH_MACDMAConfig(heth, err);
432
433 /* Set ETH HAL State to Ready */
434 heth->State= HAL_ETH_STATE_READY;
435
436 /* Return function status */
437 return HAL_OK;
438 }
439
440 /**
441 * @brief De-Initializes the ETH peripheral.
442 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
443 * the configuration information for ETHERNET module
444 * @retval HAL status
445 */
446 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
447 {
448 /* Set the ETH peripheral state to BUSY */
449 heth->State = HAL_ETH_STATE_BUSY;
450
451 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
452 HAL_ETH_MspDeInit(heth);
453
454 /* Set ETH HAL state to Disabled */
455 heth->State= HAL_ETH_STATE_RESET;
456
457 /* Release Lock */
458 __HAL_UNLOCK(heth);
459
460 /* Return function status */
461 return HAL_OK;
462 }
463
464 /**
465 * @brief Initializes the DMA Tx descriptors in chain mode.
466 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
467 * the configuration information for ETHERNET module
468 * @param DMATxDescTab: Pointer to the first Tx desc list
469 * @param TxBuff: Pointer to the first TxBuffer list
470 * @param TxBuffCount: Number of the used Tx desc in the list
471 * @retval HAL status
472 */
473 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
474 {
475 uint32_t i = 0;
476 ETH_DMADescTypeDef *dmatxdesc;
477
478 /* Process Locked */
479 __HAL_LOCK(heth);
480
481 /* Set the ETH peripheral state to BUSY */
482 heth->State = HAL_ETH_STATE_BUSY;
483
484 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
485 heth->TxDesc = DMATxDescTab;
486
487 /* Fill each DMATxDesc descriptor with the right values */
488 for(i=0; i < TxBuffCount; i++)
489 {
490 /* Get the pointer on the ith member of the Tx Desc list */
491 dmatxdesc = DMATxDescTab + i;
492
493 /* Set Second Address Chained bit */
494 dmatxdesc->Status = ETH_DMATXDESC_TCH;
495
496 /* Set Buffer1 address pointer */
497 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
498
499 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
500 {
501 /* Set the DMA Tx descriptors checksum insertion */
502 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
503 }
504
505 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
506 if(i < (TxBuffCount-1))
507 {
508 /* Set next descriptor address register with next descriptor base address */
509 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
510 }
511 else
512 {
513 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
514 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
515 }
516 }
517
518 /* Set Transmit Descriptor List Address Register */
519 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
520
521 /* Set ETH HAL State to Ready */
522 heth->State= HAL_ETH_STATE_READY;
523
524 /* Process Unlocked */
525 __HAL_UNLOCK(heth);
526
527 /* Return function status */
528 return HAL_OK;
529 }
530
531 /**
532 * @brief Initializes the DMA Rx descriptors in chain mode.
533 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
534 * the configuration information for ETHERNET module
535 * @param DMARxDescTab: Pointer to the first Rx desc list
536 * @param RxBuff: Pointer to the first RxBuffer list
537 * @param RxBuffCount: Number of the used Rx desc in the list
538 * @retval HAL status
539 */
540 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
541 {
542 uint32_t i = 0;
543 ETH_DMADescTypeDef *DMARxDesc;
544
545 /* Process Locked */
546 __HAL_LOCK(heth);
547
548 /* Set the ETH peripheral state to BUSY */
549 heth->State = HAL_ETH_STATE_BUSY;
550
551 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
552 heth->RxDesc = DMARxDescTab;
553
554 /* Fill each DMARxDesc descriptor with the right values */
555 for(i=0; i < RxBuffCount; i++)
556 {
557 /* Get the pointer on the ith member of the Rx Desc list */
558 DMARxDesc = DMARxDescTab+i;
559
560 /* Set Own bit of the Rx descriptor Status */
561 DMARxDesc->Status = ETH_DMARXDESC_OWN;
562
563 /* Set Buffer1 size and Second Address Chained bit */
564 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
565
566 /* Set Buffer1 address pointer */
567 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
568
569 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
570 {
571 /* Enable Ethernet DMA Rx Descriptor interrupt */
572 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
573 }
574
575 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
576 if(i < (RxBuffCount-1))
577 {
578 /* Set next descriptor address register with next descriptor base address */
579 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
580 }
581 else
582 {
583 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
584 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
585 }
586 }
587
588 /* Set Receive Descriptor List Address Register */
589 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
590
591 /* Set ETH HAL State to Ready */
592 heth->State= HAL_ETH_STATE_READY;
593
594 /* Process Unlocked */
595 __HAL_UNLOCK(heth);
596
597 /* Return function status */
598 return HAL_OK;
599 }
600
601 /**
602 * @brief Initializes the ETH MSP.
603 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
604 * the configuration information for ETHERNET module
605 * @retval None
606 */
607 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
608 {
609 /* Prevent unused argument(s) compilation warning */
610 UNUSED(heth);
611
612 /* NOTE : This function Should not be modified, when the callback is needed,
613 the HAL_ETH_MspInit could be implemented in the user file
614 */
615 }
616
617 /**
618 * @brief DeInitializes ETH MSP.
619 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
620 * the configuration information for ETHERNET module
621 * @retval None
622 */
623 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
624 {
625 /* Prevent unused argument(s) compilation warning */
626 UNUSED(heth);
627
628 /* NOTE : This function Should not be modified, when the callback is needed,
629 the HAL_ETH_MspDeInit could be implemented in the user file
630 */
631 }
632
633 /**
634 * @}
635 */
636
637 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
638 * @brief Data transfers functions
639 *
640 @verbatim
641 ==============================================================================
642 ##### IO operation functions #####
643 ==============================================================================
644 [..] This section provides functions allowing to:
645 (+) Transmit a frame
646 HAL_ETH_TransmitFrame();
647 (+) Receive a frame
648 HAL_ETH_GetReceivedFrame();
649 HAL_ETH_GetReceivedFrame_IT();
650 (+) Read from an External PHY register
651 HAL_ETH_ReadPHYRegister();
652 (+) Write to an External PHY register
653 HAL_ETH_WritePHYRegister();
654
655 @endverbatim
656
657 * @{
658 */
659
660 /**
661 * @brief Sends an Ethernet frame.
662 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
663 * the configuration information for ETHERNET module
664 * @param FrameLength: Amount of data to be sent
665 * @retval HAL status
666 */
667 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
668 {
669 uint32_t bufcount = 0, size = 0, i = 0;
670
671 /* Process Locked */
672 __HAL_LOCK(heth);
673
674 /* Set the ETH peripheral state to BUSY */
675 heth->State = HAL_ETH_STATE_BUSY;
676
677 if (FrameLength == 0)
678 {
679 /* Set ETH HAL state to READY */
680 heth->State = HAL_ETH_STATE_READY;
681
682 /* Process Unlocked */
683 __HAL_UNLOCK(heth);
684
685 return HAL_ERROR;
686 }
687
688 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
689 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
690 {
691 /* OWN bit set */
692 heth->State = HAL_ETH_STATE_BUSY_TX;
693
694 /* Process Unlocked */
695 __HAL_UNLOCK(heth);
696
697 return HAL_ERROR;
698 }
699
700 /* Get the number of needed Tx buffers for the current frame */
701 if (FrameLength > ETH_TX_BUF_SIZE)
702 {
703 bufcount = FrameLength/ETH_TX_BUF_SIZE;
704 if (FrameLength % ETH_TX_BUF_SIZE)
705 {
706 bufcount++;
707 }
708 }
709 else
710 {
711 bufcount = 1;
712 }
713 if (bufcount == 1)
714 {
715 /* Set LAST and FIRST segment */
716 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
717 /* Set frame size */
718 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
719 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
720 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
721 /* Point to next descriptor */
722 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
723 }
724 else
725 {
726 for (i=0; i< bufcount; i++)
727 {
728 /* Clear FIRST and LAST segment bits */
729 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
730
731 if (i == 0)
732 {
733 /* Setting the first segment bit */
734 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
735 }
736
737 /* Program size */
738 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
739
740 if (i == (bufcount-1))
741 {
742 /* Setting the last segment bit */
743 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
744 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
745 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
746 }
747
748 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
749 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
750 /* point to next descriptor */
751 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
752 }
753 }
754
755 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
756 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
757 {
758 /* Clear TBUS ETHERNET DMA flag */
759 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
760 /* Resume DMA transmission*/
761 (heth->Instance)->DMATPDR = 0;
762 }
763
764 /* Set ETH HAL State to Ready */
765 heth->State = HAL_ETH_STATE_READY;
766
767 /* Process Unlocked */
768 __HAL_UNLOCK(heth);
769
770 /* Return function status */
771 return HAL_OK;
772 }
773
774 /**
775 * @brief Checks for received frames.
776 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
777 * the configuration information for ETHERNET module
778 * @retval HAL status
779 */
780 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
781 {
782 uint32_t framelength = 0;
783
784 /* Process Locked */
785 __HAL_LOCK(heth);
786
787 /* Check the ETH state to BUSY */
788 heth->State = HAL_ETH_STATE_BUSY;
789
790 /* Check if segment is not owned by DMA */
791 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
792 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
793 {
794 /* Check if last segment */
795 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
796 {
797 /* increment segment count */
798 (heth->RxFrameInfos).SegCount++;
799
800 /* Check if last segment is first segment: one segment contains the frame */
801 if ((heth->RxFrameInfos).SegCount == 1)
802 {
803 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
804 }
805
806 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
807
808 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
809 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
810 heth->RxFrameInfos.length = framelength;
811
812 /* Get the address of the buffer start address */
813 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
814 /* point to next descriptor */
815 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
816
817 /* Set HAL State to Ready */
818 heth->State = HAL_ETH_STATE_READY;
819
820 /* Process Unlocked */
821 __HAL_UNLOCK(heth);
822
823 /* Return function status */
824 return HAL_OK;
825 }
826 /* Check if first segment */
827 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
828 {
829 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
830 (heth->RxFrameInfos).LSRxDesc = NULL;
831 (heth->RxFrameInfos).SegCount = 1;
832 /* Point to next descriptor */
833 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
834 }
835 /* Check if intermediate segment */
836 else
837 {
838 (heth->RxFrameInfos).SegCount++;
839 /* Point to next descriptor */
840 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
841 }
842 }
843
844 /* Set ETH HAL State to Ready */
845 heth->State = HAL_ETH_STATE_READY;
846
847 /* Process Unlocked */
848 __HAL_UNLOCK(heth);
849
850 /* Return function status */
851 return HAL_ERROR;
852 }
853
854 /**
855 * @brief Gets the Received frame in interrupt mode.
856 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
857 * the configuration information for ETHERNET module
858 * @retval HAL status
859 */
860 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
861 {
862 uint32_t descriptorscancounter = 0;
863
864 /* Process Locked */
865 __HAL_LOCK(heth);
866
867 /* Set ETH HAL State to BUSY */
868 heth->State = HAL_ETH_STATE_BUSY;
869
870 /* Scan descriptors owned by CPU */
871 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
872 {
873 /* Just for security */
874 descriptorscancounter++;
875
876 /* Check if first segment in frame */
877 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
878 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
879 {
880 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
881 heth->RxFrameInfos.SegCount = 1;
882 /* Point to next descriptor */
883 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
884 }
885 /* Check if intermediate segment */
886 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
887 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
888 {
889 /* Increment segment count */
890 (heth->RxFrameInfos.SegCount)++;
891 /* Point to next descriptor */
892 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
893 }
894 /* Should be last segment */
895 else
896 {
897 /* Last segment */
898 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
899
900 /* Increment segment count */
901 (heth->RxFrameInfos.SegCount)++;
902
903 /* Check if last segment is first segment: one segment contains the frame */
904 if ((heth->RxFrameInfos.SegCount) == 1)
905 {
906 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
907 }
908
909 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
910 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
911
912 /* Get the address of the buffer start address */
913 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
914
915 /* Point to next descriptor */
916 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
917
918 /* Set HAL State to Ready */
919 heth->State = HAL_ETH_STATE_READY;
920
921 /* Process Unlocked */
922 __HAL_UNLOCK(heth);
923
924 /* Return function status */
925 return HAL_OK;
926 }
927 }
928
929 /* Set HAL State to Ready */
930 heth->State = HAL_ETH_STATE_READY;
931
932 /* Process Unlocked */
933 __HAL_UNLOCK(heth);
934
935 /* Return function status */
936 return HAL_ERROR;
937 }
938
939 /**
940 * @brief This function handles ETH interrupt request.
941 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
942 * the configuration information for ETHERNET module
943 * @retval HAL status
944 */
945 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
946 {
947 /* Frame received */
948 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
949 {
950 /* Receive complete callback */
951 HAL_ETH_RxCpltCallback(heth);
952
953 /* Clear the Eth DMA Rx IT pending bits */
954 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
955
956 /* Set HAL State to Ready */
957 heth->State = HAL_ETH_STATE_READY;
958
959 /* Process Unlocked */
960 __HAL_UNLOCK(heth);
961
962 }
963 /* Frame transmitted */
964 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
965 {
966 /* Transfer complete callback */
967 HAL_ETH_TxCpltCallback(heth);
968
969 /* Clear the Eth DMA Tx IT pending bits */
970 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
971
972 /* Set HAL State to Ready */
973 heth->State = HAL_ETH_STATE_READY;
974
975 /* Process Unlocked */
976 __HAL_UNLOCK(heth);
977 }
978
979 /* Clear the interrupt flags */
980 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
981
982 /* ETH DMA Error */
983 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
984 {
985 /* Ethernet Error callback */
986 HAL_ETH_ErrorCallback(heth);
987
988 /* Clear the interrupt flags */
989 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
990
991 /* Set HAL State to Ready */
992 heth->State = HAL_ETH_STATE_READY;
993
994 /* Process Unlocked */
995 __HAL_UNLOCK(heth);
996 }
997 }
998
999 /**
1000 * @brief Tx Transfer completed callbacks.
1001 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1002 * the configuration information for ETHERNET module
1003 * @retval None
1004 */
1005 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
1006 {
1007 /* Prevent unused argument(s) compilation warning */
1008 UNUSED(heth);
1009
1010 /* NOTE : This function Should not be modified, when the callback is needed,
1011 the HAL_ETH_TxCpltCallback could be implemented in the user file
1012 */
1013 }
1014
1015 /**
1016 * @brief Rx Transfer completed callbacks.
1017 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1018 * the configuration information for ETHERNET module
1019 * @retval None
1020 */
1021 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
1022 {
1023 /* Prevent unused argument(s) compilation warning */
1024 UNUSED(heth);
1025
1026 /* NOTE : This function Should not be modified, when the callback is needed,
1027 the HAL_ETH_TxCpltCallback could be implemented in the user file
1028 */
1029 }
1030
1031 /**
1032 * @brief Ethernet transfer error callbacks
1033 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1034 * the configuration information for ETHERNET module
1035 * @retval None
1036 */
1037 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
1038 {
1039 /* Prevent unused argument(s) compilation warning */
1040 UNUSED(heth);
1041
1042 /* NOTE : This function Should not be modified, when the callback is needed,
1043 the HAL_ETH_TxCpltCallback could be implemented in the user file
1044 */
1045 }
1046
1047 /**
1048 * @brief Reads a PHY register
1049 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1050 * the configuration information for ETHERNET module
1051 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
1052 * This parameter can be one of the following values:
1053 * PHY_BCR: Transceiver Basic Control Register,
1054 * PHY_BSR: Transceiver Basic Status Register.
1055 * More PHY register could be read depending on the used PHY
1056 * @param RegValue: PHY register value
1057 * @retval HAL status
1058 */
1059 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
1060 {
1061 uint32_t tmpreg = 0;
1062 uint32_t tickstart = 0;
1063
1064 /* Check parameters */
1065 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1066
1067 /* Check the ETH peripheral state */
1068 if(heth->State == HAL_ETH_STATE_BUSY_RD)
1069 {
1070 return HAL_BUSY;
1071 }
1072 /* Set ETH HAL State to BUSY_RD */
1073 heth->State = HAL_ETH_STATE_BUSY_RD;
1074
1075 /* Get the ETHERNET MACMIIAR value */
1076 tmpreg = heth->Instance->MACMIIAR;
1077
1078 /* Keep only the CSR Clock Range CR[2:0] bits value */
1079 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
1080
1081 /* Prepare the MII address register value */
1082 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1083 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1084 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
1085 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1086
1087 /* Write the result value into the MII Address register */
1088 heth->Instance->MACMIIAR = tmpreg;
1089
1090 /* Get tick */
1091 tickstart = HAL_GetTick();
1092
1093 /* Check for the Busy flag */
1094 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1095 {
1096 /* Check for the Timeout */
1097 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
1098 {
1099 heth->State= HAL_ETH_STATE_READY;
1100
1101 /* Process Unlocked */
1102 __HAL_UNLOCK(heth);
1103
1104 return HAL_TIMEOUT;
1105 }
1106
1107 tmpreg = heth->Instance->MACMIIAR;
1108 }
1109
1110 /* Get MACMIIDR value */
1111 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
1112
1113 /* Set ETH HAL State to READY */
1114 heth->State = HAL_ETH_STATE_READY;
1115
1116 /* Return function status */
1117 return HAL_OK;
1118 }
1119
1120 /**
1121 * @brief Writes to a PHY register.
1122 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1123 * the configuration information for ETHERNET module
1124 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
1125 * This parameter can be one of the following values:
1126 * PHY_BCR: Transceiver Control Register.
1127 * More PHY register could be written depending on the used PHY
1128 * @param RegValue: the value to write
1129 * @retval HAL status
1130 */
1131 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
1132 {
1133 uint32_t tmpreg = 0;
1134 uint32_t tickstart = 0;
1135
1136 /* Check parameters */
1137 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1138
1139 /* Check the ETH peripheral state */
1140 if(heth->State == HAL_ETH_STATE_BUSY_WR)
1141 {
1142 return HAL_BUSY;
1143 }
1144 /* Set ETH HAL State to BUSY_WR */
1145 heth->State = HAL_ETH_STATE_BUSY_WR;
1146
1147 /* Get the ETHERNET MACMIIAR value */
1148 tmpreg = heth->Instance->MACMIIAR;
1149
1150 /* Keep only the CSR Clock Range CR[2:0] bits value */
1151 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
1152
1153 /* Prepare the MII register address value */
1154 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1155 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1156 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
1157 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1158
1159 /* Give the value to the MII data register */
1160 heth->Instance->MACMIIDR = (uint16_t)RegValue;
1161
1162 /* Write the result value into the MII Address register */
1163 heth->Instance->MACMIIAR = tmpreg;
1164
1165 /* Get tick */
1166 tickstart = HAL_GetTick();
1167
1168 /* Check for the Busy flag */
1169 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1170 {
1171 /* Check for the Timeout */
1172 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
1173 {
1174 heth->State= HAL_ETH_STATE_READY;
1175
1176 /* Process Unlocked */
1177 __HAL_UNLOCK(heth);
1178
1179 return HAL_TIMEOUT;
1180 }
1181
1182 tmpreg = heth->Instance->MACMIIAR;
1183 }
1184
1185 /* Set ETH HAL State to READY */
1186 heth->State = HAL_ETH_STATE_READY;
1187
1188 /* Return function status */
1189 return HAL_OK;
1190 }
1191
1192 /**
1193 * @}
1194 */
1195
1196 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
1197 * @brief Peripheral Control functions
1198 *
1199 @verbatim
1200 ===============================================================================
1201 ##### Peripheral Control functions #####
1202 ===============================================================================
1203 [..] This section provides functions allowing to:
1204 (+) Enable MAC and DMA transmission and reception.
1205 HAL_ETH_Start();
1206 (+) Disable MAC and DMA transmission and reception.
1207 HAL_ETH_Stop();
1208 (+) Set the MAC configuration in runtime mode
1209 HAL_ETH_ConfigMAC();
1210 (+) Set the DMA configuration in runtime mode
1211 HAL_ETH_ConfigDMA();
1212
1213 @endverbatim
1214 * @{
1215 */
1216
1217 /**
1218 * @brief Enables Ethernet MAC and DMA reception/transmission
1219 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1220 * the configuration information for ETHERNET module
1221 * @retval HAL status
1222 */
1223 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
1224 {
1225 /* Process Locked */
1226 __HAL_LOCK(heth);
1227
1228 /* Set the ETH peripheral state to BUSY */
1229 heth->State = HAL_ETH_STATE_BUSY;
1230
1231 /* Enable transmit state machine of the MAC for transmission on the MII */
1232 ETH_MACTransmissionEnable(heth);
1233
1234 /* Enable receive state machine of the MAC for reception from the MII */
1235 ETH_MACReceptionEnable(heth);
1236
1237 /* Flush Transmit FIFO */
1238 ETH_FlushTransmitFIFO(heth);
1239
1240 /* Start DMA transmission */
1241 ETH_DMATransmissionEnable(heth);
1242
1243 /* Start DMA reception */
1244 ETH_DMAReceptionEnable(heth);
1245
1246 /* Set the ETH state to READY*/
1247 heth->State= HAL_ETH_STATE_READY;
1248
1249 /* Process Unlocked */
1250 __HAL_UNLOCK(heth);
1251
1252 /* Return function status */
1253 return HAL_OK;
1254 }
1255
1256 /**
1257 * @brief Stop Ethernet MAC and DMA reception/transmission
1258 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1259 * the configuration information for ETHERNET module
1260 * @retval HAL status
1261 */
1262 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
1263 {
1264 /* Process Locked */
1265 __HAL_LOCK(heth);
1266
1267 /* Set the ETH peripheral state to BUSY */
1268 heth->State = HAL_ETH_STATE_BUSY;
1269
1270 /* Stop DMA transmission */
1271 ETH_DMATransmissionDisable(heth);
1272
1273 /* Stop DMA reception */
1274 ETH_DMAReceptionDisable(heth);
1275
1276 /* Disable receive state machine of the MAC for reception from the MII */
1277 ETH_MACReceptionDisable(heth);
1278
1279 /* Flush Transmit FIFO */
1280 ETH_FlushTransmitFIFO(heth);
1281
1282 /* Disable transmit state machine of the MAC for transmission on the MII */
1283 ETH_MACTransmissionDisable(heth);
1284
1285 /* Set the ETH state*/
1286 heth->State = HAL_ETH_STATE_READY;
1287
1288 /* Process Unlocked */
1289 __HAL_UNLOCK(heth);
1290
1291 /* Return function status */
1292 return HAL_OK;
1293 }
1294
1295 /**
1296 * @brief Set ETH MAC Configuration.
1297 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1298 * the configuration information for ETHERNET module
1299 * @param macconf: MAC Configuration structure
1300 * @retval HAL status
1301 */
1302 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
1303 {
1304 uint32_t tmpreg = 0;
1305
1306 /* Process Locked */
1307 __HAL_LOCK(heth);
1308
1309 /* Set the ETH peripheral state to BUSY */
1310 heth->State= HAL_ETH_STATE_BUSY;
1311
1312 assert_param(IS_ETH_SPEED(heth->Init.Speed));
1313 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
1314
1315 if (macconf != NULL)
1316 {
1317 /* Check the parameters */
1318 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
1319 assert_param(IS_ETH_JABBER(macconf->Jabber));
1320 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
1321 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
1322 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
1323 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
1324 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
1325 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
1326 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
1327 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
1328 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
1329 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
1330 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
1331 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
1332 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
1333 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
1334 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
1335 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
1336 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
1337 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
1338 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
1339 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
1340 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
1341 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
1342 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
1343 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
1344 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
1345
1346 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1347 /* Get the ETHERNET MACCR value */
1348 tmpreg = (heth->Instance)->MACCR;
1349 /* Clear WD, PCE, PS, TE and RE bits */
1350 tmpreg &= ETH_MACCR_CLEAR_MASK;
1351
1352 tmpreg |= (uint32_t)(macconf->Watchdog |
1353 macconf->Jabber |
1354 macconf->InterFrameGap |
1355 macconf->CarrierSense |
1356 (heth->Init).Speed |
1357 macconf->ReceiveOwn |
1358 macconf->LoopbackMode |
1359 (heth->Init).DuplexMode |
1360 macconf->ChecksumOffload |
1361 macconf->RetryTransmission |
1362 macconf->AutomaticPadCRCStrip |
1363 macconf->BackOffLimit |
1364 macconf->DeferralCheck);
1365
1366 /* Write to ETHERNET MACCR */
1367 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1368
1369 /* Wait until the write operation will be taken into account :
1370 at least four TX_CLK/RX_CLK clock cycles */
1371 tmpreg = (heth->Instance)->MACCR;
1372 HAL_Delay(ETH_REG_WRITE_DELAY);
1373 (heth->Instance)->MACCR = tmpreg;
1374
1375 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1376 /* Write to ETHERNET MACFFR */
1377 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
1378 macconf->SourceAddrFilter |
1379 macconf->PassControlFrames |
1380 macconf->BroadcastFramesReception |
1381 macconf->DestinationAddrFilter |
1382 macconf->PromiscuousMode |
1383 macconf->MulticastFramesFilter |
1384 macconf->UnicastFramesFilter);
1385
1386 /* Wait until the write operation will be taken into account :
1387 at least four TX_CLK/RX_CLK clock cycles */
1388 tmpreg = (heth->Instance)->MACFFR;
1389 HAL_Delay(ETH_REG_WRITE_DELAY);
1390 (heth->Instance)->MACFFR = tmpreg;
1391
1392 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
1393 /* Write to ETHERNET MACHTHR */
1394 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
1395
1396 /* Write to ETHERNET MACHTLR */
1397 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
1398 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
1399
1400 /* Get the ETHERNET MACFCR value */
1401 tmpreg = (heth->Instance)->MACFCR;
1402 /* Clear xx bits */
1403 tmpreg &= ETH_MACFCR_CLEAR_MASK;
1404
1405 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
1406 macconf->ZeroQuantaPause |
1407 macconf->PauseLowThreshold |
1408 macconf->UnicastPauseFrameDetect |
1409 macconf->ReceiveFlowControl |
1410 macconf->TransmitFlowControl);
1411
1412 /* Write to ETHERNET MACFCR */
1413 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
1414
1415 /* Wait until the write operation will be taken into account :
1416 at least four TX_CLK/RX_CLK clock cycles */
1417 tmpreg = (heth->Instance)->MACFCR;
1418 HAL_Delay(ETH_REG_WRITE_DELAY);
1419 (heth->Instance)->MACFCR = tmpreg;
1420
1421 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
1422 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
1423 macconf->VLANTagIdentifier);
1424
1425 /* Wait until the write operation will be taken into account :
1426 at least four TX_CLK/RX_CLK clock cycles */
1427 tmpreg = (heth->Instance)->MACVLANTR;
1428 HAL_Delay(ETH_REG_WRITE_DELAY);
1429 (heth->Instance)->MACVLANTR = tmpreg;
1430 }
1431 else /* macconf == NULL : here we just configure Speed and Duplex mode */
1432 {
1433 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1434 /* Get the ETHERNET MACCR value */
1435 tmpreg = (heth->Instance)->MACCR;
1436
1437 /* Clear FES and DM bits */
1438 tmpreg &= ~((uint32_t)0x00004800);
1439
1440 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
1441
1442 /* Write to ETHERNET MACCR */
1443 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1444
1445 /* Wait until the write operation will be taken into account:
1446 at least four TX_CLK/RX_CLK clock cycles */
1447 tmpreg = (heth->Instance)->MACCR;
1448 HAL_Delay(ETH_REG_WRITE_DELAY);
1449 (heth->Instance)->MACCR = tmpreg;
1450 }
1451
1452 /* Set the ETH state to Ready */
1453 heth->State= HAL_ETH_STATE_READY;
1454
1455 /* Process Unlocked */
1456 __HAL_UNLOCK(heth);
1457
1458 /* Return function status */
1459 return HAL_OK;
1460 }
1461
1462 /**
1463 * @brief Sets ETH DMA Configuration.
1464 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1465 * the configuration information for ETHERNET module
1466 * @param dmaconf: DMA Configuration structure
1467 * @retval HAL status
1468 */
1469 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
1470 {
1471 uint32_t tmpreg = 0;
1472
1473 /* Process Locked */
1474 __HAL_LOCK(heth);
1475
1476 /* Set the ETH peripheral state to BUSY */
1477 heth->State= HAL_ETH_STATE_BUSY;
1478
1479 /* Check parameters */
1480 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
1481 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
1482 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
1483 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
1484 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
1485 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
1486 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
1487 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
1488 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
1489 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
1490 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
1491 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
1492 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
1493 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
1494 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
1495 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
1496
1497 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
1498 /* Get the ETHERNET DMAOMR value */
1499 tmpreg = (heth->Instance)->DMAOMR;
1500 /* Clear xx bits */
1501 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
1502
1503 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
1504 dmaconf->ReceiveStoreForward |
1505 dmaconf->FlushReceivedFrame |
1506 dmaconf->TransmitStoreForward |
1507 dmaconf->TransmitThresholdControl |
1508 dmaconf->ForwardErrorFrames |
1509 dmaconf->ForwardUndersizedGoodFrames |
1510 dmaconf->ReceiveThresholdControl |
1511 dmaconf->SecondFrameOperate);
1512
1513 /* Write to ETHERNET DMAOMR */
1514 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
1515
1516 /* Wait until the write operation will be taken into account:
1517 at least four TX_CLK/RX_CLK clock cycles */
1518 tmpreg = (heth->Instance)->DMAOMR;
1519 HAL_Delay(ETH_REG_WRITE_DELAY);
1520 (heth->Instance)->DMAOMR = tmpreg;
1521
1522 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
1523 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
1524 dmaconf->FixedBurst |
1525 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1526 dmaconf->TxDMABurstLength |
1527 dmaconf->EnhancedDescriptorFormat |
1528 (dmaconf->DescriptorSkipLength << 2) |
1529 dmaconf->DMAArbitration |
1530 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1531
1532 /* Wait until the write operation will be taken into account:
1533 at least four TX_CLK/RX_CLK clock cycles */
1534 tmpreg = (heth->Instance)->DMABMR;
1535 HAL_Delay(ETH_REG_WRITE_DELAY);
1536 (heth->Instance)->DMABMR = tmpreg;
1537
1538 /* Set the ETH state to Ready */
1539 heth->State= HAL_ETH_STATE_READY;
1540
1541 /* Process Unlocked */
1542 __HAL_UNLOCK(heth);
1543
1544 /* Return function status */
1545 return HAL_OK;
1546 }
1547
1548 /**
1549 * @}
1550 */
1551
1552 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
1553 * @brief Peripheral State functions
1554 *
1555 @verbatim
1556 ===============================================================================
1557 ##### Peripheral State functions #####
1558 ===============================================================================
1559 [..]
1560 This subsection permits to get in run-time the status of the peripheral
1561 and the data flow.
1562 (+) Get the ETH handle state:
1563 HAL_ETH_GetState();
1564
1565
1566 @endverbatim
1567 * @{
1568 */
1569
1570 /**
1571 * @brief Return the ETH HAL state
1572 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1573 * the configuration information for ETHERNET module
1574 * @retval HAL state
1575 */
1576 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
1577 {
1578 /* Return ETH state */
1579 return heth->State;
1580 }
1581
1582 /**
1583 * @}
1584 */
1585
1586 /**
1587 * @}
1588 */
1589
1590 /** @addtogroup ETH_Private_Functions
1591 * @{
1592 */
1593
1594 /**
1595 * @brief Configures Ethernet MAC and DMA with default parameters.
1596 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1597 * the configuration information for ETHERNET module
1598 * @param err: Ethernet Init error
1599 * @retval HAL status
1600 */
1601 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
1602 {
1603 ETH_MACInitTypeDef macinit;
1604 ETH_DMAInitTypeDef dmainit;
1605 uint32_t tmpreg = 0;
1606
1607 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
1608 {
1609 /* Set Ethernet duplex mode to Full-duplex */
1610 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
1611
1612 /* Set Ethernet speed to 100M */
1613 (heth->Init).Speed = ETH_SPEED_100M;
1614 }
1615
1616 /* Ethernet MAC default initialization **************************************/
1617 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
1618 macinit.Jabber = ETH_JABBER_ENABLE;
1619 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
1620 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
1621 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
1622 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
1623 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
1624 {
1625 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
1626 }
1627 else
1628 {
1629 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
1630 }
1631 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
1632 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
1633 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
1634 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
1635 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
1636 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
1637 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
1638 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
1639 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
1640 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
1641 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
1642 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
1643 macinit.HashTableHigh = 0x0;
1644 macinit.HashTableLow = 0x0;
1645 macinit.PauseTime = 0x0;
1646 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
1647 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
1648 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
1649 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
1650 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
1651 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
1652 macinit.VLANTagIdentifier = 0x0;
1653
1654 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1655 /* Get the ETHERNET MACCR value */
1656 tmpreg = (heth->Instance)->MACCR;
1657 /* Clear WD, PCE, PS, TE and RE bits */
1658 tmpreg &= ETH_MACCR_CLEAR_MASK;
1659 /* Set the WD bit according to ETH Watchdog value */
1660 /* Set the JD: bit according to ETH Jabber value */
1661 /* Set the IFG bit according to ETH InterFrameGap value */
1662 /* Set the DCRS bit according to ETH CarrierSense value */
1663 /* Set the FES bit according to ETH Speed value */
1664 /* Set the DO bit according to ETH ReceiveOwn value */
1665 /* Set the LM bit according to ETH LoopbackMode value */
1666 /* Set the DM bit according to ETH Mode value */
1667 /* Set the IPCO bit according to ETH ChecksumOffload value */
1668 /* Set the DR bit according to ETH RetryTransmission value */
1669 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
1670 /* Set the BL bit according to ETH BackOffLimit value */
1671 /* Set the DC bit according to ETH DeferralCheck value */
1672 tmpreg |= (uint32_t)(macinit.Watchdog |
1673 macinit.Jabber |
1674 macinit.InterFrameGap |
1675 macinit.CarrierSense |
1676 (heth->Init).Speed |
1677 macinit.ReceiveOwn |
1678 macinit.LoopbackMode |
1679 (heth->Init).DuplexMode |
1680 macinit.ChecksumOffload |
1681 macinit.RetryTransmission |
1682 macinit.AutomaticPadCRCStrip |
1683 macinit.BackOffLimit |
1684 macinit.DeferralCheck);
1685
1686 /* Write to ETHERNET MACCR */
1687 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1688
1689 /* Wait until the write operation will be taken into account:
1690 at least four TX_CLK/RX_CLK clock cycles */
1691 tmpreg = (heth->Instance)->MACCR;
1692 HAL_Delay(ETH_REG_WRITE_DELAY);
1693 (heth->Instance)->MACCR = tmpreg;
1694
1695 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1696 /* Set the RA bit according to ETH ReceiveAll value */
1697 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
1698 /* Set the PCF bit according to ETH PassControlFrames value */
1699 /* Set the DBF bit according to ETH BroadcastFramesReception value */
1700 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
1701 /* Set the PR bit according to ETH PromiscuousMode value */
1702 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
1703 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
1704 /* Write to ETHERNET MACFFR */
1705 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
1706 macinit.SourceAddrFilter |
1707 macinit.PassControlFrames |
1708 macinit.BroadcastFramesReception |
1709 macinit.DestinationAddrFilter |
1710 macinit.PromiscuousMode |
1711 macinit.MulticastFramesFilter |
1712 macinit.UnicastFramesFilter);
1713
1714 /* Wait until the write operation will be taken into account:
1715 at least four TX_CLK/RX_CLK clock cycles */
1716 tmpreg = (heth->Instance)->MACFFR;
1717 HAL_Delay(ETH_REG_WRITE_DELAY);
1718 (heth->Instance)->MACFFR = tmpreg;
1719
1720 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
1721 /* Write to ETHERNET MACHTHR */
1722 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
1723
1724 /* Write to ETHERNET MACHTLR */
1725 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
1726 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
1727
1728 /* Get the ETHERNET MACFCR value */
1729 tmpreg = (heth->Instance)->MACFCR;
1730 /* Clear xx bits */
1731 tmpreg &= ETH_MACFCR_CLEAR_MASK;
1732
1733 /* Set the PT bit according to ETH PauseTime value */
1734 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
1735 /* Set the PLT bit according to ETH PauseLowThreshold value */
1736 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
1737 /* Set the RFE bit according to ETH ReceiveFlowControl value */
1738 /* Set the TFE bit according to ETH TransmitFlowControl value */
1739 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
1740 macinit.ZeroQuantaPause |
1741 macinit.PauseLowThreshold |
1742 macinit.UnicastPauseFrameDetect |
1743 macinit.ReceiveFlowControl |
1744 macinit.TransmitFlowControl);
1745
1746 /* Write to ETHERNET MACFCR */
1747 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
1748
1749 /* Wait until the write operation will be taken into account:
1750 at least four TX_CLK/RX_CLK clock cycles */
1751 tmpreg = (heth->Instance)->MACFCR;
1752 HAL_Delay(ETH_REG_WRITE_DELAY);
1753 (heth->Instance)->MACFCR = tmpreg;
1754
1755 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
1756 /* Set the ETV bit according to ETH VLANTagComparison value */
1757 /* Set the VL bit according to ETH VLANTagIdentifier value */
1758 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
1759 macinit.VLANTagIdentifier);
1760
1761 /* Wait until the write operation will be taken into account:
1762 at least four TX_CLK/RX_CLK clock cycles */
1763 tmpreg = (heth->Instance)->MACVLANTR;
1764 HAL_Delay(ETH_REG_WRITE_DELAY);
1765 (heth->Instance)->MACVLANTR = tmpreg;
1766
1767 /* Ethernet DMA default initialization ************************************/
1768 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
1769 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
1770 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
1771 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
1772 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
1773 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
1774 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
1775 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
1776 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
1777 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
1778 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
1779 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
1780 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
1781 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
1782 dmainit.DescriptorSkipLength = 0x0;
1783 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
1784
1785 /* Get the ETHERNET DMAOMR value */
1786 tmpreg = (heth->Instance)->DMAOMR;
1787 /* Clear xx bits */
1788 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
1789
1790 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
1791 /* Set the RSF bit according to ETH ReceiveStoreForward value */
1792 /* Set the DFF bit according to ETH FlushReceivedFrame value */
1793 /* Set the TSF bit according to ETH TransmitStoreForward value */
1794 /* Set the TTC bit according to ETH TransmitThresholdControl value */
1795 /* Set the FEF bit according to ETH ForwardErrorFrames value */
1796 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
1797 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
1798 /* Set the OSF bit according to ETH SecondFrameOperate value */
1799 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
1800 dmainit.ReceiveStoreForward |
1801 dmainit.FlushReceivedFrame |
1802 dmainit.TransmitStoreForward |
1803 dmainit.TransmitThresholdControl |
1804 dmainit.ForwardErrorFrames |
1805 dmainit.ForwardUndersizedGoodFrames |
1806 dmainit.ReceiveThresholdControl |
1807 dmainit.SecondFrameOperate);
1808
1809 /* Write to ETHERNET DMAOMR */
1810 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
1811
1812 /* Wait until the write operation will be taken into account:
1813 at least four TX_CLK/RX_CLK clock cycles */
1814 tmpreg = (heth->Instance)->DMAOMR;
1815 HAL_Delay(ETH_REG_WRITE_DELAY);
1816 (heth->Instance)->DMAOMR = tmpreg;
1817
1818 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
1819 /* Set the AAL bit according to ETH AddressAlignedBeats value */
1820 /* Set the FB bit according to ETH FixedBurst value */
1821 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
1822 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
1823 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
1824 /* Set the DSL bit according to ETH DesciptorSkipLength value */
1825 /* Set the PR and DA bits according to ETH DMAArbitration value */
1826 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
1827 dmainit.FixedBurst |
1828 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1829 dmainit.TxDMABurstLength |
1830 dmainit.EnhancedDescriptorFormat |
1831 (dmainit.DescriptorSkipLength << 2) |
1832 dmainit.DMAArbitration |
1833 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1834
1835 /* Wait until the write operation will be taken into account:
1836 at least four TX_CLK/RX_CLK clock cycles */
1837 tmpreg = (heth->Instance)->DMABMR;
1838 HAL_Delay(ETH_REG_WRITE_DELAY);
1839 (heth->Instance)->DMABMR = tmpreg;
1840
1841 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
1842 {
1843 /* Enable the Ethernet Rx Interrupt */
1844 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
1845 }
1846
1847 /* Initialize MAC address in ethernet MAC */
1848 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
1849 }
1850
1851 /**
1852 * @brief Configures the selected MAC address.
1853 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1854 * the configuration information for ETHERNET module
1855 * @param MacAddr: The MAC address to configure
1856 * This parameter can be one of the following values:
1857 * @arg ETH_MAC_Address0: MAC Address0
1858 * @arg ETH_MAC_Address1: MAC Address1
1859 * @arg ETH_MAC_Address2: MAC Address2
1860 * @arg ETH_MAC_Address3: MAC Address3
1861 * @param Addr: Pointer to MAC address buffer data (6 bytes)
1862 * @retval HAL status
1863 */
1864 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
1865 {
1866 uint32_t tmpreg;
1867
1868 /* Check the parameters */
1869 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1870
1871 /* Calculate the selected MAC address high register */
1872 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
1873 /* Load the selected MAC address high register */
1874 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
1875 /* Calculate the selected MAC address low register */
1876 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
1877
1878 /* Load the selected MAC address low register */
1879 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
1880 }
1881
1882 /**
1883 * @brief Enables the MAC transmission.
1884 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1885 * the configuration information for ETHERNET module
1886 * @retval None
1887 */
1888 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
1889 {
1890 __IO uint32_t tmpreg = 0;
1891
1892 /* Enable the MAC transmission */
1893 (heth->Instance)->MACCR |= ETH_MACCR_TE;
1894
1895 /* Wait until the write operation will be taken into account:
1896 at least four TX_CLK/RX_CLK clock cycles */
1897 tmpreg = (heth->Instance)->MACCR;
1898 HAL_Delay(ETH_REG_WRITE_DELAY);
1899 (heth->Instance)->MACCR = tmpreg;
1900 }
1901
1902 /**
1903 * @brief Disables the MAC transmission.
1904 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1905 * the configuration information for ETHERNET module
1906 * @retval None
1907 */
1908 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
1909 {
1910 __IO uint32_t tmpreg = 0;
1911
1912 /* Disable the MAC transmission */
1913 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
1914
1915 /* Wait until the write operation will be taken into account:
1916 at least four TX_CLK/RX_CLK clock cycles */
1917 tmpreg = (heth->Instance)->MACCR;
1918 HAL_Delay(ETH_REG_WRITE_DELAY);
1919 (heth->Instance)->MACCR = tmpreg;
1920 }
1921
1922 /**
1923 * @brief Enables the MAC reception.
1924 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1925 * the configuration information for ETHERNET module
1926 * @retval None
1927 */
1928 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
1929 {
1930 __IO uint32_t tmpreg = 0;
1931
1932 /* Enable the MAC reception */
1933 (heth->Instance)->MACCR |= ETH_MACCR_RE;
1934
1935 /* Wait until the write operation will be taken into account:
1936 at least four TX_CLK/RX_CLK clock cycles */
1937 tmpreg = (heth->Instance)->MACCR;
1938 HAL_Delay(ETH_REG_WRITE_DELAY);
1939 (heth->Instance)->MACCR = tmpreg;
1940 }
1941
1942 /**
1943 * @brief Disables the MAC reception.
1944 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1945 * the configuration information for ETHERNET module
1946 * @retval None
1947 */
1948 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
1949 {
1950 __IO uint32_t tmpreg = 0;
1951
1952 /* Disable the MAC reception */
1953 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
1954
1955 /* Wait until the write operation will be taken into account:
1956 at least four TX_CLK/RX_CLK clock cycles */
1957 tmpreg = (heth->Instance)->MACCR;
1958 HAL_Delay(ETH_REG_WRITE_DELAY);
1959 (heth->Instance)->MACCR = tmpreg;
1960 }
1961
1962 /**
1963 * @brief Enables the DMA transmission.
1964 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1965 * the configuration information for ETHERNET module
1966 * @retval None
1967 */
1968 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
1969 {
1970 /* Enable the DMA transmission */
1971 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
1972 }
1973
1974 /**
1975 * @brief Disables the DMA transmission.
1976 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1977 * the configuration information for ETHERNET module
1978 * @retval None
1979 */
1980 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
1981 {
1982 /* Disable the DMA transmission */
1983 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
1984 }
1985
1986 /**
1987 * @brief Enables the DMA reception.
1988 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1989 * the configuration information for ETHERNET module
1990 * @retval None
1991 */
1992 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
1993 {
1994 /* Enable the DMA reception */
1995 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
1996 }
1997
1998 /**
1999 * @brief Disables the DMA reception.
2000 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2001 * the configuration information for ETHERNET module
2002 * @retval None
2003 */
2004 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
2005 {
2006 /* Disable the DMA reception */
2007 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
2008 }
2009
2010 /**
2011 * @brief Clears the ETHERNET transmit FIFO.
2012 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2013 * the configuration information for ETHERNET module
2014 * @retval None
2015 */
2016 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
2017 {
2018 __IO uint32_t tmpreg = 0;
2019
2020 /* Set the Flush Transmit FIFO bit */
2021 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
2022
2023 /* Wait until the write operation will be taken into account:
2024 at least four TX_CLK/RX_CLK clock cycles */
2025 tmpreg = (heth->Instance)->DMAOMR;
2026 HAL_Delay(ETH_REG_WRITE_DELAY);
2027 (heth->Instance)->DMAOMR = tmpreg;
2028 }
2029
2030 /**
2031 * @}
2032 */
2033
2034 #endif /* HAL_ETH_MODULE_ENABLED */
2035 /**
2036 * @}
2037 */
2038
2039 /**
2040 * @}
2041 */
2042
2043 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)