repositories / mTask.git / blob
? search:


5cec4d961e647ae89ec663ba1bf10453ebaa8032
[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_flash_ex.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief Extended FLASH HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the FLASH extension peripheral:
10 * + Extended programming operations functions
11 *
12 @verbatim
13 ==============================================================================
14 ##### Flash Extension features #####
15 ==============================================================================
16
17 [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx
18 devices contains the following additional features
19
20 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
21 capability (RWW)
22 (+) Dual bank memory organization
23 (+) Dual boot mode
24
25 ##### How to use this driver #####
26 ==============================================================================
27 [..] This driver provides functions to configure and program the FLASH memory
28 of all STM32F7xx devices. It includes
29 (#) FLASH Memory Erase functions:
30 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
31 HAL_FLASH_Lock() functions
32 (++) Erase function: Erase sector, erase all sectors
33 (++) There are two modes of erase :
34 (+++) Polling Mode using HAL_FLASHEx_Erase()
35 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
36
37 (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
38 (++) Set/Reset the write protection
39 (++) Set the Read protection Level
40 (++) Set the BOR level
41 (++) Program the user Option Bytes
42
43 @endverbatim
44 ******************************************************************************
45 * @attention
46 *
47 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
48 *
49 * Redistribution and use in source and binary forms, with or without modification,
50 * are permitted provided that the following conditions are met:
51 * 1. Redistributions of source code must retain the above copyright notice,
52 * this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright notice,
54 * this list of conditions and the following disclaimer in the documentation
55 * and/or other materials provided with the distribution.
56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
57 * may be used to endorse or promote products derived from this software
58 * without specific prior written permission.
59 *
60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70 *
71 ******************************************************************************
72 */
73
74 /* Includes ------------------------------------------------------------------*/
75 #include "stm32f7xx_hal.h"
76
77 /** @addtogroup STM32F7xx_HAL_Driver
78 * @{
79 */
80
81 /** @defgroup FLASHEx FLASHEx
82 * @brief FLASH HAL Extension module driver
83 * @{
84 */
85
86 #ifdef HAL_FLASH_MODULE_ENABLED
87
88 /* Private typedef -----------------------------------------------------------*/
89 /* Private define ------------------------------------------------------------*/
90 /** @addtogroup FLASHEx_Private_Constants
91 * @{
92 */
93 #define SECTOR_MASK ((uint32_t)0xFFFFFF07)
94 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
95 /**
96 * @}
97 */
98
99 /* Private macro -------------------------------------------------------------*/
100 /* Private variables ---------------------------------------------------------*/
101 /** @addtogroup FLASHEx_Private_Variables
102 * @{
103 */
104 extern FLASH_ProcessTypeDef pFlash;
105 /**
106 * @}
107 */
108
109 /* Private function prototypes -----------------------------------------------*/
110 /** @addtogroup FLASHEx_Private_Functions
111 * @{
112 */
113 /* Option bytes control */
114 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
115 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
116 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
117 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
118 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
119 static uint32_t FLASH_OB_GetUser(void);
120 static uint32_t FLASH_OB_GetWRP(void);
121 static uint8_t FLASH_OB_GetRDP(void);
122 static uint32_t FLASH_OB_GetBOR(void);
123 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
124
125 #if defined (FLASH_OPTCR_nDBANK)
126 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
127 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
128 uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);
129 #else
130 static void FLASH_MassErase(uint8_t VoltageRange);
131 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
132 #endif /* FLASH_OPTCR_nDBANK */
133
134 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
135 /**
136 * @}
137 */
138
139 /* Exported functions --------------------------------------------------------*/
140 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
141 * @{
142 */
143
144 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
145 * @brief Extended IO operation functions
146 *
147 @verbatim
148 ===============================================================================
149 ##### Extended programming operation functions #####
150 ===============================================================================
151 [..]
152 This subsection provides a set of functions allowing to manage the Extension FLASH
153 programming operations Operations.
154
155 @endverbatim
156 * @{
157 */
158 /**
159 * @brief Perform a mass erase or erase the specified FLASH memory sectors
160 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
161 * contains the configuration information for the erasing.
162 *
163 * @param[out] SectorError: pointer to variable that
164 * contains the configuration information on faulty sector in case of error
165 * (0xFFFFFFFF means that all the sectors have been correctly erased)
166 *
167 * @retval HAL Status
168 */
169 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
170 {
171 HAL_StatusTypeDef status = HAL_ERROR;
172 uint32_t index = 0;
173
174 /* Process Locked */
175 __HAL_LOCK(&pFlash);
176
177 /* Check the parameters */
178 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
179
180 /* Wait for last operation to be completed */
181 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
182
183 if(status == HAL_OK)
184 {
185 /*Initialization of SectorError variable*/
186 *SectorError = 0xFFFFFFFFU;
187
188 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
189 {
190 /*Mass erase to be done*/
191 #if defined (FLASH_OPTCR_nDBANK)
192 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
193 #else
194 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
195 #endif /* FLASH_OPTCR_nDBANK */
196
197 /* Wait for last operation to be completed */
198 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
199
200 /* if the erase operation is completed, disable the MER Bit */
201 FLASH->CR &= (~FLASH_MER_BIT);
202 }
203 else
204 {
205 /* Check the parameters */
206 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
207
208 /* Erase by sector by sector to be done*/
209 for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
210 {
211 FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
212
213 /* Wait for last operation to be completed */
214 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
215
216 /* If the erase operation is completed, disable the SER Bit and SNB Bits */
217 CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
218
219 if(status != HAL_OK)
220 {
221 /* In case of error, stop erase procedure and return the faulty sector*/
222 *SectorError = index;
223 break;
224 }
225 }
226 }
227 }
228
229 /* Process Unlocked */
230 __HAL_UNLOCK(&pFlash);
231
232 return status;
233 }
234
235 /**
236 * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
237 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
238 * contains the configuration information for the erasing.
239 *
240 * @retval HAL Status
241 */
242 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
243 {
244 HAL_StatusTypeDef status = HAL_OK;
245
246 /* Process Locked */
247 __HAL_LOCK(&pFlash);
248
249 /* Check the parameters */
250 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
251
252 /* Enable End of FLASH Operation interrupt */
253 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
254
255 /* Enable Error source interrupt */
256 __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
257
258 /* Clear pending flags (if any) */
259 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
260 FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
261
262 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
263 {
264 /*Mass erase to be done*/
265 pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
266 #if defined (FLASH_OPTCR_nDBANK)
267 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
268 #else
269 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
270 #endif /* FLASH_OPTCR_nDBANK */
271 }
272 else
273 {
274 /* Erase by sector to be done*/
275
276 /* Check the parameters */
277 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
278
279 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
280 pFlash.NbSectorsToErase = pEraseInit->NbSectors;
281 pFlash.Sector = pEraseInit->Sector;
282 pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
283
284 /*Erase 1st sector and wait for IT*/
285 FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
286 }
287
288 return status;
289 }
290
291 /**
292 * @brief Program option bytes
293 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
294 * contains the configuration information for the programming.
295 *
296 * @retval HAL Status
297 */
298 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
299 {
300 HAL_StatusTypeDef status = HAL_ERROR;
301
302 /* Process Locked */
303 __HAL_LOCK(&pFlash);
304
305 /* Check the parameters */
306 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
307
308 /* Write protection configuration */
309 if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
310 {
311 assert_param(IS_WRPSTATE(pOBInit->WRPState));
312 if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
313 {
314 /*Enable of Write protection on the selected Sector*/
315 status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
316 }
317 else
318 {
319 /*Disable of Write protection on the selected Sector*/
320 status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
321 }
322 }
323
324 /* Read protection configuration */
325 if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
326 {
327 status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
328 }
329
330 /* USER configuration */
331 if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
332 {
333 #if defined (FLASH_OPTCR_nDBANK)
334 status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
335 pOBInit->USERConfig & OB_IWDG_SW,
336 pOBInit->USERConfig & OB_STOP_NO_RST,
337 pOBInit->USERConfig & OB_STDBY_NO_RST,
338 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
339 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
340 pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
341 pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
342 #else
343 status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
344 pOBInit->USERConfig & OB_IWDG_SW,
345 pOBInit->USERConfig & OB_STOP_NO_RST,
346 pOBInit->USERConfig & OB_STDBY_NO_RST,
347 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
348 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
349 #endif /* FLASH_OPTCR_nDBANK */
350 }
351
352 /* BOR Level configuration */
353 if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
354 {
355 status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
356 }
357
358 /* Boot 0 Address configuration */
359 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
360 {
361 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
362 }
363
364 /* Boot 1 Address configuration */
365 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
366 {
367 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
368 }
369
370 /* Process Unlocked */
371 __HAL_UNLOCK(&pFlash);
372
373 return status;
374 }
375
376 /**
377 * @brief Get the Option byte configuration
378 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
379 * contains the configuration information for the programming.
380 *
381 * @retval None
382 */
383 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
384 {
385 pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
386 OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
387
388 /*Get WRP*/
389 pOBInit->WRPSector = FLASH_OB_GetWRP();
390
391 /*Get RDP Level*/
392 pOBInit->RDPLevel = FLASH_OB_GetRDP();
393
394 /*Get USER*/
395 pOBInit->USERConfig = FLASH_OB_GetUser();
396
397 /*Get BOR Level*/
398 pOBInit->BORLevel = FLASH_OB_GetBOR();
399
400 /*Get Boot Address when Boot pin = 0 */
401 pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
402
403 /*Get Boot Address when Boot pin = 1 */
404 pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
405 }
406 /**
407 * @}
408 */
409
410 #if defined (FLASH_OPTCR_nDBANK)
411 /**
412 * @brief Full erase of FLASH memory sectors
413 * @param VoltageRange: The device voltage range which defines the erase parallelism.
414 * This parameter can be one of the following values:
415 * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
416 * the operation will be done by byte (8-bit)
417 * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
418 * the operation will be done by half word (16-bit)
419 * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
420 * the operation will be done by word (32-bit)
421 * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
422 * the operation will be done by double word (64-bit)
423 * @param Banks: Banks to be erased
424 * This parameter can be one of the following values:
425 * @arg FLASH_BANK_1: Bank1 to be erased
426 * @arg FLASH_BANK_2: Bank2 to be erased
427 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
428 *
429 * @retval HAL Status
430 */
431 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
432 {
433 /* Check the parameters */
434 assert_param(IS_VOLTAGERANGE(VoltageRange));
435 assert_param(IS_FLASH_BANK(Banks));
436
437 /* if the previous operation is completed, proceed to erase all sectors */
438 FLASH->CR &= CR_PSIZE_MASK;
439 if(Banks == FLASH_BANK_BOTH)
440 {
441 /* bank1 & bank2 will be erased*/
442 FLASH->CR |= FLASH_MER_BIT;
443 }
444 else if(Banks == FLASH_BANK_2)
445 {
446 /*Only bank2 will be erased*/
447 FLASH->CR |= FLASH_CR_MER2;
448 }
449 else
450 {
451 /*Only bank1 will be erased*/
452 FLASH->CR |= FLASH_CR_MER1;
453 }
454 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
455 /* Data synchronous Barrier (DSB) Just after the write operation
456 This will force the CPU to respect the sequence of instruction (no optimization).*/
457 __DSB();
458 }
459
460 /**
461 * @brief Erase the specified FLASH memory sector
462 * @param Sector: FLASH sector to erase
463 * The value of this parameter depend on device used within the same series
464 * @param VoltageRange: The device voltage range which defines the erase parallelism.
465 * This parameter can be one of the following values:
466 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
467 * the operation will be done by byte (8-bit)
468 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
469 * the operation will be done by half word (16-bit)
470 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
471 * the operation will be done by word (32-bit)
472 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
473 * the operation will be done by double word (64-bit)
474 *
475 * @retval None
476 */
477 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
478 {
479 uint32_t tmp_psize = 0;
480
481 /* Check the parameters */
482 assert_param(IS_FLASH_SECTOR(Sector));
483 assert_param(IS_VOLTAGERANGE(VoltageRange));
484
485 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
486 {
487 tmp_psize = FLASH_PSIZE_BYTE;
488 }
489 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
490 {
491 tmp_psize = FLASH_PSIZE_HALF_WORD;
492 }
493 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
494 {
495 tmp_psize = FLASH_PSIZE_WORD;
496 }
497 else
498 {
499 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
500 }
501
502 /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
503 if(Sector > FLASH_SECTOR_11)
504 {
505 Sector += 4;
506 }
507
508 /* If the previous operation is completed, proceed to erase the sector */
509 FLASH->CR &= CR_PSIZE_MASK;
510 FLASH->CR |= tmp_psize;
511 CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
512 FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
513 FLASH->CR |= FLASH_CR_STRT;
514
515 /* Data synchronous Barrier (DSB) Just after the write operation
516 This will force the CPU to respect the sequence of instruction (no optimization).*/
517 __DSB();
518 }
519
520 /**
521 * @brief Return the FLASH Write Protection Option Bytes value.
522 * @retval uint32_t FLASH Write Protection Option Bytes value
523 */
524 static uint32_t FLASH_OB_GetWRP(void)
525 {
526 /* Return the FLASH write protection Register value */
527 return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
528 }
529
530 /**
531 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
532 * @param Wwdg: Selects the IWDG mode
533 * This parameter can be one of the following values:
534 * @arg OB_WWDG_SW: Software WWDG selected
535 * @arg OB_WWDG_HW: Hardware WWDG selected
536 * @param Iwdg: Selects the WWDG mode
537 * This parameter can be one of the following values:
538 * @arg OB_IWDG_SW: Software IWDG selected
539 * @arg OB_IWDG_HW: Hardware IWDG selected
540 * @param Stop: Reset event when entering STOP mode.
541 * This parameter can be one of the following values:
542 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
543 * @arg OB_STOP_RST: Reset generated when entering in STOP
544 * @param Stdby: Reset event when entering Standby mode.
545 * This parameter can be one of the following values:
546 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
547 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
548 * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
549 * This parameter can be one of the following values:
550 * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
551 * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
552 * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
553 * This parameter can be one of the following values:
554 * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
555 * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
556 * @param NDBank: Flash Single Bank mode enabled.
557 * This parameter can be one of the following values:
558 * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
559 * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)
560 * @param NDBoot: Flash Dual boot mode disable.
561 * This parameter can be one of the following values:
562 * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
563 * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
564
565 * @retval HAL Status
566 */
567 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
568 uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
569 {
570 uint32_t useroptionmask = 0x00;
571 uint32_t useroptionvalue = 0x00;
572
573 HAL_StatusTypeDef status = HAL_OK;
574
575 /* Check the parameters */
576 assert_param(IS_OB_WWDG_SOURCE(Wwdg));
577 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
578 assert_param(IS_OB_STOP_SOURCE(Stop));
579 assert_param(IS_OB_STDBY_SOURCE(Stdby));
580 assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
581 assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
582 assert_param(IS_OB_NDBANK(NDBank));
583 assert_param(IS_OB_NDBOOT(NDBoot));
584
585 /* Wait for last operation to be completed */
586 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
587
588 if(status == HAL_OK)
589 {
590 useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
591 FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
592 FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
593
594 useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
595
596 /* Update User Option Byte */
597 MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
598 }
599
600 return status;
601 }
602
603 /**
604 * @brief Return the FLASH User Option Byte value.
605 * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
606 * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
607 */
608 static uint32_t FLASH_OB_GetUser(void)
609 {
610 /* Return the User Option Byte */
611 return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
612 }
613 #else
614
615 /**
616 * @brief Full erase of FLASH memory sectors
617 * @param VoltageRange: The device voltage range which defines the erase parallelism.
618 * This parameter can be one of the following values:
619 * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
620 * the operation will be done by byte (8-bit)
621 * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
622 * the operation will be done by half word (16-bit)
623 * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
624 * the operation will be done by word (32-bit)
625 * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
626 * the operation will be done by double word (64-bit)
627 *
628 * @retval HAL Status
629 */
630 static void FLASH_MassErase(uint8_t VoltageRange)
631 {
632 /* Check the parameters */
633 assert_param(IS_VOLTAGERANGE(VoltageRange));
634
635 /* if the previous operation is completed, proceed to erase all sectors */
636 FLASH->CR &= CR_PSIZE_MASK;
637 FLASH->CR |= FLASH_CR_MER;
638 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
639 /* Data synchronous Barrier (DSB) Just after the write operation
640 This will force the CPU to respect the sequence of instruction (no optimization).*/
641 __DSB();
642 }
643
644 /**
645 * @brief Erase the specified FLASH memory sector
646 * @param Sector: FLASH sector to erase
647 * The value of this parameter depend on device used within the same series
648 * @param VoltageRange: The device voltage range which defines the erase parallelism.
649 * This parameter can be one of the following values:
650 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
651 * the operation will be done by byte (8-bit)
652 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
653 * the operation will be done by half word (16-bit)
654 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
655 * the operation will be done by word (32-bit)
656 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
657 * the operation will be done by double word (64-bit)
658 *
659 * @retval None
660 */
661 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
662 {
663 uint32_t tmp_psize = 0;
664
665 /* Check the parameters */
666 assert_param(IS_FLASH_SECTOR(Sector));
667 assert_param(IS_VOLTAGERANGE(VoltageRange));
668
669 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
670 {
671 tmp_psize = FLASH_PSIZE_BYTE;
672 }
673 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
674 {
675 tmp_psize = FLASH_PSIZE_HALF_WORD;
676 }
677 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
678 {
679 tmp_psize = FLASH_PSIZE_WORD;
680 }
681 else
682 {
683 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
684 }
685
686 /* If the previous operation is completed, proceed to erase the sector */
687 FLASH->CR &= CR_PSIZE_MASK;
688 FLASH->CR |= tmp_psize;
689 FLASH->CR &= SECTOR_MASK;
690 FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
691 FLASH->CR |= FLASH_CR_STRT;
692
693 /* Data synchronous Barrier (DSB) Just after the write operation
694 This will force the CPU to respect the sequence of instruction (no optimization).*/
695 __DSB();
696 }
697
698 /**
699 * @brief Return the FLASH Write Protection Option Bytes value.
700 * @retval uint32_t FLASH Write Protection Option Bytes value
701 */
702 static uint32_t FLASH_OB_GetWRP(void)
703 {
704 /* Return the FLASH write protection Register value */
705 return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
706 }
707
708 /**
709 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
710 * @param Wwdg: Selects the IWDG mode
711 * This parameter can be one of the following values:
712 * @arg OB_WWDG_SW: Software WWDG selected
713 * @arg OB_WWDG_HW: Hardware WWDG selected
714 * @param Iwdg: Selects the WWDG mode
715 * This parameter can be one of the following values:
716 * @arg OB_IWDG_SW: Software IWDG selected
717 * @arg OB_IWDG_HW: Hardware IWDG selected
718 * @param Stop: Reset event when entering STOP mode.
719 * This parameter can be one of the following values:
720 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
721 * @arg OB_STOP_RST: Reset generated when entering in STOP
722 * @param Stdby: Reset event when entering Standby mode.
723 * This parameter can be one of the following values:
724 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
725 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
726 * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
727 * This parameter can be one of the following values:
728 * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
729 * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
730 * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
731 * This parameter can be one of the following values:
732 * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
733 * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
734 * @retval HAL Status
735 */
736 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
737 {
738 uint32_t useroptionmask = 0x00;
739 uint32_t useroptionvalue = 0x00;
740
741 HAL_StatusTypeDef status = HAL_OK;
742
743 /* Check the parameters */
744 assert_param(IS_OB_WWDG_SOURCE(Wwdg));
745 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
746 assert_param(IS_OB_STOP_SOURCE(Stop));
747 assert_param(IS_OB_STDBY_SOURCE(Stdby));
748 assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
749 assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
750
751 /* Wait for last operation to be completed */
752 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
753
754 if(status == HAL_OK)
755 {
756 useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
757 FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
758
759 useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
760
761 /* Update User Option Byte */
762 MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
763 }
764
765 return status;
766
767 }
768
769 /**
770 * @brief Return the FLASH User Option Byte value.
771 * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
772 * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
773 */
774 static uint32_t FLASH_OB_GetUser(void)
775 {
776 /* Return the User Option Byte */
777 return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
778 }
779 #endif /* FLASH_OPTCR_nDBANK */
780
781 /**
782 * @brief Enable the write protection of the desired bank1 or bank2 sectors
783 *
784 * @note When the memory read protection level is selected (RDP level = 1),
785 * it is not possible to program or erase the flash sector i if CortexM7
786 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
787 *
788 * @param WRPSector: specifies the sector(s) to be write protected.
789 * This parameter can be one of the following values:
790 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
791 * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
792 * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
793 * @arg OB_WRP_SECTOR_All
794 *
795 * @retval HAL FLASH State
796 */
797 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
798 {
799 HAL_StatusTypeDef status = HAL_OK;
800
801 /* Check the parameters */
802 assert_param(IS_OB_WRP_SECTOR(WRPSector));
803
804 /* Wait for last operation to be completed */
805 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
806
807 if(status == HAL_OK)
808 {
809 /*Write protection enabled on sectors */
810 FLASH->OPTCR &= (~WRPSector);
811 }
812
813 return status;
814 }
815
816 /**
817 * @brief Disable the write protection of the desired bank1 or bank 2 sectors
818 *
819 * @note When the memory read protection level is selected (RDP level = 1),
820 * it is not possible to program or erase the flash sector i if CortexM4
821 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
822 *
823 * @param WRPSector: specifies the sector(s) to be write protected.
824 * This parameter can be one of the following values:
825 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
826 * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
827 * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
828 * @arg OB_WRP_Sector_All
829 *
830 *
831 * @retval HAL Status
832 */
833 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
834 {
835 HAL_StatusTypeDef status = HAL_OK;
836
837 /* Check the parameters */
838 assert_param(IS_OB_WRP_SECTOR(WRPSector));
839
840 /* Wait for last operation to be completed */
841 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
842
843 if(status == HAL_OK)
844 {
845 /* Write protection disabled on sectors */
846 FLASH->OPTCR |= (WRPSector);
847 }
848
849 return status;
850 }
851
852 /**
853 * @brief Set the read protection level.
854 * @param Level: specifies the read protection level.
855 * This parameter can be one of the following values:
856 * @arg OB_RDP_LEVEL_0: No protection
857 * @arg OB_RDP_LEVEL_1: Read protection of the memory
858 * @arg OB_RDP_LEVEL_2: Full chip protection
859 *
860 * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
861 *
862 * @retval HAL Status
863 */
864 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
865 {
866 HAL_StatusTypeDef status = HAL_OK;
867
868 /* Check the parameters */
869 assert_param(IS_OB_RDP_LEVEL(Level));
870
871 /* Wait for last operation to be completed */
872 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
873
874 if(status == HAL_OK)
875 {
876 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
877 }
878
879 return status;
880 }
881
882 /**
883 * @brief Set the BOR Level.
884 * @param Level: specifies the Option Bytes BOR Reset Level.
885 * This parameter can be one of the following values:
886 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
887 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
888 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
889 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
890 * @retval HAL Status
891 */
892 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
893 {
894 /* Check the parameters */
895 assert_param(IS_OB_BOR_LEVEL(Level));
896
897 /* Set the BOR Level */
898 MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
899
900 return HAL_OK;
901
902 }
903
904 /**
905 * @brief Configure Boot base address.
906 *
907 * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
908 * This parameter can be one of the following values:
909 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
910 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
911 * @param Address: specifies Boot base address
912 * This parameter can be one of the following values:
913 * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
914 * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
915 * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
916 * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
917 * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
918 * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
919 * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
920 *
921 * @retval HAL Status
922 */
923 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
924 {
925 HAL_StatusTypeDef status = HAL_OK;
926
927 /* Check the parameters */
928 assert_param(IS_OB_BOOT_ADDRESS(Address));
929
930 /* Wait for last operation to be completed */
931 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
932
933 if(status == HAL_OK)
934 {
935 if(BootOption == OPTIONBYTE_BOOTADDR_0)
936 {
937 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
938 }
939 else
940 {
941 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
942 }
943 }
944
945 return status;
946 }
947
948 /**
949 * @brief Returns the FLASH Read Protection level.
950 * @retval FlagStatus FLASH ReadOut Protection Status:
951 * This parameter can be one of the following values:
952 * @arg OB_RDP_LEVEL_0: No protection
953 * @arg OB_RDP_LEVEL_1: Read protection of the memory
954 * @arg OB_RDP_LEVEL_2: Full chip protection
955 */
956 static uint8_t FLASH_OB_GetRDP(void)
957 {
958 uint8_t readstatus = OB_RDP_LEVEL_0;
959
960 if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
961 {
962 readstatus = OB_RDP_LEVEL_0;
963 }
964 else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
965 {
966 readstatus = OB_RDP_LEVEL_2;
967 }
968 else
969 {
970 readstatus = OB_RDP_LEVEL_1;
971 }
972
973 return readstatus;
974 }
975
976 /**
977 * @brief Returns the FLASH BOR level.
978 * @retval uint32_t The FLASH BOR level:
979 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
980 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
981 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
982 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
983 */
984 static uint32_t FLASH_OB_GetBOR(void)
985 {
986 /* Return the FLASH BOR level */
987 return ((uint32_t)(FLASH->OPTCR & 0x0C));
988 }
989
990 /**
991 * @brief Configure Boot base address.
992 *
993 * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
994 * This parameter can be one of the following values:
995 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
996 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
997 *
998 * @retval uint32_t Boot Base Address:
999 * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
1000 * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
1001 * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
1002 * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
1003 * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
1004 * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
1005 * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
1006 */
1007 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
1008 {
1009 uint32_t Address = 0;
1010
1011 /* Return the Boot base Address */
1012 if(BootOption == OPTIONBYTE_BOOTADDR_0)
1013 {
1014 Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
1015 }
1016 else
1017 {
1018 Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
1019 }
1020
1021 return Address;
1022 }
1023
1024 /**
1025 * @}
1026 */
1027
1028 #endif /* HAL_FLASH_MODULE_ENABLED */
1029
1030 /**
1031 * @}
1032 */
1033
1034 /**
1035 * @}
1036 */
1037
1038 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)