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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_i2c.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_i2c.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief I2C HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral State and Errors functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 The I2C HAL driver can be used as follows:
20
21 (#) Declare a I2C_HandleTypeDef handle structure, for example:
22 I2C_HandleTypeDef hi2c;
23
24 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
25 (##) Enable the I2Cx interface clock
26 (##) I2C pins configuration
27 (+++) Enable the clock for the I2C GPIOs
28 (+++) Configure I2C pins as alternate function open-drain
29 (##) NVIC configuration if you need to use interrupt process
30 (+++) Configure the I2Cx interrupt priority
31 (+++) Enable the NVIC I2C IRQ Channel
32 (##) DMA Configuration if you need to use DMA process
33 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
34 (+++) Enable the DMAx interface clock using
35 (+++) Configure the DMA handle parameters
36 (+++) Configure the DMA Tx or Rx stream
37 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
38 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
39 the DMA Tx or Rx stream
40
41 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
42 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
43
44 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
45 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
46
47 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
48
49 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
50
51 *** Polling mode IO operation ***
52 =================================
53 [..]
54 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
55 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
56 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
57 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
58
59 *** Polling mode IO MEM operation ***
60 =====================================
61 [..]
62 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
63 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
64
65
66 *** Interrupt mode IO operation ***
67 ===================================
68 [..]
69 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
70 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
71 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
72 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
73 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
74 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
75 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
76 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
77 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
78 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
79 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
80 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
81 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
82 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
83 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
84 (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
85 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
86 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
87 This action will inform Master to generate a Stop condition to discard the communication.
88
89
90 *** Interrupt mode IO sequential operation ***
91 ===================================
92 [..]
93 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
94 when a direction change during transfer
95 [..]
96 (+) A specific option field manage the different steps of a sequential transfer
97 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
98 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
99 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
100 and data to transfer without a final stop condition
101 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
102 and with new data to transfer if the direction change or manage only the new data to transfer
103 if no direction change and without a final stop condition in both cases
104 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
105 and with new data to transfer if the direction change or manage only the new data to transfer
106 if no direction change and with a final stop condition in both cases
107
108 (+) Differents sequential I2C interfaces are listed below:
109 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
110 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
111 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
112 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
113 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
114 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
115 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
116 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
117 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
118 (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
119 (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
120 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
121 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
122 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
123 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
124 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
125 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
126 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
127 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
128 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
129 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
130 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
131 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
132 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
133 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
134 (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
135 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
136 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
137 This action will inform Master to generate a Stop condition to discard the communication.
138
139 *** Interrupt mode IO MEM operation ***
140 =======================================
141 [..]
142 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
143 HAL_I2C_Mem_Write_IT()
144 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
145 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
146 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
147 HAL_I2C_Mem_Read_IT()
148 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
149 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
150 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
151 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
152
153 *** DMA mode IO operation ***
154 ==============================
155 [..]
156 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
157 HAL_I2C_Master_Transmit_DMA()
158 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
159 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
160 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
161 HAL_I2C_Master_Receive_DMA()
162 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
163 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
164 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
165 HAL_I2C_Slave_Transmit_DMA()
166 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
167 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
168 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
169 HAL_I2C_Slave_Receive_DMA()
170 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
171 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
172 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
173 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
174 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
175 (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
176 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
177 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
178 This action will inform Master to generate a Stop condition to discard the communication.
179
180 *** DMA mode IO MEM operation ***
181 =================================
182 [..]
183 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
184 HAL_I2C_Mem_Write_DMA()
185 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
186 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
187 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
188 HAL_I2C_Mem_Read_DMA()
189 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
190 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
191 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
192 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
193
194
195 *** I2C HAL driver macros list ***
196 ==================================
197 [..]
198 Below the list of most used macros in I2C HAL driver.
199
200 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
201 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
202 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
203 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
204 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
205 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
206 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
207
208 [..]
209 (@) You can refer to the I2C HAL driver header file for more useful macros
210
211 @endverbatim
212 ******************************************************************************
213 * @attention
214 *
215 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
216 *
217 * Redistribution and use in source and binary forms, with or without modification,
218 * are permitted provided that the following conditions are met:
219 * 1. Redistributions of source code must retain the above copyright notice,
220 * this list of conditions and the following disclaimer.
221 * 2. Redistributions in binary form must reproduce the above copyright notice,
222 * this list of conditions and the following disclaimer in the documentation
223 * and/or other materials provided with the distribution.
224 * 3. Neither the name of STMicroelectronics nor the names of its contributors
225 * may be used to endorse or promote products derived from this software
226 * without specific prior written permission.
227 *
228 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
229 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
230 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
231 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
232 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
233 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
234 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
235 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
236 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
237 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
238 *
239 ******************************************************************************
240 */
241
242 /* Includes ------------------------------------------------------------------*/
243 #include "stm32f7xx_hal.h"
244
245 /** @addtogroup STM32F7xx_HAL_Driver
246 * @{
247 */
248
249 /** @defgroup I2C I2C
250 * @brief I2C HAL module driver
251 * @{
252 */
253
254 #ifdef HAL_I2C_MODULE_ENABLED
255
256 /* Private typedef -----------------------------------------------------------*/
257 /* Private define ------------------------------------------------------------*/
258
259 /** @defgroup I2C_Private_Define I2C Private Define
260 * @{
261 */
262 #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
263 #define I2C_TIMEOUT_ADDR ((uint32_t)10000U) /*!< 10 s */
264 #define I2C_TIMEOUT_BUSY ((uint32_t)25U) /*!< 25 ms */
265 #define I2C_TIMEOUT_DIR ((uint32_t)25U) /*!< 25 ms */
266 #define I2C_TIMEOUT_RXNE ((uint32_t)25U) /*!< 25 ms */
267 #define I2C_TIMEOUT_STOPF ((uint32_t)25U) /*!< 25 ms */
268 #define I2C_TIMEOUT_TC ((uint32_t)25U) /*!< 25 ms */
269 #define I2C_TIMEOUT_TCR ((uint32_t)25U) /*!< 25 ms */
270 #define I2C_TIMEOUT_TXIS ((uint32_t)25U) /*!< 25 ms */
271 #define I2C_TIMEOUT_FLAG ((uint32_t)25U) /*!< 25 ms */
272
273 #define MAX_NBYTE_SIZE 255U
274 #define SlaveAddr_SHIFT 7U
275 #define SlaveAddr_MSK 0x06U
276
277 /* Private define for @ref PreviousState usage */
278 #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
279 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
280 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
281 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
282 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
283 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
284 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
285 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
286
287
288 /* Private define to centralize the enable/disable of Interrupts */
289 #define I2C_XFER_TX_IT ((uint32_t)0x00000001)
290 #define I2C_XFER_RX_IT ((uint32_t)0x00000002)
291 #define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004)
292
293 #define I2C_XFER_ERROR_IT ((uint32_t)0x00000011)
294 #define I2C_XFER_CPLT_IT ((uint32_t)0x00000012)
295 #define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012)
296 /**
297 * @}
298 */
299
300 /* Private macro -------------------------------------------------------------*/
301 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
302 ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
303 ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
304
305 /* Private variables ---------------------------------------------------------*/
306 /* Private function prototypes -----------------------------------------------*/
307
308 /** @defgroup I2C_Private_Functions I2C Private Functions
309 * @{
310 */
311 /* Private functions to handle DMA transfer */
312 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
313 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
314 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
315 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
316 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
317 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
318
319 /* Private functions to handle IT transfer */
320 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
321 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
322 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
323 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
324 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
325 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
326 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
327
328 /* Private functions to handle IT transfer */
329 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
330 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
331
332 /* Private functions for I2C transfer IRQ handler */
333 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
334 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
335 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
336 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
337
338 /* Private functions to handle flags during polling transfer */
339 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
340 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
341 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
342 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
343 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
344
345 /* Private functions to centralize the enable/disable of Interrupts */
346 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
347 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
348
349 /* Private functions to flush TXDR register */
350 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
351
352 /* Private functions to handle start, restart or stop a transfer */
353 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
354 /**
355 * @}
356 */
357
358 /* Exported functions --------------------------------------------------------*/
359
360 /** @defgroup I2C_Exported_Functions I2C Exported Functions
361 * @{
362 */
363
364 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
365 * @brief Initialization and Configuration functions
366 *
367 @verbatim
368 ===============================================================================
369 ##### Initialization and de-initialization functions #####
370 ===============================================================================
371 [..] This subsection provides a set of functions allowing to initialize and
372 deinitialize the I2Cx peripheral:
373
374 (+) User must Implement HAL_I2C_MspInit() function in which he configures
375 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
376
377 (+) Call the function HAL_I2C_Init() to configure the selected device with
378 the selected configuration:
379 (++) Clock Timing
380 (++) Own Address 1
381 (++) Addressing mode (Master, Slave)
382 (++) Dual Addressing mode
383 (++) Own Address 2
384 (++) Own Address 2 Mask
385 (++) General call mode
386 (++) Nostretch mode
387
388 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
389 of the selected I2Cx peripheral.
390
391 @endverbatim
392 * @{
393 */
394
395 /**
396 * @brief Initializes the I2C according to the specified parameters
397 * in the I2C_InitTypeDef and initialize the associated handle.
398 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
399 * the configuration information for the specified I2C.
400 * @retval HAL status
401 */
402 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
403 {
404 /* Check the I2C handle allocation */
405 if(hi2c == NULL)
406 {
407 return HAL_ERROR;
408 }
409
410 /* Check the parameters */
411 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
412 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
413 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
414 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
415 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
416 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
417 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
418 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
419
420 if(hi2c->State == HAL_I2C_STATE_RESET)
421 {
422 /* Allocate lock resource and initialize it */
423 hi2c->Lock = HAL_UNLOCKED;
424
425 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
426 HAL_I2C_MspInit(hi2c);
427 }
428
429 hi2c->State = HAL_I2C_STATE_BUSY;
430
431 /* Disable the selected I2C peripheral */
432 __HAL_I2C_DISABLE(hi2c);
433
434 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
435 /* Configure I2Cx: Frequency range */
436 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
437
438 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
439 /* Configure I2Cx: Own Address1 and ack own address1 mode */
440 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
441 if(hi2c->Init.OwnAddress1 != 0)
442 {
443 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
444 {
445 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
446 }
447 else /* I2C_ADDRESSINGMODE_10BIT */
448 {
449 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
450 }
451 }
452
453 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
454 /* Configure I2Cx: Addressing Master mode */
455 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
456 {
457 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
458 }
459 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
460 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
461
462 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
463 /* Configure I2Cx: Dual mode and Own Address2 */
464 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
465
466 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
467 /* Configure I2Cx: Generalcall and NoStretch mode */
468 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
469
470 /* Enable the selected I2C peripheral */
471 __HAL_I2C_ENABLE(hi2c);
472
473 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
474 hi2c->State = HAL_I2C_STATE_READY;
475 hi2c->PreviousState = I2C_STATE_NONE;
476 hi2c->Mode = HAL_I2C_MODE_NONE;
477
478 return HAL_OK;
479 }
480
481 /**
482 * @brief DeInitialize the I2C peripheral.
483 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
484 * the configuration information for the specified I2C.
485 * @retval HAL status
486 */
487 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
488 {
489 /* Check the I2C handle allocation */
490 if(hi2c == NULL)
491 {
492 return HAL_ERROR;
493 }
494
495 /* Check the parameters */
496 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
497
498 hi2c->State = HAL_I2C_STATE_BUSY;
499
500 /* Disable the I2C Peripheral Clock */
501 __HAL_I2C_DISABLE(hi2c);
502
503 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
504 HAL_I2C_MspDeInit(hi2c);
505
506 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
507 hi2c->State = HAL_I2C_STATE_RESET;
508 hi2c->PreviousState = I2C_STATE_NONE;
509 hi2c->Mode = HAL_I2C_MODE_NONE;
510
511 /* Release Lock */
512 __HAL_UNLOCK(hi2c);
513
514 return HAL_OK;
515 }
516
517 /**
518 * @brief Initialize the I2C MSP.
519 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
520 * the configuration information for the specified I2C.
521 * @retval None
522 */
523 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
524 {
525 /* Prevent unused argument(s) compilation warning */
526 UNUSED(hi2c);
527
528 /* NOTE : This function should not be modified, when the callback is needed,
529 the HAL_I2C_MspInit could be implemented in the user file
530 */
531 }
532
533 /**
534 * @brief DeInitialize the I2C MSP.
535 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
536 * the configuration information for the specified I2C.
537 * @retval None
538 */
539 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
540 {
541 /* Prevent unused argument(s) compilation warning */
542 UNUSED(hi2c);
543
544 /* NOTE : This function should not be modified, when the callback is needed,
545 the HAL_I2C_MspDeInit could be implemented in the user file
546 */
547 }
548
549 /**
550 * @}
551 */
552
553 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
554 * @brief Data transfers functions
555 *
556 @verbatim
557 ===============================================================================
558 ##### IO operation functions #####
559 ===============================================================================
560 [..]
561 This subsection provides a set of functions allowing to manage the I2C data
562 transfers.
563
564 (#) There are two modes of transfer:
565 (++) Blocking mode : The communication is performed in the polling mode.
566 The status of all data processing is returned by the same function
567 after finishing transfer.
568 (++) No-Blocking mode : The communication is performed using Interrupts
569 or DMA. These functions return the status of the transfer startup.
570 The end of the data processing will be indicated through the
571 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
572 using DMA mode.
573
574 (#) Blocking mode functions are :
575 (++) HAL_I2C_Master_Transmit()
576 (++) HAL_I2C_Master_Receive()
577 (++) HAL_I2C_Slave_Transmit()
578 (++) HAL_I2C_Slave_Receive()
579 (++) HAL_I2C_Mem_Write()
580 (++) HAL_I2C_Mem_Read()
581 (++) HAL_I2C_IsDeviceReady()
582
583 (#) No-Blocking mode functions with Interrupt are :
584 (++) HAL_I2C_Master_Transmit_IT()
585 (++) HAL_I2C_Master_Receive_IT()
586 (++) HAL_I2C_Slave_Transmit_IT()
587 (++) HAL_I2C_Slave_Receive_IT()
588 (++) HAL_I2C_Mem_Write_IT()
589 (++) HAL_I2C_Mem_Read_IT()
590
591 (#) No-Blocking mode functions with DMA are :
592 (++) HAL_I2C_Master_Transmit_DMA()
593 (++) HAL_I2C_Master_Receive_DMA()
594 (++) HAL_I2C_Slave_Transmit_DMA()
595 (++) HAL_I2C_Slave_Receive_DMA()
596 (++) HAL_I2C_Mem_Write_DMA()
597 (++) HAL_I2C_Mem_Read_DMA()
598
599 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
600 (++) HAL_I2C_MemTxCpltCallback()
601 (++) HAL_I2C_MemRxCpltCallback()
602 (++) HAL_I2C_MasterTxCpltCallback()
603 (++) HAL_I2C_MasterRxCpltCallback()
604 (++) HAL_I2C_SlaveTxCpltCallback()
605 (++) HAL_I2C_SlaveRxCpltCallback()
606 (++) HAL_I2C_ErrorCallback()
607
608 @endverbatim
609 * @{
610 */
611
612 /**
613 * @brief Transmits in master mode an amount of data in blocking mode.
614 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
615 * the configuration information for the specified I2C.
616 * @param DevAddress: Target device address
617 * @param pData: Pointer to data buffer
618 * @param Size: Amount of data to be sent
619 * @param Timeout: Timeout duration
620 * @retval HAL status
621 */
622 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
623 {
624 uint32_t tickstart = 0;
625
626 if(hi2c->State == HAL_I2C_STATE_READY)
627 {
628 /* Process Locked */
629 __HAL_LOCK(hi2c);
630
631 /* Init tickstart for timeout management*/
632 tickstart = HAL_GetTick();
633
634 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
635 {
636 return HAL_TIMEOUT;
637 }
638
639 hi2c->State = HAL_I2C_STATE_BUSY_TX;
640 hi2c->Mode = HAL_I2C_MODE_MASTER;
641 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
642
643 /* Prepare transfer parameters */
644 hi2c->pBuffPtr = pData;
645 hi2c->XferCount = Size;
646 hi2c->XferISR = NULL;
647
648 /* Send Slave Address */
649 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
650 if(hi2c->XferCount > MAX_NBYTE_SIZE)
651 {
652 hi2c->XferSize = MAX_NBYTE_SIZE;
653 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
654 }
655 else
656 {
657 hi2c->XferSize = hi2c->XferCount;
658 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
659 }
660
661 while(hi2c->XferSize > 0)
662 {
663 /* Wait until TXIS flag is set */
664 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
665 {
666 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
667 {
668 return HAL_ERROR;
669 }
670 else
671 {
672 return HAL_TIMEOUT;
673 }
674 }
675 /* Write data to TXDR */
676 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
677 hi2c->XferCount--;
678 hi2c->XferSize--;
679
680 if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
681 {
682 /* Wait until TCR flag is set */
683 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
684 {
685 return HAL_TIMEOUT;
686 }
687
688 if(hi2c->XferCount > MAX_NBYTE_SIZE)
689 {
690 hi2c->XferSize = MAX_NBYTE_SIZE;
691 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
692 }
693 else
694 {
695 hi2c->XferSize = hi2c->XferCount;
696 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
697 }
698 }
699 }
700
701 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
702 /* Wait until STOPF flag is set */
703 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
704 {
705 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
706 {
707 return HAL_ERROR;
708 }
709 else
710 {
711 return HAL_TIMEOUT;
712 }
713 }
714
715 /* Clear STOP Flag */
716 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
717
718 /* Clear Configuration Register 2 */
719 I2C_RESET_CR2(hi2c);
720
721 hi2c->State = HAL_I2C_STATE_READY;
722 hi2c->Mode = HAL_I2C_MODE_NONE;
723
724 /* Process Unlocked */
725 __HAL_UNLOCK(hi2c);
726
727 return HAL_OK;
728 }
729 else
730 {
731 return HAL_BUSY;
732 }
733 }
734
735 /**
736 * @brief Receives in master mode an amount of data in blocking mode.
737 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
738 * the configuration information for the specified I2C.
739 * @param DevAddress: Target device address
740 * @param pData: Pointer to data buffer
741 * @param Size: Amount of data to be sent
742 * @param Timeout: Timeout duration
743 * @retval HAL status
744 */
745 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
746 {
747 uint32_t tickstart = 0;
748
749 if(hi2c->State == HAL_I2C_STATE_READY)
750 {
751 /* Process Locked */
752 __HAL_LOCK(hi2c);
753
754 /* Init tickstart for timeout management*/
755 tickstart = HAL_GetTick();
756
757 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
758 {
759 return HAL_TIMEOUT;
760 }
761
762 hi2c->State = HAL_I2C_STATE_BUSY_RX;
763 hi2c->Mode = HAL_I2C_MODE_MASTER;
764 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
765
766 /* Prepare transfer parameters */
767 hi2c->pBuffPtr = pData;
768 hi2c->XferCount = Size;
769 hi2c->XferISR = NULL;
770
771 /* Send Slave Address */
772 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
773 if(hi2c->XferCount > MAX_NBYTE_SIZE)
774 {
775 hi2c->XferSize = MAX_NBYTE_SIZE;
776 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
777 }
778 else
779 {
780 hi2c->XferSize = hi2c->XferCount;
781 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
782 }
783
784 while(hi2c->XferSize > 0)
785 {
786 /* Wait until RXNE flag is set */
787 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
788 {
789 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
790 {
791 return HAL_ERROR;
792 }
793 else
794 {
795 return HAL_TIMEOUT;
796 }
797 }
798
799 /* Read data from RXDR */
800 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
801 hi2c->XferSize--;
802 hi2c->XferCount--;
803
804 if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
805 {
806 /* Wait until TCR flag is set */
807 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
808 {
809 return HAL_TIMEOUT;
810 }
811
812 if(hi2c->XferCount > MAX_NBYTE_SIZE)
813 {
814 hi2c->XferSize = MAX_NBYTE_SIZE;
815 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
816 }
817 else
818 {
819 hi2c->XferSize = hi2c->XferCount;
820 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
821 }
822 }
823 }
824
825 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
826 /* Wait until STOPF flag is set */
827 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
828 {
829 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
830 {
831 return HAL_ERROR;
832 }
833 else
834 {
835 return HAL_TIMEOUT;
836 }
837 }
838
839 /* Clear STOP Flag */
840 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
841
842 /* Clear Configuration Register 2 */
843 I2C_RESET_CR2(hi2c);
844
845 hi2c->State = HAL_I2C_STATE_READY;
846 hi2c->Mode = HAL_I2C_MODE_NONE;
847
848 /* Process Unlocked */
849 __HAL_UNLOCK(hi2c);
850
851 return HAL_OK;
852 }
853 else
854 {
855 return HAL_BUSY;
856 }
857 }
858
859 /**
860 * @brief Transmits in slave mode an amount of data in blocking mode.
861 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
862 * the configuration information for the specified I2C.
863 * @param pData: Pointer to data buffer
864 * @param Size: Amount of data to be sent
865 * @param Timeout: Timeout duration
866 * @retval HAL status
867 */
868 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
869 {
870 uint32_t tickstart = 0;
871
872 if(hi2c->State == HAL_I2C_STATE_READY)
873 {
874 if((pData == NULL ) || (Size == 0))
875 {
876 return HAL_ERROR;
877 }
878 /* Process Locked */
879 __HAL_LOCK(hi2c);
880
881 /* Init tickstart for timeout management*/
882 tickstart = HAL_GetTick();
883
884 hi2c->State = HAL_I2C_STATE_BUSY_TX;
885 hi2c->Mode = HAL_I2C_MODE_SLAVE;
886 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
887
888 /* Prepare transfer parameters */
889 hi2c->pBuffPtr = pData;
890 hi2c->XferCount = Size;
891 hi2c->XferISR = NULL;
892
893 /* Enable Address Acknowledge */
894 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
895
896 /* Wait until ADDR flag is set */
897 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
898 {
899 /* Disable Address Acknowledge */
900 hi2c->Instance->CR2 |= I2C_CR2_NACK;
901 return HAL_TIMEOUT;
902 }
903
904 /* Clear ADDR flag */
905 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
906
907 /* If 10bit addressing mode is selected */
908 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
909 {
910 /* Wait until ADDR flag is set */
911 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
912 {
913 /* Disable Address Acknowledge */
914 hi2c->Instance->CR2 |= I2C_CR2_NACK;
915 return HAL_TIMEOUT;
916 }
917
918 /* Clear ADDR flag */
919 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
920 }
921
922 /* Wait until DIR flag is set Transmitter mode */
923 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
924 {
925 /* Disable Address Acknowledge */
926 hi2c->Instance->CR2 |= I2C_CR2_NACK;
927 return HAL_TIMEOUT;
928 }
929
930 while(hi2c->XferCount > 0)
931 {
932 /* Wait until TXIS flag is set */
933 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
934 {
935 /* Disable Address Acknowledge */
936 hi2c->Instance->CR2 |= I2C_CR2_NACK;
937
938 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
939 {
940 return HAL_ERROR;
941 }
942 else
943 {
944 return HAL_TIMEOUT;
945 }
946 }
947
948 /* Write data to TXDR */
949 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
950 hi2c->XferCount--;
951 }
952
953 /* Wait until STOP flag is set */
954 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
955 {
956 /* Disable Address Acknowledge */
957 hi2c->Instance->CR2 |= I2C_CR2_NACK;
958
959 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
960 {
961 /* Normal use case for Transmitter mode */
962 /* A NACK is generated to confirm the end of transfer */
963 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
964 }
965 else
966 {
967 return HAL_TIMEOUT;
968 }
969 }
970
971 /* Clear STOP flag */
972 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
973
974 /* Wait until BUSY flag is reset */
975 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
976 {
977 /* Disable Address Acknowledge */
978 hi2c->Instance->CR2 |= I2C_CR2_NACK;
979 return HAL_TIMEOUT;
980 }
981
982 /* Disable Address Acknowledge */
983 hi2c->Instance->CR2 |= I2C_CR2_NACK;
984
985 hi2c->State = HAL_I2C_STATE_READY;
986 hi2c->Mode = HAL_I2C_MODE_NONE;
987
988 /* Process Unlocked */
989 __HAL_UNLOCK(hi2c);
990
991 return HAL_OK;
992 }
993 else
994 {
995 return HAL_BUSY;
996 }
997 }
998
999 /**
1000 * @brief Receive in slave mode an amount of data in blocking mode
1001 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1002 * the configuration information for the specified I2C.
1003 * @param pData: Pointer to data buffer
1004 * @param Size: Amount of data to be sent
1005 * @param Timeout: Timeout duration
1006 * @retval HAL status
1007 */
1008 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1009 {
1010 uint32_t tickstart = 0;
1011
1012 if(hi2c->State == HAL_I2C_STATE_READY)
1013 {
1014 if((pData == NULL ) || (Size == 0))
1015 {
1016 return HAL_ERROR;
1017 }
1018 /* Process Locked */
1019 __HAL_LOCK(hi2c);
1020
1021 /* Init tickstart for timeout management*/
1022 tickstart = HAL_GetTick();
1023
1024 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1025 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1026 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1027
1028 /* Prepare transfer parameters */
1029 hi2c->pBuffPtr = pData;
1030 hi2c->XferCount = Size;
1031 hi2c->XferISR = NULL;
1032
1033 /* Enable Address Acknowledge */
1034 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1035
1036 /* Wait until ADDR flag is set */
1037 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1038 {
1039 /* Disable Address Acknowledge */
1040 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1041 return HAL_TIMEOUT;
1042 }
1043
1044 /* Clear ADDR flag */
1045 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
1046
1047 /* Wait until DIR flag is reset Receiver mode */
1048 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1049 {
1050 /* Disable Address Acknowledge */
1051 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1052 return HAL_TIMEOUT;
1053 }
1054
1055 while(hi2c->XferCount > 0)
1056 {
1057 /* Wait until RXNE flag is set */
1058 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1059 {
1060 /* Disable Address Acknowledge */
1061 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1062
1063 /* Store Last receive data if any */
1064 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1065 {
1066 /* Read data from RXDR */
1067 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
1068 hi2c->XferCount--;
1069 }
1070
1071 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
1072 {
1073 return HAL_TIMEOUT;
1074 }
1075 else
1076 {
1077 return HAL_ERROR;
1078 }
1079 }
1080
1081 /* Read data from RXDR */
1082 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
1083 hi2c->XferCount--;
1084 }
1085
1086 /* Wait until STOP flag is set */
1087 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1088 {
1089 /* Disable Address Acknowledge */
1090 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1091
1092 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1093 {
1094 return HAL_ERROR;
1095 }
1096 else
1097 {
1098 return HAL_TIMEOUT;
1099 }
1100 }
1101
1102 /* Clear STOP flag */
1103 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
1104
1105 /* Wait until BUSY flag is reset */
1106 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1107 {
1108 /* Disable Address Acknowledge */
1109 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1110 return HAL_TIMEOUT;
1111 }
1112
1113 /* Disable Address Acknowledge */
1114 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1115
1116 hi2c->State = HAL_I2C_STATE_READY;
1117 hi2c->Mode = HAL_I2C_MODE_NONE;
1118
1119 /* Process Unlocked */
1120 __HAL_UNLOCK(hi2c);
1121
1122 return HAL_OK;
1123 }
1124 else
1125 {
1126 return HAL_BUSY;
1127 }
1128 }
1129
1130 /**
1131 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1132 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1133 * the configuration information for the specified I2C.
1134 * @param DevAddress: Target device address
1135 * @param pData: Pointer to data buffer
1136 * @param Size: Amount of data to be sent
1137 * @retval HAL status
1138 */
1139 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1140 {
1141 uint32_t xfermode = 0;
1142
1143 if(hi2c->State == HAL_I2C_STATE_READY)
1144 {
1145 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1146 {
1147 return HAL_BUSY;
1148 }
1149
1150 /* Process Locked */
1151 __HAL_LOCK(hi2c);
1152
1153 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1154 hi2c->Mode = HAL_I2C_MODE_MASTER;
1155 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1156
1157 /* Prepare transfer parameters */
1158 hi2c->pBuffPtr = pData;
1159 hi2c->XferCount = Size;
1160 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1161 hi2c->XferISR = I2C_Master_ISR_IT;
1162
1163 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1164 {
1165 hi2c->XferSize = MAX_NBYTE_SIZE;
1166 xfermode = I2C_RELOAD_MODE;
1167 }
1168 else
1169 {
1170 hi2c->XferSize = hi2c->XferCount;
1171 xfermode = I2C_AUTOEND_MODE;
1172 }
1173
1174 /* Send Slave Address */
1175 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1176 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1177
1178 /* Process Unlocked */
1179 __HAL_UNLOCK(hi2c);
1180
1181 /* Note : The I2C interrupts must be enabled after unlocking current process
1182 to avoid the risk of I2C interrupt handle execution before current
1183 process unlock */
1184
1185 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1186 /* possible to enable all of these */
1187 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1188 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1189
1190 return HAL_OK;
1191 }
1192 else
1193 {
1194 return HAL_BUSY;
1195 }
1196 }
1197
1198 /**
1199 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1200 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1201 * the configuration information for the specified I2C.
1202 * @param DevAddress: Target device address
1203 * @param pData: Pointer to data buffer
1204 * @param Size: Amount of data to be sent
1205 * @retval HAL status
1206 */
1207 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1208 {
1209 uint32_t xfermode = 0;
1210
1211 if(hi2c->State == HAL_I2C_STATE_READY)
1212 {
1213 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1214 {
1215 return HAL_BUSY;
1216 }
1217
1218 /* Process Locked */
1219 __HAL_LOCK(hi2c);
1220
1221 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1222 hi2c->Mode = HAL_I2C_MODE_MASTER;
1223 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1224
1225 /* Prepare transfer parameters */
1226 hi2c->pBuffPtr = pData;
1227 hi2c->XferCount = Size;
1228 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1229 hi2c->XferISR = I2C_Master_ISR_IT;
1230
1231 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1232 {
1233 hi2c->XferSize = MAX_NBYTE_SIZE;
1234 xfermode = I2C_RELOAD_MODE;
1235 }
1236 else
1237 {
1238 hi2c->XferSize = hi2c->XferCount;
1239 xfermode = I2C_AUTOEND_MODE;
1240 }
1241
1242 /* Send Slave Address */
1243 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1244 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1245
1246 /* Process Unlocked */
1247 __HAL_UNLOCK(hi2c);
1248
1249 /* Note : The I2C interrupts must be enabled after unlocking current process
1250 to avoid the risk of I2C interrupt handle execution before current
1251 process unlock */
1252
1253 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1254 /* possible to enable all of these */
1255 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1256 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1257
1258 return HAL_OK;
1259 }
1260 else
1261 {
1262 return HAL_BUSY;
1263 }
1264 }
1265
1266 /**
1267 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1268 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1269 * the configuration information for the specified I2C.
1270 * @param pData: Pointer to data buffer
1271 * @param Size: Amount of data to be sent
1272 * @retval HAL status
1273 */
1274 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1275 {
1276 if(hi2c->State == HAL_I2C_STATE_READY)
1277 {
1278 /* Process Locked */
1279 __HAL_LOCK(hi2c);
1280
1281 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1282 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1283 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1284
1285 /* Enable Address Acknowledge */
1286 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1287
1288 /* Prepare transfer parameters */
1289 hi2c->pBuffPtr = pData;
1290 hi2c->XferCount = Size;
1291 hi2c->XferSize = hi2c->XferCount;
1292 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1293 hi2c->XferISR = I2C_Slave_ISR_IT;
1294
1295 /* Process Unlocked */
1296 __HAL_UNLOCK(hi2c);
1297
1298 /* Note : The I2C interrupts must be enabled after unlocking current process
1299 to avoid the risk of I2C interrupt handle execution before current
1300 process unlock */
1301
1302 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1303 /* possible to enable all of these */
1304 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1305 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1306
1307 return HAL_OK;
1308 }
1309 else
1310 {
1311 return HAL_BUSY;
1312 }
1313 }
1314
1315 /**
1316 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1317 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1318 * the configuration information for the specified I2C.
1319 * @param pData: Pointer to data buffer
1320 * @param Size: Amount of data to be sent
1321 * @retval HAL status
1322 */
1323 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1324 {
1325 if(hi2c->State == HAL_I2C_STATE_READY)
1326 {
1327 /* Process Locked */
1328 __HAL_LOCK(hi2c);
1329
1330 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1331 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1332 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1333
1334 /* Enable Address Acknowledge */
1335 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1336
1337 /* Prepare transfer parameters */
1338 hi2c->pBuffPtr = pData;
1339 hi2c->XferCount = Size;
1340 hi2c->XferSize = hi2c->XferCount;
1341 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1342 hi2c->XferISR = I2C_Slave_ISR_IT;
1343
1344 /* Process Unlocked */
1345 __HAL_UNLOCK(hi2c);
1346
1347 /* Note : The I2C interrupts must be enabled after unlocking current process
1348 to avoid the risk of I2C interrupt handle execution before current
1349 process unlock */
1350
1351 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1352 /* possible to enable all of these */
1353 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1354 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1355
1356 return HAL_OK;
1357 }
1358 else
1359 {
1360 return HAL_BUSY;
1361 }
1362 }
1363
1364 /**
1365 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1366 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1367 * the configuration information for the specified I2C.
1368 * @param DevAddress: Target device address
1369 * @param pData: Pointer to data buffer
1370 * @param Size: Amount of data to be sent
1371 * @retval HAL status
1372 */
1373 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1374 {
1375 uint32_t xfermode = 0;
1376
1377 if(hi2c->State == HAL_I2C_STATE_READY)
1378 {
1379 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1380 {
1381 return HAL_BUSY;
1382 }
1383
1384 /* Process Locked */
1385 __HAL_LOCK(hi2c);
1386
1387 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1388 hi2c->Mode = HAL_I2C_MODE_MASTER;
1389 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1390
1391 /* Prepare transfer parameters */
1392 hi2c->pBuffPtr = pData;
1393 hi2c->XferCount = Size;
1394 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1395 hi2c->XferISR = I2C_Master_ISR_DMA;
1396
1397 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1398 {
1399 hi2c->XferSize = MAX_NBYTE_SIZE;
1400 xfermode = I2C_RELOAD_MODE;
1401 }
1402 else
1403 {
1404 hi2c->XferSize = hi2c->XferCount;
1405 xfermode = I2C_AUTOEND_MODE;
1406 }
1407
1408 /* Set the I2C DMA transfer complete callback */
1409 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1410
1411 /* Set the DMA error callback */
1412 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1413
1414 /* Set the unused DMA callbacks to NULL */
1415 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1416 hi2c->hdmatx->XferAbortCallback = NULL;
1417
1418 /* Enable the DMA channel */
1419 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
1420
1421 /* Send Slave Address */
1422 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1423 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1424
1425 /* Update XferCount value */
1426 hi2c->XferCount -= hi2c->XferSize;
1427
1428 /* Process Unlocked */
1429 __HAL_UNLOCK(hi2c);
1430
1431 /* Note : The I2C interrupts must be enabled after unlocking current process
1432 to avoid the risk of I2C interrupt handle execution before current
1433 process unlock */
1434 /* Enable ERR and NACK interrupts */
1435 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1436
1437 /* Enable DMA Request */
1438 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1439
1440 return HAL_OK;
1441 }
1442 else
1443 {
1444 return HAL_BUSY;
1445 }
1446 }
1447
1448 /**
1449 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
1450 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1451 * the configuration information for the specified I2C.
1452 * @param DevAddress: Target device address
1453 * @param pData: Pointer to data buffer
1454 * @param Size: Amount of data to be sent
1455 * @retval HAL status
1456 */
1457 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1458 {
1459 uint32_t xfermode = 0;
1460
1461 if(hi2c->State == HAL_I2C_STATE_READY)
1462 {
1463 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1464 {
1465 return HAL_BUSY;
1466 }
1467
1468 /* Process Locked */
1469 __HAL_LOCK(hi2c);
1470
1471 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1472 hi2c->Mode = HAL_I2C_MODE_MASTER;
1473 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1474
1475 /* Prepare transfer parameters */
1476 hi2c->pBuffPtr = pData;
1477 hi2c->XferCount = Size;
1478 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1479 hi2c->XferISR = I2C_Master_ISR_DMA;
1480
1481 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1482 {
1483 hi2c->XferSize = MAX_NBYTE_SIZE;
1484 xfermode = I2C_RELOAD_MODE;
1485 }
1486 else
1487 {
1488 hi2c->XferSize = hi2c->XferCount;
1489 xfermode = I2C_AUTOEND_MODE;
1490 }
1491
1492 if(hi2c->XferSize > 0)
1493 {
1494 /* Set the I2C DMA transfer complete callback */
1495 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
1496
1497 /* Set the DMA error callback */
1498 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
1499
1500 /* Set the unused DMA callbacks to NULL */
1501 hi2c->hdmarx->XferHalfCpltCallback = NULL;
1502 hi2c->hdmarx->XferAbortCallback = NULL;
1503
1504 /* Enable the DMA channel */
1505 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
1506
1507 /* Send Slave Address */
1508 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1509 I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1510
1511 /* Update XferCount value */
1512 hi2c->XferCount -= hi2c->XferSize;
1513
1514 /* Process Unlocked */
1515 __HAL_UNLOCK(hi2c);
1516
1517 /* Note : The I2C interrupts must be enabled after unlocking current process
1518 to avoid the risk of I2C interrupt handle execution before current
1519 process unlock */
1520 /* Enable ERR and NACK interrupts */
1521 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1522
1523 /* Enable DMA Request */
1524 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
1525 }
1526 else
1527 {
1528 hi2c->State = HAL_I2C_STATE_READY;
1529 hi2c->Mode = HAL_I2C_MODE_NONE;
1530
1531 /* Process Unlocked */
1532 __HAL_UNLOCK(hi2c);
1533 }
1534 return HAL_OK;
1535 }
1536 else
1537 {
1538 return HAL_BUSY;
1539 }
1540 }
1541
1542 /**
1543 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
1544 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1545 * the configuration information for the specified I2C.
1546 * @param pData: Pointer to data buffer
1547 * @param Size: Amount of data to be sent
1548 * @retval HAL status
1549 */
1550 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1551 {
1552 if(hi2c->State == HAL_I2C_STATE_READY)
1553 {
1554 if((pData == NULL) || (Size == 0))
1555 {
1556 return HAL_ERROR;
1557 }
1558 /* Process Locked */
1559 __HAL_LOCK(hi2c);
1560
1561 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1562 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1563 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1564
1565 /* Prepare transfer parameters */
1566 hi2c->pBuffPtr = pData;
1567 hi2c->XferCount = Size;
1568 hi2c->XferSize = hi2c->XferCount;
1569 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1570 hi2c->XferISR = I2C_Slave_ISR_DMA;
1571
1572 /* Set the I2C DMA transfer complete callback */
1573 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
1574
1575 /* Set the DMA error callback */
1576 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1577
1578 /* Set the unused DMA callbacks to NULL */
1579 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1580 hi2c->hdmatx->XferAbortCallback = NULL;
1581
1582 /* Enable the DMA channel */
1583 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
1584
1585 /* Enable Address Acknowledge */
1586 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1587
1588 /* Process Unlocked */
1589 __HAL_UNLOCK(hi2c);
1590
1591 /* Note : The I2C interrupts must be enabled after unlocking current process
1592 to avoid the risk of I2C interrupt handle execution before current
1593 process unlock */
1594 /* Enable ERR, STOP, NACK, ADDR interrupts */
1595 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
1596
1597 /* Enable DMA Request */
1598 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1599
1600 return HAL_OK;
1601 }
1602 else
1603 {
1604 return HAL_BUSY;
1605 }
1606 }
1607
1608 /**
1609 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
1610 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1611 * the configuration information for the specified I2C.
1612 * @param pData: Pointer to data buffer
1613 * @param Size: Amount of data to be sent
1614 * @retval HAL status
1615 */
1616 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1617 {
1618 if(hi2c->State == HAL_I2C_STATE_READY)
1619 {
1620 if((pData == NULL) || (Size == 0))
1621 {
1622 return HAL_ERROR;
1623 }
1624 /* Process Locked */
1625 __HAL_LOCK(hi2c);
1626
1627 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1628 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1629 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1630
1631 /* Prepare transfer parameters */
1632 hi2c->pBuffPtr = pData;
1633 hi2c->XferCount = Size;
1634 hi2c->XferSize = hi2c->XferCount;
1635 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1636 hi2c->XferISR = I2C_Slave_ISR_DMA;
1637
1638 /* Set the I2C DMA transfer complete callback */
1639 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
1640
1641 /* Set the DMA error callback */
1642 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
1643
1644 /* Set the unused DMA callbacks to NULL */
1645 hi2c->hdmarx->XferHalfCpltCallback = NULL;
1646 hi2c->hdmarx->XferAbortCallback = NULL;
1647
1648 /* Enable the DMA channel */
1649 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
1650
1651 /* Enable Address Acknowledge */
1652 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1653
1654 /* Process Unlocked */
1655 __HAL_UNLOCK(hi2c);
1656
1657 /* Note : The I2C interrupts must be enabled after unlocking current process
1658 to avoid the risk of I2C interrupt handle execution before current
1659 process unlock */
1660 /* Enable ERR, STOP, NACK, ADDR interrupts */
1661 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
1662
1663 /* Enable DMA Request */
1664 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
1665
1666 return HAL_OK;
1667 }
1668 else
1669 {
1670 return HAL_BUSY;
1671 }
1672 }
1673 /**
1674 * @brief Write an amount of data in blocking mode to a specific memory address
1675 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1676 * the configuration information for the specified I2C.
1677 * @param DevAddress: Target device address
1678 * @param MemAddress: Internal memory address
1679 * @param MemAddSize: Size of internal memory address
1680 * @param pData: Pointer to data buffer
1681 * @param Size: Amount of data to be sent
1682 * @param Timeout: Timeout duration
1683 * @retval HAL status
1684 */
1685 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1686 {
1687 uint32_t tickstart = 0;
1688
1689 /* Check the parameters */
1690 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
1691
1692 if(hi2c->State == HAL_I2C_STATE_READY)
1693 {
1694 if((pData == NULL) || (Size == 0))
1695 {
1696 return HAL_ERROR;
1697 }
1698
1699 /* Process Locked */
1700 __HAL_LOCK(hi2c);
1701
1702 /* Init tickstart for timeout management*/
1703 tickstart = HAL_GetTick();
1704
1705 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1706 {
1707 return HAL_TIMEOUT;
1708 }
1709
1710 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1711 hi2c->Mode = HAL_I2C_MODE_MEM;
1712 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1713
1714 /* Prepare transfer parameters */
1715 hi2c->pBuffPtr = pData;
1716 hi2c->XferCount = Size;
1717 hi2c->XferISR = NULL;
1718
1719 /* Send Slave Address and Memory Address */
1720 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
1721 {
1722 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1723 {
1724 /* Process Unlocked */
1725 __HAL_UNLOCK(hi2c);
1726 return HAL_ERROR;
1727 }
1728 else
1729 {
1730 /* Process Unlocked */
1731 __HAL_UNLOCK(hi2c);
1732 return HAL_TIMEOUT;
1733 }
1734 }
1735
1736 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1737 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1738 {
1739 hi2c->XferSize = MAX_NBYTE_SIZE;
1740 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1741 }
1742 else
1743 {
1744 hi2c->XferSize = hi2c->XferCount;
1745 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1746 }
1747
1748 do
1749 {
1750 /* Wait until TXIS flag is set */
1751 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1752 {
1753 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1754 {
1755 return HAL_ERROR;
1756 }
1757 else
1758 {
1759 return HAL_TIMEOUT;
1760 }
1761 }
1762
1763 /* Write data to TXDR */
1764 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
1765 hi2c->XferCount--;
1766 hi2c->XferSize--;
1767
1768 if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
1769 {
1770 /* Wait until TCR flag is set */
1771 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1772 {
1773 return HAL_TIMEOUT;
1774 }
1775
1776 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1777 {
1778 hi2c->XferSize = MAX_NBYTE_SIZE;
1779 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1780 }
1781 else
1782 {
1783 hi2c->XferSize = hi2c->XferCount;
1784 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1785 }
1786 }
1787
1788 }while(hi2c->XferCount > 0);
1789
1790 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1791 /* Wait until STOPF flag is reset */
1792 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1793 {
1794 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1795 {
1796 return HAL_ERROR;
1797 }
1798 else
1799 {
1800 return HAL_TIMEOUT;
1801 }
1802 }
1803
1804 /* Clear STOP Flag */
1805 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1806
1807 /* Clear Configuration Register 2 */
1808 I2C_RESET_CR2(hi2c);
1809
1810 hi2c->State = HAL_I2C_STATE_READY;
1811 hi2c->Mode = HAL_I2C_MODE_NONE;
1812
1813 /* Process Unlocked */
1814 __HAL_UNLOCK(hi2c);
1815
1816 return HAL_OK;
1817 }
1818 else
1819 {
1820 return HAL_BUSY;
1821 }
1822 }
1823
1824 /**
1825 * @brief Read an amount of data in blocking mode from a specific memory address
1826 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1827 * the configuration information for the specified I2C.
1828 * @param DevAddress: Target device address
1829 * @param MemAddress: Internal memory address
1830 * @param MemAddSize: Size of internal memory address
1831 * @param pData: Pointer to data buffer
1832 * @param Size: Amount of data to be sent
1833 * @param Timeout: Timeout duration
1834 * @retval HAL status
1835 */
1836 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1837 {
1838 uint32_t tickstart = 0;
1839
1840 /* Check the parameters */
1841 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
1842
1843 if(hi2c->State == HAL_I2C_STATE_READY)
1844 {
1845 if((pData == NULL) || (Size == 0))
1846 {
1847 return HAL_ERROR;
1848 }
1849
1850 /* Process Locked */
1851 __HAL_LOCK(hi2c);
1852
1853 /* Init tickstart for timeout management*/
1854 tickstart = HAL_GetTick();
1855
1856 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1857 {
1858 return HAL_TIMEOUT;
1859 }
1860
1861 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1862 hi2c->Mode = HAL_I2C_MODE_MEM;
1863 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1864
1865 /* Prepare transfer parameters */
1866 hi2c->pBuffPtr = pData;
1867 hi2c->XferCount = Size;
1868 hi2c->XferISR = NULL;
1869
1870 /* Send Slave Address and Memory Address */
1871 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
1872 {
1873 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1874 {
1875 /* Process Unlocked */
1876 __HAL_UNLOCK(hi2c);
1877 return HAL_ERROR;
1878 }
1879 else
1880 {
1881 /* Process Unlocked */
1882 __HAL_UNLOCK(hi2c);
1883 return HAL_TIMEOUT;
1884 }
1885 }
1886
1887 /* Send Slave Address */
1888 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1889 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1890 {
1891 hi2c->XferSize = MAX_NBYTE_SIZE;
1892 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
1893 }
1894 else
1895 {
1896 hi2c->XferSize = hi2c->XferCount;
1897 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
1898 }
1899
1900 do
1901 {
1902 /* Wait until RXNE flag is set */
1903 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
1904 {
1905 return HAL_TIMEOUT;
1906 }
1907
1908 /* Read data from RXDR */
1909 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
1910 hi2c->XferSize--;
1911 hi2c->XferCount--;
1912
1913 if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
1914 {
1915 /* Wait until TCR flag is set */
1916 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1917 {
1918 return HAL_TIMEOUT;
1919 }
1920
1921 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1922 {
1923 hi2c->XferSize = MAX_NBYTE_SIZE;
1924 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1925 }
1926 else
1927 {
1928 hi2c->XferSize = hi2c->XferCount;
1929 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1930 }
1931 }
1932 }while(hi2c->XferCount > 0);
1933
1934 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1935 /* Wait until STOPF flag is reset */
1936 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1937 {
1938 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1939 {
1940 return HAL_ERROR;
1941 }
1942 else
1943 {
1944 return HAL_TIMEOUT;
1945 }
1946 }
1947
1948 /* Clear STOP Flag */
1949 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1950
1951 /* Clear Configuration Register 2 */
1952 I2C_RESET_CR2(hi2c);
1953
1954 hi2c->State = HAL_I2C_STATE_READY;
1955 hi2c->Mode = HAL_I2C_MODE_NONE;
1956
1957 /* Process Unlocked */
1958 __HAL_UNLOCK(hi2c);
1959
1960 return HAL_OK;
1961 }
1962 else
1963 {
1964 return HAL_BUSY;
1965 }
1966 }
1967 /**
1968 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
1969 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
1970 * the configuration information for the specified I2C.
1971 * @param DevAddress: Target device address
1972 * @param MemAddress: Internal memory address
1973 * @param MemAddSize: Size of internal memory address
1974 * @param pData: Pointer to data buffer
1975 * @param Size: Amount of data to be sent
1976 * @retval HAL status
1977 */
1978 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
1979 {
1980 uint32_t tickstart = 0;
1981 uint32_t xfermode = 0;
1982
1983 /* Check the parameters */
1984 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
1985
1986 if(hi2c->State == HAL_I2C_STATE_READY)
1987 {
1988 if((pData == NULL) || (Size == 0))
1989 {
1990 return HAL_ERROR;
1991 }
1992
1993 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1994 {
1995 return HAL_BUSY;
1996 }
1997
1998 /* Process Locked */
1999 __HAL_LOCK(hi2c);
2000
2001 /* Init tickstart for timeout management*/
2002 tickstart = HAL_GetTick();
2003
2004 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2005 hi2c->Mode = HAL_I2C_MODE_MEM;
2006 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2007
2008 /* Prepare transfer parameters */
2009 hi2c->pBuffPtr = pData;
2010 hi2c->XferCount = Size;
2011 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2012 hi2c->XferISR = I2C_Master_ISR_IT;
2013
2014 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2015 {
2016 hi2c->XferSize = MAX_NBYTE_SIZE;
2017 xfermode = I2C_RELOAD_MODE;
2018 }
2019 else
2020 {
2021 hi2c->XferSize = hi2c->XferCount;
2022 xfermode = I2C_AUTOEND_MODE;
2023 }
2024
2025 /* Send Slave Address and Memory Address */
2026 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2027 {
2028 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2029 {
2030 /* Process Unlocked */
2031 __HAL_UNLOCK(hi2c);
2032 return HAL_ERROR;
2033 }
2034 else
2035 {
2036 /* Process Unlocked */
2037 __HAL_UNLOCK(hi2c);
2038 return HAL_TIMEOUT;
2039 }
2040 }
2041
2042 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2043 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
2044
2045 /* Process Unlocked */
2046 __HAL_UNLOCK(hi2c);
2047
2048 /* Note : The I2C interrupts must be enabled after unlocking current process
2049 to avoid the risk of I2C interrupt handle execution before current
2050 process unlock */
2051
2052 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2053 /* possible to enable all of these */
2054 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2055 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2056
2057 return HAL_OK;
2058 }
2059 else
2060 {
2061 return HAL_BUSY;
2062 }
2063 }
2064
2065 /**
2066 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2067 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2068 * the configuration information for the specified I2C.
2069 * @param DevAddress: Target device address
2070 * @param MemAddress: Internal memory address
2071 * @param MemAddSize: Size of internal memory address
2072 * @param pData: Pointer to data buffer
2073 * @param Size: Amount of data to be sent
2074 * @retval HAL status
2075 */
2076 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2077 {
2078 uint32_t tickstart = 0;
2079 uint32_t xfermode = 0;
2080
2081 /* Check the parameters */
2082 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2083
2084 if(hi2c->State == HAL_I2C_STATE_READY)
2085 {
2086 if((pData == NULL) || (Size == 0))
2087 {
2088 return HAL_ERROR;
2089 }
2090
2091 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2092 {
2093 return HAL_BUSY;
2094 }
2095
2096 /* Process Locked */
2097 __HAL_LOCK(hi2c);
2098
2099 /* Init tickstart for timeout management*/
2100 tickstart = HAL_GetTick();
2101
2102 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2103 hi2c->Mode = HAL_I2C_MODE_MEM;
2104 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2105
2106 /* Prepare transfer parameters */
2107 hi2c->pBuffPtr = pData;
2108 hi2c->XferCount = Size;
2109 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2110 hi2c->XferISR = I2C_Master_ISR_IT;
2111
2112 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2113 {
2114 hi2c->XferSize = MAX_NBYTE_SIZE;
2115 xfermode = I2C_RELOAD_MODE;
2116 }
2117 else
2118 {
2119 hi2c->XferSize = hi2c->XferCount;
2120 xfermode = I2C_AUTOEND_MODE;
2121 }
2122
2123 /* Send Slave Address and Memory Address */
2124 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2125 {
2126 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2127 {
2128 /* Process Unlocked */
2129 __HAL_UNLOCK(hi2c);
2130 return HAL_ERROR;
2131 }
2132 else
2133 {
2134 /* Process Unlocked */
2135 __HAL_UNLOCK(hi2c);
2136 return HAL_TIMEOUT;
2137 }
2138 }
2139
2140 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2141 I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2142
2143 /* Process Unlocked */
2144 __HAL_UNLOCK(hi2c);
2145
2146 /* Note : The I2C interrupts must be enabled after unlocking current process
2147 to avoid the risk of I2C interrupt handle execution before current
2148 process unlock */
2149
2150 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2151 /* possible to enable all of these */
2152 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2153 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2154
2155 return HAL_OK;
2156 }
2157 else
2158 {
2159 return HAL_BUSY;
2160 }
2161 }
2162 /**
2163 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2164 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2165 * the configuration information for the specified I2C.
2166 * @param DevAddress: Target device address
2167 * @param MemAddress: Internal memory address
2168 * @param MemAddSize: Size of internal memory address
2169 * @param pData: Pointer to data buffer
2170 * @param Size: Amount of data to be sent
2171 * @retval HAL status
2172 */
2173 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2174 {
2175 uint32_t tickstart = 0;
2176 uint32_t xfermode = 0;
2177
2178 /* Check the parameters */
2179 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2180
2181 if(hi2c->State == HAL_I2C_STATE_READY)
2182 {
2183 if((pData == NULL) || (Size == 0))
2184 {
2185 return HAL_ERROR;
2186 }
2187
2188 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2189 {
2190 return HAL_BUSY;
2191 }
2192
2193 /* Process Locked */
2194 __HAL_LOCK(hi2c);
2195
2196 /* Init tickstart for timeout management*/
2197 tickstart = HAL_GetTick();
2198
2199 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2200 hi2c->Mode = HAL_I2C_MODE_MEM;
2201 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2202
2203 /* Prepare transfer parameters */
2204 hi2c->pBuffPtr = pData;
2205 hi2c->XferCount = Size;
2206 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2207 hi2c->XferISR = I2C_Master_ISR_DMA;
2208
2209 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2210 {
2211 hi2c->XferSize = MAX_NBYTE_SIZE;
2212 xfermode = I2C_RELOAD_MODE;
2213 }
2214 else
2215 {
2216 hi2c->XferSize = hi2c->XferCount;
2217 xfermode = I2C_AUTOEND_MODE;
2218 }
2219
2220 /* Send Slave Address and Memory Address */
2221 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2222 {
2223 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2224 {
2225 /* Process Unlocked */
2226 __HAL_UNLOCK(hi2c);
2227 return HAL_ERROR;
2228 }
2229 else
2230 {
2231 /* Process Unlocked */
2232 __HAL_UNLOCK(hi2c);
2233 return HAL_TIMEOUT;
2234 }
2235 }
2236
2237 /* Set the I2C DMA transfer complete callback */
2238 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2239
2240 /* Set the DMA error callback */
2241 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2242
2243 /* Set the unused DMA callbacks to NULL */
2244 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2245 hi2c->hdmatx->XferAbortCallback = NULL;
2246
2247 /* Enable the DMA channel */
2248 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
2249
2250 /* Send Slave Address */
2251 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2252 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
2253
2254 /* Update XferCount value */
2255 hi2c->XferCount -= hi2c->XferSize;
2256
2257 /* Process Unlocked */
2258 __HAL_UNLOCK(hi2c);
2259
2260 /* Note : The I2C interrupts must be enabled after unlocking current process
2261 to avoid the risk of I2C interrupt handle execution before current
2262 process unlock */
2263 /* Enable ERR and NACK interrupts */
2264 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2265
2266 /* Enable DMA Request */
2267 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2268
2269 return HAL_OK;
2270 }
2271 else
2272 {
2273 return HAL_BUSY;
2274 }
2275 }
2276
2277 /**
2278 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
2279 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2280 * the configuration information for the specified I2C.
2281 * @param DevAddress: Target device address
2282 * @param MemAddress: Internal memory address
2283 * @param MemAddSize: Size of internal memory address
2284 * @param pData: Pointer to data buffer
2285 * @param Size: Amount of data to be read
2286 * @retval HAL status
2287 */
2288 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2289 {
2290 uint32_t tickstart = 0;
2291 uint32_t xfermode = 0;
2292
2293 /* Check the parameters */
2294 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2295
2296 if(hi2c->State == HAL_I2C_STATE_READY)
2297 {
2298 if((pData == NULL) || (Size == 0))
2299 {
2300 return HAL_ERROR;
2301 }
2302
2303 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2304 {
2305 return HAL_BUSY;
2306 }
2307
2308 /* Process Locked */
2309 __HAL_LOCK(hi2c);
2310
2311 /* Init tickstart for timeout management*/
2312 tickstart = HAL_GetTick();
2313
2314 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2315 hi2c->Mode = HAL_I2C_MODE_MEM;
2316 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2317
2318 /* Prepare transfer parameters */
2319 hi2c->pBuffPtr = pData;
2320 hi2c->XferCount = Size;
2321 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2322 hi2c->XferISR = I2C_Master_ISR_DMA;
2323
2324 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2325 {
2326 hi2c->XferSize = MAX_NBYTE_SIZE;
2327 xfermode = I2C_RELOAD_MODE;
2328 }
2329 else
2330 {
2331 hi2c->XferSize = hi2c->XferCount;
2332 xfermode = I2C_AUTOEND_MODE;
2333 }
2334
2335 /* Send Slave Address and Memory Address */
2336 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2337 {
2338 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2339 {
2340 /* Process Unlocked */
2341 __HAL_UNLOCK(hi2c);
2342 return HAL_ERROR;
2343 }
2344 else
2345 {
2346 /* Process Unlocked */
2347 __HAL_UNLOCK(hi2c);
2348 return HAL_TIMEOUT;
2349 }
2350 }
2351
2352 /* Set the I2C DMA transfer complete callback */
2353 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2354
2355 /* Set the DMA error callback */
2356 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2357
2358 /* Set the unused DMA callbacks to NULL */
2359 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2360 hi2c->hdmarx->XferAbortCallback = NULL;
2361
2362 /* Enable the DMA channel */
2363 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
2364
2365 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2366 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2367
2368 /* Update XferCount value */
2369 hi2c->XferCount -= hi2c->XferSize;
2370
2371 /* Process Unlocked */
2372 __HAL_UNLOCK(hi2c);
2373
2374 /* Enable DMA Request */
2375 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2376
2377 /* Note : The I2C interrupts must be enabled after unlocking current process
2378 to avoid the risk of I2C interrupt handle execution before current
2379 process unlock */
2380 /* Enable ERR and NACK interrupts */
2381 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2382
2383 return HAL_OK;
2384 }
2385 else
2386 {
2387 return HAL_BUSY;
2388 }
2389 }
2390
2391 /**
2392 * @brief Checks if target device is ready for communication.
2393 * @note This function is used with Memory devices
2394 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2395 * the configuration information for the specified I2C.
2396 * @param DevAddress: Target device address
2397 * @param Trials: Number of trials
2398 * @param Timeout: Timeout duration
2399 * @retval HAL status
2400 */
2401 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
2402 {
2403 uint32_t tickstart = 0;
2404
2405 __IO uint32_t I2C_Trials = 0;
2406
2407 if(hi2c->State == HAL_I2C_STATE_READY)
2408 {
2409 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2410 {
2411 return HAL_BUSY;
2412 }
2413
2414 /* Process Locked */
2415 __HAL_LOCK(hi2c);
2416
2417 hi2c->State = HAL_I2C_STATE_BUSY;
2418 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2419
2420 do
2421 {
2422 /* Generate Start */
2423 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
2424
2425 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2426 /* Wait until STOPF flag is set or a NACK flag is set*/
2427 tickstart = HAL_GetTick();
2428 while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
2429 {
2430 if(Timeout != HAL_MAX_DELAY)
2431 {
2432 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
2433 {
2434 /* Device is ready */
2435 hi2c->State = HAL_I2C_STATE_READY;
2436 /* Process Unlocked */
2437 __HAL_UNLOCK(hi2c);
2438 return HAL_TIMEOUT;
2439 }
2440 }
2441 }
2442
2443 /* Check if the NACKF flag has not been set */
2444 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
2445 {
2446 /* Wait until STOPF flag is reset */
2447 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
2448 {
2449 return HAL_TIMEOUT;
2450 }
2451
2452 /* Clear STOP Flag */
2453 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2454
2455 /* Device is ready */
2456 hi2c->State = HAL_I2C_STATE_READY;
2457
2458 /* Process Unlocked */
2459 __HAL_UNLOCK(hi2c);
2460
2461 return HAL_OK;
2462 }
2463 else
2464 {
2465 /* Wait until STOPF flag is reset */
2466 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
2467 {
2468 return HAL_TIMEOUT;
2469 }
2470
2471 /* Clear NACK Flag */
2472 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
2473
2474 /* Clear STOP Flag, auto generated with autoend*/
2475 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2476 }
2477
2478 /* Check if the maximum allowed number of trials has been reached */
2479 if (I2C_Trials++ == Trials)
2480 {
2481 /* Generate Stop */
2482 hi2c->Instance->CR2 |= I2C_CR2_STOP;
2483
2484 /* Wait until STOPF flag is reset */
2485 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
2486 {
2487 return HAL_TIMEOUT;
2488 }
2489
2490 /* Clear STOP Flag */
2491 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2492 }
2493 }while(I2C_Trials < Trials);
2494
2495 hi2c->State = HAL_I2C_STATE_READY;
2496
2497 /* Process Unlocked */
2498 __HAL_UNLOCK(hi2c);
2499
2500 return HAL_TIMEOUT;
2501 }
2502 else
2503 {
2504 return HAL_BUSY;
2505 }
2506 }
2507
2508 /**
2509 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
2510 * @note This interface allow to manage repeated start condition when a direction change during transfer
2511 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2512 * the configuration information for the specified I2C.
2513 * @param DevAddress: Target device address
2514 * @param pData: Pointer to data buffer
2515 * @param Size: Amount of data to be sent
2516 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
2517 * @retval HAL status
2518 */
2519 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2520 {
2521 uint32_t xfermode = 0;
2522 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
2523
2524 /* Check the parameters */
2525 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2526
2527 if(hi2c->State == HAL_I2C_STATE_READY)
2528 {
2529 /* Process Locked */
2530 __HAL_LOCK(hi2c);
2531
2532 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2533 hi2c->Mode = HAL_I2C_MODE_MASTER;
2534 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2535
2536 /* Prepare transfer parameters */
2537 hi2c->pBuffPtr = pData;
2538 hi2c->XferCount = Size;
2539 hi2c->XferOptions = XferOptions;
2540 hi2c->XferISR = I2C_Master_ISR_IT;
2541
2542 /* If size > MAX_NBYTE_SIZE, use reload mode */
2543 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2544 {
2545 hi2c->XferSize = MAX_NBYTE_SIZE;
2546 xfermode = I2C_RELOAD_MODE;
2547 }
2548 else
2549 {
2550 hi2c->XferSize = hi2c->XferCount;
2551 xfermode = hi2c->XferOptions;
2552
2553 /* If transfer direction not change, do not generate Restart Condition */
2554 /* Mean Previous state is same as current state */
2555 if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX)
2556 {
2557 xferrequest = I2C_NO_STARTSTOP;
2558 }
2559 }
2560
2561 /* Send Slave Address and set NBYTES to write */
2562 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
2563
2564 /* Process Unlocked */
2565 __HAL_UNLOCK(hi2c);
2566
2567 /* Note : The I2C interrupts must be enabled after unlocking current process
2568 to avoid the risk of I2C interrupt handle execution before current
2569 process unlock */
2570 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2571
2572 return HAL_OK;
2573 }
2574 else
2575 {
2576 return HAL_BUSY;
2577 }
2578 }
2579
2580 /**
2581 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
2582 * @note This interface allow to manage repeated start condition when a direction change during transfer
2583 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2584 * the configuration information for the specified I2C.
2585 * @param DevAddress: Target device address
2586 * @param pData: Pointer to data buffer
2587 * @param Size: Amount of data to be sent
2588 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
2589 * @retval HAL status
2590 */
2591 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2592 {
2593 uint32_t xfermode = 0;
2594 uint32_t xferrequest = I2C_GENERATE_START_READ;
2595
2596 /* Check the parameters */
2597 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2598
2599 if(hi2c->State == HAL_I2C_STATE_READY)
2600 {
2601 /* Process Locked */
2602 __HAL_LOCK(hi2c);
2603
2604 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2605 hi2c->Mode = HAL_I2C_MODE_MASTER;
2606 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2607
2608 /* Prepare transfer parameters */
2609 hi2c->pBuffPtr = pData;
2610 hi2c->XferCount = Size;
2611 hi2c->XferOptions = XferOptions;
2612 hi2c->XferISR = I2C_Master_ISR_IT;
2613
2614 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
2615 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2616 {
2617 hi2c->XferSize = MAX_NBYTE_SIZE;
2618 xfermode = I2C_RELOAD_MODE;
2619 }
2620 else
2621 {
2622 hi2c->XferSize = hi2c->XferCount;
2623 xfermode = hi2c->XferOptions;
2624
2625 /* If transfer direction not change, do not generate Restart Condition */
2626 /* Mean Previous state is same as current state */
2627 if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
2628 {
2629 xferrequest = I2C_NO_STARTSTOP;
2630 }
2631 }
2632
2633 /* Send Slave Address and set NBYTES to read */
2634 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
2635
2636 /* Process Unlocked */
2637 __HAL_UNLOCK(hi2c);
2638
2639 /* Note : The I2C interrupts must be enabled after unlocking current process
2640 to avoid the risk of I2C interrupt handle execution before current
2641 process unlock */
2642 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2643
2644 return HAL_OK;
2645 }
2646 else
2647 {
2648 return HAL_BUSY;
2649 }
2650 }
2651
2652 /**
2653 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
2654 * @note This interface allow to manage repeated start condition when a direction change during transfer
2655 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2656 * the configuration information for the specified I2C.
2657 * @param pData: Pointer to data buffer
2658 * @param Size: Amount of data to be sent
2659 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
2660 * @retval HAL status
2661 */
2662 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2663 {
2664 /* Check the parameters */
2665 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2666
2667 if(hi2c->State == HAL_I2C_STATE_LISTEN)
2668 {
2669 if((pData == NULL) || (Size == 0))
2670 {
2671 return HAL_ERROR;
2672 }
2673
2674 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
2675 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
2676
2677 /* Process Locked */
2678 __HAL_LOCK(hi2c);
2679
2680 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
2681 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2682 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2683
2684 /* Enable Address Acknowledge */
2685 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2686
2687 /* Prepare transfer parameters */
2688 hi2c->pBuffPtr = pData;
2689 hi2c->XferCount = Size;
2690 hi2c->XferSize = hi2c->XferCount;
2691 hi2c->XferOptions = XferOptions;
2692 hi2c->XferISR = I2C_Slave_ISR_IT;
2693
2694 if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
2695 {
2696 /* Clear ADDR flag after prepare the transfer parameters */
2697 /* This action will generate an acknowledge to the Master */
2698 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
2699 }
2700
2701 /* Process Unlocked */
2702 __HAL_UNLOCK(hi2c);
2703
2704 /* Note : The I2C interrupts must be enabled after unlocking current process
2705 to avoid the risk of I2C interrupt handle execution before current
2706 process unlock */
2707 /* REnable ADDR interrupt */
2708 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
2709
2710 return HAL_OK;
2711 }
2712 else
2713 {
2714 return HAL_ERROR;
2715 }
2716 }
2717
2718 /**
2719 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
2720 * @note This interface allow to manage repeated start condition when a direction change during transfer
2721 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2722 * the configuration information for the specified I2C.
2723 * @param pData: Pointer to data buffer
2724 * @param Size: Amount of data to be sent
2725 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
2726 * @retval HAL status
2727 */
2728 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2729 {
2730 /* Check the parameters */
2731 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2732
2733 if(hi2c->State == HAL_I2C_STATE_LISTEN)
2734 {
2735 if((pData == NULL) || (Size == 0))
2736 {
2737 return HAL_ERROR;
2738 }
2739
2740 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
2741 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
2742
2743 /* Process Locked */
2744 __HAL_LOCK(hi2c);
2745
2746 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
2747 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2748 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2749
2750 /* Enable Address Acknowledge */
2751 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2752
2753 /* Prepare transfer parameters */
2754 hi2c->pBuffPtr = pData;
2755 hi2c->XferCount = Size;
2756 hi2c->XferSize = hi2c->XferCount;
2757 hi2c->XferOptions = XferOptions;
2758 hi2c->XferISR = I2C_Slave_ISR_IT;
2759
2760 if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
2761 {
2762 /* Clear ADDR flag after prepare the transfer parameters */
2763 /* This action will generate an acknowledge to the Master */
2764 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
2765 }
2766
2767 /* Process Unlocked */
2768 __HAL_UNLOCK(hi2c);
2769
2770 /* Note : The I2C interrupts must be enabled after unlocking current process
2771 to avoid the risk of I2C interrupt handle execution before current
2772 process unlock */
2773 /* REnable ADDR interrupt */
2774 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
2775
2776 return HAL_OK;
2777 }
2778 else
2779 {
2780 return HAL_ERROR;
2781 }
2782 }
2783
2784 /**
2785 * @brief Enable the Address listen mode with Interrupt.
2786 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2787 * the configuration information for the specified I2C.
2788 * @retval HAL status
2789 */
2790 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
2791 {
2792 if(hi2c->State == HAL_I2C_STATE_READY)
2793 {
2794 hi2c->State = HAL_I2C_STATE_LISTEN;
2795 hi2c->XferISR = I2C_Slave_ISR_IT;
2796
2797 /* Enable the Address Match interrupt */
2798 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2799
2800 return HAL_OK;
2801 }
2802 else
2803 {
2804 return HAL_BUSY;
2805 }
2806 }
2807
2808 /**
2809 * @brief Disable the Address listen mode with Interrupt.
2810 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2811 * the configuration information for the specified I2C
2812 * @retval HAL status
2813 */
2814 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
2815 {
2816 /* Declaration of tmp to prevent undefined behavior of volatile usage */
2817 uint32_t tmp;
2818
2819 /* Disable Address listen mode only if a transfer is not ongoing */
2820 if(hi2c->State == HAL_I2C_STATE_LISTEN)
2821 {
2822 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
2823 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
2824 hi2c->State = HAL_I2C_STATE_READY;
2825 hi2c->Mode = HAL_I2C_MODE_NONE;
2826 hi2c->XferISR = NULL;
2827
2828 /* Disable the Address Match interrupt */
2829 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2830
2831 return HAL_OK;
2832 }
2833 else
2834 {
2835 return HAL_BUSY;
2836 }
2837 }
2838
2839 /**
2840 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
2841 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2842 * the configuration information for the specified I2C.
2843 * @param DevAddress: Target device address
2844 * @retval HAL status
2845 */
2846 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
2847 {
2848 if(hi2c->Mode == HAL_I2C_MODE_MASTER)
2849 {
2850 /* Process Locked */
2851 __HAL_LOCK(hi2c);
2852
2853 /* Disable Interrupts */
2854 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
2855 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
2856
2857 /* Set State at HAL_I2C_STATE_ABORT */
2858 hi2c->State = HAL_I2C_STATE_ABORT;
2859
2860 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
2861 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
2862 I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
2863
2864 /* Process Unlocked */
2865 __HAL_UNLOCK(hi2c);
2866
2867 /* Note : The I2C interrupts must be enabled after unlocking current process
2868 to avoid the risk of I2C interrupt handle execution before current
2869 process unlock */
2870 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
2871
2872 return HAL_OK;
2873 }
2874 else
2875 {
2876 /* Wrong usage of abort function */
2877 /* This function should be used only in case of abort monitored by master device */
2878 return HAL_ERROR;
2879 }
2880 }
2881
2882 /**
2883 * @}
2884 */
2885
2886 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
2887 * @{
2888 */
2889
2890 /**
2891 * @brief This function handles I2C event interrupt request.
2892 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2893 * the configuration information for the specified I2C.
2894 * @retval None
2895 */
2896 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
2897 {
2898 /* Get current IT Flags and IT sources value */
2899 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
2900 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
2901
2902 /* I2C events treatment -------------------------------------*/
2903 if(hi2c->XferISR != NULL)
2904 {
2905 hi2c->XferISR(hi2c, itflags, itsources);
2906 }
2907 }
2908
2909 /**
2910 * @brief This function handles I2C error interrupt request.
2911 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2912 * the configuration information for the specified I2C.
2913 * @retval None
2914 */
2915 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
2916 {
2917 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
2918 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
2919
2920 /* I2C Bus error interrupt occurred ------------------------------------*/
2921 if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
2922 {
2923 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
2924
2925 /* Clear BERR flag */
2926 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
2927 }
2928
2929 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
2930 if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
2931 {
2932 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
2933
2934 /* Clear OVR flag */
2935 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
2936 }
2937
2938 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
2939 if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
2940 {
2941 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
2942
2943 /* Clear ARLO flag */
2944 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
2945 }
2946
2947 /* Call the Error Callback in case of Error detected */
2948 if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
2949 {
2950 I2C_ITError(hi2c, hi2c->ErrorCode);
2951 }
2952 }
2953
2954 /**
2955 * @brief Master Tx Transfer completed callback.
2956 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2957 * the configuration information for the specified I2C.
2958 * @retval None
2959 */
2960 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
2961 {
2962 /* Prevent unused argument(s) compilation warning */
2963 UNUSED(hi2c);
2964
2965 /* NOTE : This function should not be modified, when the callback is needed,
2966 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
2967 */
2968 }
2969
2970 /**
2971 * @brief Master Rx Transfer completed callback.
2972 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2973 * the configuration information for the specified I2C.
2974 * @retval None
2975 */
2976 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
2977 {
2978 /* Prevent unused argument(s) compilation warning */
2979 UNUSED(hi2c);
2980
2981 /* NOTE : This function should not be modified, when the callback is needed,
2982 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
2983 */
2984 }
2985
2986 /** @brief Slave Tx Transfer completed callback.
2987 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
2988 * the configuration information for the specified I2C.
2989 * @retval None
2990 */
2991 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
2992 {
2993 /* Prevent unused argument(s) compilation warning */
2994 UNUSED(hi2c);
2995
2996 /* NOTE : This function should not be modified, when the callback is needed,
2997 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
2998 */
2999 }
3000
3001 /**
3002 * @brief Slave Rx Transfer completed callback.
3003 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3004 * the configuration information for the specified I2C.
3005 * @retval None
3006 */
3007 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
3008 {
3009 /* Prevent unused argument(s) compilation warning */
3010 UNUSED(hi2c);
3011
3012 /* NOTE : This function should not be modified, when the callback is needed,
3013 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
3014 */
3015 }
3016
3017 /**
3018 * @brief Slave Address Match callback.
3019 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3020 * the configuration information for the specified I2C.
3021 * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
3022 * @param AddrMatchCode: Address Match Code
3023 * @retval None
3024 */
3025 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
3026 {
3027 /* Prevent unused argument(s) compilation warning */
3028 UNUSED(hi2c);
3029 UNUSED(TransferDirection);
3030 UNUSED(AddrMatchCode);
3031
3032 /* NOTE : This function should not be modified, when the callback is needed,
3033 the HAL_I2C_AddrCallback() could be implemented in the user file
3034 */
3035 }
3036
3037 /**
3038 * @brief Listen Complete callback.
3039 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3040 * the configuration information for the specified I2C.
3041 * @retval None
3042 */
3043 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
3044 {
3045 /* Prevent unused argument(s) compilation warning */
3046 UNUSED(hi2c);
3047
3048 /* NOTE : This function should not be modified, when the callback is needed,
3049 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
3050 */
3051 }
3052
3053 /**
3054 * @brief Memory Tx Transfer completed callback.
3055 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3056 * the configuration information for the specified I2C.
3057 * @retval None
3058 */
3059 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
3060 {
3061 /* Prevent unused argument(s) compilation warning */
3062 UNUSED(hi2c);
3063
3064 /* NOTE : This function should not be modified, when the callback is needed,
3065 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
3066 */
3067 }
3068
3069 /**
3070 * @brief Memory Rx Transfer completed callback.
3071 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3072 * the configuration information for the specified I2C.
3073 * @retval None
3074 */
3075 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
3076 {
3077 /* Prevent unused argument(s) compilation warning */
3078 UNUSED(hi2c);
3079
3080 /* NOTE : This function should not be modified, when the callback is needed,
3081 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
3082 */
3083 }
3084
3085 /**
3086 * @brief I2C error callback.
3087 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3088 * the configuration information for the specified I2C.
3089 * @retval None
3090 */
3091 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
3092 {
3093 /* Prevent unused argument(s) compilation warning */
3094 UNUSED(hi2c);
3095
3096 /* NOTE : This function should not be modified, when the callback is needed,
3097 the HAL_I2C_ErrorCallback could be implemented in the user file
3098 */
3099 }
3100
3101 /**
3102 * @brief I2C abort callback.
3103 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3104 * the configuration information for the specified I2C.
3105 * @retval None
3106 */
3107 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
3108 {
3109 /* Prevent unused argument(s) compilation warning */
3110 UNUSED(hi2c);
3111
3112 /* NOTE : This function should not be modified, when the callback is needed,
3113 the HAL_I2C_AbortCpltCallback could be implemented in the user file
3114 */
3115 }
3116
3117 /**
3118 * @}
3119 */
3120
3121 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
3122 * @brief Peripheral State, Mode and Error functions
3123 *
3124 @verbatim
3125 ===============================================================================
3126 ##### Peripheral State, Mode and Error functions #####
3127 ===============================================================================
3128 [..]
3129 This subsection permit to get in run-time the status of the peripheral
3130 and the data flow.
3131
3132 @endverbatim
3133 * @{
3134 */
3135
3136 /**
3137 * @brief Return the I2C handle state.
3138 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3139 * the configuration information for the specified I2C.
3140 * @retval HAL state
3141 */
3142 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
3143 {
3144 /* Return I2C handle state */
3145 return hi2c->State;
3146 }
3147
3148 /**
3149 * @brief Returns the I2C Master, Slave, Memory or no mode.
3150 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3151 * the configuration information for I2C module
3152 * @retval HAL mode
3153 */
3154 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
3155 {
3156 return hi2c->Mode;
3157 }
3158
3159 /**
3160 * @brief Return the I2C error code.
3161 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3162 * the configuration information for the specified I2C.
3163 * @retval I2C Error Code
3164 */
3165 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
3166 {
3167 return hi2c->ErrorCode;
3168 }
3169
3170 /**
3171 * @}
3172 */
3173
3174 /**
3175 * @}
3176 */
3177
3178 /** @addtogroup I2C_Private_Functions
3179 * @{
3180 */
3181
3182 /**
3183 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
3184 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3185 * the configuration information for the specified I2C.
3186 * @param ITFlags: Interrupt flags to handle.
3187 * @param ITSources: Interrupt sources enabled.
3188 * @retval HAL status
3189 */
3190 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3191 {
3192 uint16_t devaddress = 0;
3193
3194 /* Process Locked */
3195 __HAL_LOCK(hi2c);
3196
3197 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3198 {
3199 /* Clear NACK Flag */
3200 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3201
3202 /* Set corresponding Error Code */
3203 /* No need to generate STOP, it is automatically done */
3204 /* Error callback will be send during stop flag treatment */
3205 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3206
3207 /* Flush TX register */
3208 I2C_Flush_TXDR(hi2c);
3209 }
3210 else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
3211 {
3212 /* Read data from RXDR */
3213 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
3214 hi2c->XferSize--;
3215 hi2c->XferCount--;
3216 }
3217 else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
3218 {
3219 /* Write data to TXDR */
3220 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
3221 hi2c->XferSize--;
3222 hi2c->XferCount--;
3223 }
3224 else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
3225 {
3226 if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
3227 {
3228 devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
3229
3230 if(hi2c->XferCount > MAX_NBYTE_SIZE)
3231 {
3232 hi2c->XferSize = MAX_NBYTE_SIZE;
3233 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
3234 }
3235 else
3236 {
3237 hi2c->XferSize = hi2c->XferCount;
3238 if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
3239 {
3240 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
3241 }
3242 else
3243 {
3244 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
3245 }
3246 }
3247 }
3248 else
3249 {
3250 /* Call TxCpltCallback() if no stop mode is set */
3251 if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
3252 {
3253 /* Call I2C Master Sequential complete process */
3254 I2C_ITMasterSequentialCplt(hi2c);
3255 }
3256 else
3257 {
3258 /* Wrong size Status regarding TCR flag event */
3259 /* Call the corresponding callback to inform upper layer of End of Transfer */
3260 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
3261 }
3262 }
3263 }
3264 else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
3265 {
3266 if(hi2c->XferCount == 0)
3267 {
3268 if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
3269 {
3270 /* Call I2C Master Sequential complete process */
3271 I2C_ITMasterSequentialCplt(hi2c);
3272 }
3273 }
3274 else
3275 {
3276 /* Wrong size Status regarding TC flag event */
3277 /* Call the corresponding callback to inform upper layer of End of Transfer */
3278 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
3279 }
3280 }
3281
3282 if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3283 {
3284 /* Call I2C Master complete process */
3285 I2C_ITMasterCplt(hi2c, ITFlags);
3286 }
3287
3288 /* Process Unlocked */
3289 __HAL_UNLOCK(hi2c);
3290
3291 return HAL_OK;
3292 }
3293
3294 /**
3295 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
3296 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3297 * the configuration information for the specified I2C.
3298 * @param ITFlags: Interrupt flags to handle.
3299 * @param ITSources: Interrupt sources enabled.
3300 * @retval HAL status
3301 */
3302 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3303 {
3304 /* Process locked */
3305 __HAL_LOCK(hi2c);
3306
3307 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3308 {
3309 /* Check that I2C transfer finished */
3310 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
3311 /* Mean XferCount == 0*/
3312 /* So clear Flag NACKF only */
3313 if(hi2c->XferCount == 0)
3314 {
3315 if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
3316 (hi2c->State == HAL_I2C_STATE_LISTEN))
3317 {
3318 /* Call I2C Listen complete process */
3319 I2C_ITListenCplt(hi2c, ITFlags);
3320 }
3321 else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
3322 {
3323 /* Clear NACK Flag */
3324 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3325
3326 /* Flush TX register */
3327 I2C_Flush_TXDR(hi2c);
3328
3329 /* Last Byte is Transmitted */
3330 /* Call I2C Slave Sequential complete process */
3331 I2C_ITSlaveSequentialCplt(hi2c);
3332 }
3333 else
3334 {
3335 /* Clear NACK Flag */
3336 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3337 }
3338 }
3339 else
3340 {
3341 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
3342 /* Clear NACK Flag */
3343 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3344
3345 /* Set ErrorCode corresponding to a Non-Acknowledge */
3346 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3347 }
3348 }
3349 else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
3350 {
3351 if(hi2c->XferCount > 0)
3352 {
3353 /* Read data from RXDR */
3354 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
3355 hi2c->XferSize--;
3356 hi2c->XferCount--;
3357 }
3358
3359 if((hi2c->XferCount == 0) && \
3360 (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
3361 {
3362 /* Call I2C Slave Sequential complete process */
3363 I2C_ITSlaveSequentialCplt(hi2c);
3364 }
3365 }
3366 else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
3367 {
3368 I2C_ITAddrCplt(hi2c, ITFlags);
3369 }
3370 else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
3371 {
3372 /* Write data to TXDR only if XferCount not reach "0" */
3373 /* A TXIS flag can be set, during STOP treatment */
3374 /* Check if all Datas have already been sent */
3375 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
3376 if(hi2c->XferCount > 0)
3377 {
3378 /* Write data to TXDR */
3379 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
3380 hi2c->XferCount--;
3381 hi2c->XferSize--;
3382 }
3383 else
3384 {
3385 if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
3386 {
3387 /* Last Byte is Transmitted */
3388 /* Call I2C Slave Sequential complete process */
3389 I2C_ITSlaveSequentialCplt(hi2c);
3390 }
3391 }
3392 }
3393
3394 /* Check if STOPF is set */
3395 if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3396 {
3397 /* Call I2C Slave complete process */
3398 I2C_ITSlaveCplt(hi2c, ITFlags);
3399 }
3400
3401 /* Process Unlocked */
3402 __HAL_UNLOCK(hi2c);
3403
3404 return HAL_OK;
3405 }
3406
3407 /**
3408 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
3409 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3410 * the configuration information for the specified I2C.
3411 * @param ITFlags: Interrupt flags to handle.
3412 * @param ITSources: Interrupt sources enabled.
3413 * @retval HAL status
3414 */
3415 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3416 {
3417 uint16_t devaddress = 0;
3418 uint32_t xfermode = 0;
3419
3420 /* Process Locked */
3421 __HAL_LOCK(hi2c);
3422
3423 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3424 {
3425 /* Clear NACK Flag */
3426 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3427
3428 /* Set corresponding Error Code */
3429 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3430
3431 /* No need to generate STOP, it is automatically done */
3432 /* But enable STOP interrupt, to treat it */
3433 /* Error callback will be send during stop flag treatment */
3434 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
3435
3436 /* Flush TX register */
3437 I2C_Flush_TXDR(hi2c);
3438 }
3439 else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
3440 {
3441 /* Disable TC interrupt */
3442 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
3443
3444 if(hi2c->XferCount != 0)
3445 {
3446 /* Recover Slave address */
3447 devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
3448
3449 /* Prepare the new XferSize to transfer */
3450 if(hi2c->XferCount > MAX_NBYTE_SIZE)
3451 {
3452 hi2c->XferSize = MAX_NBYTE_SIZE;
3453 xfermode = I2C_RELOAD_MODE;
3454 }
3455 else
3456 {
3457 hi2c->XferSize = hi2c->XferCount;
3458 xfermode = I2C_AUTOEND_MODE;
3459 }
3460
3461 /* Set the new XferSize in Nbytes register */
3462 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
3463
3464 /* Update XferCount value */
3465 hi2c->XferCount -= hi2c->XferSize;
3466
3467 /* Enable DMA Request */
3468 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
3469 {
3470 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3471 }
3472 else
3473 {
3474 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3475 }
3476 }
3477 else
3478 {
3479 /* Wrong size Status regarding TCR flag event */
3480 /* Call the corresponding callback to inform upper layer of End of Transfer */
3481 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
3482 }
3483 }
3484 else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3485 {
3486 /* Call I2C Master complete process */
3487 I2C_ITMasterCplt(hi2c, ITFlags);
3488 }
3489
3490 /* Process Unlocked */
3491 __HAL_UNLOCK(hi2c);
3492
3493 return HAL_OK;
3494 }
3495
3496 /**
3497 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
3498 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3499 * the configuration information for the specified I2C.
3500 * @param ITFlags: Interrupt flags to handle.
3501 * @param ITSources: Interrupt sources enabled.
3502 * @retval HAL status
3503 */
3504 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3505 {
3506 /* Process locked */
3507 __HAL_LOCK(hi2c);
3508
3509 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3510 {
3511 /* Check that I2C transfer finished */
3512 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
3513 /* Mean XferCount == 0 */
3514 /* So clear Flag NACKF only */
3515 if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0)
3516 {
3517 /* Clear NACK Flag */
3518 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3519 }
3520 else
3521 {
3522 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
3523 /* Clear NACK Flag */
3524 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3525
3526 /* Set ErrorCode corresponding to a Non-Acknowledge */
3527 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3528 }
3529 }
3530 else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
3531 {
3532 /* Clear ADDR flag */
3533 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3534 }
3535 else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3536 {
3537 /* Call I2C Slave complete process */
3538 I2C_ITSlaveCplt(hi2c, ITFlags);
3539 }
3540
3541 /* Process Unlocked */
3542 __HAL_UNLOCK(hi2c);
3543
3544 return HAL_OK;
3545 }
3546
3547 /**
3548 * @brief Master sends target device address followed by internal memory address for write request.
3549 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3550 * the configuration information for the specified I2C.
3551 * @param DevAddress: Target device address
3552 * @param MemAddress: Internal memory address
3553 * @param MemAddSize: Size of internal memory address
3554 * @param Timeout: Timeout duration
3555 * @param Tickstart Tick start value
3556 * @retval HAL status
3557 */
3558 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
3559 {
3560 I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3561
3562 /* Wait until TXIS flag is set */
3563 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3564 {
3565 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3566 {
3567 return HAL_ERROR;
3568 }
3569 else
3570 {
3571 return HAL_TIMEOUT;
3572 }
3573 }
3574
3575 /* If Memory address size is 8Bit */
3576 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
3577 {
3578 /* Send Memory Address */
3579 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3580 }
3581 /* If Memory address size is 16Bit */
3582 else
3583 {
3584 /* Send MSB of Memory Address */
3585 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3586
3587 /* Wait until TXIS flag is set */
3588 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3589 {
3590 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3591 {
3592 return HAL_ERROR;
3593 }
3594 else
3595 {
3596 return HAL_TIMEOUT;
3597 }
3598 }
3599
3600 /* Send LSB of Memory Address */
3601 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3602 }
3603
3604 /* Wait until TCR flag is set */
3605 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
3606 {
3607 return HAL_TIMEOUT;
3608 }
3609
3610 return HAL_OK;
3611 }
3612
3613 /**
3614 * @brief Master sends target device address followed by internal memory address for read request.
3615 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
3616 * the configuration information for the specified I2C.
3617 * @param DevAddress: Target device address
3618 * @param MemAddress: Internal memory address
3619 * @param MemAddSize: Size of internal memory address
3620 * @param Timeout: Timeout duration
3621 * @param Tickstart Tick start value
3622 * @retval HAL status
3623 */
3624 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
3625 {
3626 I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3627
3628 /* Wait until TXIS flag is set */
3629 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3630 {
3631 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3632 {
3633 return HAL_ERROR;
3634 }
3635 else
3636 {
3637 return HAL_TIMEOUT;
3638 }
3639 }
3640
3641 /* If Memory address size is 8Bit */
3642 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
3643 {
3644 /* Send Memory Address */
3645 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3646 }
3647 /* If Memory address size is 16Bit */
3648 else
3649 {
3650 /* Send MSB of Memory Address */
3651 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3652
3653 /* Wait until TXIS flag is set */
3654 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3655 {
3656 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3657 {
3658 return HAL_ERROR;
3659 }
3660 else
3661 {
3662 return HAL_TIMEOUT;
3663 }
3664 }
3665
3666 /* Send LSB of Memory Address */
3667 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3668 }
3669
3670 /* Wait until TC flag is set */
3671 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
3672 {
3673 return HAL_TIMEOUT;
3674 }
3675
3676 return HAL_OK;
3677 }
3678
3679 /**
3680 * @brief I2C Address complete process callback.
3681 * @param hi2c: I2C handle.
3682 * @param ITFlags: Interrupt flags to handle.
3683 * @retval None
3684 */
3685 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
3686 {
3687 uint8_t transferdirection = 0;
3688 uint16_t slaveaddrcode = 0;
3689 uint16_t ownadd1code = 0;
3690 uint16_t ownadd2code = 0;
3691
3692 /* In case of Listen state, need to inform upper layer of address match code event */
3693 if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
3694 {
3695 transferdirection = I2C_GET_DIR(hi2c);
3696 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
3697 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
3698 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
3699
3700 /* If 10bits addressing mode is selected */
3701 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
3702 {
3703 if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
3704 {
3705 slaveaddrcode = ownadd1code;
3706 hi2c->AddrEventCount++;
3707 if(hi2c->AddrEventCount == 2)
3708 {
3709 /* Reset Address Event counter */
3710 hi2c->AddrEventCount = 0;
3711
3712 /* Clear ADDR flag */
3713 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
3714
3715 /* Process Unlocked */
3716 __HAL_UNLOCK(hi2c);
3717
3718 /* Call Slave Addr callback */
3719 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
3720 }
3721 }
3722 else
3723 {
3724 slaveaddrcode = ownadd2code;
3725
3726 /* Disable ADDR Interrupts */
3727 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
3728
3729 /* Process Unlocked */
3730 __HAL_UNLOCK(hi2c);
3731
3732 /* Call Slave Addr callback */
3733 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
3734 }
3735 }
3736 /* else 7 bits addressing mode is selected */
3737 else
3738 {
3739 /* Disable ADDR Interrupts */
3740 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
3741
3742 /* Process Unlocked */
3743 __HAL_UNLOCK(hi2c);
3744
3745 /* Call Slave Addr callback */
3746 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
3747 }
3748 }
3749 /* Else clear address flag only */
3750 else
3751 {
3752 /* Clear ADDR flag */
3753 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3754
3755 /* Process Unlocked */
3756 __HAL_UNLOCK(hi2c);
3757 }
3758 }
3759
3760 /**
3761 * @brief I2C Master sequential complete process.
3762 * @param hi2c: I2C handle.
3763 * @retval None
3764 */
3765 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
3766 {
3767 /* Reset I2C handle mode */
3768 hi2c->Mode = HAL_I2C_MODE_NONE;
3769
3770 /* No Generate Stop, to permit restart mode */
3771 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
3772 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
3773 {
3774 hi2c->State = HAL_I2C_STATE_READY;
3775 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
3776 hi2c->XferISR = NULL;
3777
3778 /* Disable Interrupts */
3779 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
3780
3781 /* Process Unlocked */
3782 __HAL_UNLOCK(hi2c);
3783
3784 /* Call the corresponding callback to inform upper layer of End of Transfer */
3785 HAL_I2C_MasterTxCpltCallback(hi2c);
3786 }
3787 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
3788 else
3789 {
3790 hi2c->State = HAL_I2C_STATE_READY;
3791 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
3792 hi2c->XferISR = NULL;
3793
3794 /* Disable Interrupts */
3795 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3796
3797 /* Process Unlocked */
3798 __HAL_UNLOCK(hi2c);
3799
3800 /* Call the corresponding callback to inform upper layer of End of Transfer */
3801 HAL_I2C_MasterRxCpltCallback(hi2c);
3802 }
3803 }
3804
3805 /**
3806 * @brief I2C Slave sequential complete process.
3807 * @param hi2c: I2C handle.
3808 * @retval None
3809 */
3810 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
3811 {
3812 /* Reset I2C handle mode */
3813 hi2c->Mode = HAL_I2C_MODE_NONE;
3814
3815 if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3816 {
3817 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
3818 hi2c->State = HAL_I2C_STATE_LISTEN;
3819 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
3820
3821 /* Disable Interrupts */
3822 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
3823
3824 /* Process Unlocked */
3825 __HAL_UNLOCK(hi2c);
3826
3827 /* Call the Tx complete callback to inform upper layer of the end of transmit process */
3828 HAL_I2C_SlaveTxCpltCallback(hi2c);
3829 }
3830
3831 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3832 {
3833 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
3834 hi2c->State = HAL_I2C_STATE_LISTEN;
3835 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
3836
3837 /* Disable Interrupts */
3838 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3839
3840 /* Process Unlocked */
3841 __HAL_UNLOCK(hi2c);
3842
3843 /* Call the Rx complete callback to inform upper layer of the end of receive process */
3844 HAL_I2C_SlaveRxCpltCallback(hi2c);
3845 }
3846 }
3847
3848 /**
3849 * @brief I2C Master complete process.
3850 * @param hi2c: I2C handle.
3851 * @param ITFlags: Interrupt flags to handle.
3852 * @retval None
3853 */
3854 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
3855 {
3856 /* Clear STOP Flag */
3857 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3858
3859 /* Clear Configuration Register 2 */
3860 I2C_RESET_CR2(hi2c);
3861
3862 /* Reset handle parameters */
3863 hi2c->PreviousState = I2C_STATE_NONE;
3864 hi2c->XferISR = NULL;
3865 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3866
3867 if((ITFlags & I2C_FLAG_AF) != RESET)
3868 {
3869 /* Clear NACK Flag */
3870 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3871
3872 /* Set acknowledge error code */
3873 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3874 }
3875
3876 /* Flush TX register */
3877 I2C_Flush_TXDR(hi2c);
3878
3879 /* Disable Interrupts */
3880 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
3881
3882 /* Call the corresponding callback to inform upper layer of End of Transfer */
3883 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
3884 {
3885 /* Call the corresponding callback to inform upper layer of End of Transfer */
3886 I2C_ITError(hi2c, hi2c->ErrorCode);
3887 }
3888 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
3889 else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
3890 {
3891 hi2c->State = HAL_I2C_STATE_READY;
3892
3893 if (hi2c->Mode == HAL_I2C_MODE_MEM)
3894 {
3895 hi2c->Mode = HAL_I2C_MODE_NONE;
3896
3897 /* Process Unlocked */
3898 __HAL_UNLOCK(hi2c);
3899
3900 /* Call the corresponding callback to inform upper layer of End of Transfer */
3901 HAL_I2C_MemTxCpltCallback(hi2c);
3902 }
3903 else
3904 {
3905 hi2c->Mode = HAL_I2C_MODE_NONE;
3906
3907 /* Process Unlocked */
3908 __HAL_UNLOCK(hi2c);
3909
3910 /* Call the corresponding callback to inform upper layer of End of Transfer */
3911 HAL_I2C_MasterTxCpltCallback(hi2c);
3912 }
3913 }
3914 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
3915 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
3916 {
3917 hi2c->State = HAL_I2C_STATE_READY;
3918
3919 if (hi2c->Mode == HAL_I2C_MODE_MEM)
3920 {
3921 hi2c->Mode = HAL_I2C_MODE_NONE;
3922
3923 /* Process Unlocked */
3924 __HAL_UNLOCK(hi2c);
3925
3926 HAL_I2C_MemRxCpltCallback(hi2c);
3927 }
3928 else
3929 {
3930 hi2c->Mode = HAL_I2C_MODE_NONE;
3931
3932 /* Process Unlocked */
3933 __HAL_UNLOCK(hi2c);
3934
3935 HAL_I2C_MasterRxCpltCallback(hi2c);
3936 }
3937 }
3938 }
3939
3940 /**
3941 * @brief I2C Slave complete process.
3942 * @param hi2c: I2C handle.
3943 * @param ITFlags: Interrupt flags to handle.
3944 * @retval None
3945 */
3946 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
3947 {
3948 /* Clear STOP Flag */
3949 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3950
3951 /* Clear ADDR flag */
3952 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
3953
3954 /* Disable all interrupts */
3955 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
3956
3957 /* Disable Address Acknowledge */
3958 hi2c->Instance->CR2 |= I2C_CR2_NACK;
3959
3960 /* Clear Configuration Register 2 */
3961 I2C_RESET_CR2(hi2c);
3962
3963 /* Flush TX register */
3964 I2C_Flush_TXDR(hi2c);
3965
3966 /* If a DMA is ongoing, Update handle size context */
3967 if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
3968 ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
3969 {
3970 if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize)
3971 {
3972 hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c);
3973 hi2c->XferCount += hi2c->XferSize;
3974
3975 /* Set ErrorCode corresponding to a Non-Acknowledge */
3976 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3977 }
3978 }
3979
3980 /* Store Last receive data if any */
3981 if(((ITFlags & I2C_FLAG_RXNE) != RESET))
3982 {
3983 /* Read data from RXDR */
3984 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
3985
3986 if((hi2c->XferSize > 0))
3987 {
3988 hi2c->XferSize--;
3989 hi2c->XferCount--;
3990
3991 /* Set ErrorCode corresponding to a Non-Acknowledge */
3992 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3993 }
3994 }
3995
3996 hi2c->PreviousState = I2C_STATE_NONE;
3997 hi2c->Mode = HAL_I2C_MODE_NONE;
3998 hi2c->XferISR = NULL;
3999
4000 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4001 {
4002 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4003 hi2c->State = HAL_I2C_STATE_READY;
4004
4005 /* Call the corresponding callback to inform upper layer of End of Transfer */
4006 I2C_ITError(hi2c, hi2c->ErrorCode);
4007 }
4008 else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4009 {
4010 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4011 hi2c->State = HAL_I2C_STATE_READY;
4012
4013 /* Process Unlocked */
4014 __HAL_UNLOCK(hi2c);
4015
4016 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4017 HAL_I2C_ListenCpltCallback(hi2c);
4018 }
4019 /* Call the corresponding callback to inform upper layer of End of Transfer */
4020 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
4021 {
4022 hi2c->State = HAL_I2C_STATE_READY;
4023
4024 /* Process Unlocked */
4025 __HAL_UNLOCK(hi2c);
4026
4027 /* Call the Slave Rx Complete callback */
4028 HAL_I2C_SlaveRxCpltCallback(hi2c);
4029 }
4030 else
4031 {
4032 hi2c->State = HAL_I2C_STATE_READY;
4033
4034 /* Process Unlocked */
4035 __HAL_UNLOCK(hi2c);
4036
4037 /* Call the Slave Tx Complete callback */
4038 HAL_I2C_SlaveTxCpltCallback(hi2c);
4039 }
4040 }
4041
4042 /**
4043 * @brief I2C Listen complete process.
4044 * @param hi2c: I2C handle.
4045 * @param ITFlags: Interrupt flags to handle.
4046 * @retval None
4047 */
4048 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
4049 {
4050 /* Reset handle parameters */
4051 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4052 hi2c->PreviousState = I2C_STATE_NONE;
4053 hi2c->State = HAL_I2C_STATE_READY;
4054 hi2c->Mode = HAL_I2C_MODE_NONE;
4055 hi2c->XferISR = NULL;
4056
4057 /* Store Last receive data if any */
4058 if(((ITFlags & I2C_FLAG_RXNE) != RESET))
4059 {
4060 /* Read data from RXDR */
4061 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
4062
4063 if((hi2c->XferSize > 0))
4064 {
4065 hi2c->XferSize--;
4066 hi2c->XferCount--;
4067
4068 /* Set ErrorCode corresponding to a Non-Acknowledge */
4069 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4070 }
4071 }
4072
4073 /* Disable all Interrupts*/
4074 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
4075
4076 /* Clear NACK Flag */
4077 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4078
4079 /* Process Unlocked */
4080 __HAL_UNLOCK(hi2c);
4081
4082 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4083 HAL_I2C_ListenCpltCallback(hi2c);
4084 }
4085
4086 /**
4087 * @brief I2C interrupts error process.
4088 * @param hi2c: I2C handle.
4089 * @param ErrorCode: Error code to handle.
4090 * @retval None
4091 */
4092 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
4093 {
4094 /* Reset handle parameters */
4095 hi2c->Mode = HAL_I2C_MODE_NONE;
4096 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4097 hi2c->XferCount = 0;
4098
4099 /* Set new error code */
4100 hi2c->ErrorCode |= ErrorCode;
4101
4102 /* Disable Interrupts */
4103 if((hi2c->State == HAL_I2C_STATE_LISTEN) ||
4104 (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
4105 (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
4106 {
4107 /* Disable all interrupts, except interrupts related to LISTEN state */
4108 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
4109
4110 /* keep HAL_I2C_STATE_LISTEN if set */
4111 hi2c->State = HAL_I2C_STATE_LISTEN;
4112 hi2c->PreviousState = I2C_STATE_NONE;
4113 hi2c->XferISR = I2C_Slave_ISR_IT;
4114 }
4115 else
4116 {
4117 /* Disable all interrupts */
4118 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
4119
4120 /* Set HAL_I2C_STATE_READY */
4121 hi2c->State = HAL_I2C_STATE_READY;
4122 hi2c->PreviousState = I2C_STATE_NONE;
4123 hi2c->XferISR = NULL;
4124 }
4125
4126 /* Abort DMA TX transfer if any */
4127 if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4128 {
4129 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4130
4131 /* Set the I2C DMA Abort callback :
4132 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4133 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4134
4135 /* Process Unlocked */
4136 __HAL_UNLOCK(hi2c);
4137
4138 /* Abort DMA TX */
4139 if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4140 {
4141 /* Call Directly XferAbortCallback function in case of error */
4142 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4143 }
4144 }
4145 /* Abort DMA RX transfer if any */
4146 else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4147 {
4148 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4149
4150 /* Set the I2C DMA Abort callback :
4151 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4152 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4153
4154 /* Process Unlocked */
4155 __HAL_UNLOCK(hi2c);
4156
4157 /* Abort DMA RX */
4158 if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4159 {
4160 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
4161 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4162 }
4163 }
4164 else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
4165 {
4166 hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
4167
4168 /* Process Unlocked */
4169 __HAL_UNLOCK(hi2c);
4170
4171 /* Call the corresponding callback to inform upper layer of End of Transfer */
4172 HAL_I2C_AbortCpltCallback(hi2c);
4173 }
4174 else
4175 {
4176 /* Process Unlocked */
4177 __HAL_UNLOCK(hi2c);
4178
4179 /* Call the corresponding callback to inform upper layer of End of Transfer */
4180 HAL_I2C_ErrorCallback(hi2c);
4181 }
4182 }
4183
4184 /**
4185 * @brief I2C Tx data register flush process.
4186 * @param hi2c: I2C handle.
4187 * @retval None
4188 */
4189 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
4190 {
4191 /* If a pending TXIS flag is set */
4192 /* Write a dummy data in TXDR to clear it */
4193 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
4194 {
4195 hi2c->Instance->TXDR = 0x00;
4196 }
4197
4198 /* Flush TX register if not empty */
4199 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
4200 {
4201 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
4202 }
4203 }
4204
4205 /**
4206 * @brief DMA I2C master transmit process complete callback.
4207 * @param hdma: DMA handle
4208 * @retval None
4209 */
4210 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
4211 {
4212 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
4213
4214 /* Disable DMA Request */
4215 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4216
4217 /* If last transfer, enable STOP interrupt */
4218 if(hi2c->XferCount == 0)
4219 {
4220 /* Enable STOP interrupt */
4221 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4222 }
4223 /* else prepare a new DMA transfer and enable TCReload interrupt */
4224 else
4225 {
4226 /* Update Buffer pointer */
4227 hi2c->pBuffPtr += hi2c->XferSize;
4228
4229 /* Set the XferSize to transfer */
4230 if(hi2c->XferCount > MAX_NBYTE_SIZE)
4231 {
4232 hi2c->XferSize = MAX_NBYTE_SIZE;
4233 }
4234 else
4235 {
4236 hi2c->XferSize = hi2c->XferCount;
4237 }
4238
4239 /* Enable the DMA channel */
4240 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
4241
4242 /* Enable TC interrupts */
4243 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
4244 }
4245 }
4246
4247 /**
4248 * @brief DMA I2C slave transmit process complete callback.
4249 * @param hdma: DMA handle
4250 * @retval None
4251 */
4252 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
4253 {
4254 /* No specific action, Master fully manage the generation of STOP condition */
4255 /* Mean that this generation can arrive at any time, at the end or during DMA process */
4256 /* So STOP condition should be manage through Interrupt treatment */
4257 }
4258
4259 /**
4260 * @brief DMA I2C master receive process complete callback.
4261 * @param hdma: DMA handle
4262 * @retval None
4263 */
4264 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
4265 {
4266 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
4267
4268 /* Disable DMA Request */
4269 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4270
4271 /* If last transfer, enable STOP interrupt */
4272 if(hi2c->XferCount == 0)
4273 {
4274 /* Enable STOP interrupt */
4275 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4276 }
4277 /* else prepare a new DMA transfer and enable TCReload interrupt */
4278 else
4279 {
4280 /* Update Buffer pointer */
4281 hi2c->pBuffPtr += hi2c->XferSize;
4282
4283 /* Set the XferSize to transfer */
4284 if(hi2c->XferCount > MAX_NBYTE_SIZE)
4285 {
4286 hi2c->XferSize = MAX_NBYTE_SIZE;
4287 }
4288 else
4289 {
4290 hi2c->XferSize = hi2c->XferCount;
4291 }
4292
4293 /* Enable the DMA channel */
4294 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4295
4296 /* Enable TC interrupts */
4297 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
4298 }
4299 }
4300
4301 /**
4302 * @brief DMA I2C slave receive process complete callback.
4303 * @param hdma: DMA handle
4304 * @retval None
4305 */
4306 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
4307 {
4308 /* No specific action, Master fully manage the generation of STOP condition */
4309 /* Mean that this generation can arrive at any time, at the end or during DMA process */
4310 /* So STOP condition should be manage through Interrupt treatment */
4311 }
4312
4313 /**
4314 * @brief DMA I2C communication error callback.
4315 * @param hdma: DMA handle
4316 * @retval None
4317 */
4318 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
4319 {
4320 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4321
4322 /* Disable Acknowledge */
4323 hi2c->Instance->CR2 |= I2C_CR2_NACK;
4324
4325 /* Call the corresponding callback to inform upper layer of End of Transfer */
4326 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
4327 }
4328
4329 /**
4330 * @brief DMA I2C communication abort callback
4331 * (To be called at end of DMA Abort procedure).
4332 * @param hdma: DMA handle.
4333 * @retval None
4334 */
4335 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
4336 {
4337 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4338
4339 /* Disable Acknowledge */
4340 hi2c->Instance->CR2 |= I2C_CR2_NACK;
4341
4342 /* Reset AbortCpltCallback */
4343 hi2c->hdmatx->XferAbortCallback = NULL;
4344 hi2c->hdmarx->XferAbortCallback = NULL;
4345
4346 /* Check if come from abort from user */
4347 if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
4348 {
4349 hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
4350
4351 /* Call the corresponding callback to inform upper layer of End of Transfer */
4352 HAL_I2C_AbortCpltCallback(hi2c);
4353 }
4354 else
4355 {
4356 /* Call the corresponding callback to inform upper layer of End of Transfer */
4357 HAL_I2C_ErrorCallback(hi2c);
4358 }
4359 }
4360
4361 /**
4362 * @brief This function handles I2C Communication Timeout.
4363 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
4364 * the configuration information for the specified I2C.
4365 * @param Flag: Specifies the I2C flag to check.
4366 * @param Status: The new Flag status (SET or RESET).
4367 * @param Timeout: Timeout duration
4368 * @param Tickstart: Tick start value
4369 * @retval HAL status
4370 */
4371 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
4372 {
4373 while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
4374 {
4375 /* Check for the Timeout */
4376 if(Timeout != HAL_MAX_DELAY)
4377 {
4378 if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
4379 {
4380 hi2c->State= HAL_I2C_STATE_READY;
4381 hi2c->Mode = HAL_I2C_MODE_NONE;
4382
4383 /* Process Unlocked */
4384 __HAL_UNLOCK(hi2c);
4385 return HAL_TIMEOUT;
4386 }
4387 }
4388 }
4389 return HAL_OK;
4390 }
4391
4392 /**
4393 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
4394 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
4395 * the configuration information for the specified I2C.
4396 * @param Timeout: Timeout duration
4397 * @param Tickstart: Tick start value
4398 * @retval HAL status
4399 */
4400 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4401 {
4402 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
4403 {
4404 /* Check if a NACK is detected */
4405 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
4406 {
4407 return HAL_ERROR;
4408 }
4409
4410 /* Check for the Timeout */
4411 if(Timeout != HAL_MAX_DELAY)
4412 {
4413 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
4414 {
4415 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
4416 hi2c->State= HAL_I2C_STATE_READY;
4417 hi2c->Mode = HAL_I2C_MODE_NONE;
4418
4419 /* Process Unlocked */
4420 __HAL_UNLOCK(hi2c);
4421
4422 return HAL_TIMEOUT;
4423 }
4424 }
4425 }
4426 return HAL_OK;
4427 }
4428
4429 /**
4430 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
4431 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
4432 * the configuration information for the specified I2C.
4433 * @param Timeout: Timeout duration
4434 * @param Tickstart: Tick start value
4435 * @retval HAL status
4436 */
4437 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4438 {
4439 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
4440 {
4441 /* Check if a NACK is detected */
4442 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
4443 {
4444 return HAL_ERROR;
4445 }
4446
4447 /* Check for the Timeout */
4448 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
4449 {
4450 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
4451 hi2c->State= HAL_I2C_STATE_READY;
4452 hi2c->Mode = HAL_I2C_MODE_NONE;
4453
4454 /* Process Unlocked */
4455 __HAL_UNLOCK(hi2c);
4456
4457 return HAL_TIMEOUT;
4458 }
4459 }
4460 return HAL_OK;
4461 }
4462
4463 /**
4464 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
4465 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
4466 * the configuration information for the specified I2C.
4467 * @param Timeout: Timeout duration
4468 * @param Tickstart: Tick start value
4469 * @retval HAL status
4470 */
4471 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4472 {
4473 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
4474 {
4475 /* Check if a NACK is detected */
4476 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
4477 {
4478 return HAL_ERROR;
4479 }
4480
4481 /* Check if a STOPF is detected */
4482 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
4483 {
4484 /* Clear STOP Flag */
4485 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
4486
4487 /* Clear Configuration Register 2 */
4488 I2C_RESET_CR2(hi2c);
4489
4490 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4491 hi2c->State= HAL_I2C_STATE_READY;
4492 hi2c->Mode = HAL_I2C_MODE_NONE;
4493
4494 /* Process Unlocked */
4495 __HAL_UNLOCK(hi2c);
4496
4497 return HAL_ERROR;
4498 }
4499
4500 /* Check for the Timeout */
4501 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
4502 {
4503 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
4504 hi2c->State= HAL_I2C_STATE_READY;
4505
4506 /* Process Unlocked */
4507 __HAL_UNLOCK(hi2c);
4508
4509 return HAL_TIMEOUT;
4510 }
4511 }
4512 return HAL_OK;
4513 }
4514
4515 /**
4516 * @brief This function handles Acknowledge failed detection during an I2C Communication.
4517 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
4518 * the configuration information for the specified I2C.
4519 * @param Timeout: Timeout duration
4520 * @param Tickstart: Tick start value
4521 * @retval HAL status
4522 */
4523 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4524 {
4525 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
4526 {
4527 /* Wait until STOP Flag is reset */
4528 /* AutoEnd should be initiate after AF */
4529 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
4530 {
4531 /* Check for the Timeout */
4532 if(Timeout != HAL_MAX_DELAY)
4533 {
4534 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
4535 {
4536 hi2c->State= HAL_I2C_STATE_READY;
4537 hi2c->Mode = HAL_I2C_MODE_NONE;
4538
4539 /* Process Unlocked */
4540 __HAL_UNLOCK(hi2c);
4541 return HAL_TIMEOUT;
4542 }
4543 }
4544 }
4545
4546 /* Clear NACKF Flag */
4547 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4548
4549 /* Clear STOP Flag */
4550 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
4551
4552 /* Flush TX register */
4553 I2C_Flush_TXDR(hi2c);
4554
4555 /* Clear Configuration Register 2 */
4556 I2C_RESET_CR2(hi2c);
4557
4558 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
4559 hi2c->State= HAL_I2C_STATE_READY;
4560 hi2c->Mode = HAL_I2C_MODE_NONE;
4561
4562 /* Process Unlocked */
4563 __HAL_UNLOCK(hi2c);
4564
4565 return HAL_ERROR;
4566 }
4567 return HAL_OK;
4568 }
4569
4570 /**
4571 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
4572 * @param hi2c: I2C handle.
4573 * @param DevAddress: Specifies the slave address to be programmed.
4574 * @param Size: Specifies the number of bytes to be programmed.
4575 * This parameter must be a value between 0 and 255.
4576 * @param Mode: New state of the I2C START condition generation.
4577 * This parameter can be a value of @ref I2C_RELOAD_END_MODE.
4578 * @param Request: New state of the I2C START condition generation.
4579 * This parameter can be a value of I2C_START_STOP_MODE.
4580 * @retval None
4581 */
4582 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
4583 {
4584 uint32_t tmpreg = 0;
4585
4586 /* Check the parameters */
4587 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
4588 assert_param(IS_TRANSFER_MODE(Mode));
4589 assert_param(IS_TRANSFER_REQUEST(Request));
4590
4591 /* Get the CR2 register value */
4592 tmpreg = hi2c->Instance->CR2;
4593
4594 /* clear tmpreg specific bits */
4595 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
4596
4597 /* update tmpreg */
4598 tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
4599 (uint32_t)Mode | (uint32_t)Request);
4600
4601 /* update CR2 register */
4602 hi2c->Instance->CR2 = tmpreg;
4603 }
4604
4605 /**
4606 * @brief Manage the enabling of Interrupts.
4607 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
4608 * the configuration information for the specified I2C.
4609 * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
4610 * @retval HAL status
4611 */
4612 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
4613 {
4614 uint32_t tmpisr = 0;
4615
4616 if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
4617 (hi2c->XferISR == I2C_Slave_ISR_DMA))
4618 {
4619 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4620 {
4621 /* Enable ERR, STOP, NACK and ADDR interrupts */
4622 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4623 }
4624
4625 if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
4626 {
4627 /* Enable ERR and NACK interrupts */
4628 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
4629 }
4630
4631 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4632 {
4633 /* Enable STOP interrupts */
4634 tmpisr |= I2C_IT_STOPI;
4635 }
4636
4637 if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
4638 {
4639 /* Enable TC interrupts */
4640 tmpisr |= I2C_IT_TCI;
4641 }
4642 }
4643 else
4644 {
4645 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4646 {
4647 /* Enable ERR, STOP, NACK, and ADDR interrupts */
4648 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4649 }
4650
4651 if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
4652 {
4653 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
4654 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
4655 }
4656
4657 if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
4658 {
4659 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
4660 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
4661 }
4662
4663 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4664 {
4665 /* Enable STOP interrupts */
4666 tmpisr |= I2C_IT_STOPI;
4667 }
4668 }
4669
4670 /* Enable interrupts only at the end */
4671 /* to avoid the risk of I2C interrupt handle execution before */
4672 /* all interrupts requested done */
4673 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
4674
4675 return HAL_OK;
4676 }
4677
4678 /**
4679 * @brief Manage the disabling of Interrupts.
4680 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
4681 * the configuration information for the specified I2C.
4682 * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
4683 * @retval HAL status
4684 */
4685 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
4686 {
4687 uint32_t tmpisr = 0;
4688
4689 if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
4690 {
4691 /* Disable TC and TXI interrupts */
4692 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
4693
4694 if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
4695 {
4696 /* Disable NACK and STOP interrupts */
4697 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4698 }
4699 }
4700
4701 if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
4702 {
4703 /* Disable TC and RXI interrupts */
4704 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
4705
4706 if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
4707 {
4708 /* Disable NACK and STOP interrupts */
4709 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4710 }
4711 }
4712
4713 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4714 {
4715 /* Disable ADDR, NACK and STOP interrupts */
4716 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4717 }
4718
4719 if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
4720 {
4721 /* Enable ERR and NACK interrupts */
4722 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
4723 }
4724
4725 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4726 {
4727 /* Enable STOP interrupts */
4728 tmpisr |= I2C_IT_STOPI;
4729 }
4730
4731 if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
4732 {
4733 /* Enable TC interrupts */
4734 tmpisr |= I2C_IT_TCI;
4735 }
4736
4737 /* Disable interrupts only at the end */
4738 /* to avoid a breaking situation like at "t" time */
4739 /* all disable interrupts request are not done */
4740 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
4741
4742 return HAL_OK;
4743 }
4744
4745 /**
4746 * @}
4747 */
4748
4749 #endif /* HAL_I2C_MODULE_ENABLED */
4750 /**
4751 * @}
4752 */
4753
4754 /**
4755 * @}
4756 */
4757
4758 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)