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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_nand.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_nand.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief NAND HAL module driver.
8 * This file provides a generic firmware to drive NAND memories mounted
9 * as external device.
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 This driver is a generic layered driver which contains a set of APIs used to
17 control NAND flash memories. It uses the FMC/FSMC layer functions to interface
18 with NAND devices. This driver is used as follows:
19
20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
21 with control and timing parameters for both common and attribute spaces.
22
23 (+) Read NAND flash memory maker and device IDs using the function
24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
25 structure declared by the function caller.
26
27 (+) Access NAND flash memory by read/write operations using the functions
28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
29 to read/write page(s)/spare area(s). These functions use specific device
30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
31 structure. The read/write address information is contained by the Nand_Address_Typedef
32 structure passed as parameter.
33
34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
35
36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
37 The erase block address information is contained in the Nand_Address_Typedef
38 structure passed as parameter.
39
40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
41
42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
45
46 (+) You can monitor the NAND device HAL state by calling the function
47 HAL_NAND_GetState()
48
49 [..]
50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
51 If a NAND flash device contains different operations and/or implementations,
52 it should be implemented separately.
53
54 @endverbatim
55 ******************************************************************************
56 * @attention
57 *
58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
59 *
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
70 *
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 *
82 ******************************************************************************
83 */
84
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f7xx_hal.h"
87
88 /** @addtogroup STM32F7xx_HAL_Driver
89 * @{
90 */
91
92
93 #ifdef HAL_NAND_MODULE_ENABLED
94
95 /** @defgroup NAND NAND
96 * @brief NAND HAL module driver
97 * @{
98 */
99
100 /* Private typedef -----------------------------------------------------------*/
101 /* Private Constants ------------------------------------------------------------*/
102 /* Private macro -------------------------------------------------------------*/
103 /* Private variables ---------------------------------------------------------*/
104 /* Private function prototypes -----------------------------------------------*/
105 /* Exported functions ---------------------------------------------------------*/
106
107 /** @defgroup NAND_Exported_Functions NAND Exported Functions
108 * @{
109 */
110
111 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
112 * @brief Initialization and Configuration functions
113 *
114 @verbatim
115 ==============================================================================
116 ##### NAND Initialization and de-initialization functions #####
117 ==============================================================================
118 [..]
119 This section provides functions allowing to initialize/de-initialize
120 the NAND memory
121
122 @endverbatim
123 * @{
124 */
125
126 /**
127 * @brief Perform NAND memory Initialization sequence
128 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
129 * the configuration information for NAND module.
130 * @param ComSpace_Timing: pointer to Common space timing structure
131 * @param AttSpace_Timing: pointer to Attribute space timing structure
132 * @retval HAL status
133 */
134 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
135 {
136 /* Check the NAND handle state */
137 if(hnand == NULL)
138 {
139 return HAL_ERROR;
140 }
141
142 if(hnand->State == HAL_NAND_STATE_RESET)
143 {
144 /* Allocate lock resource and initialize it */
145 hnand->Lock = HAL_UNLOCKED;
146 /* Initialize the low level hardware (MSP) */
147 HAL_NAND_MspInit(hnand);
148 }
149
150 /* Initialize NAND control Interface */
151 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
152
153 /* Initialize NAND common space timing Interface */
154 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
155
156 /* Initialize NAND attribute space timing Interface */
157 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
158
159 /* Enable the NAND device */
160 __FMC_NAND_ENABLE(hnand->Instance);
161
162 /* Update the NAND controller state */
163 hnand->State = HAL_NAND_STATE_READY;
164
165 return HAL_OK;
166 }
167
168 /**
169 * @brief Perform NAND memory De-Initialization sequence
170 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
171 * the configuration information for NAND module.
172 * @retval HAL status
173 */
174 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
175 {
176 /* Initialize the low level hardware (MSP) */
177 HAL_NAND_MspDeInit(hnand);
178
179 /* Configure the NAND registers with their reset values */
180 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
181
182 /* Reset the NAND controller state */
183 hnand->State = HAL_NAND_STATE_RESET;
184
185 /* Release Lock */
186 __HAL_UNLOCK(hnand);
187
188 return HAL_OK;
189 }
190
191 /**
192 * @brief NAND MSP Init
193 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
194 * the configuration information for NAND module.
195 * @retval None
196 */
197 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
198 {
199 /* Prevent unused argument(s) compilation warning */
200 UNUSED(hnand);
201
202 /* NOTE : This function Should not be modified, when the callback is needed,
203 the HAL_NAND_MspInit could be implemented in the user file
204 */
205 }
206
207 /**
208 * @brief NAND MSP DeInit
209 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
210 * the configuration information for NAND module.
211 * @retval None
212 */
213 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
214 {
215 /* Prevent unused argument(s) compilation warning */
216 UNUSED(hnand);
217
218 /* NOTE : This function Should not be modified, when the callback is needed,
219 the HAL_NAND_MspDeInit could be implemented in the user file
220 */
221 }
222
223
224 /**
225 * @brief This function handles NAND device interrupt request.
226 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
227 * the configuration information for NAND module.
228 * @retval HAL status
229 */
230 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
231 {
232 /* Check NAND interrupt Rising edge flag */
233 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
234 {
235 /* NAND interrupt callback*/
236 HAL_NAND_ITCallback(hnand);
237
238 /* Clear NAND interrupt Rising edge pending bit */
239 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
240 }
241
242 /* Check NAND interrupt Level flag */
243 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
244 {
245 /* NAND interrupt callback*/
246 HAL_NAND_ITCallback(hnand);
247
248 /* Clear NAND interrupt Level pending bit */
249 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
250 }
251
252 /* Check NAND interrupt Falling edge flag */
253 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
254 {
255 /* NAND interrupt callback*/
256 HAL_NAND_ITCallback(hnand);
257
258 /* Clear NAND interrupt Falling edge pending bit */
259 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
260 }
261
262 /* Check NAND interrupt FIFO empty flag */
263 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
264 {
265 /* NAND interrupt callback*/
266 HAL_NAND_ITCallback(hnand);
267
268 /* Clear NAND interrupt FIFO empty pending bit */
269 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
270 }
271
272 }
273
274 /**
275 * @brief NAND interrupt feature callback
276 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
277 * the configuration information for NAND module.
278 * @retval None
279 */
280 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
281 {
282 /* Prevent unused argument(s) compilation warning */
283 UNUSED(hnand);
284
285 /* NOTE : This function Should not be modified, when the callback is needed,
286 the HAL_NAND_ITCallback could be implemented in the user file
287 */
288 }
289
290 /**
291 * @}
292 */
293
294 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
295 * @brief Input Output and memory control functions
296 *
297 @verbatim
298 ==============================================================================
299 ##### NAND Input and Output functions #####
300 ==============================================================================
301 [..]
302 This section provides functions allowing to use and control the NAND
303 memory
304
305 @endverbatim
306 * @{
307 */
308
309 /**
310 * @brief Read the NAND memory electronic signature
311 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
312 * the configuration information for NAND module.
313 * @param pNAND_ID: NAND ID structure
314 * @retval HAL status
315 */
316 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
317 {
318 __IO uint32_t data = 0;
319 __IO uint32_t data1 = 0;
320 uint32_t deviceAddress = 0;
321
322 /* Process Locked */
323 __HAL_LOCK(hnand);
324
325 /* Check the NAND controller state */
326 if(hnand->State == HAL_NAND_STATE_BUSY)
327 {
328 return HAL_BUSY;
329 }
330
331 /* Identify the device address */
332 deviceAddress = NAND_DEVICE;
333
334 /* Update the NAND controller state */
335 hnand->State = HAL_NAND_STATE_BUSY;
336
337 /* Send Read ID command sequence */
338 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
339 __DSB();
340 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
341 __DSB();
342
343 /* Read the electronic signature from NAND flash */
344 if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
345 {
346 data = *(__IO uint32_t *)deviceAddress;
347
348 /* Return the data read */
349 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
350 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
351 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
352 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
353 }
354 else
355 {
356 data = *(__IO uint32_t *)deviceAddress;
357 data1 = *((__IO uint32_t *)deviceAddress + 4);
358
359 /* Return the data read */
360 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
361 pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
362 pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
363 pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
364 }
365
366
367 /* Update the NAND controller state */
368 hnand->State = HAL_NAND_STATE_READY;
369
370 /* Process unlocked */
371 __HAL_UNLOCK(hnand);
372
373 return HAL_OK;
374 }
375
376 /**
377 * @brief NAND memory reset
378 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
379 * the configuration information for NAND module.
380 * @retval HAL status
381 */
382 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
383 {
384 uint32_t deviceAddress = 0;
385
386 /* Process Locked */
387 __HAL_LOCK(hnand);
388
389 /* Check the NAND controller state */
390 if(hnand->State == HAL_NAND_STATE_BUSY)
391 {
392 return HAL_BUSY;
393 }
394
395 /* Identify the device address */
396 deviceAddress = NAND_DEVICE;
397
398 /* Update the NAND controller state */
399 hnand->State = HAL_NAND_STATE_BUSY;
400
401 /* Send NAND reset command */
402 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
403
404
405 /* Update the NAND controller state */
406 hnand->State = HAL_NAND_STATE_READY;
407
408 /* Process unlocked */
409 __HAL_UNLOCK(hnand);
410
411 return HAL_OK;
412
413 }
414
415 /**
416 * @brief Read Page(s) from NAND memory block (8-bits addressing)
417 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
418 * the configuration information for NAND module.
419 * @param pAddress : pointer to NAND address structure
420 * @param pBuffer : pointer to destination read buffer
421 * @param NumPageToRead : number of pages to read from block
422 * @retval HAL status
423 */
424 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
425 {
426 __IO uint32_t index = 0;
427 uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
428
429 /* Process Locked */
430 __HAL_LOCK(hnand);
431
432 /* Check the NAND controller state */
433 if(hnand->State == HAL_NAND_STATE_BUSY)
434 {
435 return HAL_BUSY;
436 }
437
438 /* Identify the device address */
439 deviceAddress = NAND_DEVICE;
440
441 /* Update the NAND controller state */
442 hnand->State = HAL_NAND_STATE_BUSY;
443
444 /* NAND raw address calculation */
445 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
446
447 /* Page(s) read loop */
448 while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
449 {
450 /* update the buffer size */
451 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
452
453 /* Send read page command sequence */
454 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
455 __DSB();
456 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
457 __DSB();
458 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
459 __DSB();
460 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
461 __DSB();
462 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
463 __DSB();
464
465 /* for 512 and 1 GB devices, 4th cycle is required */
466 if(hnand->Info.BlockNbr >= 1024)
467 {
468 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
469 __DSB();
470 }
471
472 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
473 __DSB();
474
475 if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
476 {
477 /* Get Data into Buffer */
478 for(; index < size; index++)
479 {
480 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
481 }
482 }
483 else
484 {
485 /* Get Data into Buffer */
486 for(; index < size; index++)
487 {
488 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
489 }
490 }
491
492 /* Increment read pages number */
493 numPagesRead++;
494
495 /* Decrement pages to read */
496 NumPageToRead--;
497
498 /* Increment the NAND address */
499 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
500 }
501
502 /* Update the NAND controller state */
503 hnand->State = HAL_NAND_STATE_READY;
504
505 /* Process unlocked */
506 __HAL_UNLOCK(hnand);
507
508 return HAL_OK;
509
510 }
511
512 /**
513 * @brief Read Page(s) from NAND memory block (16-bits addressing)
514 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
515 * the configuration information for NAND module.
516 * @param pAddress : pointer to NAND address structure
517 * @param pBuffer : pointer to destination read buffer
518 * @param NumPageToRead : number of pages to read from block
519 * @retval HAL status
520 */
521 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
522 {
523 __IO uint32_t index = 0;
524 uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
525
526 /* Process Locked */
527 __HAL_LOCK(hnand);
528
529 /* Check the NAND controller state */
530 if(hnand->State == HAL_NAND_STATE_BUSY)
531 {
532 return HAL_BUSY;
533 }
534
535 /* Identify the device address */
536 deviceAddress = NAND_DEVICE;
537
538 /* Update the NAND controller state */
539 hnand->State = HAL_NAND_STATE_BUSY;
540
541 /* NAND raw address calculation */
542 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
543
544 /* Page(s) read loop */
545 while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
546 {
547 /* update the buffer size */
548 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
549
550 /* Send read page command sequence */
551 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
552 __DSB();
553 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
554 __DSB();
555 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
556 __DSB();
557 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
558 __DSB();
559 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
560 __DSB();
561
562 /* for 512 and 1 GB devices, 4th cycle is required */
563 if(hnand->Info.BlockNbr >= 1024)
564 {
565 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
566 __DSB();
567 }
568
569 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
570 __DSB();
571
572 /* Get Data into Buffer */
573 for(; index < size; index++)
574 {
575 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
576 }
577
578 /* Increment read pages number */
579 numPagesRead++;
580
581 /* Decrement pages to read */
582 NumPageToRead--;
583
584 /* Increment the NAND address */
585 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
586 }
587
588 /* Update the NAND controller state */
589 hnand->State = HAL_NAND_STATE_READY;
590
591 /* Process unlocked */
592 __HAL_UNLOCK(hnand);
593
594 return HAL_OK;
595 }
596
597 /**
598 * @brief Write Page(s) to NAND memory block (8-bits addressing)
599 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
600 * the configuration information for NAND module.
601 * @param pAddress : pointer to NAND address structure
602 * @param pBuffer : pointer to source buffer to write
603 * @param NumPageToWrite : number of pages to write to block
604 * @retval HAL status
605 */
606 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
607 {
608 __IO uint32_t index = 0;
609 uint32_t tickstart = 0;
610 uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
611
612 /* Process Locked */
613 __HAL_LOCK(hnand);
614
615 /* Check the NAND controller state */
616 if(hnand->State == HAL_NAND_STATE_BUSY)
617 {
618 return HAL_BUSY;
619 }
620
621 /* Identify the device address */
622 deviceAddress = NAND_DEVICE;
623
624 /* Update the NAND controller state */
625 hnand->State = HAL_NAND_STATE_BUSY;
626
627 /* NAND raw address calculation */
628 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
629
630 /* Page(s) write loop */
631 while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
632 {
633 /* update the buffer size */
634 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
635
636 /* Send write page command sequence */
637 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
638 __DSB();
639 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
640 __DSB();
641
642 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
643 __DSB();
644 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
645 __DSB();
646 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
647 __DSB();
648 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
649 __DSB();
650
651 /* for 512 and 1 GB devices, 4th cycle is required */
652 if(hnand->Info.BlockNbr >= 1024)
653 {
654 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
655 __DSB();
656 }
657
658 if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
659 {
660 /* Write data to memory */
661 for(; index < size; index++)
662 {
663 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
664 __DSB();
665 }
666 }
667 else
668 {
669 /* Write data to memory */
670 for(; index < size; index++)
671 {
672 *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
673 __DSB();
674 }
675 }
676
677 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
678 __DSB();
679
680 /* Read status until NAND is ready */
681 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
682 {
683 /* Get tick */
684 tickstart = HAL_GetTick();
685
686 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
687 {
688 return HAL_TIMEOUT;
689 }
690 }
691
692 /* Increment written pages number */
693 numPagesWritten++;
694
695 /* Decrement pages to write */
696 NumPageToWrite--;
697
698 /* Increment the NAND address */
699 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
700 }
701
702 /* Update the NAND controller state */
703 hnand->State = HAL_NAND_STATE_READY;
704
705 /* Process unlocked */
706 __HAL_UNLOCK(hnand);
707
708 return HAL_OK;
709 }
710
711 /**
712 * @brief Write Page(s) to NAND memory block (16-bits addressing)
713 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
714 * the configuration information for NAND module.
715 * @param pAddress : pointer to NAND address structure
716 * @param pBuffer : pointer to source buffer to write
717 * @param NumPageToWrite : number of pages to write to block
718 * @retval HAL status
719 */
720 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
721 {
722 __IO uint32_t index = 0;
723 uint32_t tickstart = 0;
724 uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
725
726 /* Process Locked */
727 __HAL_LOCK(hnand);
728
729 /* Check the NAND controller state */
730 if(hnand->State == HAL_NAND_STATE_BUSY)
731 {
732 return HAL_BUSY;
733 }
734
735 /* Identify the device address */
736 deviceAddress = NAND_DEVICE;
737
738 /* Update the NAND controller state */
739 hnand->State = HAL_NAND_STATE_BUSY;
740
741 /* NAND raw address calculation */
742 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
743
744 /* Page(s) write loop */
745 while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
746 {
747 /* update the buffer size */
748 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
749
750 /* Send write page command sequence */
751 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
752 __DSB();
753 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
754 __DSB();
755
756 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
757 __DSB();
758 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
759 __DSB();
760 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
761 __DSB();
762 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
763 __DSB();
764
765 /* for 512 and 1 GB devices, 4th cycle is required */
766 if(hnand->Info.BlockNbr >= 1024)
767 {
768 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
769 __DSB();
770 }
771
772 /* Write data to memory */
773 for(; index < size; index++)
774 {
775 *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
776 __DSB();
777 }
778
779 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
780 __DSB();
781
782 /* Read status until NAND is ready */
783 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
784 {
785 /* Get tick */
786 tickstart = HAL_GetTick();
787
788 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
789 {
790 return HAL_TIMEOUT;
791 }
792 }
793
794 /* Increment written pages number */
795 numPagesWritten++;
796
797 /* Decrement pages to write */
798 NumPageToWrite--;
799
800 /* Increment the NAND address */
801 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
802 }
803
804 /* Update the NAND controller state */
805 hnand->State = HAL_NAND_STATE_READY;
806
807 /* Process unlocked */
808 __HAL_UNLOCK(hnand);
809
810 return HAL_OK;
811 }
812
813 /**
814 * @brief Read Spare area(s) from NAND memory (8-bits addressing)
815 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
816 * the configuration information for NAND module.
817 * @param pAddress : pointer to NAND address structure
818 * @param pBuffer: pointer to source buffer to write
819 * @param NumSpareAreaToRead: Number of spare area to read
820 * @retval HAL status
821 */
822 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
823 {
824 __IO uint32_t index = 0;
825 uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
826
827 /* Process Locked */
828 __HAL_LOCK(hnand);
829
830 /* Check the NAND controller state */
831 if(hnand->State == HAL_NAND_STATE_BUSY)
832 {
833 return HAL_BUSY;
834 }
835
836 /* Identify the device address */
837 deviceAddress = NAND_DEVICE;
838
839 /* Update the NAND controller state */
840 hnand->State = HAL_NAND_STATE_BUSY;
841
842 /* NAND raw address calculation */
843 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
844
845 /* Spare area(s) read loop */
846 while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
847 {
848 /* update the buffer size */
849 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
850
851 /* Send read spare area command sequence */
852 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
853 __DSB();
854 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
855 __DSB();
856 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
857 __DSB();
858 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
859 __DSB();
860 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
861 __DSB();
862
863 /* for 512 and 1 GB devices, 4th cycle is required */
864 if(hnand->Info.BlockNbr >= 1024)
865 {
866 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
867 __DSB();
868 }
869
870 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
871 __DSB();
872
873 /* Get Data into Buffer */
874 for(; index < size; index++)
875 {
876 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
877 }
878
879 /* Increment read spare areas number */
880 numSpareAreaRead++;
881
882 /* Decrement spare areas to read */
883 NumSpareAreaToRead--;
884
885 /* Increment the NAND address */
886 nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
887 }
888
889 /* Update the NAND controller state */
890 hnand->State = HAL_NAND_STATE_READY;
891
892 /* Process unlocked */
893 __HAL_UNLOCK(hnand);
894
895 return HAL_OK;
896 }
897
898 /**
899 * @brief Read Spare area(s) from NAND memory (16-bits addressing)
900 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
901 * the configuration information for NAND module.
902 * @param pAddress : pointer to NAND address structure
903 * @param pBuffer: pointer to source buffer to write
904 * @param NumSpareAreaToRead: Number of spare area to read
905 * @retval HAL status
906 */
907 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
908 {
909 __IO uint32_t index = 0;
910 uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
911
912 /* Process Locked */
913 __HAL_LOCK(hnand);
914
915 /* Check the NAND controller state */
916 if(hnand->State == HAL_NAND_STATE_BUSY)
917 {
918 return HAL_BUSY;
919 }
920
921 /* Identify the device address */
922 deviceAddress = NAND_DEVICE;
923
924 /* Update the NAND controller state */
925 hnand->State = HAL_NAND_STATE_BUSY;
926
927 /* NAND raw address calculation */
928 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
929
930 /* Spare area(s) read loop */
931 while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
932 {
933 /* update the buffer size */
934 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
935
936 /* Send read spare area command sequence */
937 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
938 __DSB();
939 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
940 __DSB();
941 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
942 __DSB();
943 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
944 __DSB();
945 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
946 __DSB();
947
948 /* for 512 and 1 GB devices, 4th cycle is required */
949 if(hnand->Info.BlockNbr >= 1024)
950 {
951 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
952 __DSB();
953 }
954
955 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
956 __DSB();
957
958 /* Get Data into Buffer */
959 for(; index < size; index++)
960 {
961 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
962 }
963
964 /* Increment read spare areas number */
965 numSpareAreaRead++;
966
967 /* Decrement spare areas to read */
968 NumSpareAreaToRead--;
969
970 /* Increment the NAND address */
971 nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
972 }
973
974 /* Update the NAND controller state */
975 hnand->State = HAL_NAND_STATE_READY;
976
977 /* Process unlocked */
978 __HAL_UNLOCK(hnand);
979
980 return HAL_OK;
981 }
982
983 /**
984 * @brief Write Spare area(s) to NAND memory (8-bits addressing)
985 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
986 * the configuration information for NAND module.
987 * @param pAddress : pointer to NAND address structure
988 * @param pBuffer : pointer to source buffer to write
989 * @param NumSpareAreaTowrite : number of spare areas to write to block
990 * @retval HAL status
991 */
992 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
993 {
994 __IO uint32_t index = 0;
995 uint32_t tickstart = 0;
996 uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
997
998 /* Process Locked */
999 __HAL_LOCK(hnand);
1000
1001 /* Check the NAND controller state */
1002 if(hnand->State == HAL_NAND_STATE_BUSY)
1003 {
1004 return HAL_BUSY;
1005 }
1006
1007 /* Identify the device address */
1008 deviceAddress = NAND_DEVICE;
1009
1010 /* Update the FMC_NAND controller state */
1011 hnand->State = HAL_NAND_STATE_BUSY;
1012
1013 /* NAND raw address calculation */
1014 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1015
1016 /* Spare area(s) write loop */
1017 while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
1018 {
1019 /* update the buffer size */
1020 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
1021
1022 /* Send write Spare area command sequence */
1023 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1024 __DSB();
1025 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1026 __DSB();
1027 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1028 __DSB();
1029 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1030 __DSB();
1031 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1032 __DSB();
1033 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1034 __DSB();
1035 /* for 512 and 1 GB devices, 4th cycle is required */
1036 if(hnand->Info.BlockNbr >= 1024)
1037 {
1038 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
1039 __DSB();
1040 }
1041
1042 /* Write data to memory */
1043 for(; index < size; index++)
1044 {
1045 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
1046 __DSB();
1047 }
1048
1049 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1050 __DSB();
1051
1052 /* Read status until NAND is ready */
1053 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1054 {
1055 /* Get tick */
1056 tickstart = HAL_GetTick();
1057
1058 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1059 {
1060 return HAL_TIMEOUT;
1061 }
1062 }
1063
1064 /* Increment written spare areas number */
1065 numSpareAreaWritten++;
1066
1067 /* Decrement spare areas to write */
1068 NumSpareAreaTowrite--;
1069
1070 /* Increment the NAND address */
1071 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
1072 }
1073
1074 /* Update the NAND controller state */
1075 hnand->State = HAL_NAND_STATE_READY;
1076
1077 /* Process unlocked */
1078 __HAL_UNLOCK(hnand);
1079
1080 return HAL_OK;
1081 }
1082
1083 /**
1084 * @brief Write Spare area(s) to NAND memory (16-bits addressing)
1085 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1086 * the configuration information for NAND module.
1087 * @param pAddress : pointer to NAND address structure
1088 * @param pBuffer : pointer to source buffer to write
1089 * @param NumSpareAreaTowrite : number of spare areas to write to block
1090 * @retval HAL status
1091 */
1092 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
1093 {
1094 __IO uint32_t index = 0;
1095 uint32_t tickstart = 0;
1096 uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
1097
1098 /* Process Locked */
1099 __HAL_LOCK(hnand);
1100
1101 /* Check the NAND controller state */
1102 if(hnand->State == HAL_NAND_STATE_BUSY)
1103 {
1104 return HAL_BUSY;
1105 }
1106
1107 /* Identify the device address */
1108 deviceAddress = NAND_DEVICE;
1109
1110 /* Update the FMC_NAND controller state */
1111 hnand->State = HAL_NAND_STATE_BUSY;
1112
1113 /* NAND raw address calculation */
1114 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1115
1116 /* Spare area(s) write loop */
1117 while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
1118 {
1119 /* update the buffer size */
1120 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
1121
1122 /* Send write Spare area command sequence */
1123 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1124 __DSB();
1125 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1126 __DSB();
1127 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1128 __DSB();
1129 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1130 __DSB();
1131 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1132 __DSB();
1133 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1134 __DSB();
1135 /* for 512 and 1 GB devices, 4th cycle is required */
1136 if(hnand->Info.BlockNbr >= 1024)
1137 {
1138 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
1139 __DSB();
1140 }
1141
1142 /* Write data to memory */
1143 for(; index < size; index++)
1144 {
1145 *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
1146 __DSB();
1147 }
1148
1149 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1150 __DSB();
1151
1152 /* Read status until NAND is ready */
1153 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1154 {
1155 /* Get tick */
1156 tickstart = HAL_GetTick();
1157
1158 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1159 {
1160 return HAL_TIMEOUT;
1161 }
1162 }
1163
1164 /* Increment written spare areas number */
1165 numSpareAreaWritten++;
1166
1167 /* Decrement spare areas to write */
1168 NumSpareAreaTowrite--;
1169
1170 /* Increment the NAND address */
1171 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
1172 }
1173
1174 /* Update the NAND controller state */
1175 hnand->State = HAL_NAND_STATE_READY;
1176
1177 /* Process unlocked */
1178 __HAL_UNLOCK(hnand);
1179
1180 return HAL_OK;
1181 }
1182
1183 /**
1184 * @brief NAND memory Block erase
1185 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1186 * the configuration information for NAND module.
1187 * @param pAddress : pointer to NAND address structure
1188 * @retval HAL status
1189 */
1190 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1191 {
1192 uint32_t DeviceAddress = 0;
1193
1194 /* Process Locked */
1195 __HAL_LOCK(hnand);
1196
1197 /* Check the NAND controller state */
1198 if(hnand->State == HAL_NAND_STATE_BUSY)
1199 {
1200 return HAL_BUSY;
1201 }
1202
1203 /* Identify the device address */
1204 DeviceAddress = NAND_DEVICE;
1205
1206 /* Update the NAND controller state */
1207 hnand->State = HAL_NAND_STATE_BUSY;
1208
1209 /* Send Erase block command sequence */
1210 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
1211 __DSB();
1212 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1213 __DSB();
1214 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1215 __DSB();
1216 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1217 __DSB();
1218
1219 /* for 512 and 1 GB devices, 4th cycle is required */
1220 if(hnand->Info.BlockNbr >= 1024)
1221 {
1222 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1223 __DSB();
1224 }
1225
1226 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
1227 __DSB();
1228
1229 /* Update the NAND controller state */
1230 hnand->State = HAL_NAND_STATE_READY;
1231
1232 /* Process unlocked */
1233 __HAL_UNLOCK(hnand);
1234
1235 return HAL_OK;
1236 }
1237
1238 /**
1239 * @brief NAND memory read status
1240 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1241 * the configuration information for NAND module.
1242 * @retval NAND status
1243 */
1244 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
1245 {
1246 uint32_t data = 0;
1247 uint32_t DeviceAddress = 0;
1248
1249 /* Identify the device address */
1250 DeviceAddress = NAND_DEVICE;
1251
1252 /* Send Read status operation command */
1253 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
1254
1255 /* Read status register data */
1256 data = *(__IO uint8_t *)DeviceAddress;
1257
1258 /* Return the status */
1259 if((data & NAND_ERROR) == NAND_ERROR)
1260 {
1261 return NAND_ERROR;
1262 }
1263 else if((data & NAND_READY) == NAND_READY)
1264 {
1265 return NAND_READY;
1266 }
1267
1268 return NAND_BUSY;
1269 }
1270
1271 /**
1272 * @brief Increment the NAND memory address
1273 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1274 * the configuration information for NAND module.
1275 * @param pAddress: pointer to NAND address structure
1276 * @retval The new status of the increment address operation. It can be:
1277 * - NAND_VALID_ADDRESS: When the new address is valid address
1278 * - NAND_INVALID_ADDRESS: When the new address is invalid address
1279 */
1280 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1281 {
1282 uint32_t status = NAND_VALID_ADDRESS;
1283
1284 /* Increment page address */
1285 pAddress->Page++;
1286
1287 /* Check NAND address is valid */
1288 if(pAddress->Page == hnand->Info.BlockSize)
1289 {
1290 pAddress->Page = 0;
1291 pAddress->Block++;
1292
1293 if(pAddress->Block == hnand->Info.ZoneSize)
1294 {
1295 pAddress->Block = 0;
1296 pAddress->Zone++;
1297
1298 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
1299 {
1300 status = NAND_INVALID_ADDRESS;
1301 }
1302 }
1303 }
1304
1305 return (status);
1306 }
1307 /**
1308 * @}
1309 */
1310
1311 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
1312 * @brief management functions
1313 *
1314 @verbatim
1315 ==============================================================================
1316 ##### NAND Control functions #####
1317 ==============================================================================
1318 [..]
1319 This subsection provides a set of functions allowing to control dynamically
1320 the NAND interface.
1321
1322 @endverbatim
1323 * @{
1324 */
1325
1326
1327 /**
1328 * @brief Enables dynamically NAND ECC feature.
1329 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1330 * the configuration information for NAND module.
1331 * @retval HAL status
1332 */
1333 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
1334 {
1335 /* Check the NAND controller state */
1336 if(hnand->State == HAL_NAND_STATE_BUSY)
1337 {
1338 return HAL_BUSY;
1339 }
1340
1341 /* Update the NAND state */
1342 hnand->State = HAL_NAND_STATE_BUSY;
1343
1344 /* Enable ECC feature */
1345 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
1346
1347 /* Update the NAND state */
1348 hnand->State = HAL_NAND_STATE_READY;
1349
1350 return HAL_OK;
1351 }
1352
1353 /**
1354 * @brief Disables dynamically FMC_NAND ECC feature.
1355 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1356 * the configuration information for NAND module.
1357 * @retval HAL status
1358 */
1359 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
1360 {
1361 /* Check the NAND controller state */
1362 if(hnand->State == HAL_NAND_STATE_BUSY)
1363 {
1364 return HAL_BUSY;
1365 }
1366
1367 /* Update the NAND state */
1368 hnand->State = HAL_NAND_STATE_BUSY;
1369
1370 /* Disable ECC feature */
1371 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
1372
1373 /* Update the NAND state */
1374 hnand->State = HAL_NAND_STATE_READY;
1375
1376 return HAL_OK;
1377 }
1378
1379 /**
1380 * @brief Disables dynamically NAND ECC feature.
1381 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1382 * the configuration information for NAND module.
1383 * @param ECCval: pointer to ECC value
1384 * @param Timeout: maximum timeout to wait
1385 * @retval HAL status
1386 */
1387 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
1388 {
1389 HAL_StatusTypeDef status = HAL_OK;
1390
1391 /* Check the NAND controller state */
1392 if(hnand->State == HAL_NAND_STATE_BUSY)
1393 {
1394 return HAL_BUSY;
1395 }
1396
1397 /* Update the NAND state */
1398 hnand->State = HAL_NAND_STATE_BUSY;
1399
1400 /* Get NAND ECC value */
1401 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
1402
1403 /* Update the NAND state */
1404 hnand->State = HAL_NAND_STATE_READY;
1405
1406 return status;
1407 }
1408
1409 /**
1410 * @}
1411 */
1412
1413
1414 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
1415 * @brief Peripheral State functions
1416 *
1417 @verbatim
1418 ==============================================================================
1419 ##### NAND State functions #####
1420 ==============================================================================
1421 [..]
1422 This subsection permits to get in run-time the status of the NAND controller
1423 and the data flow.
1424
1425 @endverbatim
1426 * @{
1427 */
1428
1429 /**
1430 * @brief return the NAND state
1431 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
1432 * the configuration information for NAND module.
1433 * @retval HAL state
1434 */
1435 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
1436 {
1437 return hnand->State;
1438 }
1439
1440 /**
1441 * @}
1442 */
1443
1444 /**
1445 * @}
1446 */
1447
1448 #endif /* HAL_NAND_MODULE_ENABLED */
1449
1450 /**
1451 * @}
1452 */
1453
1454 /**
1455 * @}
1456 */
1457
1458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)