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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_nor.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_nor.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief NOR HAL module driver.
8 * This file provides a generic firmware to drive NOR memories mounted
9 * as external device.
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 This driver is a generic layered driver which contains a set of APIs used to
17 control NOR flash memories. It uses the FMC layer functions to interface
18 with NOR devices. This driver is used as follows:
19
20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
21 with control and timing parameters for both normal and extended mode.
22
23 (+) Read NOR flash memory manufacturer code and device IDs using the function
24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
25 structure declared by the function caller.
26
27 (+) Access NOR flash memory by read/write data unit operations using the functions
28 HAL_NOR_Read(), HAL_NOR_Program().
29
30 (+) Perform NOR flash erase block/chip operations using the functions
31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
32
33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
35 structure declared by the function caller.
36
37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
39
40 (+) You can monitor the NOR device HAL state by calling the function
41 HAL_NOR_GetState()
42 [..]
43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
44 If a NOR flash device contains different operations and/or implementations,
45 it should be implemented separately.
46
47 *** NOR HAL driver macros list ***
48 =============================================
49 [..]
50 Below the list of most used macros in NOR HAL driver.
51
52 (+) NOR_WRITE : NOR memory write data to specified address
53
54 @endverbatim
55 ******************************************************************************
56 * @attention
57 *
58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
59 *
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
70 *
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 *
82 ******************************************************************************
83 */
84
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f7xx_hal.h"
87
88 /** @addtogroup STM32F7xx_HAL_Driver
89 * @{
90 */
91
92 /** @defgroup NOR NOR
93 * @brief NOR driver modules
94 * @{
95 */
96 #ifdef HAL_NOR_MODULE_ENABLED
97
98 /* Private typedef -----------------------------------------------------------*/
99 /* Private define ------------------------------------------------------------*/
100
101 /** @defgroup NOR_Private_Defines NOR Private Defines
102 * @{
103 */
104
105 /* Constants to define address to set to write a command */
106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
113
114 /* Constants to define data to program a command */
115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
125
126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
129
130 /* Mask on NOR STATUS REGISTER */
131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
133
134 /**
135 * @}
136 */
137
138 /* Private macro -------------------------------------------------------------*/
139 /* Private variables ---------------------------------------------------------*/
140 /** @defgroup NOR_Private_Variables NOR Private Variables
141 * @{
142 */
143
144 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
145
146 /**
147 * @}
148 */
149
150 /* Private functions ---------------------------------------------------------*/
151 /* Exported functions --------------------------------------------------------*/
152 /** @defgroup NOR_Exported_Functions NOR Exported Functions
153 * @{
154 */
155
156 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
157 * @brief Initialization and Configuration functions
158 *
159 @verbatim
160 ==============================================================================
161 ##### NOR Initialization and de_initialization functions #####
162 ==============================================================================
163 [..]
164 This section provides functions allowing to initialize/de-initialize
165 the NOR memory
166
167 @endverbatim
168 * @{
169 */
170
171 /**
172 * @brief Perform the NOR memory Initialization sequence
173 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
174 * the configuration information for NOR module.
175 * @param Timing: pointer to NOR control timing structure
176 * @param ExtTiming: pointer to NOR extended mode timing structure
177 * @retval HAL status
178 */
179 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
180 {
181 /* Check the NOR handle parameter */
182 if(hnor == NULL)
183 {
184 return HAL_ERROR;
185 }
186
187 if(hnor->State == HAL_NOR_STATE_RESET)
188 {
189 /* Allocate lock resource and initialize it */
190 hnor->Lock = HAL_UNLOCKED;
191 /* Initialize the low level hardware (MSP) */
192 HAL_NOR_MspInit(hnor);
193 }
194
195 /* Initialize NOR control Interface */
196 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
197
198 /* Initialize NOR timing Interface */
199 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
200
201 /* Initialize NOR extended mode timing Interface */
202 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
203
204 /* Enable the NORSRAM device */
205 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
206
207 /* Initialize NOR Memory Data Width*/
208 if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
209 {
210 uwNORMemoryDataWidth = NOR_MEMORY_8B;
211 }
212 else
213 {
214 uwNORMemoryDataWidth = NOR_MEMORY_16B;
215 }
216
217 /* Check the NOR controller state */
218 hnor->State = HAL_NOR_STATE_READY;
219
220 return HAL_OK;
221 }
222
223 /**
224 * @brief Perform NOR memory De-Initialization sequence
225 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
226 * the configuration information for NOR module.
227 * @retval HAL status
228 */
229 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
230 {
231 /* De-Initialize the low level hardware (MSP) */
232 HAL_NOR_MspDeInit(hnor);
233
234 /* Configure the NOR registers with their reset values */
235 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
236
237 /* Update the NOR controller state */
238 hnor->State = HAL_NOR_STATE_RESET;
239
240 /* Release Lock */
241 __HAL_UNLOCK(hnor);
242
243 return HAL_OK;
244 }
245
246 /**
247 * @brief NOR MSP Init
248 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
249 * the configuration information for NOR module.
250 * @retval None
251 */
252 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
253 {
254 /* Prevent unused argument(s) compilation warning */
255 UNUSED(hnor);
256
257 /* NOTE : This function Should not be modified, when the callback is needed,
258 the HAL_NOR_MspInit could be implemented in the user file
259 */
260 }
261
262 /**
263 * @brief NOR MSP DeInit
264 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
265 * the configuration information for NOR module.
266 * @retval None
267 */
268 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
269 {
270 /* Prevent unused argument(s) compilation warning */
271 UNUSED(hnor);
272
273 /* NOTE : This function Should not be modified, when the callback is needed,
274 the HAL_NOR_MspDeInit could be implemented in the user file
275 */
276 }
277
278 /**
279 * @brief NOR MSP Wait for Ready/Busy signal
280 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
281 * the configuration information for NOR module.
282 * @param Timeout: Maximum timeout value
283 * @retval None
284 */
285 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
286 {
287 /* Prevent unused argument(s) compilation warning */
288 UNUSED(hnor);
289 UNUSED(Timeout);
290
291 /* NOTE : This function Should not be modified, when the callback is needed,
292 the HAL_NOR_MspWait could be implemented in the user file
293 */
294 }
295
296 /**
297 * @}
298 */
299
300 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
301 * @brief Input Output and memory control functions
302 *
303 @verbatim
304 ==============================================================================
305 ##### NOR Input and Output functions #####
306 ==============================================================================
307 [..]
308 This section provides functions allowing to use and control the NOR memory
309
310 @endverbatim
311 * @{
312 */
313
314 /**
315 * @brief Read NOR flash IDs
316 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
317 * the configuration information for NOR module.
318 * @param pNOR_ID : pointer to NOR ID structure
319 * @retval HAL status
320 */
321 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
322 {
323 uint32_t deviceaddress = 0;
324
325 /* Process Locked */
326 __HAL_LOCK(hnor);
327
328 /* Check the NOR controller state */
329 if(hnor->State == HAL_NOR_STATE_BUSY)
330 {
331 return HAL_BUSY;
332 }
333
334 /* Select the NOR device address */
335 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
336 {
337 deviceaddress = NOR_MEMORY_ADRESS1;
338 }
339 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
340 {
341 deviceaddress = NOR_MEMORY_ADRESS2;
342 }
343 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
344 {
345 deviceaddress = NOR_MEMORY_ADRESS3;
346 }
347 else /* FMC_NORSRAM_BANK4 */
348 {
349 deviceaddress = NOR_MEMORY_ADRESS4;
350 }
351
352 /* Update the NOR controller state */
353 hnor->State = HAL_NOR_STATE_BUSY;
354
355 /* Send read ID command */
356 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
357 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
358 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
359
360 /* Read the NOR IDs */
361 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
362 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
363 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
364 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
365
366 /* Check the NOR controller state */
367 hnor->State = HAL_NOR_STATE_READY;
368
369 /* Process unlocked */
370 __HAL_UNLOCK(hnor);
371
372 return HAL_OK;
373 }
374
375 /**
376 * @brief Returns the NOR memory to Read mode.
377 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
378 * the configuration information for NOR module.
379 * @retval HAL status
380 */
381 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
382 {
383 uint32_t deviceaddress = 0;
384
385 /* Process Locked */
386 __HAL_LOCK(hnor);
387
388 /* Check the NOR controller state */
389 if(hnor->State == HAL_NOR_STATE_BUSY)
390 {
391 return HAL_BUSY;
392 }
393
394 /* Select the NOR device address */
395 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
396 {
397 deviceaddress = NOR_MEMORY_ADRESS1;
398 }
399 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
400 {
401 deviceaddress = NOR_MEMORY_ADRESS2;
402 }
403 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
404 {
405 deviceaddress = NOR_MEMORY_ADRESS3;
406 }
407 else /* FMC_NORSRAM_BANK4 */
408 {
409 deviceaddress = NOR_MEMORY_ADRESS4;
410 }
411
412 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
413
414 /* Check the NOR controller state */
415 hnor->State = HAL_NOR_STATE_READY;
416
417 /* Process unlocked */
418 __HAL_UNLOCK(hnor);
419
420 return HAL_OK;
421 }
422
423 /**
424 * @brief Read data from NOR memory
425 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
426 * the configuration information for NOR module.
427 * @param pAddress: pointer to Device address
428 * @param pData : pointer to read data
429 * @retval HAL status
430 */
431 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
432 {
433 uint32_t deviceaddress = 0;
434
435 /* Process Locked */
436 __HAL_LOCK(hnor);
437
438 /* Check the NOR controller state */
439 if(hnor->State == HAL_NOR_STATE_BUSY)
440 {
441 return HAL_BUSY;
442 }
443
444 /* Select the NOR device address */
445 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
446 {
447 deviceaddress = NOR_MEMORY_ADRESS1;
448 }
449 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
450 {
451 deviceaddress = NOR_MEMORY_ADRESS2;
452 }
453 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
454 {
455 deviceaddress = NOR_MEMORY_ADRESS3;
456 }
457 else /* FMC_NORSRAM_BANK4 */
458 {
459 deviceaddress = NOR_MEMORY_ADRESS4;
460 }
461
462 /* Update the NOR controller state */
463 hnor->State = HAL_NOR_STATE_BUSY;
464
465 /* Send read data command */
466 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
467 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
468 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
469
470 /* Read the data */
471 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
472
473 /* Check the NOR controller state */
474 hnor->State = HAL_NOR_STATE_READY;
475
476 /* Process unlocked */
477 __HAL_UNLOCK(hnor);
478
479 return HAL_OK;
480 }
481
482 /**
483 * @brief Program data to NOR memory
484 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
485 * the configuration information for NOR module.
486 * @param pAddress: Device address
487 * @param pData : pointer to the data to write
488 * @retval HAL status
489 */
490 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
491 {
492 uint32_t deviceaddress = 0;
493
494 /* Process Locked */
495 __HAL_LOCK(hnor);
496
497 /* Check the NOR controller state */
498 if(hnor->State == HAL_NOR_STATE_BUSY)
499 {
500 return HAL_BUSY;
501 }
502
503 /* Select the NOR device address */
504 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
505 {
506 deviceaddress = NOR_MEMORY_ADRESS1;
507 }
508 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
509 {
510 deviceaddress = NOR_MEMORY_ADRESS2;
511 }
512 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
513 {
514 deviceaddress = NOR_MEMORY_ADRESS3;
515 }
516 else /* FMC_NORSRAM_BANK4 */
517 {
518 deviceaddress = NOR_MEMORY_ADRESS4;
519 }
520
521 /* Update the NOR controller state */
522 hnor->State = HAL_NOR_STATE_BUSY;
523
524 /* Send program data command */
525 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
526 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
527 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
528
529 /* Write the data */
530 NOR_WRITE(pAddress, *pData);
531
532 /* Check the NOR controller state */
533 hnor->State = HAL_NOR_STATE_READY;
534
535 /* Process unlocked */
536 __HAL_UNLOCK(hnor);
537
538 return HAL_OK;
539 }
540
541 /**
542 * @brief Reads a half-word buffer from the NOR memory.
543 * @param hnor: pointer to the NOR handle
544 * @param uwAddress: NOR memory internal address to read from.
545 * @param pData: pointer to the buffer that receives the data read from the
546 * NOR memory.
547 * @param uwBufferSize : number of Half word to read.
548 * @retval HAL status
549 */
550 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
551 {
552 uint32_t deviceaddress = 0;
553
554 /* Process Locked */
555 __HAL_LOCK(hnor);
556
557 /* Check the NOR controller state */
558 if(hnor->State == HAL_NOR_STATE_BUSY)
559 {
560 return HAL_BUSY;
561 }
562
563 /* Select the NOR device address */
564 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
565 {
566 deviceaddress = NOR_MEMORY_ADRESS1;
567 }
568 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
569 {
570 deviceaddress = NOR_MEMORY_ADRESS2;
571 }
572 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
573 {
574 deviceaddress = NOR_MEMORY_ADRESS3;
575 }
576 else /* FMC_NORSRAM_BANK4 */
577 {
578 deviceaddress = NOR_MEMORY_ADRESS4;
579 }
580
581 /* Update the NOR controller state */
582 hnor->State = HAL_NOR_STATE_BUSY;
583
584 /* Send read data command */
585 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
586 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
587 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
588
589 /* Read buffer */
590 while( uwBufferSize > 0)
591 {
592 *pData++ = *(__IO uint16_t *)uwAddress;
593 uwAddress += 2;
594 uwBufferSize--;
595 }
596
597 /* Check the NOR controller state */
598 hnor->State = HAL_NOR_STATE_READY;
599
600 /* Process unlocked */
601 __HAL_UNLOCK(hnor);
602
603 return HAL_OK;
604 }
605
606 /**
607 * @brief Writes a half-word buffer to the NOR memory. This function must be used
608 only with S29GL128P NOR memory.
609 * @param hnor: pointer to the NOR handle
610 * @param uwAddress: NOR memory internal start write address
611 * @param pData: pointer to source data buffer.
612 * @param uwBufferSize: Size of the buffer to write
613 * @retval HAL status
614 */
615 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
616 {
617 uint16_t * p_currentaddress = (uint16_t *)NULL;
618 uint16_t * p_endaddress = (uint16_t *)NULL;
619 uint32_t lastloadedaddress = 0, deviceaddress = 0;
620
621 /* Process Locked */
622 __HAL_LOCK(hnor);
623
624 /* Check the NOR controller state */
625 if(hnor->State == HAL_NOR_STATE_BUSY)
626 {
627 return HAL_BUSY;
628 }
629
630 /* Select the NOR device address */
631 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
632 {
633 deviceaddress = NOR_MEMORY_ADRESS1;
634 }
635 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
636 {
637 deviceaddress = NOR_MEMORY_ADRESS2;
638 }
639 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
640 {
641 deviceaddress = NOR_MEMORY_ADRESS3;
642 }
643 else /* FMC_NORSRAM_BANK4 */
644 {
645 deviceaddress = NOR_MEMORY_ADRESS4;
646 }
647
648 /* Update the NOR controller state */
649 hnor->State = HAL_NOR_STATE_BUSY;
650
651 /* Initialize variables */
652 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
653 p_endaddress = p_currentaddress + (uwBufferSize-1);
654 lastloadedaddress = (uint32_t)(uwAddress);
655
656 /* Issue unlock command sequence */
657 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
658 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
659
660 /* Write Buffer Load Command */
661 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
662 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1));
663
664 /* Load Data into NOR Buffer */
665 while(p_currentaddress <= p_endaddress)
666 {
667 /* Store last loaded address & data value (for polling) */
668 lastloadedaddress = (uint32_t)p_currentaddress;
669
670 NOR_WRITE(p_currentaddress, *pData++);
671
672 p_currentaddress ++;
673 }
674
675 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
676
677 /* Check the NOR controller state */
678 hnor->State = HAL_NOR_STATE_READY;
679
680 /* Process unlocked */
681 __HAL_UNLOCK(hnor);
682
683 return HAL_OK;
684
685 }
686
687 /**
688 * @brief Erase the specified block of the NOR memory
689 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
690 * the configuration information for NOR module.
691 * @param BlockAddress : Block to erase address
692 * @param Address: Device address
693 * @retval HAL status
694 */
695 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
696 {
697 uint32_t deviceaddress = 0;
698
699 /* Process Locked */
700 __HAL_LOCK(hnor);
701
702 /* Check the NOR controller state */
703 if(hnor->State == HAL_NOR_STATE_BUSY)
704 {
705 return HAL_BUSY;
706 }
707
708 /* Select the NOR device address */
709 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
710 {
711 deviceaddress = NOR_MEMORY_ADRESS1;
712 }
713 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
714 {
715 deviceaddress = NOR_MEMORY_ADRESS2;
716 }
717 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
718 {
719 deviceaddress = NOR_MEMORY_ADRESS3;
720 }
721 else /* FMC_NORSRAM_BANK4 */
722 {
723 deviceaddress = NOR_MEMORY_ADRESS4;
724 }
725
726 /* Update the NOR controller state */
727 hnor->State = HAL_NOR_STATE_BUSY;
728
729 /* Send block erase command sequence */
730 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
731 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
732 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
733 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
734 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
735 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
736
737 /* Check the NOR memory status and update the controller state */
738 hnor->State = HAL_NOR_STATE_READY;
739
740 /* Process unlocked */
741 __HAL_UNLOCK(hnor);
742
743 return HAL_OK;
744
745 }
746
747 /**
748 * @brief Erase the entire NOR chip.
749 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
750 * the configuration information for NOR module.
751 * @param Address : Device address
752 * @retval HAL status
753 */
754 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
755 {
756 uint32_t deviceaddress = 0;
757
758 /* Process Locked */
759 __HAL_LOCK(hnor);
760
761 /* Check the NOR controller state */
762 if(hnor->State == HAL_NOR_STATE_BUSY)
763 {
764 return HAL_BUSY;
765 }
766
767 /* Select the NOR device address */
768 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
769 {
770 deviceaddress = NOR_MEMORY_ADRESS1;
771 }
772 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
773 {
774 deviceaddress = NOR_MEMORY_ADRESS2;
775 }
776 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
777 {
778 deviceaddress = NOR_MEMORY_ADRESS3;
779 }
780 else /* FMC_NORSRAM_BANK4 */
781 {
782 deviceaddress = NOR_MEMORY_ADRESS4;
783 }
784
785 /* Update the NOR controller state */
786 hnor->State = HAL_NOR_STATE_BUSY;
787
788 /* Send NOR chip erase command sequence */
789 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
790 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
791 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
792 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
793 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
794 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
795
796 /* Check the NOR memory status and update the controller state */
797 hnor->State = HAL_NOR_STATE_READY;
798
799 /* Process unlocked */
800 __HAL_UNLOCK(hnor);
801
802 return HAL_OK;
803 }
804
805 /**
806 * @brief Read NOR flash CFI IDs
807 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
808 * the configuration information for NOR module.
809 * @param pNOR_CFI : pointer to NOR CFI IDs structure
810 * @retval HAL status
811 */
812 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
813 {
814 uint32_t deviceaddress = 0;
815
816 /* Process Locked */
817 __HAL_LOCK(hnor);
818
819 /* Check the NOR controller state */
820 if(hnor->State == HAL_NOR_STATE_BUSY)
821 {
822 return HAL_BUSY;
823 }
824
825 /* Select the NOR device address */
826 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
827 {
828 deviceaddress = NOR_MEMORY_ADRESS1;
829 }
830 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
831 {
832 deviceaddress = NOR_MEMORY_ADRESS2;
833 }
834 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
835 {
836 deviceaddress = NOR_MEMORY_ADRESS3;
837 }
838 else /* FMC_NORSRAM_BANK4 */
839 {
840 deviceaddress = NOR_MEMORY_ADRESS4;
841 }
842
843 /* Update the NOR controller state */
844 hnor->State = HAL_NOR_STATE_BUSY;
845
846 /* Send read CFI query command */
847 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
848
849 /* read the NOR CFI information */
850 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
851 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
852 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
853 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
854
855 /* Check the NOR controller state */
856 hnor->State = HAL_NOR_STATE_READY;
857
858 /* Process unlocked */
859 __HAL_UNLOCK(hnor);
860
861 return HAL_OK;
862 }
863
864 /**
865 * @}
866 */
867
868 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
869 * @brief management functions
870 *
871 @verbatim
872 ==============================================================================
873 ##### NOR Control functions #####
874 ==============================================================================
875 [..]
876 This subsection provides a set of functions allowing to control dynamically
877 the NOR interface.
878
879 @endverbatim
880 * @{
881 */
882
883 /**
884 * @brief Enables dynamically NOR write operation.
885 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
886 * the configuration information for NOR module.
887 * @retval HAL status
888 */
889 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
890 {
891 /* Process Locked */
892 __HAL_LOCK(hnor);
893
894 /* Enable write operation */
895 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
896
897 /* Update the NOR controller state */
898 hnor->State = HAL_NOR_STATE_READY;
899
900 /* Process unlocked */
901 __HAL_UNLOCK(hnor);
902
903 return HAL_OK;
904 }
905
906 /**
907 * @brief Disables dynamically NOR write operation.
908 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
909 * the configuration information for NOR module.
910 * @retval HAL status
911 */
912 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
913 {
914 /* Process Locked */
915 __HAL_LOCK(hnor);
916
917 /* Update the SRAM controller state */
918 hnor->State = HAL_NOR_STATE_BUSY;
919
920 /* Disable write operation */
921 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
922
923 /* Update the NOR controller state */
924 hnor->State = HAL_NOR_STATE_PROTECTED;
925
926 /* Process unlocked */
927 __HAL_UNLOCK(hnor);
928
929 return HAL_OK;
930 }
931
932 /**
933 * @}
934 */
935
936 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
937 * @brief Peripheral State functions
938 *
939 @verbatim
940 ==============================================================================
941 ##### NOR State functions #####
942 ==============================================================================
943 [..]
944 This subsection permits to get in run-time the status of the NOR controller
945 and the data flow.
946
947 @endverbatim
948 * @{
949 */
950
951 /**
952 * @brief return the NOR controller state
953 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
954 * the configuration information for NOR module.
955 * @retval NOR controller state
956 */
957 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
958 {
959 return hnor->State;
960 }
961
962 /**
963 * @brief Returns the NOR operation status.
964 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
965 * the configuration information for NOR module.
966 * @param Address: Device address
967 * @param Timeout: NOR programming Timeout
968 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
969 * or HAL_NOR_STATUS_TIMEOUT
970 */
971 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
972 {
973 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
974 uint16_t tmpSR1 = 0, tmpSR2 = 0;
975 uint32_t tickstart = 0;
976
977 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
978 HAL_NOR_MspWait(hnor, Timeout);
979
980 /* Get the NOR memory operation status -------------------------------------*/
981
982 /* Get tick */
983 tickstart = HAL_GetTick();
984 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
985 {
986 /* Check for the Timeout */
987 if(Timeout != HAL_MAX_DELAY)
988 {
989 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
990 {
991 status = HAL_NOR_STATUS_TIMEOUT;
992 }
993 }
994
995 /* Read NOR status register (DQ6 and DQ5) */
996 tmpSR1 = *(__IO uint16_t *)Address;
997 tmpSR2 = *(__IO uint16_t *)Address;
998
999 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1000 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
1001 {
1002 return HAL_NOR_STATUS_SUCCESS ;
1003 }
1004
1005 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
1006 {
1007 status = HAL_NOR_STATUS_ONGOING;
1008 }
1009
1010 tmpSR1 = *(__IO uint16_t *)Address;
1011 tmpSR2 = *(__IO uint16_t *)Address;
1012
1013 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1014 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
1015 {
1016 return HAL_NOR_STATUS_SUCCESS;
1017 }
1018 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
1019 {
1020 return HAL_NOR_STATUS_ERROR;
1021 }
1022 }
1023
1024 /* Return the operation status */
1025 return status;
1026 }
1027
1028 /**
1029 * @}
1030 */
1031
1032 /**
1033 * @}
1034 */
1035 #endif /* HAL_NOR_MODULE_ENABLED */
1036 /**
1037 * @}
1038 */
1039
1040 /**
1041 * @}
1042 */
1043
1044 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)