2 ******************************************************************************
3 * @file stm32f7xx_hal_nor.c
4 * @author MCD Application Team
7 * @brief NOR HAL module driver.
8 * This file provides a generic firmware to drive NOR memories mounted
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
16 This driver is a generic layered driver which contains a set of APIs used to
17 control NOR flash memories. It uses the FMC layer functions to interface
18 with NOR devices. This driver is used as follows:
20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
21 with control and timing parameters for both normal and extended mode.
23 (+) Read NOR flash memory manufacturer code and device IDs using the function
24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
25 structure declared by the function caller.
27 (+) Access NOR flash memory by read/write data unit operations using the functions
28 HAL_NOR_Read(), HAL_NOR_Program().
30 (+) Perform NOR flash erase block/chip operations using the functions
31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
35 structure declared by the function caller.
37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
40 (+) You can monitor the NOR device HAL state by calling the function
43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
44 If a NOR flash device contains different operations and/or implementations,
45 it should be implemented separately.
47 *** NOR HAL driver macros list ***
48 =============================================
50 Below the list of most used macros in NOR HAL driver.
52 (+) NOR_WRITE : NOR memory write data to specified address
55 ******************************************************************************
58 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 ******************************************************************************
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f7xx_hal.h"
88 /** @addtogroup STM32F7xx_HAL_Driver
93 * @brief NOR driver modules
96 #ifdef HAL_NOR_MODULE_ENABLED
98 /* Private typedef -----------------------------------------------------------*/
99 /* Private define ------------------------------------------------------------*/
101 /** @defgroup NOR_Private_Defines NOR Private Defines
105 /* Constants to define address to set to write a command */
106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
114 /* Constants to define data to program a command */
115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
130 /* Mask on NOR STATUS REGISTER */
131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
138 /* Private macro -------------------------------------------------------------*/
139 /* Private variables ---------------------------------------------------------*/
140 /** @defgroup NOR_Private_Variables NOR Private Variables
144 static uint32_t uwNORMemoryDataWidth
= NOR_MEMORY_8B
;
150 /* Private functions ---------------------------------------------------------*/
151 /* Exported functions --------------------------------------------------------*/
152 /** @defgroup NOR_Exported_Functions NOR Exported Functions
156 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
157 * @brief Initialization and Configuration functions
160 ==============================================================================
161 ##### NOR Initialization and de_initialization functions #####
162 ==============================================================================
164 This section provides functions allowing to initialize/de-initialize
172 * @brief Perform the NOR memory Initialization sequence
173 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
174 * the configuration information for NOR module.
175 * @param Timing: pointer to NOR control timing structure
176 * @param ExtTiming: pointer to NOR extended mode timing structure
179 HAL_StatusTypeDef
HAL_NOR_Init(NOR_HandleTypeDef
*hnor
, FMC_NORSRAM_TimingTypeDef
*Timing
, FMC_NORSRAM_TimingTypeDef
*ExtTiming
)
181 /* Check the NOR handle parameter */
187 if(hnor
->State
== HAL_NOR_STATE_RESET
)
189 /* Allocate lock resource and initialize it */
190 hnor
->Lock
= HAL_UNLOCKED
;
191 /* Initialize the low level hardware (MSP) */
192 HAL_NOR_MspInit(hnor
);
195 /* Initialize NOR control Interface */
196 FMC_NORSRAM_Init(hnor
->Instance
, &(hnor
->Init
));
198 /* Initialize NOR timing Interface */
199 FMC_NORSRAM_Timing_Init(hnor
->Instance
, Timing
, hnor
->Init
.NSBank
);
201 /* Initialize NOR extended mode timing Interface */
202 FMC_NORSRAM_Extended_Timing_Init(hnor
->Extended
, ExtTiming
, hnor
->Init
.NSBank
, hnor
->Init
.ExtendedMode
);
204 /* Enable the NORSRAM device */
205 __FMC_NORSRAM_ENABLE(hnor
->Instance
, hnor
->Init
.NSBank
);
207 /* Initialize NOR Memory Data Width*/
208 if (hnor
->Init
.MemoryDataWidth
== FMC_NORSRAM_MEM_BUS_WIDTH_8
)
210 uwNORMemoryDataWidth
= NOR_MEMORY_8B
;
214 uwNORMemoryDataWidth
= NOR_MEMORY_16B
;
217 /* Check the NOR controller state */
218 hnor
->State
= HAL_NOR_STATE_READY
;
224 * @brief Perform NOR memory De-Initialization sequence
225 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
226 * the configuration information for NOR module.
229 HAL_StatusTypeDef
HAL_NOR_DeInit(NOR_HandleTypeDef
*hnor
)
231 /* De-Initialize the low level hardware (MSP) */
232 HAL_NOR_MspDeInit(hnor
);
234 /* Configure the NOR registers with their reset values */
235 FMC_NORSRAM_DeInit(hnor
->Instance
, hnor
->Extended
, hnor
->Init
.NSBank
);
237 /* Update the NOR controller state */
238 hnor
->State
= HAL_NOR_STATE_RESET
;
247 * @brief NOR MSP Init
248 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
249 * the configuration information for NOR module.
252 __weak
void HAL_NOR_MspInit(NOR_HandleTypeDef
*hnor
)
254 /* Prevent unused argument(s) compilation warning */
257 /* NOTE : This function Should not be modified, when the callback is needed,
258 the HAL_NOR_MspInit could be implemented in the user file
263 * @brief NOR MSP DeInit
264 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
265 * the configuration information for NOR module.
268 __weak
void HAL_NOR_MspDeInit(NOR_HandleTypeDef
*hnor
)
270 /* Prevent unused argument(s) compilation warning */
273 /* NOTE : This function Should not be modified, when the callback is needed,
274 the HAL_NOR_MspDeInit could be implemented in the user file
279 * @brief NOR MSP Wait for Ready/Busy signal
280 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
281 * the configuration information for NOR module.
282 * @param Timeout: Maximum timeout value
285 __weak
void HAL_NOR_MspWait(NOR_HandleTypeDef
*hnor
, uint32_t Timeout
)
287 /* Prevent unused argument(s) compilation warning */
291 /* NOTE : This function Should not be modified, when the callback is needed,
292 the HAL_NOR_MspWait could be implemented in the user file
300 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
301 * @brief Input Output and memory control functions
304 ==============================================================================
305 ##### NOR Input and Output functions #####
306 ==============================================================================
308 This section provides functions allowing to use and control the NOR memory
315 * @brief Read NOR flash IDs
316 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
317 * the configuration information for NOR module.
318 * @param pNOR_ID : pointer to NOR ID structure
321 HAL_StatusTypeDef
HAL_NOR_Read_ID(NOR_HandleTypeDef
*hnor
, NOR_IDTypeDef
*pNOR_ID
)
323 uint32_t deviceaddress
= 0;
328 /* Check the NOR controller state */
329 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
334 /* Select the NOR device address */
335 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
337 deviceaddress
= NOR_MEMORY_ADRESS1
;
339 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
341 deviceaddress
= NOR_MEMORY_ADRESS2
;
343 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
345 deviceaddress
= NOR_MEMORY_ADRESS3
;
347 else /* FMC_NORSRAM_BANK4 */
349 deviceaddress
= NOR_MEMORY_ADRESS4
;
352 /* Update the NOR controller state */
353 hnor
->State
= HAL_NOR_STATE_BUSY
;
355 /* Send read ID command */
356 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST
), NOR_CMD_DATA_FIRST
);
357 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SECOND
), NOR_CMD_DATA_SECOND
);
358 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_THIRD
), NOR_CMD_DATA_AUTO_SELECT
);
360 /* Read the NOR IDs */
361 pNOR_ID
->Manufacturer_Code
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, MC_ADDRESS
);
362 pNOR_ID
->Device_Code1
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, DEVICE_CODE1_ADDR
);
363 pNOR_ID
->Device_Code2
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, DEVICE_CODE2_ADDR
);
364 pNOR_ID
->Device_Code3
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, DEVICE_CODE3_ADDR
);
366 /* Check the NOR controller state */
367 hnor
->State
= HAL_NOR_STATE_READY
;
369 /* Process unlocked */
376 * @brief Returns the NOR memory to Read mode.
377 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
378 * the configuration information for NOR module.
381 HAL_StatusTypeDef
HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef
*hnor
)
383 uint32_t deviceaddress
= 0;
388 /* Check the NOR controller state */
389 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
394 /* Select the NOR device address */
395 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
397 deviceaddress
= NOR_MEMORY_ADRESS1
;
399 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
401 deviceaddress
= NOR_MEMORY_ADRESS2
;
403 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
405 deviceaddress
= NOR_MEMORY_ADRESS3
;
407 else /* FMC_NORSRAM_BANK4 */
409 deviceaddress
= NOR_MEMORY_ADRESS4
;
412 NOR_WRITE(deviceaddress
, NOR_CMD_DATA_READ_RESET
);
414 /* Check the NOR controller state */
415 hnor
->State
= HAL_NOR_STATE_READY
;
417 /* Process unlocked */
424 * @brief Read data from NOR memory
425 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
426 * the configuration information for NOR module.
427 * @param pAddress: pointer to Device address
428 * @param pData : pointer to read data
431 HAL_StatusTypeDef
HAL_NOR_Read(NOR_HandleTypeDef
*hnor
, uint32_t *pAddress
, uint16_t *pData
)
433 uint32_t deviceaddress
= 0;
438 /* Check the NOR controller state */
439 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
444 /* Select the NOR device address */
445 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
447 deviceaddress
= NOR_MEMORY_ADRESS1
;
449 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
451 deviceaddress
= NOR_MEMORY_ADRESS2
;
453 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
455 deviceaddress
= NOR_MEMORY_ADRESS3
;
457 else /* FMC_NORSRAM_BANK4 */
459 deviceaddress
= NOR_MEMORY_ADRESS4
;
462 /* Update the NOR controller state */
463 hnor
->State
= HAL_NOR_STATE_BUSY
;
465 /* Send read data command */
466 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST
), NOR_CMD_DATA_FIRST
);
467 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SECOND
), NOR_CMD_DATA_SECOND
);
468 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_THIRD
), NOR_CMD_DATA_READ_RESET
);
471 *pData
= *(__IO
uint32_t *)(uint32_t)pAddress
;
473 /* Check the NOR controller state */
474 hnor
->State
= HAL_NOR_STATE_READY
;
476 /* Process unlocked */
483 * @brief Program data to NOR memory
484 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
485 * the configuration information for NOR module.
486 * @param pAddress: Device address
487 * @param pData : pointer to the data to write
490 HAL_StatusTypeDef
HAL_NOR_Program(NOR_HandleTypeDef
*hnor
, uint32_t *pAddress
, uint16_t *pData
)
492 uint32_t deviceaddress
= 0;
497 /* Check the NOR controller state */
498 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
503 /* Select the NOR device address */
504 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
506 deviceaddress
= NOR_MEMORY_ADRESS1
;
508 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
510 deviceaddress
= NOR_MEMORY_ADRESS2
;
512 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
514 deviceaddress
= NOR_MEMORY_ADRESS3
;
516 else /* FMC_NORSRAM_BANK4 */
518 deviceaddress
= NOR_MEMORY_ADRESS4
;
521 /* Update the NOR controller state */
522 hnor
->State
= HAL_NOR_STATE_BUSY
;
524 /* Send program data command */
525 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST
), NOR_CMD_DATA_FIRST
);
526 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SECOND
), NOR_CMD_DATA_SECOND
);
527 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_THIRD
), NOR_CMD_DATA_PROGRAM
);
530 NOR_WRITE(pAddress
, *pData
);
532 /* Check the NOR controller state */
533 hnor
->State
= HAL_NOR_STATE_READY
;
535 /* Process unlocked */
542 * @brief Reads a half-word buffer from the NOR memory.
543 * @param hnor: pointer to the NOR handle
544 * @param uwAddress: NOR memory internal address to read from.
545 * @param pData: pointer to the buffer that receives the data read from the
547 * @param uwBufferSize : number of Half word to read.
550 HAL_StatusTypeDef
HAL_NOR_ReadBuffer(NOR_HandleTypeDef
*hnor
, uint32_t uwAddress
, uint16_t *pData
, uint32_t uwBufferSize
)
552 uint32_t deviceaddress
= 0;
557 /* Check the NOR controller state */
558 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
563 /* Select the NOR device address */
564 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
566 deviceaddress
= NOR_MEMORY_ADRESS1
;
568 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
570 deviceaddress
= NOR_MEMORY_ADRESS2
;
572 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
574 deviceaddress
= NOR_MEMORY_ADRESS3
;
576 else /* FMC_NORSRAM_BANK4 */
578 deviceaddress
= NOR_MEMORY_ADRESS4
;
581 /* Update the NOR controller state */
582 hnor
->State
= HAL_NOR_STATE_BUSY
;
584 /* Send read data command */
585 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST
), NOR_CMD_DATA_FIRST
);
586 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SECOND
), NOR_CMD_DATA_SECOND
);
587 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_THIRD
), NOR_CMD_DATA_READ_RESET
);
590 while( uwBufferSize
> 0)
592 *pData
++ = *(__IO
uint16_t *)uwAddress
;
597 /* Check the NOR controller state */
598 hnor
->State
= HAL_NOR_STATE_READY
;
600 /* Process unlocked */
607 * @brief Writes a half-word buffer to the NOR memory. This function must be used
608 only with S29GL128P NOR memory.
609 * @param hnor: pointer to the NOR handle
610 * @param uwAddress: NOR memory internal start write address
611 * @param pData: pointer to source data buffer.
612 * @param uwBufferSize: Size of the buffer to write
615 HAL_StatusTypeDef
HAL_NOR_ProgramBuffer(NOR_HandleTypeDef
*hnor
, uint32_t uwAddress
, uint16_t *pData
, uint32_t uwBufferSize
)
617 uint16_t * p_currentaddress
= (uint16_t *)NULL
;
618 uint16_t * p_endaddress
= (uint16_t *)NULL
;
619 uint32_t lastloadedaddress
= 0, deviceaddress
= 0;
624 /* Check the NOR controller state */
625 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
630 /* Select the NOR device address */
631 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
633 deviceaddress
= NOR_MEMORY_ADRESS1
;
635 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
637 deviceaddress
= NOR_MEMORY_ADRESS2
;
639 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
641 deviceaddress
= NOR_MEMORY_ADRESS3
;
643 else /* FMC_NORSRAM_BANK4 */
645 deviceaddress
= NOR_MEMORY_ADRESS4
;
648 /* Update the NOR controller state */
649 hnor
->State
= HAL_NOR_STATE_BUSY
;
651 /* Initialize variables */
652 p_currentaddress
= (uint16_t*)((uint32_t)(uwAddress
));
653 p_endaddress
= p_currentaddress
+ (uwBufferSize
-1);
654 lastloadedaddress
= (uint32_t)(uwAddress
);
656 /* Issue unlock command sequence */
657 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST
), NOR_CMD_DATA_FIRST
);
658 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SECOND
), NOR_CMD_DATA_SECOND
);
660 /* Write Buffer Load Command */
661 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, uwAddress
), NOR_CMD_DATA_BUFFER_AND_PROG
);
662 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, uwAddress
), (uwBufferSize
- 1));
664 /* Load Data into NOR Buffer */
665 while(p_currentaddress
<= p_endaddress
)
667 /* Store last loaded address & data value (for polling) */
668 lastloadedaddress
= (uint32_t)p_currentaddress
;
670 NOR_WRITE(p_currentaddress
, *pData
++);
675 NOR_WRITE((uint32_t)(lastloadedaddress
), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM
);
677 /* Check the NOR controller state */
678 hnor
->State
= HAL_NOR_STATE_READY
;
680 /* Process unlocked */
688 * @brief Erase the specified block of the NOR memory
689 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
690 * the configuration information for NOR module.
691 * @param BlockAddress : Block to erase address
692 * @param Address: Device address
695 HAL_StatusTypeDef
HAL_NOR_Erase_Block(NOR_HandleTypeDef
*hnor
, uint32_t BlockAddress
, uint32_t Address
)
697 uint32_t deviceaddress
= 0;
702 /* Check the NOR controller state */
703 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
708 /* Select the NOR device address */
709 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
711 deviceaddress
= NOR_MEMORY_ADRESS1
;
713 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
715 deviceaddress
= NOR_MEMORY_ADRESS2
;
717 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
719 deviceaddress
= NOR_MEMORY_ADRESS3
;
721 else /* FMC_NORSRAM_BANK4 */
723 deviceaddress
= NOR_MEMORY_ADRESS4
;
726 /* Update the NOR controller state */
727 hnor
->State
= HAL_NOR_STATE_BUSY
;
729 /* Send block erase command sequence */
730 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST
), NOR_CMD_DATA_FIRST
);
731 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SECOND
), NOR_CMD_DATA_SECOND
);
732 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_THIRD
), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
);
733 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FOURTH
), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
);
734 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIFTH
), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
);
735 NOR_WRITE((uint32_t)(BlockAddress
+ Address
), NOR_CMD_DATA_BLOCK_ERASE
);
737 /* Check the NOR memory status and update the controller state */
738 hnor
->State
= HAL_NOR_STATE_READY
;
740 /* Process unlocked */
748 * @brief Erase the entire NOR chip.
749 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
750 * the configuration information for NOR module.
751 * @param Address : Device address
754 HAL_StatusTypeDef
HAL_NOR_Erase_Chip(NOR_HandleTypeDef
*hnor
, uint32_t Address
)
756 uint32_t deviceaddress
= 0;
761 /* Check the NOR controller state */
762 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
767 /* Select the NOR device address */
768 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
770 deviceaddress
= NOR_MEMORY_ADRESS1
;
772 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
774 deviceaddress
= NOR_MEMORY_ADRESS2
;
776 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
778 deviceaddress
= NOR_MEMORY_ADRESS3
;
780 else /* FMC_NORSRAM_BANK4 */
782 deviceaddress
= NOR_MEMORY_ADRESS4
;
785 /* Update the NOR controller state */
786 hnor
->State
= HAL_NOR_STATE_BUSY
;
788 /* Send NOR chip erase command sequence */
789 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST
), NOR_CMD_DATA_FIRST
);
790 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SECOND
), NOR_CMD_DATA_SECOND
);
791 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_THIRD
), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
);
792 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FOURTH
), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
);
793 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIFTH
), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
);
794 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_SIXTH
), NOR_CMD_DATA_CHIP_ERASE
);
796 /* Check the NOR memory status and update the controller state */
797 hnor
->State
= HAL_NOR_STATE_READY
;
799 /* Process unlocked */
806 * @brief Read NOR flash CFI IDs
807 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
808 * the configuration information for NOR module.
809 * @param pNOR_CFI : pointer to NOR CFI IDs structure
812 HAL_StatusTypeDef
HAL_NOR_Read_CFI(NOR_HandleTypeDef
*hnor
, NOR_CFITypeDef
*pNOR_CFI
)
814 uint32_t deviceaddress
= 0;
819 /* Check the NOR controller state */
820 if(hnor
->State
== HAL_NOR_STATE_BUSY
)
825 /* Select the NOR device address */
826 if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK1
)
828 deviceaddress
= NOR_MEMORY_ADRESS1
;
830 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK2
)
832 deviceaddress
= NOR_MEMORY_ADRESS2
;
834 else if (hnor
->Init
.NSBank
== FMC_NORSRAM_BANK3
)
836 deviceaddress
= NOR_MEMORY_ADRESS3
;
838 else /* FMC_NORSRAM_BANK4 */
840 deviceaddress
= NOR_MEMORY_ADRESS4
;
843 /* Update the NOR controller state */
844 hnor
->State
= HAL_NOR_STATE_BUSY
;
846 /* Send read CFI query command */
847 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, NOR_CMD_ADDRESS_FIRST_CFI
), NOR_CMD_DATA_CFI
);
849 /* read the NOR CFI information */
850 pNOR_CFI
->CFI_1
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, CFI1_ADDRESS
);
851 pNOR_CFI
->CFI_2
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, CFI2_ADDRESS
);
852 pNOR_CFI
->CFI_3
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, CFI3_ADDRESS
);
853 pNOR_CFI
->CFI_4
= *(__IO
uint16_t *) NOR_ADDR_SHIFT(deviceaddress
, uwNORMemoryDataWidth
, CFI4_ADDRESS
);
855 /* Check the NOR controller state */
856 hnor
->State
= HAL_NOR_STATE_READY
;
858 /* Process unlocked */
868 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
869 * @brief management functions
872 ==============================================================================
873 ##### NOR Control functions #####
874 ==============================================================================
876 This subsection provides a set of functions allowing to control dynamically
884 * @brief Enables dynamically NOR write operation.
885 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
886 * the configuration information for NOR module.
889 HAL_StatusTypeDef
HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef
*hnor
)
894 /* Enable write operation */
895 FMC_NORSRAM_WriteOperation_Enable(hnor
->Instance
, hnor
->Init
.NSBank
);
897 /* Update the NOR controller state */
898 hnor
->State
= HAL_NOR_STATE_READY
;
900 /* Process unlocked */
907 * @brief Disables dynamically NOR write operation.
908 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
909 * the configuration information for NOR module.
912 HAL_StatusTypeDef
HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef
*hnor
)
917 /* Update the SRAM controller state */
918 hnor
->State
= HAL_NOR_STATE_BUSY
;
920 /* Disable write operation */
921 FMC_NORSRAM_WriteOperation_Disable(hnor
->Instance
, hnor
->Init
.NSBank
);
923 /* Update the NOR controller state */
924 hnor
->State
= HAL_NOR_STATE_PROTECTED
;
926 /* Process unlocked */
936 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
937 * @brief Peripheral State functions
940 ==============================================================================
941 ##### NOR State functions #####
942 ==============================================================================
944 This subsection permits to get in run-time the status of the NOR controller
952 * @brief return the NOR controller state
953 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
954 * the configuration information for NOR module.
955 * @retval NOR controller state
957 HAL_NOR_StateTypeDef
HAL_NOR_GetState(NOR_HandleTypeDef
*hnor
)
963 * @brief Returns the NOR operation status.
964 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
965 * the configuration information for NOR module.
966 * @param Address: Device address
967 * @param Timeout: NOR programming Timeout
968 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
969 * or HAL_NOR_STATUS_TIMEOUT
971 HAL_NOR_StatusTypeDef
HAL_NOR_GetStatus(NOR_HandleTypeDef
*hnor
, uint32_t Address
, uint32_t Timeout
)
973 HAL_NOR_StatusTypeDef status
= HAL_NOR_STATUS_ONGOING
;
974 uint16_t tmpSR1
= 0, tmpSR2
= 0;
975 uint32_t tickstart
= 0;
977 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
978 HAL_NOR_MspWait(hnor
, Timeout
);
980 /* Get the NOR memory operation status -------------------------------------*/
983 tickstart
= HAL_GetTick();
984 while((status
!= HAL_NOR_STATUS_SUCCESS
) && (status
!= HAL_NOR_STATUS_TIMEOUT
))
986 /* Check for the Timeout */
987 if(Timeout
!= HAL_MAX_DELAY
)
989 if((Timeout
== 0)||((HAL_GetTick() - tickstart
) > Timeout
))
991 status
= HAL_NOR_STATUS_TIMEOUT
;
995 /* Read NOR status register (DQ6 and DQ5) */
996 tmpSR1
= *(__IO
uint16_t *)Address
;
997 tmpSR2
= *(__IO
uint16_t *)Address
;
999 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1000 if((tmpSR1
& NOR_MASK_STATUS_DQ6
) == (tmpSR2
& NOR_MASK_STATUS_DQ6
))
1002 return HAL_NOR_STATUS_SUCCESS
;
1005 if((tmpSR1
& NOR_MASK_STATUS_DQ5
) == NOR_MASK_STATUS_DQ5
)
1007 status
= HAL_NOR_STATUS_ONGOING
;
1010 tmpSR1
= *(__IO
uint16_t *)Address
;
1011 tmpSR2
= *(__IO
uint16_t *)Address
;
1013 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1014 if((tmpSR1
& NOR_MASK_STATUS_DQ6
) == (tmpSR2
& NOR_MASK_STATUS_DQ6
))
1016 return HAL_NOR_STATUS_SUCCESS
;
1018 if((tmpSR1
& NOR_MASK_STATUS_DQ5
) == NOR_MASK_STATUS_DQ5
)
1020 return HAL_NOR_STATUS_ERROR
;
1024 /* Return the operation status */
1035 #endif /* HAL_NOR_MODULE_ENABLED */
1044 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/