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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_pwr_ex.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief Extended PWR HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of PWR extension peripheral:
10 * + Peripheral Extended features functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32f7xx_hal.h"
44
45 /** @addtogroup STM32F7xx_HAL_Driver
46 * @{
47 */
48
49 /** @defgroup PWREx PWREx
50 * @brief PWR HAL module driver
51 * @{
52 */
53
54 #ifdef HAL_PWR_MODULE_ENABLED
55
56 /* Private typedef -----------------------------------------------------------*/
57 /* Private define ------------------------------------------------------------*/
58 /** @addtogroup PWREx_Private_Constants
59 * @{
60 */
61 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
62 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
63 #define PWR_BKPREG_TIMEOUT_VALUE 1000
64 #define PWR_VOSRDY_TIMEOUT_VALUE 1000
65 /**
66 * @}
67 */
68
69 /* Private macro -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private function prototypes -----------------------------------------------*/
72 /* Private functions ---------------------------------------------------------*/
73 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
74 * @{
75 */
76
77 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
78 * @brief Peripheral Extended features functions
79 *
80 @verbatim
81
82 ===============================================================================
83 ##### Peripheral extended features functions #####
84 ===============================================================================
85
86 *** Main and Backup Regulators configuration ***
87 ================================================
88 [..]
89 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
90 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
91 retained even in Standby or VBAT mode when the low power backup regulator
92 is enabled. It can be considered as an internal EEPROM when VBAT is
93 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
94 enable the low power backup regulator.
95
96 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
97 the backup SRAM is powered from VDD which replaces the VBAT power supply to
98 save battery life.
99
100 (+) The backup SRAM is not mass erased by a tamper event. It is read
101 protected to prevent confidential data, such as cryptographic private
102 key, from being accessed. The backup SRAM can be erased only through
103 the Flash interface when a protection level change from level 1 to
104 level 0 is requested.
105 -@- Refer to the description of Read protection (RDP) in the Flash
106 programming manual.
107
108 (+) The main internal regulator can be configured to have a tradeoff between
109 performance and power consumption when the device does not operate at
110 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
111 macro which configure VOS bit in PWR_CR register
112
113 Refer to the product datasheets for more details.
114
115 *** FLASH Power Down configuration ****
116 =======================================
117 [..]
118 (+) By setting the FPDS bit in the PWR_CR register by using the
119 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
120 down mode when the device enters Stop mode. When the Flash memory
121 is in power down mode, an additional startup delay is incurred when
122 waking up from Stop mode.
123
124 *** Over-Drive and Under-Drive configuration ****
125 =================================================
126 [..]
127 (+) In Run mode: the main regulator has 2 operating modes available:
128 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
129 voltage scaling (scale 1, scale 2 or scale 3)
130 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
131 higher frequency than the normal mode for a given voltage scaling (scale 1,
132 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
133 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
134 the sequence described in Reference manual.
135
136 (+) In Stop mode: the main regulator or low power regulator supplies a low power
137 voltage to the 1.2V domain, thus preserving the content of registers
138 and internal SRAM. 2 operating modes are available:
139 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
140 available when the main regulator or the low power regulator is used in Scale 3 or
141 low voltage mode.
142 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
143 available when the main regulator or the low power regulator is in low voltage mode.
144
145 @endverbatim
146 * @{
147 */
148
149 /**
150 * @brief Enables the Backup Regulator.
151 * @retval HAL status
152 */
153 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
154 {
155 uint32_t tickstart = 0;
156
157 /* Enable Backup regulator */
158 PWR->CSR1 |= PWR_CSR1_BRE;
159
160 /* Workaround for the following hardware bug: */
161 /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
162 PWR->CSR1 |= PWR_CSR1_EIWUP;
163
164 /* Get tick */
165 tickstart = HAL_GetTick();
166
167 /* Wait till Backup regulator ready flag is set */
168 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
169 {
170 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
171 {
172 return HAL_TIMEOUT;
173 }
174 }
175 return HAL_OK;
176 }
177
178 /**
179 * @brief Disables the Backup Regulator.
180 * @retval HAL status
181 */
182 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
183 {
184 uint32_t tickstart = 0;
185
186 /* Disable Backup regulator */
187 PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
188
189 /* Workaround for the following hardware bug: */
190 /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
191 PWR->CSR1 |= PWR_CSR1_EIWUP;
192
193 /* Get tick */
194 tickstart = HAL_GetTick();
195
196 /* Wait till Backup regulator ready flag is set */
197 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
198 {
199 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
200 {
201 return HAL_TIMEOUT;
202 }
203 }
204 return HAL_OK;
205 }
206
207 /**
208 * @brief Enables the Flash Power Down in Stop mode.
209 * @retval None
210 */
211 void HAL_PWREx_EnableFlashPowerDown(void)
212 {
213 /* Enable the Flash Power Down */
214 PWR->CR1 |= PWR_CR1_FPDS;
215 }
216
217 /**
218 * @brief Disables the Flash Power Down in Stop mode.
219 * @retval None
220 */
221 void HAL_PWREx_DisableFlashPowerDown(void)
222 {
223 /* Disable the Flash Power Down */
224 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
225 }
226
227 /**
228 * @brief Enables Main Regulator low voltage mode.
229 * @retval None
230 */
231 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
232 {
233 /* Enable Main regulator low voltage */
234 PWR->CR1 |= PWR_CR1_MRUDS;
235 }
236
237 /**
238 * @brief Disables Main Regulator low voltage mode.
239 * @retval None
240 */
241 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
242 {
243 /* Disable Main regulator low voltage */
244 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
245 }
246
247 /**
248 * @brief Enables Low Power Regulator low voltage mode.
249 * @retval None
250 */
251 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
252 {
253 /* Enable low power regulator */
254 PWR->CR1 |= PWR_CR1_LPUDS;
255 }
256
257 /**
258 * @brief Disables Low Power Regulator low voltage mode.
259 * @retval None
260 */
261 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
262 {
263 /* Disable low power regulator */
264 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
265 }
266
267 /**
268 * @brief Activates the Over-Drive mode.
269 * @note This mode allows the CPU and the core logic to operate at a higher frequency
270 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
271 * @note It is recommended to enter or exit Over-drive mode when the application is not running
272 * critical tasks and when the system clock source is either HSI or HSE.
273 * During the Over-drive switch activation, no peripheral clocks should be enabled.
274 * The peripheral clocks must be enabled once the Over-drive mode is activated.
275 * @retval HAL status
276 */
277 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
278 {
279 uint32_t tickstart = 0;
280
281 __HAL_RCC_PWR_CLK_ENABLE();
282
283 /* Enable the Over-drive to extend the clock frequency to 216 MHz */
284 __HAL_PWR_OVERDRIVE_ENABLE();
285
286 /* Get tick */
287 tickstart = HAL_GetTick();
288
289 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
290 {
291 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
292 {
293 return HAL_TIMEOUT;
294 }
295 }
296
297 /* Enable the Over-drive switch */
298 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
299
300 /* Get tick */
301 tickstart = HAL_GetTick();
302
303 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
304 {
305 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
306 {
307 return HAL_TIMEOUT;
308 }
309 }
310 return HAL_OK;
311 }
312
313 /**
314 * @brief Deactivates the Over-Drive mode.
315 * @note This mode allows the CPU and the core logic to operate at a higher frequency
316 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
317 * @note It is recommended to enter or exit Over-drive mode when the application is not running
318 * critical tasks and when the system clock source is either HSI or HSE.
319 * During the Over-drive switch activation, no peripheral clocks should be enabled.
320 * The peripheral clocks must be enabled once the Over-drive mode is activated.
321 * @retval HAL status
322 */
323 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
324 {
325 uint32_t tickstart = 0;
326
327 __HAL_RCC_PWR_CLK_ENABLE();
328
329 /* Disable the Over-drive switch */
330 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
331
332 /* Get tick */
333 tickstart = HAL_GetTick();
334
335 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
336 {
337 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
338 {
339 return HAL_TIMEOUT;
340 }
341 }
342
343 /* Disable the Over-drive */
344 __HAL_PWR_OVERDRIVE_DISABLE();
345
346 /* Get tick */
347 tickstart = HAL_GetTick();
348
349 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
350 {
351 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
352 {
353 return HAL_TIMEOUT;
354 }
355 }
356
357 return HAL_OK;
358 }
359
360 /**
361 * @brief Enters in Under-Drive STOP mode.
362 *
363 * @note This mode can be selected only when the Under-Drive is already active
364 *
365 * @note This mode is enabled only with STOP low power mode.
366 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
367 * mode is only available when the main regulator or the low power regulator
368 * is in low voltage mode
369 *
370 * @note If the Under-drive mode was enabled, it is automatically disabled after
371 * exiting Stop mode.
372 * When the voltage regulator operates in Under-drive mode, an additional
373 * startup delay is induced when waking up from Stop mode.
374 *
375 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
376 *
377 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
378 * the HSI RC oscillator is selected as system clock.
379 *
380 * @note When the voltage regulator operates in low power mode, an additional
381 * startup delay is incurred when waking up from Stop mode.
382 * By keeping the internal regulator ON during Stop mode, the consumption
383 * is higher although the startup time is reduced.
384 *
385 * @param Regulator: specifies the regulator state in STOP mode.
386 * This parameter can be one of the following values:
387 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
388 * and Flash memory in power-down when the device is in Stop under-drive mode
389 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
390 * and Flash memory in power-down when the device is in Stop under-drive mode
391 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
392 * This parameter can be one of the following values:
393 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
394 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
395 * @retval None
396 */
397 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
398 {
399 uint32_t tempreg = 0;
400 uint32_t tickstart = 0;
401
402 /* Check the parameters */
403 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
404 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
405
406 /* Enable Power ctrl clock */
407 __HAL_RCC_PWR_CLK_ENABLE();
408 /* Enable the Under-drive Mode ---------------------------------------------*/
409 /* Clear Under-drive flag */
410 __HAL_PWR_CLEAR_ODRUDR_FLAG();
411
412 /* Enable the Under-drive */
413 __HAL_PWR_UNDERDRIVE_ENABLE();
414
415 /* Get tick */
416 tickstart = HAL_GetTick();
417
418 /* Wait for UnderDrive mode is ready */
419 while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
420 {
421 if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
422 {
423 return HAL_TIMEOUT;
424 }
425 }
426
427 /* Select the regulator state in STOP mode ---------------------------------*/
428 tempreg = PWR->CR1;
429 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
430 tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
431
432 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
433 tempreg |= Regulator;
434
435 /* Store the new value */
436 PWR->CR1 = tempreg;
437
438 /* Set SLEEPDEEP bit of Cortex System Control Register */
439 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
440
441 /* Select STOP mode entry --------------------------------------------------*/
442 if(STOPEntry == PWR_SLEEPENTRY_WFI)
443 {
444 /* Request Wait For Interrupt */
445 __WFI();
446 }
447 else
448 {
449 /* Request Wait For Event */
450 __WFE();
451 }
452 /* Reset SLEEPDEEP bit of Cortex System Control Register */
453 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
454
455 return HAL_OK;
456 }
457
458 /**
459 * @brief Returns Voltage Scaling Range.
460 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
461 * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
462 */
463 uint32_t HAL_PWREx_GetVoltageRange(void)
464 {
465 return (PWR->CR1 & PWR_CR1_VOS);
466 }
467
468 /**
469 * @brief Configures the main internal regulator output voltage.
470 * @param VoltageScaling: specifies the regulator output voltage to achieve
471 * a tradeoff between performance and power consumption.
472 * This parameter can be one of the following values:
473 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
474 * typical output voltage at 1.4 V,
475 * system frequency up to 216 MHz.
476 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
477 * typical output voltage at 1.2 V,
478 * system frequency up to 180 MHz.
479 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
480 * typical output voltage at 1.00 V,
481 * system frequency up to 151 MHz.
482 * @note To update the system clock frequency(SYSCLK):
483 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
484 * - Call the HAL_RCC_OscConfig() to configure the PLL.
485 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
486 * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
487 * @note The scale can be modified only when the HSI or HSE clock source is selected
488 * as system clock source, otherwise the API returns HAL_ERROR.
489 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
490 * value in the PWR_CR1 register are not taken in account.
491 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
492 * @note The new voltage scale is active only when the PLL is ON.
493 * @retval HAL Status
494 */
495 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
496 {
497 uint32_t tickstart = 0;
498
499 assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
500
501 /* Enable Power ctrl clock */
502 __HAL_RCC_PWR_CLK_ENABLE();
503
504 /* Check if the PLL is used as system clock or not */
505 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
506 {
507 /* Disable the main PLL */
508 __HAL_RCC_PLL_DISABLE();
509
510 /* Get Start Tick */
511 tickstart = HAL_GetTick();
512 /* Wait till PLL is disabled */
513 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
514 {
515 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
516 {
517 return HAL_TIMEOUT;
518 }
519 }
520
521 /* Set Range */
522 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
523
524 /* Enable the main PLL */
525 __HAL_RCC_PLL_ENABLE();
526
527 /* Get Start Tick */
528 tickstart = HAL_GetTick();
529 /* Wait till PLL is ready */
530 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
531 {
532 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
533 {
534 return HAL_TIMEOUT;
535 }
536 }
537
538 /* Get Start Tick */
539 tickstart = HAL_GetTick();
540 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
541 {
542 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
543 {
544 return HAL_TIMEOUT;
545 }
546 }
547 }
548 else
549 {
550 return HAL_ERROR;
551 }
552 return HAL_OK;
553 }
554
555 /**
556 * @}
557 */
558
559 /**
560 * @}
561 */
562
563 #endif /* HAL_PWR_MODULE_ENABLED */
564 /**
565 * @}
566 */
567
568 /**
569 * @}
570 */
571
572 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)