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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_rcc.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_rcc.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief RCC HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Reset and Clock Control (RCC) peripheral:
10 * + Initialization and de-initialization functions
11 * + Peripheral Control functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### RCC specific features #####
16 ==============================================================================
17 [..]
18 After reset the device is running from Internal High Speed oscillator
19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
20 and I-Cache are disabled, and all peripherals are off except internal
21 SRAM, Flash and JTAG.
22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
23 all peripherals mapped on these busses are running at HSI speed.
24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
25 (+) All GPIOs are in input floating state, except the JTAG pins which
26 are assigned to be used for debug purpose.
27
28 [..]
29 Once the device started from reset, the user application has to:
30 (+) Configure the clock source to be used to drive the System clock
31 (if the application needs higher frequency/performance)
32 (+) Configure the System clock frequency and Flash settings
33 (+) Configure the AHB and APB busses prescalers
34 (+) Enable the clock for the peripheral(s) to be used
35 (+) Configure the clock source(s) for peripherals which clocks are not
36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
37
38 ##### RCC Limitations #####
39 ==============================================================================
40 [..]
41 A delay between an RCC peripheral clock enable and the effective peripheral
42 enabling should be taken into account in order to manage the peripheral read/write
43 from/to registers.
44 (+) This delay depends on the peripheral mapping.
45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
46 after the clock enable bit is set on the hardware register
47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
48 after the clock enable bit is set on the hardware register
49
50 [..]
51 Implemented Workaround:
52 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
54
55 @endverbatim
56 ******************************************************************************
57 * @attention
58 *
59 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
60 *
61 * Redistribution and use in source and binary forms, with or without modification,
62 * are permitted provided that the following conditions are met:
63 * 1. Redistributions of source code must retain the above copyright notice,
64 * this list of conditions and the following disclaimer.
65 * 2. Redistributions in binary form must reproduce the above copyright notice,
66 * this list of conditions and the following disclaimer in the documentation
67 * and/or other materials provided with the distribution.
68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
69 * may be used to endorse or promote products derived from this software
70 * without specific prior written permission.
71 *
72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 *
83 ******************************************************************************
84 */
85
86 /* Includes ------------------------------------------------------------------*/
87 #include "stm32f7xx_hal.h"
88
89 /** @addtogroup STM32F7xx_HAL_Driver
90 * @{
91 */
92
93 /** @defgroup RCC RCC
94 * @brief RCC HAL module driver
95 * @{
96 */
97
98 #ifdef HAL_RCC_MODULE_ENABLED
99
100 /* Private typedef -----------------------------------------------------------*/
101 /* Private define ------------------------------------------------------------*/
102 /* Private macro -------------------------------------------------------------*/
103 /** @defgroup RCC_Private_Macros RCC Private Macros
104 * @{
105 */
106
107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
108 #define MCO1_GPIO_PORT GPIOA
109 #define MCO1_PIN GPIO_PIN_8
110
111 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
112 #define MCO2_GPIO_PORT GPIOC
113 #define MCO2_PIN GPIO_PIN_9
114
115 /**
116 * @}
117 */
118 /* Private variables ---------------------------------------------------------*/
119 /** @defgroup RCC_Private_Variables RCC Private Variables
120 * @{
121 */
122
123 /**
124 * @}
125 */
126
127 /* Private function prototypes -----------------------------------------------*/
128 /* Exported functions ---------------------------------------------------------*/
129
130 /** @defgroup RCC_Exported_Functions RCC Exported Functions
131 * @{
132 */
133
134 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
135 * @brief Initialization and Configuration functions
136 *
137 @verbatim
138 ===============================================================================
139 ##### Initialization and de-initialization functions #####
140 ===============================================================================
141 [..]
142 This section provides functions allowing to configure the internal/external oscillators
143 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
144 and APB2).
145
146 [..] Internal/external clock and PLL configuration
147 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
148 the PLL as System clock source.
149
150 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
151 clock source.
152
153 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
154 through the PLL as System clock source. Can be used also as RTC clock source.
155
156 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
157
158 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
159 (++) The first output is used to generate the high speed system clock (up to 216 MHz)
160 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
161 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
162
163 (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
164 and if a HSE clock failure occurs(HSE used directly or through PLL as System
165 clock source), the System clock is automatically switched to HSI and an interrupt
166 is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
167 (Non-Maskable Interrupt) exception vector.
168
169 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
170 clock (through a configurable prescaler) on PA8 pin.
171
172 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
173 clock (through a configurable prescaler) on PC9 pin.
174
175 [..] System, AHB and APB busses clocks configuration
176 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
177 HSE and PLL.
178 The AHB clock (HCLK) is derived from System clock through configurable
179 prescaler and used to clock the CPU, memory and peripherals mapped
180 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
181 from AHB clock through configurable prescalers and used to clock
182 the peripherals mapped on these busses. You can use
183 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
184
185 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
186 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
187 from an external clock mapped on the I2S_CKIN pin.
188 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
189 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
190 from an external clock mapped on the I2S_CKIN pin.
191 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
192 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
193 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
194 macros to configure this clock.
195 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
196 to work correctly, while the SDIO require a frequency equal or lower than
197 to 48. This clock is derived of the main PLL through PLLQ divider.
198 (+@) IWDG clock which is always the LSI clock.
199 @endverbatim
200 * @{
201 */
202
203 /**
204 * @brief Resets the RCC clock configuration to the default reset state.
205 * @note The default reset state of the clock configuration is given below:
206 * - HSI ON and used as system clock source
207 * - HSE, PLL and PLLI2S OFF
208 * - AHB, APB1 and APB2 prescaler set to 1.
209 * - CSS, MCO1 and MCO2 OFF
210 * - All interrupts disabled
211 * @note This function doesn't modify the configuration of the
212 * - Peripheral clocks
213 * - LSI, LSE and RTC clocks
214 * @retval None
215 */
216 void HAL_RCC_DeInit(void)
217 {
218 /* Set HSION bit */
219 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
220
221 /* Reset CFGR register */
222 CLEAR_REG(RCC->CFGR);
223
224 /* Reset HSEON, CSSON, PLLON, PLLI2S */
225 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
226
227 /* Reset PLLCFGR register */
228 CLEAR_REG(RCC->PLLCFGR);
229 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U));
230
231 /* Reset PLLI2SCFGR register */
232 CLEAR_REG(RCC->PLLI2SCFGR);
233 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
234
235 /* Reset HSEBYP bit */
236 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
237
238 /* Disable all interrupts */
239 CLEAR_REG(RCC->CIR);
240
241 /* Update the SystemCoreClock global variable */
242 SystemCoreClock = HSI_VALUE;
243 }
244
245 /**
246 * @brief Initializes the RCC Oscillators according to the specified parameters in the
247 * RCC_OscInitTypeDef.
248 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
249 * contains the configuration information for the RCC Oscillators.
250 * @note The PLL is not disabled when used as system clock.
251 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
252 * supported by this function. User should request a transition to LSE Off
253 * first and then LSE On or LSE Bypass.
254 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
255 * supported by this function. User should request a transition to HSE Off
256 * first and then HSE On or HSE Bypass.
257 * @retval HAL status
258 */
259 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
260 {
261 uint32_t tickstart = 0;
262
263 /* Check the parameters */
264 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
265
266 /*------------------------------- HSE Configuration ------------------------*/
267 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
268 {
269 /* Check the parameters */
270 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
271 /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
272 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
273 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
274 {
275 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
276 {
277 return HAL_ERROR;
278 }
279 }
280 else
281 {
282 /* Set the new HSE configuration ---------------------------------------*/
283 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
284
285 /* Check the HSE State */
286 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
287 {
288 /* Get Start Tick*/
289 tickstart = HAL_GetTick();
290
291 /* Wait till HSE is ready */
292 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
293 {
294 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
295 {
296 return HAL_TIMEOUT;
297 }
298 }
299 }
300 else
301 {
302 /* Get Start Tick*/
303 tickstart = HAL_GetTick();
304
305 /* Wait till HSE is bypassed or disabled */
306 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
307 {
308 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
309 {
310 return HAL_TIMEOUT;
311 }
312 }
313 }
314 }
315 }
316 /*----------------------------- HSI Configuration --------------------------*/
317 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
318 {
319 /* Check the parameters */
320 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
321 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
322
323 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
324 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
325 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
326 {
327 /* When HSI is used as system clock it will not disabled */
328 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
329 {
330 return HAL_ERROR;
331 }
332 /* Otherwise, just the calibration is allowed */
333 else
334 {
335 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
336 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
337 }
338 }
339 else
340 {
341 /* Check the HSI State */
342 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
343 {
344 /* Enable the Internal High Speed oscillator (HSI). */
345 __HAL_RCC_HSI_ENABLE();
346
347 /* Get Start Tick*/
348 tickstart = HAL_GetTick();
349
350 /* Wait till HSI is ready */
351 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
352 {
353 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
354 {
355 return HAL_TIMEOUT;
356 }
357 }
358
359 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
360 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
361 }
362 else
363 {
364 /* Disable the Internal High Speed oscillator (HSI). */
365 __HAL_RCC_HSI_DISABLE();
366
367 /* Get Start Tick*/
368 tickstart = HAL_GetTick();
369
370 /* Wait till HSI is ready */
371 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
372 {
373 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
374 {
375 return HAL_TIMEOUT;
376 }
377 }
378 }
379 }
380 }
381 /*------------------------------ LSI Configuration -------------------------*/
382 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
383 {
384 /* Check the parameters */
385 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
386
387 /* Check the LSI State */
388 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
389 {
390 /* Enable the Internal Low Speed oscillator (LSI). */
391 __HAL_RCC_LSI_ENABLE();
392
393 /* Get Start Tick*/
394 tickstart = HAL_GetTick();
395
396 /* Wait till LSI is ready */
397 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
398 {
399 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
400 {
401 return HAL_TIMEOUT;
402 }
403 }
404 }
405 else
406 {
407 /* Disable the Internal Low Speed oscillator (LSI). */
408 __HAL_RCC_LSI_DISABLE();
409
410 /* Get Start Tick*/
411 tickstart = HAL_GetTick();
412
413 /* Wait till LSI is ready */
414 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
415 {
416 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
417 {
418 return HAL_TIMEOUT;
419 }
420 }
421 }
422 }
423 /*------------------------------ LSE Configuration -------------------------*/
424 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
425 {
426 /* Check the parameters */
427 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
428
429 /* Enable Power Clock*/
430 __HAL_RCC_PWR_CLK_ENABLE();
431
432 /* Enable write access to Backup domain */
433 PWR->CR1 |= PWR_CR1_DBP;
434
435 /* Wait for Backup domain Write protection disable */
436 tickstart = HAL_GetTick();
437
438 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
439 {
440 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
441 {
442 return HAL_TIMEOUT;
443 }
444 }
445
446 /* Set the new LSE configuration -----------------------------------------*/
447 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
448 /* Check the LSE State */
449 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
450 {
451 /* Get Start Tick*/
452 tickstart = HAL_GetTick();
453
454 /* Wait till LSE is ready */
455 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
456 {
457 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
458 {
459 return HAL_TIMEOUT;
460 }
461 }
462 }
463 else
464 {
465 /* Get Start Tick*/
466 tickstart = HAL_GetTick();
467
468 /* Wait till LSE is ready */
469 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
470 {
471 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
472 {
473 return HAL_TIMEOUT;
474 }
475 }
476 }
477 }
478 /*-------------------------------- PLL Configuration -----------------------*/
479 /* Check the parameters */
480 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
481 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
482 {
483 /* Check if the PLL is used as system clock or not */
484 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
485 {
486 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
487 {
488 /* Check the parameters */
489 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
490 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
491 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
492 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
493 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
494
495 /* Disable the main PLL. */
496 __HAL_RCC_PLL_DISABLE();
497
498 /* Get Start Tick*/
499 tickstart = HAL_GetTick();
500
501 /* Wait till PLL is ready */
502 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
503 {
504 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
505 {
506 return HAL_TIMEOUT;
507 }
508 }
509
510 /* Configure the main PLL clock source, multiplication and division factors. */
511 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
512 RCC_OscInitStruct->PLL.PLLM | \
513 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
514 (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
515 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
516 /* Enable the main PLL. */
517 __HAL_RCC_PLL_ENABLE();
518
519 /* Get Start Tick*/
520 tickstart = HAL_GetTick();
521
522 /* Wait till PLL is ready */
523 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
524 {
525 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
526 {
527 return HAL_TIMEOUT;
528 }
529 }
530 }
531 else
532 {
533 /* Disable the main PLL. */
534 __HAL_RCC_PLL_DISABLE();
535
536 /* Get Start Tick*/
537 tickstart = HAL_GetTick();
538
539 /* Wait till PLL is ready */
540 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
541 {
542 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
543 {
544 return HAL_TIMEOUT;
545 }
546 }
547 }
548 }
549 else
550 {
551 return HAL_ERROR;
552 }
553 }
554 return HAL_OK;
555 }
556
557 /**
558 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
559 * parameters in the RCC_ClkInitStruct.
560 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
561 * contains the configuration information for the RCC peripheral.
562 * @param FLatency: FLASH Latency, this parameter depend on device selected
563 *
564 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
565 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
566 *
567 * @note The HSI is used (enabled by hardware) as system clock source after
568 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
569 * of failure of the HSE used directly or indirectly as system clock
570 * (if the Clock Security System CSS is enabled).
571 *
572 * @note A switch from one clock source to another occurs only if the target
573 * clock source is ready (clock stable after startup delay or PLL locked).
574 * If a clock source which is not yet ready is selected, the switch will
575 * occur when the clock source will be ready.
576 * You can use HAL_RCC_GetClockConfig() function to know which clock is
577 * currently used as system clock source.
578 * @note Depending on the device voltage range, the software has to set correctly
579 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
580 * (for more details refer to section above "Initialization/de-initialization functions")
581 * @retval None
582 */
583 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
584 {
585 uint32_t tickstart = 0;
586
587 /* Check the parameters */
588 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
589 assert_param(IS_FLASH_LATENCY(FLatency));
590
591 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
592 must be correctly programmed according to the frequency of the CPU clock
593 (HCLK) and the supply voltage of the device. */
594
595 /* Increasing the CPU frequency */
596 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
597 {
598 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
599 __HAL_FLASH_SET_LATENCY(FLatency);
600
601 /* Check that the new number of wait states is taken into account to access the Flash
602 memory by reading the FLASH_ACR register */
603 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
604 {
605 return HAL_ERROR;
606 }
607 }
608
609 /*-------------------------- HCLK Configuration --------------------------*/
610 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
611 {
612 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
613 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
614 }
615
616 /*------------------------- SYSCLK Configuration ---------------------------*/
617 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
618 {
619 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
620
621 /* HSE is selected as System Clock Source */
622 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
623 {
624 /* Check the HSE ready flag */
625 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
626 {
627 return HAL_ERROR;
628 }
629 }
630 /* PLL is selected as System Clock Source */
631 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
632 {
633 /* Check the PLL ready flag */
634 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
635 {
636 return HAL_ERROR;
637 }
638 }
639 /* HSI is selected as System Clock Source */
640 else
641 {
642 /* Check the HSI ready flag */
643 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
644 {
645 return HAL_ERROR;
646 }
647 }
648
649 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
650 /* Get Start Tick*/
651 tickstart = HAL_GetTick();
652
653 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
654 {
655 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
656 {
657 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
658 {
659 return HAL_TIMEOUT;
660 }
661 }
662 }
663 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
664 {
665 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
666 {
667 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
668 {
669 return HAL_TIMEOUT;
670 }
671 }
672 }
673 else
674 {
675 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
676 {
677 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
678 {
679 return HAL_TIMEOUT;
680 }
681 }
682 }
683 }
684
685 /* Decreasing the number of wait states because of lower CPU frequency */
686 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
687 {
688 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
689 __HAL_FLASH_SET_LATENCY(FLatency);
690
691 /* Check that the new number of wait states is taken into account to access the Flash
692 memory by reading the FLASH_ACR register */
693 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
694 {
695 return HAL_ERROR;
696 }
697 }
698
699 /*-------------------------- PCLK1 Configuration ---------------------------*/
700 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
701 {
702 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
703 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
704 }
705
706 /*-------------------------- PCLK2 Configuration ---------------------------*/
707 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
708 {
709 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
710 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
711 }
712
713 /* Update the SystemCoreClock global variable */
714 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
715
716 /* Configure the source of time base considering new system clocks settings*/
717 HAL_InitTick (TICK_INT_PRIORITY);
718
719 return HAL_OK;
720 }
721
722 /**
723 * @}
724 */
725
726 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
727 * @brief RCC clocks control functions
728 *
729 @verbatim
730 ===============================================================================
731 ##### Peripheral Control functions #####
732 ===============================================================================
733 [..]
734 This subsection provides a set of functions allowing to control the RCC Clocks
735 frequencies.
736
737 @endverbatim
738 * @{
739 */
740
741 /**
742 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
743 * @note PA8/PC9 should be configured in alternate function mode.
744 * @param RCC_MCOx: specifies the output direction for the clock source.
745 * This parameter can be one of the following values:
746 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
747 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
748 * @param RCC_MCOSource: specifies the clock source to output.
749 * This parameter can be one of the following values:
750 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
751 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
752 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
753 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
754 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
755 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
756 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
757 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
758 * @param RCC_MCODiv: specifies the MCOx prescaler.
759 * This parameter can be one of the following values:
760 * @arg RCC_MCODIV_1: no division applied to MCOx clock
761 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
762 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
763 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
764 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
765 * @retval None
766 */
767 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
768 {
769 GPIO_InitTypeDef GPIO_InitStruct;
770 /* Check the parameters */
771 assert_param(IS_RCC_MCO(RCC_MCOx));
772 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
773 /* RCC_MCO1 */
774 if(RCC_MCOx == RCC_MCO1)
775 {
776 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
777
778 /* MCO1 Clock Enable */
779 MCO1_CLK_ENABLE();
780
781 /* Configure the MCO1 pin in alternate function mode */
782 GPIO_InitStruct.Pin = MCO1_PIN;
783 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
784 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
785 GPIO_InitStruct.Pull = GPIO_NOPULL;
786 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
787 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
788
789 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
790 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
791 }
792 else
793 {
794 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
795
796 /* MCO2 Clock Enable */
797 MCO2_CLK_ENABLE();
798
799 /* Configure the MCO2 pin in alternate function mode */
800 GPIO_InitStruct.Pin = MCO2_PIN;
801 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
802 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
803 GPIO_InitStruct.Pull = GPIO_NOPULL;
804 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
805 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
806
807 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
808 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
809 }
810 }
811
812 /**
813 * @brief Enables the Clock Security System.
814 * @note If a failure is detected on the HSE oscillator clock, this oscillator
815 * is automatically disabled and an interrupt is generated to inform the
816 * software about the failure (Clock Security System Interrupt, CSSI),
817 * allowing the MCU to perform rescue operations. The CSSI is linked to
818 * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
819 * @retval None
820 */
821 void HAL_RCC_EnableCSS(void)
822 {
823 SET_BIT(RCC->CR, RCC_CR_CSSON);
824 }
825
826 /**
827 * @brief Disables the Clock Security System.
828 * @retval None
829 */
830 void HAL_RCC_DisableCSS(void)
831 {
832 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
833 }
834
835 /**
836 * @brief Returns the SYSCLK frequency
837 *
838 * @note The system frequency computed by this function is not the real
839 * frequency in the chip. It is calculated based on the predefined
840 * constant and the selected clock source:
841 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
842 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
843 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
844 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
845 * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
846 * 16 MHz) but the real value may vary depending on the variations
847 * in voltage and temperature.
848 * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
849 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
850 * frequency of the crystal used. Otherwise, this function may
851 * have wrong result.
852 *
853 * @note The result of this function could be not correct when using fractional
854 * value for HSE crystal.
855 *
856 * @note This function can be used by the user application to compute the
857 * baudrate for the communication peripherals or configure other parameters.
858 *
859 * @note Each time SYSCLK changes, this function must be called to update the
860 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
861 *
862 *
863 * @retval SYSCLK frequency
864 */
865 uint32_t HAL_RCC_GetSysClockFreq(void)
866 {
867 uint32_t pllm = 0, pllvco = 0, pllp = 0;
868 uint32_t sysclockfreq = 0;
869
870 /* Get SYSCLK source -------------------------------------------------------*/
871 switch (RCC->CFGR & RCC_CFGR_SWS)
872 {
873 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
874 {
875 sysclockfreq = HSI_VALUE;
876 break;
877 }
878 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
879 {
880 sysclockfreq = HSE_VALUE;
881 break;
882 }
883 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
884 {
885 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
886 SYSCLK = PLL_VCO / PLLP */
887 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
888 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
889 {
890 /* HSE used as PLL clock source */
891 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
892 }
893 else
894 {
895 /* HSI used as PLL clock source */
896 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
897 }
898 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
899
900 sysclockfreq = pllvco/pllp;
901 break;
902 }
903 default:
904 {
905 sysclockfreq = HSI_VALUE;
906 break;
907 }
908 }
909 return sysclockfreq;
910 }
911
912 /**
913 * @brief Returns the HCLK frequency
914 * @note Each time HCLK changes, this function must be called to update the
915 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
916 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
917 * @retval HCLK frequency
918 */
919 uint32_t HAL_RCC_GetHCLKFreq(void)
920 {
921 return SystemCoreClock;
922 }
923
924 /**
925 * @brief Returns the PCLK1 frequency
926 * @note Each time PCLK1 changes, this function must be called to update the
927 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
928 * @retval PCLK1 frequency
929 */
930 uint32_t HAL_RCC_GetPCLK1Freq(void)
931 {
932 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
933 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
934 }
935
936 /**
937 * @brief Returns the PCLK2 frequency
938 * @note Each time PCLK2 changes, this function must be called to update the
939 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
940 * @retval PCLK2 frequency
941 */
942 uint32_t HAL_RCC_GetPCLK2Freq(void)
943 {
944 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
945 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
946 }
947
948 /**
949 * @brief Configures the RCC_OscInitStruct according to the internal
950 * RCC configuration registers.
951 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
952 * will be configured.
953 * @retval None
954 */
955 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
956 {
957 /* Set all possible values for the Oscillator type parameter ---------------*/
958 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
959
960 /* Get the HSE configuration -----------------------------------------------*/
961 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
962 {
963 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
964 }
965 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
966 {
967 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
968 }
969 else
970 {
971 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
972 }
973
974 /* Get the HSI configuration -----------------------------------------------*/
975 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
976 {
977 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
978 }
979 else
980 {
981 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
982 }
983
984 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
985
986 /* Get the LSE configuration -----------------------------------------------*/
987 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
988 {
989 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
990 }
991 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
992 {
993 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
994 }
995 else
996 {
997 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
998 }
999
1000 /* Get the LSI configuration -----------------------------------------------*/
1001 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
1002 {
1003 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1004 }
1005 else
1006 {
1007 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1008 }
1009
1010 /* Get the PLL configuration -----------------------------------------------*/
1011 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
1012 {
1013 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1014 }
1015 else
1016 {
1017 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1018 }
1019 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
1020 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
1021 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
1022 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
1023 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
1024 }
1025
1026 /**
1027 * @brief Configures the RCC_ClkInitStruct according to the internal
1028 * RCC configuration registers.
1029 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1030 * will be configured.
1031 * @param pFLatency: Pointer on the Flash Latency.
1032 * @retval None
1033 */
1034 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1035 {
1036 /* Set all possible values for the Clock type parameter --------------------*/
1037 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1038
1039 /* Get the SYSCLK configuration --------------------------------------------*/
1040 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1041
1042 /* Get the HCLK configuration ----------------------------------------------*/
1043 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1044
1045 /* Get the APB1 configuration ----------------------------------------------*/
1046 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1047
1048 /* Get the APB2 configuration ----------------------------------------------*/
1049 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1050
1051 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1052 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1053 }
1054
1055 /**
1056 * @brief This function handles the RCC CSS interrupt request.
1057 * @note This API should be called under the NMI_Handler().
1058 * @retval None
1059 */
1060 void HAL_RCC_NMI_IRQHandler(void)
1061 {
1062 /* Check RCC CSSF flag */
1063 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
1064 {
1065 /* RCC Clock Security System interrupt user callback */
1066 HAL_RCC_CSSCallback();
1067
1068 /* Clear RCC CSS pending bit */
1069 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1070 }
1071 }
1072
1073 /**
1074 * @brief RCC Clock Security System interrupt callback
1075 * @retval None
1076 */
1077 __weak void HAL_RCC_CSSCallback(void)
1078 {
1079 /* NOTE : This function Should not be modified, when the callback is needed,
1080 the HAL_RCC_CSSCallback could be implemented in the user file
1081 */
1082 }
1083
1084 /**
1085 * @}
1086 */
1087
1088 /**
1089 * @}
1090 */
1091
1092 #endif /* HAL_RCC_MODULE_ENABLED */
1093 /**
1094 * @}
1095 */
1096
1097 /**
1098 * @}
1099 */
1100
1101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)