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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_spi.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_spi.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief SPI HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 The SPI HAL driver can be used as follows:
21
22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
23 SPI_HandleTypeDef hspi;
24
25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
26 (##) Enable the SPIx interface clock
27 (##) SPI pins configuration
28 (+++) Enable the clock for the SPI GPIOs
29 (+++) Configure these SPI pins as alternate function push-pull
30 (##) NVIC configuration if you need to use interrupt process
31 (+++) Configure the SPIx interrupt priority
32 (+++) Enable the NVIC SPI IRQ handle
33 (##) DMA Configuration if you need to use DMA process
34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
35 (+++) Enable the DMAx clock
36 (+++) Configure the DMA handle parameters
37 (+++) Configure the DMA Tx or Rx channel
38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
40
41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
43
44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
46 by calling the customized HAL_SPI_MspInit() API.
47 [..]
48 Circular mode restriction:
49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
50 (##) Master 2Lines RxOnly
51 (##) Master 1Line Rx
52 (#) The CRC feature is not managed when the DMA circular mode is enabled
53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
55
56 @endverbatim
57 ******************************************************************************
58 * @attention
59 *
60 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
61 *
62 * Redistribution and use in source and binary forms, with or without modification,
63 * are permitted provided that the following conditions are met:
64 * 1. Redistributions of source code must retain the above copyright notice,
65 * this list of conditions and the following disclaimer.
66 * 2. Redistributions in binary form must reproduce the above copyright notice,
67 * this list of conditions and the following disclaimer in the documentation
68 * and/or other materials provided with the distribution.
69 * 3. Neither the name of STMicroelectronics nor the names of its contributors
70 * may be used to endorse or promote products derived from this software
71 * without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
76 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
79 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
80 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
81 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
82 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 ******************************************************************************
85 */
86
87 /* Includes ------------------------------------------------------------------*/
88 #include "stm32f7xx_hal.h"
89
90 /** @addtogroup STM32F7xx_HAL_Driver
91 * @{
92 */
93
94 /** @defgroup SPI SPI
95 * @brief SPI HAL module driver
96 * @{
97 */
98 #ifdef HAL_SPI_MODULE_ENABLED
99
100 /* Private typedef -----------------------------------------------------------*/
101 /* Private defines -----------------------------------------------------------*/
102 /** @defgroup SPI_Private_Constants SPI Private Constants
103 * @{
104 */
105 #define SPI_DEFAULT_TIMEOUT 50
106 /**
107 * @}
108 */
109
110 /* Private macros ------------------------------------------------------------*/
111 /* Private variables ---------------------------------------------------------*/
112 /* Private function prototypes -----------------------------------------------*/
113 /** @defgroup SPI_Private_Functions SPI Private Functions
114 * @{
115 */
116 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
117 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
118 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
119 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
120 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
121 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
122 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
123 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
124 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
125 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
126 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
127 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
128 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
129 #if (USE_SPI_CRC != 0U)
130 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
131 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
132 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
133 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
134 #endif
135 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
136 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
137 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
138 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
139 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
140 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
141 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
142 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
143 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
144 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
145 /**
146 * @}
147 */
148
149 /* Exported functions ---------------------------------------------------------*/
150
151 /** @defgroup SPI_Exported_Functions SPI Exported Functions
152 * @{
153 */
154
155 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
156 * @brief Initialization and Configuration functions
157 *
158 @verbatim
159 ===============================================================================
160 ##### Initialization and de-initialization functions #####
161 ===============================================================================
162 [..] This subsection provides a set of functions allowing to initialize and
163 de-initialize the SPIx peripheral:
164
165 (+) User must implement HAL_SPI_MspInit() function in which he configures
166 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
167
168 (+) Call the function HAL_SPI_Init() to configure the selected device with
169 the selected configuration:
170 (++) Mode
171 (++) Direction
172 (++) Data Size
173 (++) Clock Polarity and Phase
174 (++) NSS Management
175 (++) BaudRate Prescaler
176 (++) FirstBit
177 (++) TIMode
178 (++) CRC Calculation
179 (++) CRC Polynomial if CRC enabled
180 (++) CRC Length, used only with Data8 and Data16
181 (++) FIFO reception threshold
182
183 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
184 of the selected SPIx peripheral.
185
186 @endverbatim
187 * @{
188 */
189
190 /**
191 * @brief Initialize the SPI according to the specified parameters
192 * in the SPI_InitTypeDef and initialize the associated handle.
193 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
194 * the configuration information for SPI module.
195 * @retval HAL status
196 */
197 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
198 {
199 uint32_t frxth;
200
201 /* Check the SPI handle allocation */
202 if(hspi == NULL)
203 {
204 return HAL_ERROR;
205 }
206
207 /* Check the parameters */
208 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
209 assert_param(IS_SPI_MODE(hspi->Init.Mode));
210 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
211 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
212 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
213 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
214 assert_param(IS_SPI_NSS(hspi->Init.NSS));
215 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
216 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
217 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
218 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
219 #if (USE_SPI_CRC != 0U)
220 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
221 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
222 {
223 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
224 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
225 }
226 /* Align the CRC Length on the data size */
227 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
228 {
229 /* CRC Length aligned on the data size : value set by default */
230 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
231 {
232 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
233 }
234 else
235 {
236 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
237 }
238 }
239 #endif
240
241 if(hspi->State == HAL_SPI_STATE_RESET)
242 {
243 /* Allocate lock resource and initialize it */
244 hspi->Lock = HAL_UNLOCKED;
245
246 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
247 HAL_SPI_MspInit(hspi);
248 }
249
250 hspi->State = HAL_SPI_STATE_BUSY;
251
252 /* Disable the selected SPI peripheral */
253 __HAL_SPI_DISABLE(hspi);
254
255 /* Align by default the rs fifo threshold on the data size */
256 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
257 {
258 frxth = SPI_RXFIFO_THRESHOLD_HF;
259 }
260 else
261 {
262 frxth = SPI_RXFIFO_THRESHOLD_QF;
263 }
264
265 /* CRC calculation is valid only for 16Bit and 8 Bit */
266 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
267 {
268 /* CRC must be disabled */
269 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
270 }
271
272 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
273 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
274 Communication speed, First bit, CRC calculation state, CRC Length */
275 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
276 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
277 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
278
279 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
280 {
281 hspi->Instance->CR1|= SPI_CR1_CRCL;
282 }
283
284 /* Configure : NSS management */
285 /* Configure : Rx Fifo Threshold */
286 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
287 hspi->Init.DataSize ) | frxth;
288
289 #if (USE_SPI_CRC != 0U)
290 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
291 /* Configure : CRC Polynomial */
292 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
293 #endif
294
295 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
296 hspi->State= HAL_SPI_STATE_READY;
297
298 return HAL_OK;
299 }
300
301 /**
302 * @brief DeInitialize the SPI peripheral.
303 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
304 * the configuration information for SPI module.
305 * @retval HAL status
306 */
307 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
308 {
309 /* Check the SPI handle allocation */
310 if(hspi == NULL)
311 {
312 return HAL_ERROR;
313 }
314
315 /* Check the parameters */
316 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
317
318 hspi->State = HAL_SPI_STATE_BUSY;
319
320 /* Disable the SPI Peripheral Clock */
321 __HAL_SPI_DISABLE(hspi);
322
323 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
324 HAL_SPI_MspDeInit(hspi);
325
326 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
327 hspi->State = HAL_SPI_STATE_RESET;
328
329 __HAL_UNLOCK(hspi);
330
331 return HAL_OK;
332 }
333
334 /**
335 * @brief SPI MSP Init
336 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
337 * the configuration information for SPI module.
338 * @retval None
339 */
340 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
341 {
342 /* Prevent unused argument(s) compilation warning */
343 UNUSED(hspi);
344
345 /* NOTE : This function should not be modified, when the callback is needed,
346 the HAL_SPI_MspInit should be implemented in the user file
347 */
348 }
349
350 /**
351 * @brief SPI MSP DeInit
352 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
353 * the configuration information for SPI module.
354 * @retval None
355 */
356 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
357 {
358 /* Prevent unused argument(s) compilation warning */
359 UNUSED(hspi);
360
361 /* NOTE : This function should not be modified, when the callback is needed,
362 the HAL_SPI_MspDeInit should be implemented in the user file
363 */
364 }
365
366 /**
367 * @}
368 */
369
370 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
371 * @brief Data transfers functions
372 *
373 @verbatim
374 ==============================================================================
375 ##### IO operation functions #####
376 ===============================================================================
377 [..]
378 This subsection provides a set of functions allowing to manage the SPI
379 data transfers.
380
381 [..] The SPI supports master and slave mode :
382
383 (#) There are two modes of transfer:
384 (++) Blocking mode: The communication is performed in polling mode.
385 The HAL status of all data processing is returned by the same function
386 after finishing transfer.
387 (++) No-Blocking mode: The communication is performed using Interrupts
388 or DMA, These APIs return the HAL status.
389 The end of the data processing will be indicated through the
390 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
391 using DMA mode.
392 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
393 will be executed respectively at the end of the transmit or Receive process
394 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
395
396 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
397 exist for 1Line (simplex) and 2Lines (full duplex) modes.
398
399 @endverbatim
400 * @{
401 */
402
403 /**
404 * @brief Transmit an amount of data in blocking mode.
405 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
406 * the configuration information for SPI module.
407 * @param pData: pointer to data buffer
408 * @param Size: amount of data to be sent
409 * @param Timeout: Timeout duration
410 * @retval HAL status
411 */
412 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
413 {
414 uint32_t tickstart = HAL_GetTick();
415 HAL_StatusTypeDef errorcode = HAL_OK;
416
417 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
418
419 /* Process Locked */
420 __HAL_LOCK(hspi);
421
422 if(hspi->State != HAL_SPI_STATE_READY)
423 {
424 errorcode = HAL_BUSY;
425 goto error;
426 }
427
428 if((pData == NULL ) || (Size == 0))
429 {
430 errorcode = HAL_ERROR;
431 goto error;
432 }
433
434 /* Set the transaction information */
435 hspi->State = HAL_SPI_STATE_BUSY_TX;
436 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
437 hspi->pTxBuffPtr = pData;
438 hspi->TxXferSize = Size;
439 hspi->TxXferCount = Size;
440 hspi->pRxBuffPtr = (uint8_t *)NULL;
441 hspi->RxXferSize = 0;
442 hspi->RxXferCount = 0;
443
444 /* Configure communication direction : 1Line */
445 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
446 {
447 SPI_1LINE_TX(hspi);
448 }
449
450 #if (USE_SPI_CRC != 0U)
451 /* Reset CRC Calculation */
452 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
453 {
454 SPI_RESET_CRC(hspi);
455 }
456 #endif
457
458 /* Check if the SPI is already enabled */
459 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
460 {
461 /* Enable SPI peripheral */
462 __HAL_SPI_ENABLE(hspi);
463 }
464
465 /* Transmit data in 16 Bit mode */
466 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
467 {
468 /* Transmit data in 16 Bit mode */
469 while (hspi->TxXferCount > 0)
470 {
471 /* Wait until TXE flag is set to send data */
472 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
473 {
474 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
475 hspi->pTxBuffPtr += sizeof(uint16_t);
476 hspi->TxXferCount--;
477 }
478 else
479 {
480 /* Timeout management */
481 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
482 {
483 errorcode = HAL_TIMEOUT;
484 goto error;
485 }
486 }
487 }
488 }
489 /* Transmit data in 8 Bit mode */
490 else
491 {
492 while (hspi->TxXferCount > 0)
493 {
494 /* Wait until TXE flag is set to send data */
495 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
496 {
497 if(hspi->TxXferCount > 1)
498 {
499 /* write on the data register in packing mode */
500 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
501 hspi->pTxBuffPtr += sizeof(uint16_t);
502 hspi->TxXferCount -= 2;
503 }
504 else
505 {
506 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
507 hspi->TxXferCount--;
508 }
509 }
510 else
511 {
512 /* Timeout management */
513 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
514 {
515 errorcode = HAL_TIMEOUT;
516 goto error;
517 }
518 }
519 }
520 }
521
522 #if (USE_SPI_CRC != 0U)
523 /* Enable CRC Transmission */
524 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
525 {
526 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
527 }
528 #endif
529
530 /* Check the end of the transaction */
531 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
532 {
533 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
534 }
535
536 /* Clear overrun flag in 2 Lines communication mode because received is not read */
537 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
538 {
539 __HAL_SPI_CLEAR_OVRFLAG(hspi);
540 }
541
542 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
543 {
544 errorcode = HAL_ERROR;
545 }
546
547 error:
548 hspi->State = HAL_SPI_STATE_READY;
549 /* Process Unlocked */
550 __HAL_UNLOCK(hspi);
551 return errorcode;
552 }
553
554 /**
555 * @brief Receive an amount of data in blocking mode.
556 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
557 * the configuration information for SPI module.
558 * @param pData: pointer to data buffer
559 * @param Size: amount of data to be received
560 * @param Timeout: Timeout duration
561 * @retval HAL status
562 */
563 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
564 {
565 #if (USE_SPI_CRC != 0U)
566 __IO uint16_t tmpreg;
567 #endif
568 uint32_t tickstart = HAL_GetTick();
569 HAL_StatusTypeDef errorcode = HAL_OK;
570
571 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
572 {
573 /* the receive process is not supported in 2Lines direction master mode */
574 /* in this case we call the TransmitReceive process */
575 /* Process Locked */
576 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
577 }
578
579 /* Process Locked */
580 __HAL_LOCK(hspi);
581
582 if(hspi->State != HAL_SPI_STATE_READY)
583 {
584 errorcode = HAL_BUSY;
585 goto error;
586 }
587
588 if((pData == NULL ) || (Size == 0))
589 {
590 errorcode = HAL_ERROR;
591 goto error;
592 }
593
594 hspi->State = HAL_SPI_STATE_BUSY_RX;
595 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
596 hspi->pRxBuffPtr = pData;
597 hspi->RxXferSize = Size;
598 hspi->RxXferCount = Size;
599 hspi->pTxBuffPtr = (uint8_t *)NULL;
600 hspi->TxXferSize = 0;
601 hspi->TxXferCount = 0;
602
603 #if (USE_SPI_CRC != 0U)
604 /* Reset CRC Calculation */
605 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
606 {
607 SPI_RESET_CRC(hspi);
608 /* this is done to handle the CRCNEXT before the latest data */
609 hspi->RxXferCount--;
610 }
611 #endif
612
613 /* Set the Rx Fido threshold */
614 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
615 {
616 /* set fiforxthreshold according the reception data length: 16bit */
617 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
618 }
619 else
620 {
621 /* set fiforxthreshold according the reception data length: 8bit */
622 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
623 }
624
625 /* Configure communication direction 1Line and enabled SPI if needed */
626 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
627 {
628 SPI_1LINE_RX(hspi);
629 }
630
631 /* Check if the SPI is already enabled */
632 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
633 {
634 /* Enable SPI peripheral */
635 __HAL_SPI_ENABLE(hspi);
636 }
637
638 /* Receive data in 8 Bit mode */
639 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
640 {
641 /* Transfer loop */
642 while(hspi->RxXferCount > 0)
643 {
644 /* Check the RXNE flag */
645 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
646 {
647 /* read the received data */
648 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
649 hspi->RxXferCount--;
650 }
651 else
652 {
653 /* Timeout management */
654 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
655 {
656 errorcode = HAL_TIMEOUT;
657 goto error;
658 }
659 }
660 }
661 }
662 else
663 {
664 /* Transfer loop */
665 while(hspi->RxXferCount > 0)
666 {
667 /* Check the RXNE flag */
668 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
669 {
670 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
671 hspi->pRxBuffPtr += sizeof(uint16_t);
672 hspi->RxXferCount--;
673 }
674 else
675 {
676 /* Timeout management */
677 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
678 {
679 errorcode = HAL_TIMEOUT;
680 goto error;
681 }
682 }
683 }
684 }
685
686 #if (USE_SPI_CRC != 0U)
687 /* Handle the CRC Transmission */
688 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
689 {
690 /* freeze the CRC before the latest data */
691 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
692
693 /* Read the latest data */
694 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
695 {
696 /* the latest data has not been received */
697 errorcode = HAL_TIMEOUT;
698 goto error;
699 }
700
701 /* Receive last data in 16 Bit mode */
702 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
703 {
704 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
705 }
706 /* Receive last data in 8 Bit mode */
707 else
708 {
709 *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
710 }
711
712 /* Wait until TXE flag */
713 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
714 {
715 /* Flag Error*/
716 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
717 errorcode = HAL_TIMEOUT;
718 goto error;
719 }
720
721 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
722 {
723 tmpreg = hspi->Instance->DR;
724 UNUSED(tmpreg); /* To avoid GCC warning */
725 }
726 else
727 {
728 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
729 UNUSED(tmpreg); /* To avoid GCC warning */
730
731 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
732 {
733 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
734 {
735 /* Error on the CRC reception */
736 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
737 errorcode = HAL_TIMEOUT;
738 goto error;
739 }
740 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
741 UNUSED(tmpreg); /* To avoid GCC warning */
742 }
743 }
744 }
745 #endif
746
747 /* Check the end of the transaction */
748 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
749 {
750 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
751 }
752
753 #if (USE_SPI_CRC != 0U)
754 /* Check if CRC error occurred */
755 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
756 {
757 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
758 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
759 }
760 #endif
761
762 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
763 {
764 errorcode = HAL_ERROR;
765 }
766
767 error :
768 hspi->State = HAL_SPI_STATE_READY;
769 __HAL_UNLOCK(hspi);
770 return errorcode;
771 }
772
773 /**
774 * @brief Transmit and Receive an amount of data in blocking mode.
775 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
776 * the configuration information for SPI module.
777 * @param pTxData: pointer to transmission data buffer
778 * @param pRxData: pointer to reception data buffer
779 * @param Size: amount of data to be sent and received
780 * @param Timeout: Timeout duration
781 * @retval HAL status
782 */
783 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
784 {
785 #if (USE_SPI_CRC != 0U)
786 __IO uint16_t tmpreg;
787 #endif
788 uint32_t tickstart = HAL_GetTick();
789 /* Variable used to alternate Rx and Tx during transfer */
790 uint32_t txallowed = 1U;
791
792 HAL_StatusTypeDef errorcode = HAL_OK;
793
794 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
795
796 /* Process Locked */
797 __HAL_LOCK(hspi);
798
799 if(hspi->State != HAL_SPI_STATE_READY)
800 {
801 errorcode = HAL_BUSY;
802 goto error;
803 }
804
805 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
806 {
807 errorcode = HAL_ERROR;
808 goto error;
809 }
810
811 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
812 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
813 hspi->pRxBuffPtr = pRxData;
814 hspi->RxXferCount = Size;
815 hspi->RxXferSize = Size;
816 hspi->pTxBuffPtr = pTxData;
817 hspi->TxXferCount = Size;
818 hspi->TxXferSize = Size;
819
820 #if (USE_SPI_CRC != 0U)
821 /* Reset CRC Calculation */
822 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
823 {
824 SPI_RESET_CRC(hspi);
825 }
826 #endif
827
828 /* Set the Rx Fifo threshold */
829 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
830 {
831 /* set fiforxthreshold according the reception data length: 16bit */
832 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
833 }
834 else
835 {
836 /* set fiforxthreshold according the reception data length: 8bit */
837 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
838 }
839
840 /* Check if the SPI is already enabled */
841 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
842 {
843 /* Enable SPI peripheral */
844 __HAL_SPI_ENABLE(hspi);
845 }
846
847 /* Transmit and Receive data in 16 Bit mode */
848 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
849 {
850 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
851 {
852 /* Check TXE flag */
853 if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))
854 {
855 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
856 hspi->pTxBuffPtr += sizeof(uint16_t);
857 hspi->TxXferCount--;
858 /* Next Data is a reception (Rx). Tx not allowed */
859 txallowed = 0U;
860
861 #if (USE_SPI_CRC != 0U)
862 /* Enable CRC Transmission */
863 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
864 {
865 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
866 if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
867 {
868 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
869 }
870 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
871 }
872 #endif
873 }
874 /* Check RXNE flag */
875 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
876 {
877 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
878 hspi->pRxBuffPtr += sizeof(uint16_t);
879 hspi->RxXferCount--;
880 /* Next Data is a reception (Rx). Tx not allowed */
881 txallowed = 1U;
882 }
883 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
884 {
885 errorcode = HAL_TIMEOUT;
886 goto error;
887 }
888 }
889 }
890 /* Transmit and Receive data in 8 Bit mode */
891 else
892 {
893 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
894 {
895 /* check TXE flag */
896 if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))
897 {
898 if(hspi->TxXferCount > 1)
899 {
900 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
901 hspi->pTxBuffPtr += sizeof(uint16_t);
902 hspi->TxXferCount -= 2;
903 }
904 else
905 {
906 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
907 hspi->TxXferCount--;
908 /* Next Data is a reception (Rx). Tx not allowed */
909 txallowed = 0U;
910 }
911
912 #if (USE_SPI_CRC != 0U)
913 /* Enable CRC Transmission */
914 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
915 {
916 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
917 if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
918 {
919 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
920 }
921 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
922 }
923 #endif
924 }
925
926 /* Wait until RXNE flag is reset */
927 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
928 {
929 if(hspi->RxXferCount > 1)
930 {
931 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
932 hspi->pRxBuffPtr += sizeof(uint16_t);
933 hspi->RxXferCount -= 2;
934 if(hspi->RxXferCount <= 1)
935 {
936 /* set fiforxthreshold before to switch on 8 bit data size */
937 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
938 }
939 }
940 else
941 {
942 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
943 hspi->RxXferCount--;
944 /* Next Data is a Transmission (Tx). Tx is allowed */
945 txallowed = 1U;
946 }
947 }
948 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
949 {
950 errorcode = HAL_TIMEOUT;
951 goto error;
952 }
953 }
954 }
955
956 #if (USE_SPI_CRC != 0U)
957 /* Read CRC from DR to close CRC calculation process */
958 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
959 {
960 /* Wait until TXE flag */
961 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
962 {
963 /* Error on the CRC reception */
964 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
965 errorcode = HAL_TIMEOUT;
966 goto error;
967 }
968
969 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
970 {
971 tmpreg = hspi->Instance->DR;
972 UNUSED(tmpreg); /* To avoid GCC warning */
973 }
974 else
975 {
976 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
977 UNUSED(tmpreg); /* To avoid GCC warning */
978
979 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
980 {
981 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
982 {
983 /* Error on the CRC reception */
984 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
985 errorcode = HAL_TIMEOUT;
986 goto error;
987 }
988 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
989 UNUSED(tmpreg); /* To avoid GCC warning */
990 }
991 }
992 }
993
994 /* Check if CRC error occurred */
995 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
996 {
997 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
998 /* Clear CRC Flag */
999 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1000
1001 errorcode = HAL_ERROR;
1002 }
1003 #endif
1004
1005 /* Check the end of the transaction */
1006 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
1007 {
1008 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1009 }
1010
1011 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1012 {
1013 errorcode = HAL_ERROR;
1014 }
1015
1016 error :
1017 hspi->State = HAL_SPI_STATE_READY;
1018 __HAL_UNLOCK(hspi);
1019 return errorcode;
1020 }
1021
1022 /**
1023 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1024 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1025 * the configuration information for SPI module.
1026 * @param pData: pointer to data buffer
1027 * @param Size: amount of data to be sent
1028 * @retval HAL status
1029 */
1030 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1031 {
1032 HAL_StatusTypeDef errorcode = HAL_OK;
1033 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1034
1035 /* Process Locked */
1036 __HAL_LOCK(hspi);
1037
1038 if((pData == NULL) || (Size == 0))
1039 {
1040 errorcode = HAL_ERROR;
1041 goto error;
1042 }
1043
1044 if(hspi->State != HAL_SPI_STATE_READY)
1045 {
1046 errorcode = HAL_BUSY;
1047 goto error;
1048 }
1049
1050 /* prepare the transfer */
1051 hspi->State = HAL_SPI_STATE_BUSY_TX;
1052 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1053 hspi->pTxBuffPtr = pData;
1054 hspi->TxXferSize = Size;
1055 hspi->TxXferCount = Size;
1056 hspi->pRxBuffPtr = (uint8_t *)NULL;
1057 hspi->RxXferSize = 0;
1058 hspi->RxXferCount = 0;
1059 hspi->RxISR = NULL;
1060
1061 /* Set the function for IT treatment */
1062 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1063 {
1064 hspi->TxISR = SPI_TxISR_16BIT;
1065 }
1066 else
1067 {
1068 hspi->TxISR = SPI_TxISR_8BIT;
1069 }
1070
1071 /* Configure communication direction : 1Line */
1072 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1073 {
1074 SPI_1LINE_TX(hspi);
1075 }
1076
1077 #if (USE_SPI_CRC != 0U)
1078 /* Reset CRC Calculation */
1079 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1080 {
1081 SPI_RESET_CRC(hspi);
1082 }
1083 #endif
1084
1085 /* Enable TXE and ERR interrupt */
1086 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
1087
1088 /* Check if the SPI is already enabled */
1089 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1090 {
1091 /* Enable SPI peripheral */
1092 __HAL_SPI_ENABLE(hspi);
1093 }
1094
1095 error :
1096 __HAL_UNLOCK(hspi);
1097 return errorcode;
1098 }
1099
1100 /**
1101 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1102 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1103 * the configuration information for SPI module.
1104 * @param pData: pointer to data buffer
1105 * @param Size: amount of data to be sent
1106 * @retval HAL status
1107 */
1108 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1109 {
1110 HAL_StatusTypeDef errorcode = HAL_OK;
1111
1112 /* Process Locked */
1113 __HAL_LOCK(hspi);
1114
1115 if(hspi->State != HAL_SPI_STATE_READY)
1116 {
1117 errorcode = HAL_BUSY;
1118 goto error;
1119 }
1120 if((pData == NULL) || (Size == 0))
1121 {
1122 errorcode = HAL_ERROR;
1123 goto error;
1124 }
1125
1126 /* Configure communication */
1127 hspi->State = HAL_SPI_STATE_BUSY_RX;
1128 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1129 hspi->pRxBuffPtr = pData;
1130 hspi->RxXferSize = Size;
1131 hspi->RxXferCount = Size;
1132 hspi->pTxBuffPtr = (uint8_t *)NULL;
1133 hspi->TxXferSize = 0;
1134 hspi->TxXferCount = 0;
1135
1136 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1137 {
1138 /* Process Unlocked */
1139 __HAL_UNLOCK(hspi);
1140 /* the receive process is not supported in 2Lines direction master mode */
1141 /* in this we call the TransmitReceive process */
1142 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
1143 }
1144
1145 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1146 {
1147 hspi->CRCSize = 1;
1148 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1149 {
1150 hspi->CRCSize = 2;
1151 }
1152 }
1153 else
1154 {
1155 hspi->CRCSize = 0;
1156 }
1157
1158 hspi->TxISR = NULL;
1159 /* check the data size to adapt Rx threshold and the set the function for IT treatment */
1160 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1161 {
1162 /* set fiforxthresold according the reception data length: 16 bit */
1163 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1164 hspi->RxISR = SPI_RxISR_16BIT;
1165 }
1166 else
1167 {
1168 /* set fiforxthresold according the reception data length: 8 bit */
1169 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1170 hspi->RxISR = SPI_RxISR_8BIT;
1171 }
1172
1173 /* Configure communication direction : 1Line */
1174 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1175 {
1176 SPI_1LINE_RX(hspi);
1177 }
1178
1179 #if (USE_SPI_CRC != 0U)
1180 /* Reset CRC Calculation */
1181 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1182 {
1183 SPI_RESET_CRC(hspi);
1184 }
1185 #endif
1186
1187 /* Enable TXE and ERR interrupt */
1188 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1189
1190 /* Check if the SPI is already enabled */
1191 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1192 {
1193 /* Enable SPI peripheral */
1194 __HAL_SPI_ENABLE(hspi);
1195 }
1196
1197 error :
1198 /* Process Unlocked */
1199 __HAL_UNLOCK(hspi);
1200 return errorcode;
1201 }
1202
1203 /**
1204 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1205 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1206 * the configuration information for SPI module.
1207 * @param pTxData: pointer to transmission data buffer
1208 * @param pRxData: pointer to reception data buffer
1209 * @param Size: amount of data to be sent and received
1210 * @retval HAL status
1211 */
1212 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1213 {
1214 HAL_StatusTypeDef errorcode = HAL_OK;
1215 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1216
1217 /* Process locked */
1218 __HAL_LOCK(hspi);
1219
1220 if(!((hspi->State == HAL_SPI_STATE_READY) || \
1221 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
1222 {
1223 errorcode = HAL_BUSY;
1224 goto error;
1225 }
1226
1227 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
1228 {
1229 errorcode = HAL_ERROR;
1230 goto error;
1231 }
1232
1233 hspi->CRCSize = 0;
1234 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1235 {
1236 hspi->CRCSize = 1;
1237 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1238 {
1239 hspi->CRCSize = 2;
1240 }
1241 }
1242
1243 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
1244 {
1245 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1246 }
1247
1248 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1249 hspi->pTxBuffPtr = pTxData;
1250 hspi->TxXferSize = Size;
1251 hspi->TxXferCount = Size;
1252 hspi->pRxBuffPtr = pRxData;
1253 hspi->RxXferSize = Size;
1254 hspi->RxXferCount = Size;
1255
1256 /* Set the function for IT treatment */
1257 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1258 {
1259 hspi->RxISR = SPI_2linesRxISR_16BIT;
1260 hspi->TxISR = SPI_2linesTxISR_16BIT;
1261 }
1262 else
1263 {
1264 hspi->RxISR = SPI_2linesRxISR_8BIT;
1265 hspi->TxISR = SPI_2linesTxISR_8BIT;
1266 }
1267
1268 #if (USE_SPI_CRC != 0U)
1269 /* Reset CRC Calculation */
1270 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1271 {
1272 SPI_RESET_CRC(hspi);
1273 }
1274 #endif
1275
1276 /* check if packing mode is enabled and if there is more than 2 data to receive */
1277 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
1278 {
1279 /* set fiforxthresold according the reception data length: 16 bit */
1280 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1281 }
1282 else
1283 {
1284 /* set fiforxthresold according the reception data length: 8 bit */
1285 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1286 }
1287
1288 /* Enable TXE, RXNE and ERR interrupt */
1289 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1290
1291 /* Check if the SPI is already enabled */
1292 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1293 {
1294 /* Enable SPI peripheral */
1295 __HAL_SPI_ENABLE(hspi);
1296 }
1297
1298 error :
1299 /* Process Unlocked */
1300 __HAL_UNLOCK(hspi);
1301 return errorcode;
1302 }
1303
1304 /**
1305 * @brief Transmit an amount of data in non-blocking mode with DMA.
1306 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1307 * the configuration information for SPI module.
1308 * @param pData: pointer to data buffer
1309 * @param Size: amount of data to be sent
1310 * @retval HAL status
1311 */
1312 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1313 {
1314 HAL_StatusTypeDef errorcode = HAL_OK;
1315 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1316
1317 /* Process Locked */
1318 __HAL_LOCK(hspi);
1319
1320 if(hspi->State != HAL_SPI_STATE_READY)
1321 {
1322 errorcode = HAL_BUSY;
1323 goto error;
1324 }
1325
1326 if((pData == NULL) || (Size == 0))
1327 {
1328 errorcode = HAL_ERROR;
1329 goto error;
1330 }
1331
1332 hspi->State = HAL_SPI_STATE_BUSY_TX;
1333 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1334 hspi->pTxBuffPtr = pData;
1335 hspi->TxXferSize = Size;
1336 hspi->TxXferCount = Size;
1337 hspi->pRxBuffPtr = (uint8_t *)NULL;
1338 hspi->RxXferSize = 0;
1339 hspi->RxXferCount = 0;
1340
1341 /* Configure communication direction : 1Line */
1342 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1343 {
1344 SPI_1LINE_TX(hspi);
1345 }
1346
1347 #if (USE_SPI_CRC != 0U)
1348 /* Reset CRC Calculation */
1349 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1350 {
1351 SPI_RESET_CRC(hspi);
1352 }
1353 #endif
1354
1355 /* Set the SPI TxDMA Half transfer complete callback */
1356 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1357
1358 /* Set the SPI TxDMA transfer complete callback */
1359 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1360
1361 /* Set the DMA error callback */
1362 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1363
1364 /* Set the DMA abort callback */
1365 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
1366
1367 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1368 /* packing mode is enabled only if the DMA setting is HALWORD */
1369 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1370 {
1371 /* Check the even/odd of the data size + crc if enabled */
1372 if((hspi->TxXferCount & 0x1) == 0)
1373 {
1374 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1375 hspi->TxXferCount = (hspi->TxXferCount >> 1);
1376 }
1377 else
1378 {
1379 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1380 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
1381 }
1382 }
1383
1384 /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */
1385 SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));
1386 SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
1387
1388 /* Enable the Tx DMA channel */
1389 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1390
1391 /* Check if the SPI is already enabled */
1392 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1393 {
1394 /* Enable SPI peripheral */
1395 __HAL_SPI_ENABLE(hspi);
1396 }
1397
1398 /* Enable Tx DMA Request */
1399 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1400
1401 error :
1402 /* Process Unlocked */
1403 __HAL_UNLOCK(hspi);
1404 return errorcode;
1405 }
1406
1407 /**
1408 * @brief Receive an amount of data in non-blocking mode with DMA.
1409 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1410 * the configuration information for SPI module.
1411 * @param pData: pointer to data buffer
1412 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1413 * @param Size: amount of data to be sent
1414 * @retval HAL status
1415 */
1416 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1417 {
1418 HAL_StatusTypeDef errorcode = HAL_OK;
1419
1420 /* Process Locked */
1421 __HAL_LOCK(hspi);
1422
1423 if(hspi->State != HAL_SPI_STATE_READY)
1424 {
1425 errorcode = HAL_BUSY;
1426 goto error;
1427 }
1428
1429 if((pData == NULL) || (Size == 0))
1430 {
1431 errorcode = HAL_ERROR;
1432 goto error;
1433 }
1434
1435 hspi->State = HAL_SPI_STATE_BUSY_RX;
1436 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1437 hspi->pRxBuffPtr = pData;
1438 hspi->RxXferSize = Size;
1439 hspi->RxXferCount = Size;
1440 hspi->pTxBuffPtr = (uint8_t *)NULL;
1441 hspi->TxXferSize = 0;
1442 hspi->TxXferCount = 0;
1443
1444 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1445 {
1446 /* Process Unlocked */
1447 __HAL_UNLOCK(hspi);
1448 /* the receive process is not supported in 2Lines direction master mode */
1449 /* in this case we call the TransmitReceive process */
1450 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
1451 }
1452
1453 /* Configure communication direction : 1Line */
1454 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1455 {
1456 SPI_1LINE_RX(hspi);
1457 }
1458
1459 #if (USE_SPI_CRC != 0U)
1460 /* Reset CRC Calculation */
1461 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1462 {
1463 SPI_RESET_CRC(hspi);
1464 }
1465 #endif
1466
1467 /* packing mode management is enabled by the DMA settings */
1468 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1469 {
1470 /* Restriction the DMA data received is not allowed in this mode */
1471 errorcode = HAL_ERROR;
1472 goto error;
1473 }
1474
1475 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1476 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1477 {
1478 /* set fiforxthreshold according the reception data length: 16bit */
1479 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1480 }
1481 else
1482 {
1483 /* set fiforxthreshold according the reception data length: 8bit */
1484 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1485 }
1486
1487 /* Set the SPI RxDMA Half transfer complete callback */
1488 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1489
1490 /* Set the SPI Rx DMA transfer complete callback */
1491 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1492
1493 /* Set the DMA error callback */
1494 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1495
1496 /* Set the DMA abort callback */
1497 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
1498
1499 /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */
1500 SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));
1501 SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
1502
1503 /* Enable Rx DMA Request */
1504 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1505
1506 /* Enable the Rx DMA channel */
1507 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
1508
1509 /* Check if the SPI is already enabled */
1510 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1511 {
1512 /* Enable SPI peripheral */
1513 __HAL_SPI_ENABLE(hspi);
1514 }
1515
1516 error:
1517 /* Process Unlocked */
1518 __HAL_UNLOCK(hspi);
1519 return errorcode;
1520 }
1521
1522 /**
1523 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
1524 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1525 * the configuration information for SPI module.
1526 * @param pTxData: pointer to transmission data buffer
1527 * @param pRxData: pointer to reception data buffer
1528 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
1529 * @param Size: amount of data to be sent
1530 * @retval HAL status
1531 */
1532 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1533 {
1534 HAL_StatusTypeDef errorcode = HAL_OK;
1535 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1536
1537 /* Process locked */
1538 __HAL_LOCK(hspi);
1539
1540 if(!((hspi->State == HAL_SPI_STATE_READY) ||
1541 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
1542 {
1543 errorcode = HAL_BUSY;
1544 goto error;
1545 }
1546
1547 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
1548 {
1549 errorcode = HAL_ERROR;
1550 goto error;
1551 }
1552
1553 /* check if the transmit Receive function is not called by a receive master */
1554 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
1555 {
1556 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1557 }
1558
1559 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1560 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1561 hspi->TxXferSize = Size;
1562 hspi->TxXferCount = Size;
1563 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1564 hspi->RxXferSize = Size;
1565 hspi->RxXferCount = Size;
1566
1567 #if (USE_SPI_CRC != 0U)
1568 /* Reset CRC Calculation + increase the rxsize */
1569 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1570 {
1571 SPI_RESET_CRC(hspi);
1572 }
1573 #endif
1574
1575 /* Reset the threshold bit */
1576 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
1577
1578 /* the packing mode management is enabled by the DMA settings according the spi data size */
1579 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1580 {
1581 /* set fiforxthreshold according the reception data length: 16bit */
1582 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1583 }
1584 else
1585 {
1586 /* set fiforxthresold according the reception data length: 8bit */
1587 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1588
1589 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
1590 {
1591 if((hspi->TxXferSize & 0x1) == 0x0)
1592 {
1593 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1594 hspi->TxXferCount = hspi->TxXferCount >> 1;
1595 }
1596 else
1597 {
1598 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1599 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
1600 }
1601 }
1602
1603 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
1604 {
1605 /* set fiforxthresold according the reception data length: 16bit */
1606 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1607
1608 if((hspi->RxXferCount & 0x1) == 0x0 )
1609 {
1610 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1611 hspi->RxXferCount = hspi->RxXferCount >> 1;
1612 }
1613 else
1614 {
1615 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1616 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
1617 }
1618 }
1619 }
1620
1621 /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
1622 reception request (RXNE) */
1623 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
1624 {
1625 /* Set the SPI Rx DMA Half transfer complete callback */
1626 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1627 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1628 }
1629 else
1630 {
1631 /* Set the SPI Rx DMA Half transfer complete callback */
1632 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1633 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
1634 }
1635
1636 /* Set the DMA error callback */
1637 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1638
1639 /* Set the DMA abort callback */
1640 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
1641
1642 /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */
1643 SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));
1644 SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
1645
1646 /* Enable Rx DMA Request */
1647 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1648
1649 /* Enable the Rx DMA channel */
1650 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
1651
1652 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
1653 is performed in DMA reception complete callback */
1654 hspi->hdmatx->XferHalfCpltCallback = NULL;
1655 hspi->hdmatx->XferCpltCallback = NULL;
1656
1657 /* Set the DMA error callback */
1658 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1659
1660 /* Set the DMA abort callback */
1661 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
1662
1663 /* Enable the Tx DMA channel */
1664 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1665
1666 /* Check if the SPI is already enabled */
1667 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1668 {
1669 /* Enable SPI peripheral */
1670 __HAL_SPI_ENABLE(hspi);
1671 }
1672
1673 /* Enable Tx DMA Request */
1674 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1675
1676 error :
1677 /* Process Unlocked */
1678 __HAL_UNLOCK(hspi);
1679 return errorcode;
1680 }
1681
1682 /**
1683 * @brief Pause the DMA Transfer.
1684 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1685 * the configuration information for the specified SPI module.
1686 * @retval HAL status
1687 */
1688 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
1689 {
1690 /* Process Locked */
1691 __HAL_LOCK(hspi);
1692
1693 /* Disable the SPI DMA Tx & Rx requests */
1694 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1695
1696 /* Process Unlocked */
1697 __HAL_UNLOCK(hspi);
1698
1699 return HAL_OK;
1700 }
1701
1702 /**
1703 * @brief Resumes the DMA Transfer.
1704 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1705 * the configuration information for the specified SPI module.
1706 * @retval HAL status
1707 */
1708 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
1709 {
1710 /* Process Locked */
1711 __HAL_LOCK(hspi);
1712
1713 /* Enable the SPI DMA Tx & Rx requests */
1714 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1715
1716 /* Process Unlocked */
1717 __HAL_UNLOCK(hspi);
1718
1719 return HAL_OK;
1720 }
1721
1722 /**
1723 * @brief Stops the DMA Transfer.
1724 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1725 * the configuration information for the specified SPI module.
1726 * @retval HAL status
1727 */
1728 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
1729 {
1730 /* The Lock is not implemented on this API to allow the user application
1731 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
1732 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
1733 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
1734 */
1735
1736 /* Abort the SPI DMA tx Stream */
1737 if(hspi->hdmatx != NULL)
1738 {
1739 HAL_DMA_Abort(hspi->hdmatx);
1740 }
1741 /* Abort the SPI DMA rx Stream */
1742 if(hspi->hdmarx != NULL)
1743 {
1744 HAL_DMA_Abort(hspi->hdmarx);
1745 }
1746
1747 /* Disable the SPI DMA Tx & Rx requests */
1748 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1749 hspi->State = HAL_SPI_STATE_READY;
1750 return HAL_OK;
1751 }
1752
1753 /**
1754 * @brief This function handles SPI interrupt request.
1755 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1756 * the configuration information for the specified SPI module.
1757 * @retval None
1758 */
1759 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
1760 {
1761 uint32_t itsource = hspi->Instance->CR2;
1762 uint32_t itflag = hspi->Instance->SR;
1763
1764 /* SPI in mode Receiver ----------------------------------------------------*/
1765 if(((itflag & SPI_FLAG_OVR) == RESET) &&
1766 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
1767 {
1768 hspi->RxISR(hspi);
1769 return;
1770 }
1771
1772 /* SPI in mode Transmitter ---------------------------------------------------*/
1773 if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
1774 {
1775 hspi->TxISR(hspi);
1776 return;
1777 }
1778
1779 /* SPI in Error Treatment ---------------------------------------------------*/
1780 if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
1781 {
1782 /* SPI Overrun error interrupt occurred -------------------------------------*/
1783 if((itflag & SPI_FLAG_OVR) != RESET)
1784 {
1785 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
1786 {
1787 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
1788 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1789 }
1790 else
1791 {
1792 return;
1793 }
1794 }
1795
1796 /* SPI Mode Fault error interrupt occurred -------------------------------------*/
1797 if((itflag & SPI_FLAG_MODF) != RESET)
1798 {
1799 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
1800 __HAL_SPI_CLEAR_MODFFLAG(hspi);
1801 }
1802
1803 /* SPI Frame error interrupt occurred ----------------------------------------*/
1804 if((itflag & SPI_FLAG_FRE) != RESET)
1805 {
1806 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
1807 __HAL_SPI_CLEAR_FREFLAG(hspi);
1808 }
1809
1810 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1811 {
1812 /* All SPI errors are treated as Blocking errors : transfer is aborted.
1813 Set the SPI state to ready so as to be able to restart the process,
1814 Disable Rx/Tx Interrupts, and disable DMA Rx/Tx requests, if ongoing */
1815
1816 /* Disable TXE, RXNE, MODF, OVR, FRE, and CRCERR (Master mode fault, Overrun error, TI frame format error, CRC protocol error) interrupts */
1817 CLEAR_BIT(hspi->Instance->CR1, (SPI_CR2_RXNEIE | SPI_CR2_TXEIE | SPI_CR2_ERRIE));
1818 CLEAR_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
1819
1820 /* Restore SPI State to Ready */
1821 hspi->State = HAL_SPI_STATE_READY;
1822
1823 /* Disable the SPI DMA requests if enabled */
1824 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
1825 {
1826 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
1827
1828 /* Abort the SPI DMA Rx channel */
1829 if(hspi->hdmarx != NULL)
1830 {
1831 /* Set the SPI DMA Abort callback :
1832 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
1833 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
1834
1835 /* Abort DMA RX */
1836 if(HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
1837 {
1838 /* Call Directly hspi->hdmarx->XferAbortCallback function in case of error */
1839 hspi->hdmarx->XferAbortCallback(hspi->hdmarx);
1840 }
1841 }
1842 /* Abort the SPI DMA Tx channel */
1843 if(hspi->hdmatx != NULL)
1844 {
1845 /* Set the SPI DMA Abort callback :
1846 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
1847 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
1848
1849 /* Abort DMA TX */
1850 if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
1851 {
1852 /* Call Directly hspi->hdmatx->XferAbortCallback function in case of error */
1853 hspi->hdmatx->XferAbortCallback(hspi->hdmatx);
1854 }
1855 }
1856 }
1857 else
1858 {
1859 /* Call user error callback */
1860 HAL_SPI_ErrorCallback(hspi);
1861 }
1862 }
1863 }
1864 }
1865
1866 /**
1867 * @brief Tx Transfer completed callback.
1868 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1869 * the configuration information for SPI module.
1870 * @retval None
1871 */
1872 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
1873 {
1874 /* Prevent unused argument(s) compilation warning */
1875 UNUSED(hspi);
1876
1877 /* NOTE : This function should not be modified, when the callback is needed,
1878 the HAL_SPI_TxCpltCallback should be implemented in the user file
1879 */
1880 }
1881
1882 /**
1883 * @brief Rx Transfer completed callback.
1884 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1885 * the configuration information for SPI module.
1886 * @retval None
1887 */
1888 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
1889 {
1890 /* Prevent unused argument(s) compilation warning */
1891 UNUSED(hspi);
1892
1893 /* NOTE : This function should not be modified, when the callback is needed,
1894 the HAL_SPI_RxCpltCallback should be implemented in the user file
1895 */
1896 }
1897
1898 /**
1899 * @brief Tx and Rx Transfer completed callback.
1900 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1901 * the configuration information for SPI module.
1902 * @retval None
1903 */
1904 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
1905 {
1906 /* Prevent unused argument(s) compilation warning */
1907 UNUSED(hspi);
1908
1909 /* NOTE : This function should not be modified, when the callback is needed,
1910 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
1911 */
1912 }
1913
1914 /**
1915 * @brief Tx Half Transfer completed callback.
1916 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1917 * the configuration information for SPI module.
1918 * @retval None
1919 */
1920 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1921 {
1922 /* Prevent unused argument(s) compilation warning */
1923 UNUSED(hspi);
1924
1925 /* NOTE : This function should not be modified, when the callback is needed,
1926 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
1927 */
1928 }
1929
1930 /**
1931 * @brief Rx Half Transfer completed callback.
1932 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1933 * the configuration information for SPI module.
1934 * @retval None
1935 */
1936 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1937 {
1938 /* Prevent unused argument(s) compilation warning */
1939 UNUSED(hspi);
1940
1941 /* NOTE : This function should not be modified, when the callback is needed,
1942 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
1943 */
1944 }
1945
1946 /**
1947 * @brief Tx and Rx Half Transfer callback.
1948 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1949 * the configuration information for SPI module.
1950 * @retval None
1951 */
1952 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1953 {
1954 /* Prevent unused argument(s) compilation warning */
1955 UNUSED(hspi);
1956
1957 /* NOTE : This function should not be modified, when the callback is needed,
1958 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
1959 */
1960 }
1961
1962 /**
1963 * @brief SPI error callback.
1964 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1965 * the configuration information for SPI module.
1966 * @retval None
1967 */
1968 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
1969 {
1970 /* Prevent unused argument(s) compilation warning */
1971 UNUSED(hspi);
1972
1973 /* NOTE : This function should not be modified, when the callback is needed,
1974 the HAL_SPI_ErrorCallback should be implemented in the user file
1975 */
1976 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
1977 and user can use HAL_SPI_GetError() API to check the latest error occurred
1978 */
1979 }
1980
1981 /**
1982 * @}
1983 */
1984
1985 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
1986 * @brief SPI control functions
1987 *
1988 @verbatim
1989 ===============================================================================
1990 ##### Peripheral State and Errors functions #####
1991 ===============================================================================
1992 [..]
1993 This subsection provides a set of functions allowing to control the SPI.
1994 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
1995 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
1996 @endverbatim
1997 * @{
1998 */
1999
2000 /**
2001 * @brief Return the SPI handle state.
2002 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2003 * the configuration information for SPI module.
2004 * @retval SPI state
2005 */
2006 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2007 {
2008 /* Return SPI handle state */
2009 return hspi->State;
2010 }
2011
2012 /**
2013 * @brief Return the SPI error code.
2014 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2015 * the configuration information for SPI module.
2016 * @retval SPI error code in bitmap format
2017 */
2018 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2019 {
2020 return hspi->ErrorCode;
2021 }
2022
2023 /**
2024 * @}
2025 */
2026
2027
2028 /**
2029 * @}
2030 */
2031
2032 /** @addtogroup SPI_Private_Functions
2033 * @brief Private functions
2034 * @{
2035 */
2036
2037 /**
2038 * @brief DMA SPI transmit process complete callback.
2039 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2040 * the configuration information for the specified DMA module.
2041 * @retval None
2042 */
2043 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2044 {
2045 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2046
2047 /* DMA Normal Mode */
2048 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
2049 {
2050 /* Disable Tx DMA Request */
2051 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2052
2053 /* Check the end of the transaction */
2054 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
2055 {
2056 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
2057 }
2058
2059 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2060 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
2061 {
2062 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2063 }
2064
2065 hspi->TxXferCount = 0;
2066 hspi->State = HAL_SPI_STATE_READY;
2067
2068 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2069 {
2070 HAL_SPI_ErrorCallback(hspi);
2071 return;
2072 }
2073 }
2074 HAL_SPI_TxCpltCallback(hspi);
2075 }
2076
2077 /**
2078 * @brief DMA SPI receive process complete callback.
2079 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2080 * the configuration information for the specified DMA module.
2081 * @retval None
2082 */
2083 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2084 {
2085 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2086
2087 /* DMA Normal mode */
2088 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
2089 {
2090
2091 #if (USE_SPI_CRC != 0U)
2092 __IO uint16_t tmpreg;
2093 /* CRC handling */
2094 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2095 {
2096 /* Wait until TXE flag */
2097 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
2098 {
2099 /* Error on the CRC reception */
2100 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2101 }
2102 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2103 {
2104 tmpreg = hspi->Instance->DR;
2105 UNUSED(tmpreg); /* To avoid GCC warning */
2106 }
2107 else
2108 {
2109 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
2110 UNUSED(tmpreg); /* To avoid GCC warning */
2111
2112 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
2113 {
2114 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
2115 {
2116 /* Error on the CRC reception */
2117 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2118 }
2119 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
2120 UNUSED(tmpreg); /* To avoid GCC warning */
2121 }
2122 }
2123 }
2124 #endif
2125
2126 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
2127 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2128
2129 /* Check the end of the transaction */
2130 if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
2131 {
2132 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
2133 }
2134
2135 hspi->RxXferCount = 0;
2136 hspi->State = HAL_SPI_STATE_READY;
2137
2138 #if (USE_SPI_CRC != 0U)
2139 /* Check if CRC error occurred */
2140 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2141 {
2142 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2143 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2144 }
2145 #endif
2146
2147 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2148 {
2149 HAL_SPI_ErrorCallback(hspi);
2150 return;
2151 }
2152 }
2153 HAL_SPI_RxCpltCallback(hspi);
2154 }
2155
2156 /**
2157 * @brief DMA SPI transmit receive process complete callback.
2158 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2159 * the configuration information for the specified DMA module.
2160 * @retval None
2161 */
2162 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2163 {
2164 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2165 #if (USE_SPI_CRC != 0U)
2166 __IO uint16_t tmpreg;
2167 /* CRC handling */
2168 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2169 {
2170 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
2171 {
2172 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
2173 {
2174 /* Error on the CRC reception */
2175 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2176 }
2177 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
2178 UNUSED(tmpreg); /* To avoid GCC warning */
2179 }
2180 else
2181 {
2182 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
2183 {
2184 /* Error on the CRC reception */
2185 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2186 }
2187 tmpreg = hspi->Instance->DR;
2188 UNUSED(tmpreg); /* To avoid GCC warning */
2189 }
2190 }
2191 #endif
2192
2193 /* Check the end of the transaction */
2194 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
2195 {
2196 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
2197 }
2198
2199 /* Disable Rx/Tx DMA Request */
2200 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2201
2202 hspi->TxXferCount = 0;
2203 hspi->RxXferCount = 0;
2204 hspi->State = HAL_SPI_STATE_READY;
2205
2206 #if (USE_SPI_CRC != 0U)
2207 /* Check if CRC error occurred */
2208 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2209 {
2210 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2211 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2212 }
2213 #endif
2214
2215 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2216 {
2217 HAL_SPI_ErrorCallback(hspi);
2218 return;
2219 }
2220 HAL_SPI_TxRxCpltCallback(hspi);
2221 }
2222
2223 /**
2224 * @brief DMA SPI half transmit process complete callback.
2225 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2226 * the configuration information for the specified DMA module.
2227 * @retval None
2228 */
2229 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2230 {
2231 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2232 HAL_SPI_TxHalfCpltCallback(hspi);
2233 }
2234
2235 /**
2236 * @brief DMA SPI half receive process complete callback.
2237 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2238 * the configuration information for the specified DMA module.
2239 * @retval None
2240 */
2241 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2242 {
2243 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2244 HAL_SPI_RxHalfCpltCallback(hspi);
2245 }
2246
2247 /**
2248 * @brief DMA SPI half transmit receive process complete callback.
2249 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2250 * the configuration information for the specified DMA module.
2251 * @retval None
2252 */
2253 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2254 {
2255 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2256 HAL_SPI_TxRxHalfCpltCallback(hspi);
2257 }
2258
2259 /**
2260 * @brief DMA SPI communication error callback.
2261 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2262 * the configuration information for the specified DMA module.
2263 * @retval None
2264 */
2265 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
2266 {
2267 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2268
2269 /* Stop the disable DMA transfer on SPI side */
2270 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2271
2272 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
2273 hspi->State = HAL_SPI_STATE_READY;
2274 HAL_SPI_ErrorCallback(hspi);
2275 }
2276
2277 /**
2278 * @brief DMA SPI communication abort callback
2279 * (To be called at end of DMA Abort procedure).
2280 * @param hdma: DMA handle.
2281 * @retval None
2282 */
2283 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
2284 {
2285 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2286 hspi->RxXferCount = 0U;
2287 hspi->TxXferCount = 0U;
2288
2289 HAL_SPI_ErrorCallback(hspi);
2290 }
2291
2292 /**
2293 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
2294 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2295 * the configuration information for SPI module.
2296 * @retval None
2297 */
2298 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2299 {
2300 /* Receive data in packing mode */
2301 if(hspi->RxXferCount > 1)
2302 {
2303 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
2304 hspi->pRxBuffPtr += sizeof(uint16_t);
2305 hspi->RxXferCount -= 2;
2306 if(hspi->RxXferCount == 1)
2307 {
2308 /* set fiforxthreshold according the reception data length: 8bit */
2309 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2310 }
2311 }
2312 /* Receive data in 8 Bit mode */
2313 else
2314 {
2315 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
2316 hspi->RxXferCount--;
2317 }
2318
2319 /* check end of the reception */
2320 if(hspi->RxXferCount == 0)
2321 {
2322 #if (USE_SPI_CRC != 0U)
2323 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2324 {
2325 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2326 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
2327 return;
2328 }
2329 #endif
2330
2331 /* Disable RXNE interrupt */
2332 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2333
2334 if(hspi->TxXferCount == 0)
2335 {
2336 SPI_CloseRxTx_ISR(hspi);
2337 }
2338 }
2339 }
2340
2341 #if (USE_SPI_CRC != 0U)
2342 /**
2343 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
2344 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2345 * the configuration information for SPI module.
2346 * @retval None
2347 */
2348 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
2349 {
2350 __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
2351 UNUSED(tmpreg); /* To avoid GCC warning */
2352
2353 hspi->CRCSize--;
2354
2355 /* check end of the reception */
2356 if(hspi->CRCSize == 0)
2357 {
2358 /* Disable RXNE interrupt */
2359 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2360
2361 if(hspi->TxXferCount == 0)
2362 {
2363 SPI_CloseRxTx_ISR(hspi);
2364 }
2365 }
2366 }
2367 #endif
2368
2369 /**
2370 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
2371 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2372 * the configuration information for SPI module.
2373 * @retval None
2374 */
2375 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2376 {
2377 /* Transmit data in packing Bit mode */
2378 if(hspi->TxXferCount >= 2)
2379 {
2380 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2381 hspi->pTxBuffPtr += sizeof(uint16_t);
2382 hspi->TxXferCount -= 2;
2383 }
2384 /* Transmit data in 8 Bit mode */
2385 else
2386 {
2387 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
2388 hspi->TxXferCount--;
2389 }
2390
2391 /* check the end of the transmission */
2392 if(hspi->TxXferCount == 0)
2393 {
2394 #if (USE_SPI_CRC != 0U)
2395 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2396 {
2397 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2398 }
2399 #endif
2400
2401 /* Disable TXE interrupt */
2402 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2403
2404 if(hspi->RxXferCount == 0)
2405 {
2406 SPI_CloseRxTx_ISR(hspi);
2407 }
2408 }
2409 }
2410
2411 /**
2412 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
2413 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2414 * the configuration information for SPI module.
2415 * @retval None
2416 */
2417 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2418 {
2419 /* Receive data in 16 Bit mode */
2420 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
2421 hspi->pRxBuffPtr += sizeof(uint16_t);
2422 hspi->RxXferCount--;
2423
2424 if(hspi->RxXferCount == 0)
2425 {
2426 #if (USE_SPI_CRC != 0U)
2427 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2428 {
2429 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
2430 return;
2431 }
2432 #endif
2433
2434 /* Disable RXNE interrupt */
2435 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2436
2437 if(hspi->TxXferCount == 0)
2438 {
2439 SPI_CloseRxTx_ISR(hspi);
2440 }
2441 }
2442 }
2443
2444 #if (USE_SPI_CRC != 0U)
2445 /**
2446 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
2447 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2448 * the configuration information for SPI module.
2449 * @retval None
2450 */
2451 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
2452 {
2453 /* Receive data in 16 Bit mode */
2454 __IO uint16_t tmpreg = hspi->Instance->DR;
2455 UNUSED(tmpreg); /* To avoid GCC warning */
2456
2457 /* Disable RXNE interrupt */
2458 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2459
2460 SPI_CloseRxTx_ISR(hspi);
2461 }
2462 #endif
2463
2464 /**
2465 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
2466 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2467 * the configuration information for SPI module.
2468 * @retval None
2469 */
2470 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2471 {
2472 /* Transmit data in 16 Bit mode */
2473 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2474 hspi->pTxBuffPtr += sizeof(uint16_t);
2475 hspi->TxXferCount--;
2476
2477 /* Enable CRC Transmission */
2478 if(hspi->TxXferCount == 0)
2479 {
2480 #if (USE_SPI_CRC != 0U)
2481 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2482 {
2483 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2484 }
2485 #endif
2486
2487 /* Disable TXE interrupt */
2488 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2489
2490 if(hspi->RxXferCount == 0)
2491 {
2492 SPI_CloseRxTx_ISR(hspi);
2493 }
2494 }
2495 }
2496
2497 #if (USE_SPI_CRC != 0U)
2498 /**
2499 * @brief Manage the CRC 8-bit receive in Interrupt context.
2500 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2501 * the configuration information for SPI module.
2502 * @retval None
2503 */
2504 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
2505 {
2506 __IO uint8_t tmpreg;
2507 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
2508
2509 UNUSED(tmpreg); /* To avoid GCC warning */
2510
2511 hspi->CRCSize--;
2512
2513 if(hspi->CRCSize == 0)
2514 {
2515 SPI_CloseRx_ISR(hspi);
2516 }
2517 }
2518 #endif
2519
2520 /**
2521 * @brief Manage the receive 8-bit in Interrupt context.
2522 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2523 * the configuration information for SPI module.
2524 * @retval None
2525 */
2526 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2527 {
2528 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
2529 hspi->RxXferCount--;
2530
2531 #if (USE_SPI_CRC != 0U)
2532 /* Enable CRC Transmission */
2533 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
2534 {
2535 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2536 }
2537 #endif
2538
2539 if(hspi->RxXferCount == 0)
2540 {
2541 #if (USE_SPI_CRC != 0U)
2542 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2543 {
2544 hspi->RxISR = SPI_RxISR_8BITCRC;
2545 return;
2546 }
2547 #endif
2548 SPI_CloseRx_ISR(hspi);
2549 }
2550 }
2551
2552 #if (USE_SPI_CRC != 0U)
2553 /**
2554 * @brief Manage the CRC 16-bit receive in Interrupt context.
2555 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2556 * the configuration information for SPI module.
2557 * @retval None
2558 */
2559 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
2560 {
2561 __IO uint16_t tmpreg;
2562
2563 tmpreg = hspi->Instance->DR;
2564 UNUSED(tmpreg); /* To avoid GCC warning */
2565
2566 /* Disable RXNE and ERR interrupt */
2567 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
2568
2569 SPI_CloseRx_ISR(hspi);
2570 }
2571 #endif
2572
2573 /**
2574 * @brief Manage the 16-bit receive in Interrupt context.
2575 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2576 * the configuration information for SPI module.
2577 * @retval None
2578 */
2579 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2580 {
2581 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
2582 hspi->pRxBuffPtr += sizeof(uint16_t);
2583 hspi->RxXferCount--;
2584 #if (USE_SPI_CRC != 0U)
2585 /* Enable CRC Transmission */
2586 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
2587 {
2588 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2589 }
2590 #endif
2591 if(hspi->RxXferCount == 0)
2592 {
2593 #if (USE_SPI_CRC != 0U)
2594 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2595 {
2596 hspi->RxISR = SPI_RxISR_16BITCRC;
2597 return;
2598 }
2599 #endif
2600 SPI_CloseRx_ISR(hspi);
2601 }
2602 }
2603
2604 /**
2605 * @brief Handle the data 8-bit transmit in Interrupt mode.
2606 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2607 * the configuration information for SPI module.
2608 * @retval None
2609 */
2610 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2611 {
2612 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
2613 hspi->TxXferCount--;
2614
2615 if(hspi->TxXferCount == 0)
2616 {
2617 #if (USE_SPI_CRC != 0U)
2618 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2619 {
2620 /* Enable CRC Transmission */
2621 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2622 }
2623 #endif
2624 SPI_CloseTx_ISR(hspi);
2625 }
2626 }
2627
2628 /**
2629 * @brief Handle the data 16-bit transmit in Interrupt mode.
2630 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2631 * the configuration information for SPI module.
2632 * @retval None
2633 */
2634 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2635 {
2636 /* Transmit data in 16 Bit mode */
2637 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2638 hspi->pTxBuffPtr += sizeof(uint16_t);
2639 hspi->TxXferCount--;
2640
2641 if(hspi->TxXferCount == 0)
2642 {
2643 #if (USE_SPI_CRC != 0U)
2644 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2645 {
2646 /* Enable CRC Transmission */
2647 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2648 }
2649 #endif
2650 SPI_CloseTx_ISR(hspi);
2651 }
2652 }
2653
2654 /**
2655 * @brief Handle SPI Communication Timeout.
2656 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2657 * the configuration information for SPI module.
2658 * @param Flag : SPI flag to check
2659 * @param State : flag state to check
2660 * @param Timeout : Timeout duration
2661 * @retval HAL status
2662 */
2663 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
2664 {
2665 uint32_t tickstart = HAL_GetTick();
2666
2667 while((hspi->Instance->SR & Flag) != State)
2668 {
2669 if(Timeout != HAL_MAX_DELAY)
2670 {
2671 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
2672 {
2673 /* Disable the SPI and reset the CRC: the CRC value should be cleared
2674 on both master and slave sides in order to resynchronize the master
2675 and slave for their respective CRC calculation */
2676
2677 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
2678 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
2679
2680 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2681 {
2682 /* Disable SPI peripheral */
2683 __HAL_SPI_DISABLE(hspi);
2684 }
2685
2686 /* Reset CRC Calculation */
2687 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2688 {
2689 SPI_RESET_CRC(hspi);
2690 }
2691
2692 hspi->State= HAL_SPI_STATE_READY;
2693
2694 /* Process Unlocked */
2695 __HAL_UNLOCK(hspi);
2696
2697 return HAL_TIMEOUT;
2698 }
2699 }
2700 }
2701 return HAL_OK;
2702 }
2703
2704 /**
2705 * @brief Handle SPI FIFO Communication Timeout.
2706 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2707 * the configuration information for SPI module.
2708 * @param Fifo : Fifo to check
2709 * @param State : Fifo state to check
2710 * @param Timeout : Timeout duration
2711 * @retval HAL status
2712 */
2713 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
2714 {
2715 __IO uint8_t tmpreg;
2716 uint32_t tickstart = HAL_GetTick();
2717
2718 while((hspi->Instance->SR & Fifo) != State)
2719 {
2720 if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
2721 {
2722 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
2723 UNUSED(tmpreg); /* To avoid GCC warning */
2724 }
2725
2726 if(Timeout != HAL_MAX_DELAY)
2727 {
2728 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
2729 {
2730 /* Disable the SPI and reset the CRC: the CRC value should be cleared
2731 on both master and slave sides in order to resynchronize the master
2732 and slave for their respective CRC calculation */
2733
2734 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
2735 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
2736
2737 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2738 {
2739 /* Disable SPI peripheral */
2740 __HAL_SPI_DISABLE(hspi);
2741 }
2742
2743 /* Reset CRC Calculation */
2744 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2745 {
2746 SPI_RESET_CRC(hspi);
2747 }
2748
2749 hspi->State = HAL_SPI_STATE_READY;
2750
2751 /* Process Unlocked */
2752 __HAL_UNLOCK(hspi);
2753
2754 return HAL_TIMEOUT;
2755 }
2756 }
2757 }
2758 return HAL_OK;
2759 }
2760
2761 /**
2762 * @brief Handle the check of the RX transaction complete.
2763 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2764 * the configuration information for SPI module.
2765 * @param Timeout : Timeout duration
2766 * @retval None
2767 */
2768 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
2769 {
2770 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2771 {
2772 /* Disable SPI peripheral */
2773 __HAL_SPI_DISABLE(hspi);
2774 }
2775
2776 /* Control the BSY flag */
2777 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
2778 {
2779 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
2780 return HAL_TIMEOUT;
2781 }
2782
2783 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2784 {
2785 /* Empty the FRLVL fifo */
2786 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
2787 {
2788 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
2789 return HAL_TIMEOUT;
2790 }
2791 }
2792 return HAL_OK;
2793 }
2794
2795 /**
2796 * @brief Handle the check of the RXTX or TX transaction complete.
2797 * @param hspi: SPI handle
2798 * @param Timeout : Timeout duration
2799 */
2800 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
2801 {
2802 /* Procedure to check the transaction complete */
2803 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
2804 {
2805 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
2806 return HAL_TIMEOUT;
2807 }
2808 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
2809 {
2810 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
2811 return HAL_TIMEOUT;
2812 }
2813 /* Control the BSY flag */
2814 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
2815 {
2816 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
2817 return HAL_TIMEOUT;
2818 }
2819 return HAL_OK;
2820 }
2821
2822 /**
2823 * @brief Handle the end of the RXTX transaction.
2824 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2825 * the configuration information for SPI module.
2826 * @retval None
2827 */
2828 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
2829 {
2830 /* Disable ERR interrupt */
2831 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2832
2833 /* Check the end of the transaction */
2834 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
2835 {
2836 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
2837 }
2838
2839 #if (USE_SPI_CRC != 0U)
2840 /* Check if CRC error occurred */
2841 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2842 {
2843 hspi->State = HAL_SPI_STATE_READY;
2844 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2845 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2846 HAL_SPI_ErrorCallback(hspi);
2847 }
2848 else
2849 {
2850 #endif
2851 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
2852 {
2853 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
2854 {
2855 hspi->State = HAL_SPI_STATE_READY;
2856 HAL_SPI_RxCpltCallback(hspi);
2857 }
2858 else
2859 {
2860 hspi->State = HAL_SPI_STATE_READY;
2861 HAL_SPI_TxRxCpltCallback(hspi);
2862 }
2863 }
2864 else
2865 {
2866 hspi->State = HAL_SPI_STATE_READY;
2867 HAL_SPI_ErrorCallback(hspi);
2868 }
2869 #if (USE_SPI_CRC != 0U)
2870 }
2871 #endif
2872 }
2873
2874 /**
2875 * @brief Handle the end of the RX transaction.
2876 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2877 * the configuration information for SPI module.
2878 * @retval None
2879 */
2880 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
2881 {
2882 /* Disable RXNE and ERR interrupt */
2883 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
2884
2885 /* Check the end of the transaction */
2886 if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
2887 {
2888 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
2889 }
2890 hspi->State = HAL_SPI_STATE_READY;
2891 #if (USE_SPI_CRC != 0U)
2892 /* Check if CRC error occurred */
2893 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2894 {
2895 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2896 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2897 HAL_SPI_ErrorCallback(hspi);
2898 }
2899 else
2900 {
2901 #endif
2902 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
2903 {
2904 HAL_SPI_RxCpltCallback(hspi);
2905 }
2906 else
2907 {
2908 HAL_SPI_ErrorCallback(hspi);
2909 }
2910 #if (USE_SPI_CRC != 0U)
2911 }
2912 #endif
2913 }
2914
2915 /**
2916 * @brief Handle the end of the TX transaction.
2917 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2918 * the configuration information for SPI module.
2919 * @retval None
2920 */
2921 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
2922 {
2923 /* Disable TXE and ERR interrupt */
2924 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
2925
2926 /* Check the end of the transaction */
2927 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
2928 {
2929 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
2930 }
2931
2932 /* Clear overrun flag in 2 Lines communication mode because received is not read */
2933 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
2934 {
2935 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2936 }
2937
2938 hspi->State = HAL_SPI_STATE_READY;
2939 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2940 {
2941 HAL_SPI_ErrorCallback(hspi);
2942 }
2943 else
2944 {
2945 HAL_SPI_TxCpltCallback(hspi);
2946 }
2947 }
2948
2949 /**
2950 * @}
2951 */
2952
2953 #endif /* HAL_SPI_MODULE_ENABLED */
2954
2955 /**
2956 * @}
2957 */
2958
2959 /**
2960 * @}
2961 */
2962
2963 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)