2 ******************************************************************************
3 * @file stm32f7xx_hal_tim.c
4 * @author MCD Application Team
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Time Base Initialization
12 * + Time Base Start Interruption
13 * + Time Base Start DMA
14 * + Time Output Compare/PWM Initialization
15 * + Time Output Compare/PWM Channel Configuration
16 * + Time Output Compare/PWM Start
17 * + Time Output Compare/PWM Start Interruption
18 * + Time Output Compare/PWM Start DMA
19 * + Time Input Capture Initialization
20 * + Time Input Capture Channel Configuration
21 * + Time Input Capture Start
22 * + Time Input Capture Start Interruption
23 * + Time Input Capture Start DMA
24 * + Time One Pulse Initialization
25 * + Time One Pulse Channel Configuration
26 * + Time One Pulse Start
27 * + Time Encoder Interface Initialization
28 * + Time Encoder Interface Start
29 * + Time Encoder Interface Start Interruption
30 * + Time Encoder Interface Start DMA
31 * + Commutation Event configuration with Interruption and DMA
32 * + Time OCRef clear configuration
33 * + Time External Clock configuration
35 ==============================================================================
36 ##### TIMER Generic features #####
37 ==============================================================================
38 [..] The Timer features include:
39 (#) 16-bit up, down, up/down auto-reload counter.
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
41 counter clock frequency either by any factor between 1 and 65536.
42 (#) Up to 4 independent channels for:
45 (++) PWM generation (Edge and Center-aligned Mode)
46 (++) One-pulse mode output
48 ##### How to use this driver #####
49 ==============================================================================
51 (#) Initialize the TIM low level resources by implementing the following functions
52 depending from feature used :
53 (++) Time Base : HAL_TIM_Base_MspInit()
54 (++) Input Capture : HAL_TIM_IC_MspInit()
55 (++) Output Compare : HAL_TIM_OC_MspInit()
56 (++) PWM generation : HAL_TIM_PWM_MspInit()
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60 (#) Initialize the TIM low level resources :
61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
62 (##) TIM pins configuration
63 (+++) Enable the clock for the TIM GPIOs using the following function:
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67 (#) The external Clock can be configured, if needed (the default clock is the
68 internal clock from the APBx), using the following function:
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
72 (#) Configure the TIM in the desired functioning mode using one of the
73 initialization function of this driver:
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
76 Output Compare signal.
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93 (#) The DMA Burst is managed with the two following functions:
94 HAL_TIM_DMABurst_WriteStart()
95 HAL_TIM_DMABurst_ReadStart()
98 ******************************************************************************
101 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
125 ******************************************************************************
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f7xx_hal.h"
131 /** @addtogroup STM32F7xx_HAL_Driver
135 /** @defgroup TIM TIM
136 * @brief TIM HAL module driver
140 #ifdef HAL_TIM_MODULE_ENABLED
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /* Private macro -------------------------------------------------------------*/
145 /* Private variables ---------------------------------------------------------*/
146 /** @addtogroup TIM_Private_Functions
149 /* Private function prototypes -----------------------------------------------*/
150 static void TIM_TI1_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
);
151 static void TIM_TI2_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
152 uint32_t TIM_ICFilter
);
153 static void TIM_TI2_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
);
154 static void TIM_TI3_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
155 uint32_t TIM_ICFilter
);
156 static void TIM_TI4_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
157 uint32_t TIM_ICFilter
);
159 static void TIM_ITRx_SetConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_ITRx
);
160 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef
*hdma
);
161 static void TIM_DMATriggerCplt(DMA_HandleTypeDef
*hdma
);
162 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef
*htim
,
163 TIM_SlaveConfigTypeDef
* sSlaveConfig
);
168 /* Exported functions --------------------------------------------------------*/
169 /** @defgroup TIM_Exported_Functions TIM Exported Functions
173 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
174 * @brief Time Base functions
177 ==============================================================================
178 ##### Time Base functions #####
179 ==============================================================================
181 This section provides functions allowing to:
182 (+) Initialize and configure the TIM base.
183 (+) De-initialize the TIM base.
184 (+) Start the Time Base.
185 (+) Stop the Time Base.
186 (+) Start the Time Base and enable interrupt.
187 (+) Stop the Time Base and disable interrupt.
188 (+) Start the Time Base and enable DMA transfer.
189 (+) Stop the Time Base and disable DMA transfer.
195 * @brief Initializes the TIM Time base Unit according to the specified
196 * parameters in the TIM_HandleTypeDef and create the associated handle.
197 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
198 * the configuration information for TIM module.
201 HAL_StatusTypeDef
HAL_TIM_Base_Init(TIM_HandleTypeDef
*htim
)
203 /* Check the TIM handle allocation */
209 /* Check the parameters */
210 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
211 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
212 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
214 if(htim
->State
== HAL_TIM_STATE_RESET
)
216 /* Init the low level hardware : GPIO, CLOCK, NVIC */
217 HAL_TIM_Base_MspInit(htim
);
220 /* Set the TIM state */
221 htim
->State
= HAL_TIM_STATE_BUSY
;
223 /* Set the Time Base configuration */
224 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
226 /* Initialize the TIM state*/
227 htim
->State
= HAL_TIM_STATE_READY
;
233 * @brief DeInitializes the TIM Base peripheral
234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
235 * the configuration information for TIM module.
238 HAL_StatusTypeDef
HAL_TIM_Base_DeInit(TIM_HandleTypeDef
*htim
)
240 /* Check the parameters */
241 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
243 htim
->State
= HAL_TIM_STATE_BUSY
;
245 /* Disable the TIM Peripheral Clock */
246 __HAL_TIM_DISABLE(htim
);
248 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
249 HAL_TIM_Base_MspDeInit(htim
);
251 /* Change TIM state */
252 htim
->State
= HAL_TIM_STATE_RESET
;
261 * @brief Initializes the TIM Base MSP.
262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
263 * the configuration information for TIM module.
266 __weak
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef
*htim
)
268 /* Prevent unused argument(s) compilation warning */
271 /* NOTE : This function Should not be modified, when the callback is needed,
272 the HAL_TIM_Base_MspInit could be implemented in the user file
277 * @brief DeInitializes TIM Base MSP.
278 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
279 * the configuration information for TIM module.
282 __weak
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef
*htim
)
284 /* Prevent unused argument(s) compilation warning */
287 /* NOTE : This function Should not be modified, when the callback is needed,
288 the HAL_TIM_Base_MspDeInit could be implemented in the user file
293 * @brief Starts the TIM Base generation.
294 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
295 * the configuration information for TIM module.
298 HAL_StatusTypeDef
HAL_TIM_Base_Start(TIM_HandleTypeDef
*htim
)
300 /* Check the parameters */
301 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
303 /* Set the TIM state */
304 htim
->State
= HAL_TIM_STATE_BUSY
;
306 /* Enable the Peripheral */
307 __HAL_TIM_ENABLE(htim
);
309 /* Change the TIM state*/
310 htim
->State
= HAL_TIM_STATE_READY
;
312 /* Return function status */
317 * @brief Stops the TIM Base generation.
318 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
319 * the configuration information for TIM module.
322 HAL_StatusTypeDef
HAL_TIM_Base_Stop(TIM_HandleTypeDef
*htim
)
324 /* Check the parameters */
325 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
327 /* Set the TIM state */
328 htim
->State
= HAL_TIM_STATE_BUSY
;
330 /* Disable the Peripheral */
331 __HAL_TIM_DISABLE(htim
);
333 /* Change the TIM state*/
334 htim
->State
= HAL_TIM_STATE_READY
;
336 /* Return function status */
341 * @brief Starts the TIM Base generation in interrupt mode.
342 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
343 * the configuration information for TIM module.
346 HAL_StatusTypeDef
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef
*htim
)
348 /* Check the parameters */
349 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
351 /* Enable the TIM Update interrupt */
352 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_UPDATE
);
354 /* Enable the Peripheral */
355 __HAL_TIM_ENABLE(htim
);
357 /* Return function status */
362 * @brief Stops the TIM Base generation in interrupt mode.
363 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
364 * the configuration information for TIM module.
367 HAL_StatusTypeDef
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef
*htim
)
369 /* Check the parameters */
370 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
371 /* Disable the TIM Update interrupt */
372 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_UPDATE
);
374 /* Disable the Peripheral */
375 __HAL_TIM_DISABLE(htim
);
377 /* Return function status */
382 * @brief Starts the TIM Base generation in DMA mode.
383 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
384 * the configuration information for TIM module.
385 * @param pData: The source Buffer address.
386 * @param Length: The length of data to be transferred from memory to peripheral.
389 HAL_StatusTypeDef
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t *pData
, uint16_t Length
)
391 /* Check the parameters */
392 assert_param(IS_TIM_DMA_INSTANCE(htim
->Instance
));
394 if((htim
->State
== HAL_TIM_STATE_BUSY
))
398 else if((htim
->State
== HAL_TIM_STATE_READY
))
400 if((pData
== 0 ) && (Length
> 0))
406 htim
->State
= HAL_TIM_STATE_BUSY
;
409 /* Set the DMA Period elapsed callback */
410 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferCpltCallback
= TIM_DMAPeriodElapsedCplt
;
412 /* Set the DMA error callback */
413 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferErrorCallback
= HAL_TIM_DMAError
;
415 /* Enable the DMA Stream */
416 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_UPDATE
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->ARR
, Length
);
418 /* Enable the TIM Update DMA request */
419 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_UPDATE
);
421 /* Enable the Peripheral */
422 __HAL_TIM_ENABLE(htim
);
424 /* Return function status */
429 * @brief Stops the TIM Base generation in DMA mode.
430 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
431 * the configuration information for TIM module.
434 HAL_StatusTypeDef
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef
*htim
)
436 /* Check the parameters */
437 assert_param(IS_TIM_DMA_INSTANCE(htim
->Instance
));
439 /* Disable the TIM Update DMA request */
440 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_UPDATE
);
442 /* Disable the Peripheral */
443 __HAL_TIM_DISABLE(htim
);
445 /* Change the htim state */
446 htim
->State
= HAL_TIM_STATE_READY
;
448 /* Return function status */
456 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
457 * @brief Time Output Compare functions
460 ==============================================================================
461 ##### Time Output Compare functions #####
462 ==============================================================================
464 This section provides functions allowing to:
465 (+) Initialize and configure the TIM Output Compare.
466 (+) De-initialize the TIM Output Compare.
467 (+) Start the Time Output Compare.
468 (+) Stop the Time Output Compare.
469 (+) Start the Time Output Compare and enable interrupt.
470 (+) Stop the Time Output Compare and disable interrupt.
471 (+) Start the Time Output Compare and enable DMA transfer.
472 (+) Stop the Time Output Compare and disable DMA transfer.
478 * @brief Initializes the TIM Output Compare according to the specified
479 * parameters in the TIM_HandleTypeDef and create the associated handle.
480 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
481 * the configuration information for TIM module.
484 HAL_StatusTypeDef
HAL_TIM_OC_Init(TIM_HandleTypeDef
* htim
)
486 /* Check the TIM handle allocation */
492 /* Check the parameters */
493 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
494 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
495 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
497 if(htim
->State
== HAL_TIM_STATE_RESET
)
499 /* Allocate lock resource and initialize it */
500 htim
->Lock
= HAL_UNLOCKED
;
501 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
502 HAL_TIM_OC_MspInit(htim
);
505 /* Set the TIM state */
506 htim
->State
= HAL_TIM_STATE_BUSY
;
508 /* Init the base time for the Output Compare */
509 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
511 /* Initialize the TIM state*/
512 htim
->State
= HAL_TIM_STATE_READY
;
518 * @brief DeInitializes the TIM peripheral
519 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
520 * the configuration information for TIM module.
523 HAL_StatusTypeDef
HAL_TIM_OC_DeInit(TIM_HandleTypeDef
*htim
)
525 /* Check the parameters */
526 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
528 htim
->State
= HAL_TIM_STATE_BUSY
;
530 /* Disable the TIM Peripheral Clock */
531 __HAL_TIM_DISABLE(htim
);
533 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
534 HAL_TIM_OC_MspDeInit(htim
);
536 /* Change TIM state */
537 htim
->State
= HAL_TIM_STATE_RESET
;
546 * @brief Initializes the TIM Output Compare MSP.
547 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
548 * the configuration information for TIM module.
551 __weak
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef
*htim
)
553 /* Prevent unused argument(s) compilation warning */
556 /* NOTE : This function Should not be modified, when the callback is needed,
557 the HAL_TIM_OC_MspInit could be implemented in the user file
562 * @brief DeInitializes TIM Output Compare MSP.
563 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
564 * the configuration information for TIM module.
567 __weak
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef
*htim
)
569 /* Prevent unused argument(s) compilation warning */
572 /* NOTE : This function Should not be modified, when the callback is needed,
573 the HAL_TIM_OC_MspDeInit could be implemented in the user file
578 * @brief Starts the TIM Output Compare signal generation.
579 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
580 * the configuration information for TIM module.
581 * @param Channel: TIM Channel to be enabled.
582 * This parameter can be one of the following values:
583 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
584 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
585 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
586 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
589 HAL_StatusTypeDef
HAL_TIM_OC_Start(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
591 /* Check the parameters */
592 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
594 /* Enable the Output compare channel */
595 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
597 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
599 /* Enable the main output */
600 __HAL_TIM_MOE_ENABLE(htim
);
603 /* Enable the Peripheral */
604 __HAL_TIM_ENABLE(htim
);
606 /* Return function status */
611 * @brief Stops the TIM Output Compare signal generation.
612 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
613 * the configuration information for TIM module.
614 * @param Channel: TIM Channel to be disabled.
615 * This parameter can be one of the following values:
616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
622 HAL_StatusTypeDef
HAL_TIM_OC_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
624 /* Check the parameters */
625 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
627 /* Disable the Output compare channel */
628 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
630 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
632 /* Disable the Main Output */
633 __HAL_TIM_MOE_DISABLE(htim
);
636 /* Disable the Peripheral */
637 __HAL_TIM_DISABLE(htim
);
639 /* Return function status */
644 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
645 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
646 * the configuration information for TIM module.
647 * @param Channel: TIM Channel to be enabled.
648 * This parameter can be one of the following values:
649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
655 HAL_StatusTypeDef
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
657 /* Check the parameters */
658 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
664 /* Enable the TIM Capture/Compare 1 interrupt */
665 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
671 /* Enable the TIM Capture/Compare 2 interrupt */
672 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
678 /* Enable the TIM Capture/Compare 3 interrupt */
679 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC3
);
685 /* Enable the TIM Capture/Compare 4 interrupt */
686 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC4
);
694 /* Enable the Output compare channel */
695 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
697 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
699 /* Enable the main output */
700 __HAL_TIM_MOE_ENABLE(htim
);
703 /* Enable the Peripheral */
704 __HAL_TIM_ENABLE(htim
);
706 /* Return function status */
711 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
712 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
713 * the configuration information for TIM module.
714 * @param Channel: TIM Channel to be disabled.
715 * This parameter can be one of the following values:
716 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
717 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
718 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
719 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
722 HAL_StatusTypeDef
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
724 /* Check the parameters */
725 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
731 /* Disable the TIM Capture/Compare 1 interrupt */
732 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
738 /* Disable the TIM Capture/Compare 2 interrupt */
739 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
745 /* Disable the TIM Capture/Compare 3 interrupt */
746 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC3
);
752 /* Disable the TIM Capture/Compare 4 interrupt */
753 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC4
);
761 /* Disable the Output compare channel */
762 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
764 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
766 /* Disable the Main Output */
767 __HAL_TIM_MOE_DISABLE(htim
);
770 /* Disable the Peripheral */
771 __HAL_TIM_DISABLE(htim
);
773 /* Return function status */
778 * @brief Starts the TIM Output Compare signal generation in DMA mode.
779 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
780 * the configuration information for TIM module.
781 * @param Channel: TIM Channel to be enabled.
782 * This parameter can be one of the following values:
783 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
784 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
785 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
786 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
787 * @param pData: The source Buffer address.
788 * @param Length: The length of data to be transferred from memory to TIM peripheral
791 HAL_StatusTypeDef
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData
, uint16_t Length
)
793 /* Check the parameters */
794 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
796 if((htim
->State
== HAL_TIM_STATE_BUSY
))
800 else if((htim
->State
== HAL_TIM_STATE_READY
))
802 if(((uint32_t)pData
== 0 ) && (Length
> 0))
808 htim
->State
= HAL_TIM_STATE_BUSY
;
815 /* Set the DMA Period elapsed callback */
816 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
818 /* Set the DMA error callback */
819 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= HAL_TIM_DMAError
;
821 /* Enable the DMA Stream */
822 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR1
, Length
);
824 /* Enable the TIM Capture/Compare 1 DMA request */
825 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
831 /* Set the DMA Period elapsed callback */
832 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
834 /* Set the DMA error callback */
835 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= HAL_TIM_DMAError
;
837 /* Enable the DMA Stream */
838 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR2
, Length
);
840 /* Enable the TIM Capture/Compare 2 DMA request */
841 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
847 /* Set the DMA Period elapsed callback */
848 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
850 /* Set the DMA error callback */
851 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= HAL_TIM_DMAError
;
853 /* Enable the DMA Stream */
854 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR3
,Length
);
856 /* Enable the TIM Capture/Compare 3 DMA request */
857 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC3
);
863 /* Set the DMA Period elapsed callback */
864 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
866 /* Set the DMA error callback */
867 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= HAL_TIM_DMAError
;
869 /* Enable the DMA Stream */
870 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR4
, Length
);
872 /* Enable the TIM Capture/Compare 4 DMA request */
873 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC4
);
881 /* Enable the Output compare channel */
882 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
884 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
886 /* Enable the main output */
887 __HAL_TIM_MOE_ENABLE(htim
);
890 /* Enable the Peripheral */
891 __HAL_TIM_ENABLE(htim
);
893 /* Return function status */
898 * @brief Stops the TIM Output Compare signal generation in DMA mode.
899 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
900 * the configuration information for TIM module.
901 * @param Channel: TIM Channel to be disabled.
902 * This parameter can be one of the following values:
903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
909 HAL_StatusTypeDef
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
911 /* Check the parameters */
912 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
918 /* Disable the TIM Capture/Compare 1 DMA request */
919 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
925 /* Disable the TIM Capture/Compare 2 DMA request */
926 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
932 /* Disable the TIM Capture/Compare 3 DMA request */
933 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC3
);
939 /* Disable the TIM Capture/Compare 4 interrupt */
940 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC4
);
948 /* Disable the Output compare channel */
949 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
951 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
953 /* Disable the Main Output */
954 __HAL_TIM_MOE_DISABLE(htim
);
957 /* Disable the Peripheral */
958 __HAL_TIM_DISABLE(htim
);
960 /* Change the htim state */
961 htim
->State
= HAL_TIM_STATE_READY
;
963 /* Return function status */
971 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
972 * @brief Time PWM functions
975 ==============================================================================
976 ##### Time PWM functions #####
977 ==============================================================================
979 This section provides functions allowing to:
980 (+) Initialize and configure the TIM OPWM.
981 (+) De-initialize the TIM PWM.
982 (+) Start the Time PWM.
983 (+) Stop the Time PWM.
984 (+) Start the Time PWM and enable interrupt.
985 (+) Stop the Time PWM and disable interrupt.
986 (+) Start the Time PWM and enable DMA transfer.
987 (+) Stop the Time PWM and disable DMA transfer.
993 * @brief Initializes the TIM PWM Time Base according to the specified
994 * parameters in the TIM_HandleTypeDef and create the associated handle.
995 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
996 * the configuration information for TIM module.
999 HAL_StatusTypeDef
HAL_TIM_PWM_Init(TIM_HandleTypeDef
*htim
)
1001 /* Check the TIM handle allocation */
1007 /* Check the parameters */
1008 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1009 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
1010 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
1012 if(htim
->State
== HAL_TIM_STATE_RESET
)
1014 /* Allocate lock resource and initialize it */
1015 htim
->Lock
= HAL_UNLOCKED
;
1016 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1017 HAL_TIM_PWM_MspInit(htim
);
1020 /* Set the TIM state */
1021 htim
->State
= HAL_TIM_STATE_BUSY
;
1023 /* Init the base time for the PWM */
1024 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
1026 /* Initialize the TIM state*/
1027 htim
->State
= HAL_TIM_STATE_READY
;
1033 * @brief DeInitializes the TIM peripheral
1034 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1035 * the configuration information for TIM module.
1036 * @retval HAL status
1038 HAL_StatusTypeDef
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef
*htim
)
1040 /* Check the parameters */
1041 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1043 htim
->State
= HAL_TIM_STATE_BUSY
;
1045 /* Disable the TIM Peripheral Clock */
1046 __HAL_TIM_DISABLE(htim
);
1048 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1049 HAL_TIM_PWM_MspDeInit(htim
);
1051 /* Change TIM state */
1052 htim
->State
= HAL_TIM_STATE_RESET
;
1061 * @brief Initializes the TIM PWM MSP.
1062 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1063 * the configuration information for TIM module.
1066 __weak
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef
*htim
)
1068 /* Prevent unused argument(s) compilation warning */
1071 /* NOTE : This function Should not be modified, when the callback is needed,
1072 the HAL_TIM_PWM_MspInit could be implemented in the user file
1077 * @brief DeInitializes TIM PWM MSP.
1078 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1079 * the configuration information for TIM module.
1082 __weak
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef
*htim
)
1084 /* Prevent unused argument(s) compilation warning */
1087 /* NOTE : This function Should not be modified, when the callback is needed,
1088 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1093 * @brief Starts the PWM signal generation.
1094 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1095 * the configuration information for TIM module.
1096 * @param Channel: TIM Channels to be enabled.
1097 * This parameter can be one of the following values:
1098 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1099 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1100 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1101 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1102 * @retval HAL status
1104 HAL_StatusTypeDef
HAL_TIM_PWM_Start(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1106 /* Check the parameters */
1107 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1109 /* Enable the Capture compare channel */
1110 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1112 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
1114 /* Enable the main output */
1115 __HAL_TIM_MOE_ENABLE(htim
);
1118 /* Enable the Peripheral */
1119 __HAL_TIM_ENABLE(htim
);
1121 /* Return function status */
1126 * @brief Stops the PWM signal generation.
1127 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1128 * the configuration information for TIM module.
1129 * @param Channel: TIM Channels to be disabled.
1130 * This parameter can be one of the following values:
1131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1135 * @retval HAL status
1137 HAL_StatusTypeDef
HAL_TIM_PWM_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1139 /* Check the parameters */
1140 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1142 /* Disable the Capture compare channel */
1143 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1145 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
1147 /* Disable the Main Output */
1148 __HAL_TIM_MOE_DISABLE(htim
);
1151 /* Disable the Peripheral */
1152 __HAL_TIM_DISABLE(htim
);
1154 /* Change the htim state */
1155 htim
->State
= HAL_TIM_STATE_READY
;
1157 /* Return function status */
1162 * @brief Starts the PWM signal generation in interrupt mode.
1163 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1164 * the configuration information for TIM module.
1165 * @param Channel: TIM Channel to be disabled.
1166 * This parameter can be one of the following values:
1167 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1168 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1169 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1170 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1171 * @retval HAL status
1173 HAL_StatusTypeDef
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1175 /* Check the parameters */
1176 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1182 /* Enable the TIM Capture/Compare 1 interrupt */
1183 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
1189 /* Enable the TIM Capture/Compare 2 interrupt */
1190 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
1196 /* Enable the TIM Capture/Compare 3 interrupt */
1197 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC3
);
1203 /* Enable the TIM Capture/Compare 4 interrupt */
1204 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC4
);
1212 /* Enable the Capture compare channel */
1213 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1215 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
1217 /* Enable the main output */
1218 __HAL_TIM_MOE_ENABLE(htim
);
1221 /* Enable the Peripheral */
1222 __HAL_TIM_ENABLE(htim
);
1224 /* Return function status */
1229 * @brief Stops the PWM signal generation in interrupt mode.
1230 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1231 * the configuration information for TIM module.
1232 * @param Channel: TIM Channels to be disabled.
1233 * This parameter can be one of the following values:
1234 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1235 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1236 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1237 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1238 * @retval HAL status
1240 HAL_StatusTypeDef
HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1242 /* Check the parameters */
1243 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1249 /* Disable the TIM Capture/Compare 1 interrupt */
1250 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
1256 /* Disable the TIM Capture/Compare 2 interrupt */
1257 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
1263 /* Disable the TIM Capture/Compare 3 interrupt */
1264 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC3
);
1270 /* Disable the TIM Capture/Compare 4 interrupt */
1271 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC4
);
1279 /* Disable the Capture compare channel */
1280 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1282 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
1284 /* Disable the Main Output */
1285 __HAL_TIM_MOE_DISABLE(htim
);
1288 /* Disable the Peripheral */
1289 __HAL_TIM_DISABLE(htim
);
1291 /* Return function status */
1296 * @brief Starts the TIM PWM signal generation in DMA mode.
1297 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1298 * the configuration information for TIM module.
1299 * @param Channel: TIM Channels to be enabled.
1300 * This parameter can be one of the following values:
1301 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1302 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1303 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1304 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1305 * @param pData: The source Buffer address.
1306 * @param Length: The length of data to be transferred from memory to TIM peripheral
1307 * @retval HAL status
1309 HAL_StatusTypeDef
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData
, uint16_t Length
)
1311 /* Check the parameters */
1312 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1314 if((htim
->State
== HAL_TIM_STATE_BUSY
))
1318 else if((htim
->State
== HAL_TIM_STATE_READY
))
1320 if(((uint32_t)pData
== 0 ) && (Length
> 0))
1326 htim
->State
= HAL_TIM_STATE_BUSY
;
1333 /* Set the DMA Period elapsed callback */
1334 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
1336 /* Set the DMA error callback */
1337 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= HAL_TIM_DMAError
;
1339 /* Enable the DMA Stream */
1340 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR1
, Length
);
1342 /* Enable the TIM Capture/Compare 1 DMA request */
1343 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
1349 /* Set the DMA Period elapsed callback */
1350 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
1352 /* Set the DMA error callback */
1353 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= HAL_TIM_DMAError
;
1355 /* Enable the DMA Stream */
1356 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR2
, Length
);
1358 /* Enable the TIM Capture/Compare 2 DMA request */
1359 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
1365 /* Set the DMA Period elapsed callback */
1366 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
1368 /* Set the DMA error callback */
1369 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= HAL_TIM_DMAError
;
1371 /* Enable the DMA Stream */
1372 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR3
,Length
);
1374 /* Enable the TIM Output Capture/Compare 3 request */
1375 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC3
);
1381 /* Set the DMA Period elapsed callback */
1382 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
1384 /* Set the DMA error callback */
1385 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= HAL_TIM_DMAError
;
1387 /* Enable the DMA Stream */
1388 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)pData
, (uint32_t)&htim
->Instance
->CCR4
, Length
);
1390 /* Enable the TIM Capture/Compare 4 DMA request */
1391 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC4
);
1399 /* Enable the Capture compare channel */
1400 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1402 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
1404 /* Enable the main output */
1405 __HAL_TIM_MOE_ENABLE(htim
);
1408 /* Enable the Peripheral */
1409 __HAL_TIM_ENABLE(htim
);
1411 /* Return function status */
1416 * @brief Stops the TIM PWM signal generation in DMA mode.
1417 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1418 * the configuration information for TIM module.
1419 * @param Channel: TIM Channels to be disabled.
1420 * This parameter can be one of the following values:
1421 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1422 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1423 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1424 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1425 * @retval HAL status
1427 HAL_StatusTypeDef
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1429 /* Check the parameters */
1430 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1436 /* Disable the TIM Capture/Compare 1 DMA request */
1437 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
1443 /* Disable the TIM Capture/Compare 2 DMA request */
1444 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
1450 /* Disable the TIM Capture/Compare 3 DMA request */
1451 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC3
);
1457 /* Disable the TIM Capture/Compare 4 interrupt */
1458 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC4
);
1466 /* Disable the Capture compare channel */
1467 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1469 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
1471 /* Disable the Main Output */
1472 __HAL_TIM_MOE_DISABLE(htim
);
1475 /* Disable the Peripheral */
1476 __HAL_TIM_DISABLE(htim
);
1478 /* Change the htim state */
1479 htim
->State
= HAL_TIM_STATE_READY
;
1481 /* Return function status */
1489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1490 * @brief Time Input Capture functions
1493 ==============================================================================
1494 ##### Time Input Capture functions #####
1495 ==============================================================================
1497 This section provides functions allowing to:
1498 (+) Initialize and configure the TIM Input Capture.
1499 (+) De-initialize the TIM Input Capture.
1500 (+) Start the Time Input Capture.
1501 (+) Stop the Time Input Capture.
1502 (+) Start the Time Input Capture and enable interrupt.
1503 (+) Stop the Time Input Capture and disable interrupt.
1504 (+) Start the Time Input Capture and enable DMA transfer.
1505 (+) Stop the Time Input Capture and disable DMA transfer.
1511 * @brief Initializes the TIM Input Capture Time base according to the specified
1512 * parameters in the TIM_HandleTypeDef and create the associated handle.
1513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1514 * the configuration information for TIM module.
1515 * @retval HAL status
1517 HAL_StatusTypeDef
HAL_TIM_IC_Init(TIM_HandleTypeDef
*htim
)
1519 /* Check the TIM handle allocation */
1525 /* Check the parameters */
1526 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1527 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
1528 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
1530 if(htim
->State
== HAL_TIM_STATE_RESET
)
1532 /* Allocate lock resource and initialize it */
1533 htim
->Lock
= HAL_UNLOCKED
;
1534 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1535 HAL_TIM_IC_MspInit(htim
);
1538 /* Set the TIM state */
1539 htim
->State
= HAL_TIM_STATE_BUSY
;
1541 /* Init the base time for the input capture */
1542 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
1544 /* Initialize the TIM state*/
1545 htim
->State
= HAL_TIM_STATE_READY
;
1551 * @brief DeInitializes the TIM peripheral
1552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1553 * the configuration information for TIM module.
1554 * @retval HAL status
1556 HAL_StatusTypeDef
HAL_TIM_IC_DeInit(TIM_HandleTypeDef
*htim
)
1558 /* Check the parameters */
1559 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
1561 htim
->State
= HAL_TIM_STATE_BUSY
;
1563 /* Disable the TIM Peripheral Clock */
1564 __HAL_TIM_DISABLE(htim
);
1566 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1567 HAL_TIM_IC_MspDeInit(htim
);
1569 /* Change TIM state */
1570 htim
->State
= HAL_TIM_STATE_RESET
;
1579 * @brief Initializes the TIM INput Capture MSP.
1580 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1581 * the configuration information for TIM module.
1584 __weak
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef
*htim
)
1586 /* Prevent unused argument(s) compilation warning */
1589 /* NOTE : This function Should not be modified, when the callback is needed,
1590 the HAL_TIM_IC_MspInit could be implemented in the user file
1595 * @brief DeInitializes TIM Input Capture MSP.
1596 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1597 * the configuration information for TIM module.
1600 __weak
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef
*htim
)
1602 /* Prevent unused argument(s) compilation warning */
1605 /* NOTE : This function Should not be modified, when the callback is needed,
1606 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1611 * @brief Starts the TIM Input Capture measurement.
1612 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1613 * the configuration information for TIM module.
1614 * @param Channel: TIM Channels to be enabled.
1615 * This parameter can be one of the following values:
1616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1620 * @retval HAL status
1622 HAL_StatusTypeDef
HAL_TIM_IC_Start (TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1624 /* Check the parameters */
1625 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1627 /* Enable the Input Capture channel */
1628 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1630 /* Enable the Peripheral */
1631 __HAL_TIM_ENABLE(htim
);
1633 /* Return function status */
1638 * @brief Stops the TIM Input Capture measurement.
1639 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1640 * the configuration information for TIM module.
1641 * @param Channel: TIM Channels to be disabled.
1642 * This parameter can be one of the following values:
1643 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1644 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1645 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1646 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1647 * @retval HAL status
1649 HAL_StatusTypeDef
HAL_TIM_IC_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1651 /* Check the parameters */
1652 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1654 /* Disable the Input Capture channel */
1655 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1657 /* Disable the Peripheral */
1658 __HAL_TIM_DISABLE(htim
);
1660 /* Return function status */
1665 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1666 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1667 * the configuration information for TIM module.
1668 * @param Channel: TIM Channels to be enabled.
1669 * This parameter can be one of the following values:
1670 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1671 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1672 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1673 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1674 * @retval HAL status
1676 HAL_StatusTypeDef
HAL_TIM_IC_Start_IT (TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1678 /* Check the parameters */
1679 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1685 /* Enable the TIM Capture/Compare 1 interrupt */
1686 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
1692 /* Enable the TIM Capture/Compare 2 interrupt */
1693 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
1699 /* Enable the TIM Capture/Compare 3 interrupt */
1700 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC3
);
1706 /* Enable the TIM Capture/Compare 4 interrupt */
1707 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC4
);
1714 /* Enable the Input Capture channel */
1715 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1717 /* Enable the Peripheral */
1718 __HAL_TIM_ENABLE(htim
);
1720 /* Return function status */
1725 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1726 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1727 * the configuration information for TIM module.
1728 * @param Channel: TIM Channels to be disabled.
1729 * This parameter can be one of the following values:
1730 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1731 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1732 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1733 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1734 * @retval HAL status
1736 HAL_StatusTypeDef
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1738 /* Check the parameters */
1739 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1745 /* Disable the TIM Capture/Compare 1 interrupt */
1746 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
1752 /* Disable the TIM Capture/Compare 2 interrupt */
1753 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
1759 /* Disable the TIM Capture/Compare 3 interrupt */
1760 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC3
);
1766 /* Disable the TIM Capture/Compare 4 interrupt */
1767 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC4
);
1775 /* Disable the Input Capture channel */
1776 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1778 /* Disable the Peripheral */
1779 __HAL_TIM_DISABLE(htim
);
1781 /* Return function status */
1786 * @brief Starts the TIM Input Capture measurement on in DMA mode.
1787 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1788 * the configuration information for TIM module.
1789 * @param Channel: TIM Channels to be enabled.
1790 * This parameter can be one of the following values:
1791 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1792 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1793 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1794 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1795 * @param pData: The destination Buffer address.
1796 * @param Length: The length of data to be transferred from TIM peripheral to memory.
1797 * @retval HAL status
1799 HAL_StatusTypeDef
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData
, uint16_t Length
)
1801 /* Check the parameters */
1802 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1803 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
1805 if((htim
->State
== HAL_TIM_STATE_BUSY
))
1809 else if((htim
->State
== HAL_TIM_STATE_READY
))
1811 if((pData
== 0 ) && (Length
> 0))
1817 htim
->State
= HAL_TIM_STATE_BUSY
;
1825 /* Set the DMA Period elapsed callback */
1826 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
1828 /* Set the DMA error callback */
1829 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= HAL_TIM_DMAError
;
1831 /* Enable the DMA Stream */
1832 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->CCR1
, (uint32_t)pData
, Length
);
1834 /* Enable the TIM Capture/Compare 1 DMA request */
1835 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
1841 /* Set the DMA Period elapsed callback */
1842 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
1844 /* Set the DMA error callback */
1845 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= HAL_TIM_DMAError
;
1847 /* Enable the DMA Stream */
1848 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->CCR2
, (uint32_t)pData
, Length
);
1850 /* Enable the TIM Capture/Compare 2 DMA request */
1851 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
1857 /* Set the DMA Period elapsed callback */
1858 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
1860 /* Set the DMA error callback */
1861 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= HAL_TIM_DMAError
;
1863 /* Enable the DMA Stream */
1864 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)&htim
->Instance
->CCR3
, (uint32_t)pData
, Length
);
1866 /* Enable the TIM Capture/Compare 3 DMA request */
1867 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC3
);
1873 /* Set the DMA Period elapsed callback */
1874 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
1876 /* Set the DMA error callback */
1877 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= HAL_TIM_DMAError
;
1879 /* Enable the DMA Stream */
1880 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)&htim
->Instance
->CCR4
, (uint32_t)pData
, Length
);
1882 /* Enable the TIM Capture/Compare 4 DMA request */
1883 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC4
);
1891 /* Enable the Input Capture channel */
1892 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_ENABLE
);
1894 /* Enable the Peripheral */
1895 __HAL_TIM_ENABLE(htim
);
1897 /* Return function status */
1902 * @brief Stops the TIM Input Capture measurement on in DMA mode.
1903 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1904 * the configuration information for TIM module.
1905 * @param Channel: TIM Channels to be disabled.
1906 * This parameter can be one of the following values:
1907 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1908 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1909 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1910 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1911 * @retval HAL status
1913 HAL_StatusTypeDef
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
1915 /* Check the parameters */
1916 assert_param(IS_TIM_CCX_INSTANCE(htim
->Instance
, Channel
));
1917 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
1923 /* Disable the TIM Capture/Compare 1 DMA request */
1924 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
1930 /* Disable the TIM Capture/Compare 2 DMA request */
1931 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
1937 /* Disable the TIM Capture/Compare 3 DMA request */
1938 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC3
);
1944 /* Disable the TIM Capture/Compare 4 DMA request */
1945 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC4
);
1953 /* Disable the Input Capture channel */
1954 TIM_CCxChannelCmd(htim
->Instance
, Channel
, TIM_CCx_DISABLE
);
1956 /* Disable the Peripheral */
1957 __HAL_TIM_DISABLE(htim
);
1959 /* Change the htim state */
1960 htim
->State
= HAL_TIM_STATE_READY
;
1962 /* Return function status */
1969 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1970 * @brief Time One Pulse functions
1973 ==============================================================================
1974 ##### Time One Pulse functions #####
1975 ==============================================================================
1977 This section provides functions allowing to:
1978 (+) Initialize and configure the TIM One Pulse.
1979 (+) De-initialize the TIM One Pulse.
1980 (+) Start the Time One Pulse.
1981 (+) Stop the Time One Pulse.
1982 (+) Start the Time One Pulse and enable interrupt.
1983 (+) Stop the Time One Pulse and disable interrupt.
1984 (+) Start the Time One Pulse and enable DMA transfer.
1985 (+) Stop the Time One Pulse and disable DMA transfer.
1991 * @brief Initializes the TIM One Pulse Time Base according to the specified
1992 * parameters in the TIM_HandleTypeDef and create the associated handle.
1993 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1994 * the configuration information for TIM module.
1995 * @param OnePulseMode: Select the One pulse mode.
1996 * This parameter can be one of the following values:
1997 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1998 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
1999 * @retval HAL status
2001 HAL_StatusTypeDef
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef
*htim
, uint32_t OnePulseMode
)
2003 /* Check the TIM handle allocation */
2009 /* Check the parameters */
2010 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
2011 assert_param(IS_TIM_COUNTER_MODE(htim
->Init
.CounterMode
));
2012 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim
->Init
.ClockDivision
));
2013 assert_param(IS_TIM_OPM_MODE(OnePulseMode
));
2015 if(htim
->State
== HAL_TIM_STATE_RESET
)
2017 /* Allocate lock resource and initialize it */
2018 htim
->Lock
= HAL_UNLOCKED
;
2019 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2020 HAL_TIM_OnePulse_MspInit(htim
);
2023 /* Set the TIM state */
2024 htim
->State
= HAL_TIM_STATE_BUSY
;
2026 /* Configure the Time base in the One Pulse Mode */
2027 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
2029 /* Reset the OPM Bit */
2030 htim
->Instance
->CR1
&= ~TIM_CR1_OPM
;
2032 /* Configure the OPM Mode */
2033 htim
->Instance
->CR1
|= OnePulseMode
;
2035 /* Initialize the TIM state*/
2036 htim
->State
= HAL_TIM_STATE_READY
;
2042 * @brief DeInitializes the TIM One Pulse
2043 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2044 * the configuration information for TIM module.
2045 * @retval HAL status
2047 HAL_StatusTypeDef
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef
*htim
)
2049 /* Check the parameters */
2050 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
2052 htim
->State
= HAL_TIM_STATE_BUSY
;
2054 /* Disable the TIM Peripheral Clock */
2055 __HAL_TIM_DISABLE(htim
);
2057 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2058 HAL_TIM_OnePulse_MspDeInit(htim
);
2060 /* Change TIM state */
2061 htim
->State
= HAL_TIM_STATE_RESET
;
2070 * @brief Initializes the TIM One Pulse MSP.
2071 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2072 * the configuration information for TIM module.
2075 __weak
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef
*htim
)
2077 /* Prevent unused argument(s) compilation warning */
2080 /* NOTE : This function Should not be modified, when the callback is needed,
2081 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2086 * @brief DeInitializes TIM One Pulse MSP.
2087 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2088 * the configuration information for TIM module.
2091 __weak
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef
*htim
)
2093 /* Prevent unused argument(s) compilation warning */
2096 /* NOTE : This function Should not be modified, when the callback is needed,
2097 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2102 * @brief Starts the TIM One Pulse signal generation.
2103 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2104 * the configuration information for TIM module.
2105 * @param OutputChannel : TIM Channels to be enabled.
2106 * This parameter can be one of the following values:
2107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2109 * @retval HAL status
2111 HAL_StatusTypeDef
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2113 /* Enable the Capture compare and the Input Capture channels
2114 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2115 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2116 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2117 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2119 No need to enable the counter, it's enabled automatically by hardware
2120 (the counter starts in response to a stimulus and generate a pulse */
2122 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2123 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2125 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
2127 /* Enable the main output */
2128 __HAL_TIM_MOE_ENABLE(htim
);
2131 /* Return function status */
2136 * @brief Stops the TIM One Pulse signal generation.
2137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2138 * the configuration information for TIM module.
2139 * @param OutputChannel : TIM Channels to be disable.
2140 * This parameter can be one of the following values:
2141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2143 * @retval HAL status
2145 HAL_StatusTypeDef
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2147 /* Disable the Capture compare and the Input Capture channels
2148 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2149 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2150 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2151 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2153 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2154 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2156 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
2158 /* Disable the Main Output */
2159 __HAL_TIM_MOE_DISABLE(htim
);
2162 /* Disable the Peripheral */
2163 __HAL_TIM_DISABLE(htim
);
2165 /* Return function status */
2170 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2171 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2172 * the configuration information for TIM module.
2173 * @param OutputChannel : TIM Channels to be enabled.
2174 * This parameter can be one of the following values:
2175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2177 * @retval HAL status
2179 HAL_StatusTypeDef
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2181 /* Enable the Capture compare and the Input Capture channels
2182 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2183 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2184 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2185 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2187 No need to enable the counter, it's enabled automatically by hardware
2188 (the counter starts in response to a stimulus and generate a pulse */
2190 /* Enable the TIM Capture/Compare 1 interrupt */
2191 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
2193 /* Enable the TIM Capture/Compare 2 interrupt */
2194 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
2196 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2197 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2199 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
2201 /* Enable the main output */
2202 __HAL_TIM_MOE_ENABLE(htim
);
2205 /* Return function status */
2210 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2211 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2212 * the configuration information for TIM module.
2213 * @param OutputChannel : TIM Channels to be enabled.
2214 * This parameter can be one of the following values:
2215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2217 * @retval HAL status
2219 HAL_StatusTypeDef
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t OutputChannel
)
2221 /* Disable the TIM Capture/Compare 1 interrupt */
2222 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
2224 /* Disable the TIM Capture/Compare 2 interrupt */
2225 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
2227 /* Disable the Capture compare and the Input Capture channels
2228 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2229 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2230 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2231 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2232 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2233 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2235 if(IS_TIM_ADVANCED_INSTANCE(htim
->Instance
) != RESET
)
2237 /* Disable the Main Output */
2238 __HAL_TIM_MOE_DISABLE(htim
);
2241 /* Disable the Peripheral */
2242 __HAL_TIM_DISABLE(htim
);
2244 /* Return function status */
2252 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2253 * @brief Time Encoder functions
2256 ==============================================================================
2257 ##### Time Encoder functions #####
2258 ==============================================================================
2260 This section provides functions allowing to:
2261 (+) Initialize and configure the TIM Encoder.
2262 (+) De-initialize the TIM Encoder.
2263 (+) Start the Time Encoder.
2264 (+) Stop the Time Encoder.
2265 (+) Start the Time Encoder and enable interrupt.
2266 (+) Stop the Time Encoder and disable interrupt.
2267 (+) Start the Time Encoder and enable DMA transfer.
2268 (+) Stop the Time Encoder and disable DMA transfer.
2274 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2275 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2276 * the configuration information for TIM module.
2277 * @param sConfig: TIM Encoder Interface configuration structure
2278 * @retval HAL status
2280 HAL_StatusTypeDef
HAL_TIM_Encoder_Init(TIM_HandleTypeDef
*htim
, TIM_Encoder_InitTypeDef
* sConfig
)
2282 uint32_t tmpsmcr
= 0;
2283 uint32_t tmpccmr1
= 0;
2284 uint32_t tmpccer
= 0;
2286 /* Check the TIM handle allocation */
2292 /* Check the parameters */
2293 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2294 assert_param(IS_TIM_ENCODER_MODE(sConfig
->EncoderMode
));
2295 assert_param(IS_TIM_IC_SELECTION(sConfig
->IC1Selection
));
2296 assert_param(IS_TIM_IC_SELECTION(sConfig
->IC2Selection
));
2297 assert_param(IS_TIM_IC_POLARITY(sConfig
->IC1Polarity
));
2298 assert_param(IS_TIM_IC_POLARITY(sConfig
->IC2Polarity
));
2299 assert_param(IS_TIM_IC_PRESCALER(sConfig
->IC1Prescaler
));
2300 assert_param(IS_TIM_IC_PRESCALER(sConfig
->IC2Prescaler
));
2301 assert_param(IS_TIM_IC_FILTER(sConfig
->IC1Filter
));
2302 assert_param(IS_TIM_IC_FILTER(sConfig
->IC2Filter
));
2304 if(htim
->State
== HAL_TIM_STATE_RESET
)
2306 /* Allocate lock resource and initialize it */
2307 htim
->Lock
= HAL_UNLOCKED
;
2308 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2309 HAL_TIM_Encoder_MspInit(htim
);
2312 /* Set the TIM state */
2313 htim
->State
= HAL_TIM_STATE_BUSY
;
2315 /* Reset the SMS bits */
2316 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
2318 /* Configure the Time base in the Encoder Mode */
2319 TIM_Base_SetConfig(htim
->Instance
, &htim
->Init
);
2321 /* Get the TIMx SMCR register value */
2322 tmpsmcr
= htim
->Instance
->SMCR
;
2324 /* Get the TIMx CCMR1 register value */
2325 tmpccmr1
= htim
->Instance
->CCMR1
;
2327 /* Get the TIMx CCER register value */
2328 tmpccer
= htim
->Instance
->CCER
;
2330 /* Set the encoder Mode */
2331 tmpsmcr
|= sConfig
->EncoderMode
;
2333 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2334 tmpccmr1
&= ~(TIM_CCMR1_CC1S
| TIM_CCMR1_CC2S
);
2335 tmpccmr1
|= (sConfig
->IC1Selection
| (sConfig
->IC2Selection
<< 8));
2337 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2338 tmpccmr1
&= ~(TIM_CCMR1_IC1PSC
| TIM_CCMR1_IC2PSC
);
2339 tmpccmr1
&= ~(TIM_CCMR1_IC1F
| TIM_CCMR1_IC2F
);
2340 tmpccmr1
|= sConfig
->IC1Prescaler
| (sConfig
->IC2Prescaler
<< 8);
2341 tmpccmr1
|= (sConfig
->IC1Filter
<< 4) | (sConfig
->IC2Filter
<< 12);
2343 /* Set the TI1 and the TI2 Polarities */
2344 tmpccer
&= ~(TIM_CCER_CC1P
| TIM_CCER_CC2P
);
2345 tmpccer
&= ~(TIM_CCER_CC1NP
| TIM_CCER_CC2NP
);
2346 tmpccer
|= sConfig
->IC1Polarity
| (sConfig
->IC2Polarity
<< 4);
2348 /* Write to TIMx SMCR */
2349 htim
->Instance
->SMCR
= tmpsmcr
;
2351 /* Write to TIMx CCMR1 */
2352 htim
->Instance
->CCMR1
= tmpccmr1
;
2354 /* Write to TIMx CCER */
2355 htim
->Instance
->CCER
= tmpccer
;
2357 /* Initialize the TIM state*/
2358 htim
->State
= HAL_TIM_STATE_READY
;
2364 * @brief DeInitializes the TIM Encoder interface
2365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2366 * the configuration information for TIM module.
2367 * @retval HAL status
2369 HAL_StatusTypeDef
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef
*htim
)
2371 /* Check the parameters */
2372 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
2374 htim
->State
= HAL_TIM_STATE_BUSY
;
2376 /* Disable the TIM Peripheral Clock */
2377 __HAL_TIM_DISABLE(htim
);
2379 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2380 HAL_TIM_Encoder_MspDeInit(htim
);
2382 /* Change TIM state */
2383 htim
->State
= HAL_TIM_STATE_RESET
;
2392 * @brief Initializes the TIM Encoder Interface MSP.
2393 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2394 * the configuration information for TIM module.
2397 __weak
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef
*htim
)
2399 /* Prevent unused argument(s) compilation warning */
2402 /* NOTE : This function Should not be modified, when the callback is needed,
2403 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2408 * @brief DeInitializes TIM Encoder Interface MSP.
2409 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2410 * the configuration information for TIM module.
2413 __weak
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef
*htim
)
2415 /* Prevent unused argument(s) compilation warning */
2418 /* NOTE : This function Should not be modified, when the callback is needed,
2419 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2424 * @brief Starts the TIM Encoder Interface.
2425 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2426 * the configuration information for TIM module.
2427 * @param Channel: TIM Channels to be enabled.
2428 * This parameter can be one of the following values:
2429 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2430 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2431 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2432 * @retval HAL status
2434 HAL_StatusTypeDef
HAL_TIM_Encoder_Start(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2436 /* Check the parameters */
2437 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2439 /* Enable the encoder interface channels */
2444 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2449 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2454 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2455 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2459 /* Enable the Peripheral */
2460 __HAL_TIM_ENABLE(htim
);
2462 /* Return function status */
2467 * @brief Stops the TIM Encoder Interface.
2468 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2469 * the configuration information for TIM module.
2470 * @param Channel: TIM Channels to be disabled.
2471 * This parameter can be one of the following values:
2472 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2473 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2474 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2475 * @retval HAL status
2477 HAL_StatusTypeDef
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2479 /* Check the parameters */
2480 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2482 /* Disable the Input Capture channels 1 and 2
2483 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2488 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2493 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2498 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2499 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2503 /* Disable the Peripheral */
2504 __HAL_TIM_DISABLE(htim
);
2506 /* Return function status */
2511 * @brief Starts the TIM Encoder Interface in interrupt mode.
2512 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2513 * the configuration information for TIM module.
2514 * @param Channel: TIM Channels to be enabled.
2515 * This parameter can be one of the following values:
2516 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2517 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2518 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2519 * @retval HAL status
2521 HAL_StatusTypeDef
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2523 /* Check the parameters */
2524 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2526 /* Enable the encoder interface channels */
2527 /* Enable the capture compare Interrupts 1 and/or 2 */
2532 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2533 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
2538 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2539 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
2544 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2545 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2546 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC1
);
2547 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_CC2
);
2552 /* Enable the Peripheral */
2553 __HAL_TIM_ENABLE(htim
);
2555 /* Return function status */
2560 * @brief Stops the TIM Encoder Interface in interrupt mode.
2561 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2562 * the configuration information for TIM module.
2563 * @param Channel: TIM Channels to be disabled.
2564 * This parameter can be one of the following values:
2565 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2566 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2567 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2568 * @retval HAL status
2570 HAL_StatusTypeDef
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2572 /* Check the parameters */
2573 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
2575 /* Disable the Input Capture channels 1 and 2
2576 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2577 if(Channel
== TIM_CHANNEL_1
)
2579 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2581 /* Disable the capture compare Interrupts 1 */
2582 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
2584 else if(Channel
== TIM_CHANNEL_2
)
2586 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2588 /* Disable the capture compare Interrupts 2 */
2589 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
2593 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2594 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2596 /* Disable the capture compare Interrupts 1 and 2 */
2597 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC1
);
2598 __HAL_TIM_DISABLE_IT(htim
, TIM_IT_CC2
);
2601 /* Disable the Peripheral */
2602 __HAL_TIM_DISABLE(htim
);
2604 /* Change the htim state */
2605 htim
->State
= HAL_TIM_STATE_READY
;
2607 /* Return function status */
2612 * @brief Starts the TIM Encoder Interface in DMA mode.
2613 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2614 * the configuration information for TIM module.
2615 * @param Channel: TIM Channels to be enabled.
2616 * This parameter can be one of the following values:
2617 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2618 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2619 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2620 * @param pData1: The destination Buffer address for IC1.
2621 * @param pData2: The destination Buffer address for IC2.
2622 * @param Length: The length of data to be transferred from TIM peripheral to memory.
2623 * @retval HAL status
2625 HAL_StatusTypeDef
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
, uint32_t *pData1
, uint32_t *pData2
, uint16_t Length
)
2627 /* Check the parameters */
2628 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
2630 if((htim
->State
== HAL_TIM_STATE_BUSY
))
2634 else if((htim
->State
== HAL_TIM_STATE_READY
))
2636 if((((pData1
== 0) || (pData2
== 0) )) && (Length
> 0))
2642 htim
->State
= HAL_TIM_STATE_BUSY
;
2650 /* Set the DMA Period elapsed callback */
2651 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
2653 /* Set the DMA error callback */
2654 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= HAL_TIM_DMAError
;
2656 /* Enable the DMA Stream */
2657 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->CCR1
, (uint32_t )pData1
, Length
);
2659 /* Enable the TIM Input Capture DMA request */
2660 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
2662 /* Enable the Peripheral */
2663 __HAL_TIM_ENABLE(htim
);
2665 /* Enable the Capture compare channel */
2666 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2672 /* Set the DMA Period elapsed callback */
2673 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
2675 /* Set the DMA error callback */
2676 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= HAL_TIM_DMAError
;
2677 /* Enable the DMA Stream */
2678 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->CCR2
, (uint32_t)pData2
, Length
);
2680 /* Enable the TIM Input Capture DMA request */
2681 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
2683 /* Enable the Peripheral */
2684 __HAL_TIM_ENABLE(htim
);
2686 /* Enable the Capture compare channel */
2687 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2691 case TIM_CHANNEL_ALL
:
2693 /* Set the DMA Period elapsed callback */
2694 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
2696 /* Set the DMA error callback */
2697 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= HAL_TIM_DMAError
;
2699 /* Enable the DMA Stream */
2700 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->CCR1
, (uint32_t)pData1
, Length
);
2702 /* Set the DMA Period elapsed callback */
2703 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
2705 /* Set the DMA error callback */
2706 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= HAL_TIM_DMAError
;
2708 /* Enable the DMA Stream */
2709 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->CCR2
, (uint32_t)pData2
, Length
);
2711 /* Enable the Peripheral */
2712 __HAL_TIM_ENABLE(htim
);
2714 /* Enable the Capture compare channel */
2715 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_ENABLE
);
2716 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_ENABLE
);
2718 /* Enable the TIM Input Capture DMA request */
2719 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC1
);
2720 /* Enable the TIM Input Capture DMA request */
2721 __HAL_TIM_ENABLE_DMA(htim
, TIM_DMA_CC2
);
2728 /* Return function status */
2733 * @brief Stops the TIM Encoder Interface in DMA mode.
2734 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2735 * the configuration information for TIM module.
2736 * @param Channel: TIM Channels to be enabled.
2737 * This parameter can be one of the following values:
2738 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2739 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2740 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2741 * @retval HAL status
2743 HAL_StatusTypeDef
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
2745 /* Check the parameters */
2746 assert_param(IS_TIM_DMA_CC_INSTANCE(htim
->Instance
));
2748 /* Disable the Input Capture channels 1 and 2
2749 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2750 if(Channel
== TIM_CHANNEL_1
)
2752 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2754 /* Disable the capture compare DMA Request 1 */
2755 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
2757 else if(Channel
== TIM_CHANNEL_2
)
2759 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2761 /* Disable the capture compare DMA Request 2 */
2762 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
2766 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_1
, TIM_CCx_DISABLE
);
2767 TIM_CCxChannelCmd(htim
->Instance
, TIM_CHANNEL_2
, TIM_CCx_DISABLE
);
2769 /* Disable the capture compare DMA Request 1 and 2 */
2770 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC1
);
2771 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_CC2
);
2774 /* Disable the Peripheral */
2775 __HAL_TIM_DISABLE(htim
);
2777 /* Change the htim state */
2778 htim
->State
= HAL_TIM_STATE_READY
;
2780 /* Return function status */
2787 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2788 * @brief IRQ handler management
2791 ==============================================================================
2792 ##### IRQ handler management #####
2793 ==============================================================================
2795 This section provides Timer IRQ handler function.
2801 * @brief This function handles TIM interrupts requests.
2802 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2803 * the configuration information for TIM module.
2806 void HAL_TIM_IRQHandler(TIM_HandleTypeDef
*htim
)
2808 /* Capture compare 1 event */
2809 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC1
) != RESET
)
2811 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC1
) !=RESET
)
2814 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC1
);
2815 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_1
;
2817 /* Input capture event */
2818 if((htim
->Instance
->CCMR1
& TIM_CCMR1_CC1S
) != 0x00)
2820 HAL_TIM_IC_CaptureCallback(htim
);
2822 /* Output compare event */
2825 HAL_TIM_OC_DelayElapsedCallback(htim
);
2826 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2828 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2832 /* Capture compare 2 event */
2833 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC2
) != RESET
)
2835 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC2
) !=RESET
)
2837 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC2
);
2838 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_2
;
2839 /* Input capture event */
2840 if((htim
->Instance
->CCMR1
& TIM_CCMR1_CC2S
) != 0x00)
2842 HAL_TIM_IC_CaptureCallback(htim
);
2844 /* Output compare event */
2847 HAL_TIM_OC_DelayElapsedCallback(htim
);
2848 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2850 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2853 /* Capture compare 3 event */
2854 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC3
) != RESET
)
2856 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC3
) !=RESET
)
2858 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC3
);
2859 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_3
;
2860 /* Input capture event */
2861 if((htim
->Instance
->CCMR2
& TIM_CCMR2_CC3S
) != 0x00)
2863 HAL_TIM_IC_CaptureCallback(htim
);
2865 /* Output compare event */
2868 HAL_TIM_OC_DelayElapsedCallback(htim
);
2869 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2871 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2874 /* Capture compare 4 event */
2875 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_CC4
) != RESET
)
2877 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_CC4
) !=RESET
)
2879 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_CC4
);
2880 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_4
;
2881 /* Input capture event */
2882 if((htim
->Instance
->CCMR2
& TIM_CCMR2_CC4S
) != 0x00)
2884 HAL_TIM_IC_CaptureCallback(htim
);
2886 /* Output compare event */
2889 HAL_TIM_OC_DelayElapsedCallback(htim
);
2890 HAL_TIM_PWM_PulseFinishedCallback(htim
);
2892 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
2895 /* TIM Update event */
2896 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_UPDATE
) != RESET
)
2898 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_UPDATE
) !=RESET
)
2900 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_UPDATE
);
2901 HAL_TIM_PeriodElapsedCallback(htim
);
2904 /* TIM Break input event */
2905 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_BREAK
) != RESET
)
2907 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_BREAK
) !=RESET
)
2909 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_BREAK
);
2910 HAL_TIMEx_BreakCallback(htim
);
2914 /* TIM Break input event */
2915 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_BREAK2
) != RESET
)
2917 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_BREAK
) !=RESET
)
2919 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_BREAK
);
2920 HAL_TIMEx_BreakCallback(htim
);
2924 /* TIM Trigger detection event */
2925 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_TRIGGER
) != RESET
)
2927 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_TRIGGER
) !=RESET
)
2929 __HAL_TIM_CLEAR_IT(htim
, TIM_IT_TRIGGER
);
2930 HAL_TIM_TriggerCallback(htim
);
2933 /* TIM commutation event */
2934 if(__HAL_TIM_GET_FLAG(htim
, TIM_FLAG_COM
) != RESET
)
2936 if(__HAL_TIM_GET_IT_SOURCE(htim
, TIM_IT_COM
) !=RESET
)
2938 __HAL_TIM_CLEAR_IT(htim
, TIM_FLAG_COM
);
2939 HAL_TIMEx_CommutationCallback(htim
);
2948 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2949 * @brief Peripheral Control functions
2952 ==============================================================================
2953 ##### Peripheral Control functions #####
2954 ==============================================================================
2956 This section provides functions allowing to:
2957 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2958 (+) Configure External Clock source.
2959 (+) Configure Complementary channels, break features and dead time.
2960 (+) Configure Master and the Slave synchronization.
2961 (+) Configure the DMA Burst Mode.
2968 * @brief Initializes the TIM Output Compare Channels according to the specified
2969 * parameters in the TIM_OC_InitTypeDef.
2970 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2971 * the configuration information for TIM module.
2972 * @param sConfig: TIM Output Compare configuration structure
2973 * @param Channel: TIM Channels to be enabled.
2974 * This parameter can be one of the following values:
2975 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2976 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2977 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2978 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2979 * @retval HAL status
2981 __weak HAL_StatusTypeDef
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_OC_InitTypeDef
* sConfig
, uint32_t Channel
)
2983 /* Check the parameters */
2984 assert_param(IS_TIM_CHANNELS(Channel
));
2985 assert_param(IS_TIM_OC_MODE(sConfig
->OCMode
));
2986 assert_param(IS_TIM_OC_POLARITY(sConfig
->OCPolarity
));
2988 /* Check input state */
2991 htim
->State
= HAL_TIM_STATE_BUSY
;
2997 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
2998 /* Configure the TIM Channel 1 in Output Compare */
2999 TIM_OC1_SetConfig(htim
->Instance
, sConfig
);
3005 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3006 /* Configure the TIM Channel 2 in Output Compare */
3007 TIM_OC2_SetConfig(htim
->Instance
, sConfig
);
3013 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
3014 /* Configure the TIM Channel 3 in Output Compare */
3015 TIM_OC3_SetConfig(htim
->Instance
, sConfig
);
3021 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
3022 /* Configure the TIM Channel 4 in Output Compare */
3023 TIM_OC4_SetConfig(htim
->Instance
, sConfig
);
3030 htim
->State
= HAL_TIM_STATE_READY
;
3038 * @brief Initializes the TIM Input Capture Channels according to the specified
3039 * parameters in the TIM_IC_InitTypeDef.
3040 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3041 * the configuration information for TIM module.
3042 * @param sConfig: TIM Input Capture configuration structure
3043 * @param Channel: TIM Channels to be enabled.
3044 * This parameter can be one of the following values:
3045 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3046 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3047 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3048 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3049 * @retval HAL status
3051 HAL_StatusTypeDef
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_IC_InitTypeDef
* sConfig
, uint32_t Channel
)
3053 /* Check the parameters */
3054 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3055 assert_param(IS_TIM_IC_POLARITY(sConfig
->ICPolarity
));
3056 assert_param(IS_TIM_IC_SELECTION(sConfig
->ICSelection
));
3057 assert_param(IS_TIM_IC_PRESCALER(sConfig
->ICPrescaler
));
3058 assert_param(IS_TIM_IC_FILTER(sConfig
->ICFilter
));
3062 htim
->State
= HAL_TIM_STATE_BUSY
;
3064 if (Channel
== TIM_CHANNEL_1
)
3066 /* TI1 Configuration */
3067 TIM_TI1_SetConfig(htim
->Instance
,
3068 sConfig
->ICPolarity
,
3069 sConfig
->ICSelection
,
3072 /* Reset the IC1PSC Bits */
3073 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC1PSC
;
3075 /* Set the IC1PSC value */
3076 htim
->Instance
->CCMR1
|= sConfig
->ICPrescaler
;
3078 else if (Channel
== TIM_CHANNEL_2
)
3080 /* TI2 Configuration */
3081 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3083 TIM_TI2_SetConfig(htim
->Instance
,
3084 sConfig
->ICPolarity
,
3085 sConfig
->ICSelection
,
3088 /* Reset the IC2PSC Bits */
3089 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC2PSC
;
3091 /* Set the IC2PSC value */
3092 htim
->Instance
->CCMR1
|= (sConfig
->ICPrescaler
<< 8);
3094 else if (Channel
== TIM_CHANNEL_3
)
3096 /* TI3 Configuration */
3097 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
3099 TIM_TI3_SetConfig(htim
->Instance
,
3100 sConfig
->ICPolarity
,
3101 sConfig
->ICSelection
,
3104 /* Reset the IC3PSC Bits */
3105 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_IC3PSC
;
3107 /* Set the IC3PSC value */
3108 htim
->Instance
->CCMR2
|= sConfig
->ICPrescaler
;
3112 /* TI4 Configuration */
3113 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
3115 TIM_TI4_SetConfig(htim
->Instance
,
3116 sConfig
->ICPolarity
,
3117 sConfig
->ICSelection
,
3120 /* Reset the IC4PSC Bits */
3121 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_IC4PSC
;
3123 /* Set the IC4PSC value */
3124 htim
->Instance
->CCMR2
|= (sConfig
->ICPrescaler
<< 8);
3127 htim
->State
= HAL_TIM_STATE_READY
;
3135 * @brief Initializes the TIM PWM channels according to the specified
3136 * parameters in the TIM_OC_InitTypeDef.
3137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3138 * the configuration information for TIM module.
3139 * @param sConfig: TIM PWM configuration structure
3140 * @param Channel: TIM Channels to be enabled.
3141 * This parameter can be one of the following values:
3142 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3143 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3144 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3145 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3146 * @retval HAL status
3148 __weak HAL_StatusTypeDef
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_OC_InitTypeDef
* sConfig
, uint32_t Channel
)
3152 /* Check the parameters */
3153 assert_param(IS_TIM_CHANNELS(Channel
));
3154 assert_param(IS_TIM_PWM_MODE(sConfig
->OCMode
));
3155 assert_param(IS_TIM_OC_POLARITY(sConfig
->OCPolarity
));
3156 assert_param(IS_TIM_FAST_STATE(sConfig
->OCFastMode
));
3158 htim
->State
= HAL_TIM_STATE_BUSY
;
3164 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3165 /* Configure the Channel 1 in PWM mode */
3166 TIM_OC1_SetConfig(htim
->Instance
, sConfig
);
3168 /* Set the Preload enable bit for channel1 */
3169 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC1PE
;
3171 /* Configure the Output Fast mode */
3172 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC1FE
;
3173 htim
->Instance
->CCMR1
|= sConfig
->OCFastMode
;
3179 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3180 /* Configure the Channel 2 in PWM mode */
3181 TIM_OC2_SetConfig(htim
->Instance
, sConfig
);
3183 /* Set the Preload enable bit for channel2 */
3184 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC2PE
;
3186 /* Configure the Output Fast mode */
3187 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC2FE
;
3188 htim
->Instance
->CCMR1
|= sConfig
->OCFastMode
<< 8;
3194 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
3195 /* Configure the Channel 3 in PWM mode */
3196 TIM_OC3_SetConfig(htim
->Instance
, sConfig
);
3198 /* Set the Preload enable bit for channel3 */
3199 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC3PE
;
3201 /* Configure the Output Fast mode */
3202 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC3FE
;
3203 htim
->Instance
->CCMR2
|= sConfig
->OCFastMode
;
3209 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
3210 /* Configure the Channel 4 in PWM mode */
3211 TIM_OC4_SetConfig(htim
->Instance
, sConfig
);
3213 /* Set the Preload enable bit for channel4 */
3214 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC4PE
;
3216 /* Configure the Output Fast mode */
3217 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC4FE
;
3218 htim
->Instance
->CCMR2
|= sConfig
->OCFastMode
<< 8;
3226 htim
->State
= HAL_TIM_STATE_READY
;
3234 * @brief Initializes the TIM One Pulse Channels according to the specified
3235 * parameters in the TIM_OnePulse_InitTypeDef.
3236 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3237 * the configuration information for TIM module.
3238 * @param sConfig: TIM One Pulse configuration structure
3239 * @param OutputChannel: TIM Channels to be enabled.
3240 * This parameter can be one of the following values:
3241 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3242 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3243 * @param InputChannel: TIM Channels to be enabled.
3244 * This parameter can be one of the following values:
3245 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3246 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3247 * @retval HAL status
3249 HAL_StatusTypeDef
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef
*htim
, TIM_OnePulse_InitTypeDef
* sConfig
, uint32_t OutputChannel
, uint32_t InputChannel
)
3251 TIM_OC_InitTypeDef temp1
;
3253 /* Check the parameters */
3254 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel
));
3255 assert_param(IS_TIM_OPM_CHANNELS(InputChannel
));
3257 if(OutputChannel
!= InputChannel
)
3261 htim
->State
= HAL_TIM_STATE_BUSY
;
3263 /* Extract the Output compare configuration from sConfig structure */
3264 temp1
.OCMode
= sConfig
->OCMode
;
3265 temp1
.Pulse
= sConfig
->Pulse
;
3266 temp1
.OCPolarity
= sConfig
->OCPolarity
;
3267 temp1
.OCNPolarity
= sConfig
->OCNPolarity
;
3268 temp1
.OCIdleState
= sConfig
->OCIdleState
;
3269 temp1
.OCNIdleState
= sConfig
->OCNIdleState
;
3271 switch (OutputChannel
)
3275 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3277 TIM_OC1_SetConfig(htim
->Instance
, &temp1
);
3282 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3284 TIM_OC2_SetConfig(htim
->Instance
, &temp1
);
3290 switch (InputChannel
)
3294 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3296 TIM_TI1_SetConfig(htim
->Instance
, sConfig
->ICPolarity
,
3297 sConfig
->ICSelection
, sConfig
->ICFilter
);
3299 /* Reset the IC1PSC Bits */
3300 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC1PSC
;
3302 /* Select the Trigger source */
3303 htim
->Instance
->SMCR
&= ~TIM_SMCR_TS
;
3304 htim
->Instance
->SMCR
|= TIM_TS_TI1FP1
;
3306 /* Select the Slave Mode */
3307 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
3308 htim
->Instance
->SMCR
|= TIM_SLAVEMODE_TRIGGER
;
3313 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3315 TIM_TI2_SetConfig(htim
->Instance
, sConfig
->ICPolarity
,
3316 sConfig
->ICSelection
, sConfig
->ICFilter
);
3318 /* Reset the IC2PSC Bits */
3319 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_IC2PSC
;
3321 /* Select the Trigger source */
3322 htim
->Instance
->SMCR
&= ~TIM_SMCR_TS
;
3323 htim
->Instance
->SMCR
|= TIM_TS_TI2FP2
;
3325 /* Select the Slave Mode */
3326 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
3327 htim
->Instance
->SMCR
|= TIM_SLAVEMODE_TRIGGER
;
3335 htim
->State
= HAL_TIM_STATE_READY
;
3348 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3350 * the configuration information for TIM module.
3351 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
3352 * This parameters can be on of the following values:
3353 * @arg TIM_DMABASE_CR1
3354 * @arg TIM_DMABASE_CR2
3355 * @arg TIM_DMABASE_SMCR
3356 * @arg TIM_DMABASE_DIER
3357 * @arg TIM_DMABASE_SR
3358 * @arg TIM_DMABASE_EGR
3359 * @arg TIM_DMABASE_CCMR1
3360 * @arg TIM_DMABASE_CCMR2
3361 * @arg TIM_DMABASE_CCER
3362 * @arg TIM_DMABASE_CNT
3363 * @arg TIM_DMABASE_PSC
3364 * @arg TIM_DMABASE_ARR
3365 * @arg TIM_DMABASE_RCR
3366 * @arg TIM_DMABASE_CCR1
3367 * @arg TIM_DMABASE_CCR2
3368 * @arg TIM_DMABASE_CCR3
3369 * @arg TIM_DMABASE_CCR4
3370 * @arg TIM_DMABASE_BDTR
3371 * @arg TIM_DMABASE_DCR
3372 * @param BurstRequestSrc: TIM DMA Request sources.
3373 * This parameters can be on of the following values:
3374 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3375 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3376 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3377 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3378 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3379 * @arg TIM_DMA_COM: TIM Commutation DMA source
3380 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3381 * @param BurstBuffer: The Buffer address.
3382 * @param BurstLength: DMA Burst length. This parameter can be one value
3383 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3384 * @retval HAL status
3386 HAL_StatusTypeDef
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef
*htim
, uint32_t BurstBaseAddress
, uint32_t BurstRequestSrc
,
3387 uint32_t* BurstBuffer
, uint32_t BurstLength
)
3389 /* Check the parameters */
3390 assert_param(IS_TIM_DMABURST_INSTANCE(htim
->Instance
));
3391 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress
));
3392 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3393 assert_param(IS_TIM_DMA_LENGTH(BurstLength
));
3395 if((htim
->State
== HAL_TIM_STATE_BUSY
))
3399 else if((htim
->State
== HAL_TIM_STATE_READY
))
3401 if((BurstBuffer
== 0 ) && (BurstLength
> 0))
3407 htim
->State
= HAL_TIM_STATE_BUSY
;
3410 switch(BurstRequestSrc
)
3412 case TIM_DMA_UPDATE
:
3414 /* Set the DMA Period elapsed callback */
3415 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferCpltCallback
= TIM_DMAPeriodElapsedCplt
;
3417 /* Set the DMA error callback */
3418 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferErrorCallback
= HAL_TIM_DMAError
;
3420 /* Enable the DMA Stream */
3421 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_UPDATE
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8) + 1);
3426 /* Set the DMA Period elapsed callback */
3427 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
3429 /* Set the DMA error callback */
3430 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= HAL_TIM_DMAError
;
3432 /* Enable the DMA Stream */
3433 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8) + 1);
3438 /* Set the DMA Period elapsed callback */
3439 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
3441 /* Set the DMA error callback */
3442 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= HAL_TIM_DMAError
;
3444 /* Enable the DMA Stream */
3445 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8) + 1);
3450 /* Set the DMA Period elapsed callback */
3451 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
3453 /* Set the DMA error callback */
3454 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= HAL_TIM_DMAError
;
3456 /* Enable the DMA Stream */
3457 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8) + 1);
3462 /* Set the DMA Period elapsed callback */
3463 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= HAL_TIM_DMADelayPulseCplt
;
3465 /* Set the DMA error callback */
3466 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= HAL_TIM_DMAError
;
3468 /* Enable the DMA Stream */
3469 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8) + 1);
3474 /* Set the DMA Period elapsed callback */
3475 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferCpltCallback
= HAL_TIMEx_DMACommutationCplt
;
3477 /* Set the DMA error callback */
3478 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferErrorCallback
= HAL_TIM_DMAError
;
3480 /* Enable the DMA Stream */
3481 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_COMMUTATION
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8) + 1);
3484 case TIM_DMA_TRIGGER
:
3486 /* Set the DMA Period elapsed callback */
3487 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferCpltCallback
= TIM_DMATriggerCplt
;
3489 /* Set the DMA error callback */
3490 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferErrorCallback
= HAL_TIM_DMAError
;
3492 /* Enable the DMA Stream */
3493 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_TRIGGER
], (uint32_t)BurstBuffer
, (uint32_t)&htim
->Instance
->DMAR
, ((BurstLength
) >> 8) + 1);
3499 /* configure the DMA Burst Mode */
3500 htim
->Instance
->DCR
= BurstBaseAddress
| BurstLength
;
3502 /* Enable the TIM DMA Request */
3503 __HAL_TIM_ENABLE_DMA(htim
, BurstRequestSrc
);
3505 htim
->State
= HAL_TIM_STATE_READY
;
3507 /* Return function status */
3512 * @brief Stops the TIM DMA Burst mode
3513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3514 * the configuration information for TIM module.
3515 * @param BurstRequestSrc: TIM DMA Request sources to disable
3516 * @retval HAL status
3518 HAL_StatusTypeDef
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef
*htim
, uint32_t BurstRequestSrc
)
3520 /* Check the parameters */
3521 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3523 /* Abort the DMA transfer (at least disable the DMA channel) */
3524 switch(BurstRequestSrc
)
3526 case TIM_DMA_UPDATE
:
3528 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_UPDATE
]);
3533 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC1
]);
3538 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC2
]);
3543 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC3
]);
3548 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC4
]);
3553 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_COMMUTATION
]);
3556 case TIM_DMA_TRIGGER
:
3558 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_TRIGGER
]);
3565 /* Disable the TIM Update DMA request */
3566 __HAL_TIM_DISABLE_DMA(htim
, BurstRequestSrc
);
3568 /* Return function status */
3573 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3574 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3575 * the configuration information for TIM module.
3576 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
3577 * This parameters can be on of the following values:
3578 * @arg TIM_DMABASE_CR1
3579 * @arg TIM_DMABASE_CR2
3580 * @arg TIM_DMABASE_SMCR
3581 * @arg TIM_DMABASE_DIER
3582 * @arg TIM_DMABASE_SR
3583 * @arg TIM_DMABASE_EGR
3584 * @arg TIM_DMABASE_CCMR1
3585 * @arg TIM_DMABASE_CCMR2
3586 * @arg TIM_DMABASE_CCER
3587 * @arg TIM_DMABASE_CNT
3588 * @arg TIM_DMABASE_PSC
3589 * @arg TIM_DMABASE_ARR
3590 * @arg TIM_DMABASE_RCR
3591 * @arg TIM_DMABASE_CCR1
3592 * @arg TIM_DMABASE_CCR2
3593 * @arg TIM_DMABASE_CCR3
3594 * @arg TIM_DMABASE_CCR4
3595 * @arg TIM_DMABASE_BDTR
3596 * @arg TIM_DMABASE_DCR
3597 * @param BurstRequestSrc: TIM DMA Request sources.
3598 * This parameters can be on of the following values:
3599 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3600 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3601 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3602 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3603 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3604 * @arg TIM_DMA_COM: TIM Commutation DMA source
3605 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3606 * @param BurstBuffer: The Buffer address.
3607 * @param BurstLength: DMA Burst length. This parameter can be one value
3608 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3609 * @retval HAL status
3611 HAL_StatusTypeDef
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef
*htim
, uint32_t BurstBaseAddress
, uint32_t BurstRequestSrc
,
3612 uint32_t *BurstBuffer
, uint32_t BurstLength
)
3614 /* Check the parameters */
3615 assert_param(IS_TIM_DMABURST_INSTANCE(htim
->Instance
));
3616 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress
));
3617 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3618 assert_param(IS_TIM_DMA_LENGTH(BurstLength
));
3620 if((htim
->State
== HAL_TIM_STATE_BUSY
))
3624 else if((htim
->State
== HAL_TIM_STATE_READY
))
3626 if((BurstBuffer
== 0 ) && (BurstLength
> 0))
3632 htim
->State
= HAL_TIM_STATE_BUSY
;
3635 switch(BurstRequestSrc
)
3637 case TIM_DMA_UPDATE
:
3639 /* Set the DMA Period elapsed callback */
3640 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferCpltCallback
= TIM_DMAPeriodElapsedCplt
;
3642 /* Set the DMA error callback */
3643 htim
->hdma
[TIM_DMA_ID_UPDATE
]->XferErrorCallback
= HAL_TIM_DMAError
;
3645 /* Enable the DMA Stream */
3646 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_UPDATE
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8) + 1);
3651 /* Set the DMA Period elapsed callback */
3652 htim
->hdma
[TIM_DMA_ID_CC1
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
3654 /* Set the DMA error callback */
3655 htim
->hdma
[TIM_DMA_ID_CC1
]->XferErrorCallback
= HAL_TIM_DMAError
;
3657 /* Enable the DMA Stream */
3658 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC1
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8) + 1);
3663 /* Set the DMA Period elapsed callback */
3664 htim
->hdma
[TIM_DMA_ID_CC2
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
3666 /* Set the DMA error callback */
3667 htim
->hdma
[TIM_DMA_ID_CC2
]->XferErrorCallback
= HAL_TIM_DMAError
;
3669 /* Enable the DMA Stream */
3670 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC2
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8) + 1);
3675 /* Set the DMA Period elapsed callback */
3676 htim
->hdma
[TIM_DMA_ID_CC3
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
3678 /* Set the DMA error callback */
3679 htim
->hdma
[TIM_DMA_ID_CC3
]->XferErrorCallback
= HAL_TIM_DMAError
;
3681 /* Enable the DMA Stream */
3682 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC3
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8) + 1);
3687 /* Set the DMA Period elapsed callback */
3688 htim
->hdma
[TIM_DMA_ID_CC4
]->XferCpltCallback
= HAL_TIM_DMACaptureCplt
;
3690 /* Set the DMA error callback */
3691 htim
->hdma
[TIM_DMA_ID_CC4
]->XferErrorCallback
= HAL_TIM_DMAError
;
3693 /* Enable the DMA Stream */
3694 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_CC4
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8) + 1);
3699 /* Set the DMA Period elapsed callback */
3700 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferCpltCallback
= HAL_TIMEx_DMACommutationCplt
;
3702 /* Set the DMA error callback */
3703 htim
->hdma
[TIM_DMA_ID_COMMUTATION
]->XferErrorCallback
= HAL_TIM_DMAError
;
3705 /* Enable the DMA Stream */
3706 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_COMMUTATION
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8) + 1);
3709 case TIM_DMA_TRIGGER
:
3711 /* Set the DMA Period elapsed callback */
3712 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferCpltCallback
= TIM_DMATriggerCplt
;
3714 /* Set the DMA error callback */
3715 htim
->hdma
[TIM_DMA_ID_TRIGGER
]->XferErrorCallback
= HAL_TIM_DMAError
;
3717 /* Enable the DMA Stream */
3718 HAL_DMA_Start_IT(htim
->hdma
[TIM_DMA_ID_TRIGGER
], (uint32_t)&htim
->Instance
->DMAR
, (uint32_t)BurstBuffer
, ((BurstLength
) >> 8) + 1);
3725 /* configure the DMA Burst Mode */
3726 htim
->Instance
->DCR
= BurstBaseAddress
| BurstLength
;
3728 /* Enable the TIM DMA Request */
3729 __HAL_TIM_ENABLE_DMA(htim
, BurstRequestSrc
);
3731 htim
->State
= HAL_TIM_STATE_READY
;
3733 /* Return function status */
3738 * @brief Stop the DMA burst reading
3739 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3740 * the configuration information for TIM module.
3741 * @param BurstRequestSrc: TIM DMA Request sources to disable.
3742 * @retval HAL status
3744 HAL_StatusTypeDef
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef
*htim
, uint32_t BurstRequestSrc
)
3746 /* Check the parameters */
3747 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc
));
3749 /* Abort the DMA transfer (at least disable the DMA channel) */
3750 switch(BurstRequestSrc
)
3752 case TIM_DMA_UPDATE
:
3754 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_UPDATE
]);
3759 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC1
]);
3764 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC2
]);
3769 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC3
]);
3774 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_CC4
]);
3779 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_COMMUTATION
]);
3782 case TIM_DMA_TRIGGER
:
3784 HAL_DMA_Abort(htim
->hdma
[TIM_DMA_ID_TRIGGER
]);
3791 /* Disable the TIM Update DMA request */
3792 __HAL_TIM_DISABLE_DMA(htim
, BurstRequestSrc
);
3794 /* Return function status */
3799 * @brief Generate a software event
3800 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3801 * the configuration information for TIM module.
3802 * @param EventSource: specifies the event source.
3803 * This parameter can be one of the following values:
3804 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
3805 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3806 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
3807 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
3808 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
3809 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
3810 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
3811 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
3812 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
3813 * @note TIM6 and TIM7 can only generate an update event.
3814 * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
3815 * @retval HAL status
3818 HAL_StatusTypeDef
HAL_TIM_GenerateEvent(TIM_HandleTypeDef
*htim
, uint32_t EventSource
)
3820 /* Check the parameters */
3821 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
3822 assert_param(IS_TIM_EVENT_SOURCE(EventSource
));
3824 /* Process Locked */
3827 /* Change the TIM state */
3828 htim
->State
= HAL_TIM_STATE_BUSY
;
3830 /* Set the event sources */
3831 htim
->Instance
->EGR
= EventSource
;
3833 /* Change the TIM state */
3834 htim
->State
= HAL_TIM_STATE_READY
;
3838 /* Return function status */
3843 * @brief Configures the OCRef clear feature
3844 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3845 * the configuration information for TIM module.
3846 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
3847 * contains the OCREF clear feature and parameters for the TIM peripheral.
3848 * @param Channel: specifies the TIM Channel.
3849 * This parameter can be one of the following values:
3850 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3851 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3852 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3853 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3854 * @retval HAL status
3856 __weak HAL_StatusTypeDef
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef
*htim
, TIM_ClearInputConfigTypeDef
* sClearInputConfig
, uint32_t Channel
)
3858 /* Check the parameters */
3859 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
3860 assert_param(IS_TIM_CHANNELS(Channel
));
3861 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig
->ClearInputSource
));
3863 /* Process Locked */
3866 htim
->State
= HAL_TIM_STATE_BUSY
;
3868 if(sClearInputConfig
->ClearInputSource
== TIM_CLEARINPUTSOURCE_ETR
)
3870 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig
->ClearInputPolarity
));
3871 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig
->ClearInputPrescaler
));
3872 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig
->ClearInputFilter
));
3874 TIM_ETR_SetConfig(htim
->Instance
,
3875 sClearInputConfig
->ClearInputPrescaler
,
3876 sClearInputConfig
->ClearInputPolarity
,
3877 sClearInputConfig
->ClearInputFilter
);
3884 if(sClearInputConfig
->ClearInputState
!= RESET
)
3886 /* Enable the Ocref clear feature for Channel 1 */
3887 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC1CE
;
3891 /* Disable the Ocref clear feature for Channel 1 */
3892 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC1CE
;
3898 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
3899 if(sClearInputConfig
->ClearInputState
!= RESET
)
3901 /* Enable the Ocref clear feature for Channel 2 */
3902 htim
->Instance
->CCMR1
|= TIM_CCMR1_OC2CE
;
3906 /* Disable the Ocref clear feature for Channel 2 */
3907 htim
->Instance
->CCMR1
&= ~TIM_CCMR1_OC2CE
;
3913 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
3914 if(sClearInputConfig
->ClearInputState
!= RESET
)
3916 /* Enable the Ocref clear feature for Channel 3 */
3917 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC3CE
;
3921 /* Disable the Ocref clear feature for Channel 3 */
3922 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC3CE
;
3928 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
3929 if(sClearInputConfig
->ClearInputState
!= RESET
)
3931 /* Enable the Ocref clear feature for Channel 4 */
3932 htim
->Instance
->CCMR2
|= TIM_CCMR2_OC4CE
;
3936 /* Disable the Ocref clear feature for Channel 4 */
3937 htim
->Instance
->CCMR2
&= ~TIM_CCMR2_OC4CE
;
3945 htim
->State
= HAL_TIM_STATE_READY
;
3953 * @brief Configures the clock source to be used
3954 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3955 * the configuration information for TIM module.
3956 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
3957 * contains the clock source information for the TIM peripheral.
3958 * @retval HAL status
3960 HAL_StatusTypeDef
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef
*htim
, TIM_ClockConfigTypeDef
* sClockSourceConfig
)
3962 uint32_t tmpsmcr
= 0;
3964 /* Process Locked */
3967 htim
->State
= HAL_TIM_STATE_BUSY
;
3969 /* Check the parameters */
3970 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig
->ClockSource
));
3972 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3973 tmpsmcr
= htim
->Instance
->SMCR
;
3974 tmpsmcr
&= ~(TIM_SMCR_SMS
| TIM_SMCR_TS
);
3975 tmpsmcr
&= ~(TIM_SMCR_ETF
| TIM_SMCR_ETPS
| TIM_SMCR_ECE
| TIM_SMCR_ETP
);
3976 htim
->Instance
->SMCR
= tmpsmcr
;
3978 switch (sClockSourceConfig
->ClockSource
)
3980 case TIM_CLOCKSOURCE_INTERNAL
:
3982 assert_param(IS_TIM_INSTANCE(htim
->Instance
));
3983 /* Disable slave mode to clock the prescaler directly with the internal clock */
3984 htim
->Instance
->SMCR
&= ~TIM_SMCR_SMS
;
3988 case TIM_CLOCKSOURCE_ETRMODE1
:
3990 assert_param(IS_TIM_ETR_INSTANCE(htim
->Instance
));
3991 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
3992 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig
->ClockPrescaler
));
3993 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
3994 /* Configure the ETR Clock source */
3995 TIM_ETR_SetConfig(htim
->Instance
,
3996 sClockSourceConfig
->ClockPrescaler
,
3997 sClockSourceConfig
->ClockPolarity
,
3998 sClockSourceConfig
->ClockFilter
);
3999 /* Get the TIMx SMCR register value */
4000 tmpsmcr
= htim
->Instance
->SMCR
;
4001 /* Reset the SMS and TS Bits */
4002 tmpsmcr
&= ~(TIM_SMCR_SMS
| TIM_SMCR_TS
);
4003 /* Select the External clock mode1 and the ETRF trigger */
4004 tmpsmcr
|= (TIM_SLAVEMODE_EXTERNAL1
| TIM_CLOCKSOURCE_ETRMODE1
);
4005 /* Write to TIMx SMCR */
4006 htim
->Instance
->SMCR
= tmpsmcr
;
4010 case TIM_CLOCKSOURCE_ETRMODE2
:
4012 assert_param(IS_TIM_ETR_INSTANCE(htim
->Instance
));
4013 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
4014 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig
->ClockPrescaler
));
4015 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
4017 /* Configure the ETR Clock source */
4018 TIM_ETR_SetConfig(htim
->Instance
,
4019 sClockSourceConfig
->ClockPrescaler
,
4020 sClockSourceConfig
->ClockPolarity
,
4021 sClockSourceConfig
->ClockFilter
);
4022 /* Enable the External clock mode2 */
4023 htim
->Instance
->SMCR
|= TIM_SMCR_ECE
;
4027 case TIM_CLOCKSOURCE_TI1
:
4029 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim
->Instance
));
4031 /* Check TI1 input conditioning related parameters */
4032 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
4033 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
4035 TIM_TI1_ConfigInputStage(htim
->Instance
,
4036 sClockSourceConfig
->ClockPolarity
,
4037 sClockSourceConfig
->ClockFilter
);
4038 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_TI1
);
4041 case TIM_CLOCKSOURCE_TI2
:
4043 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim
->Instance
));
4045 /* Check TI1 input conditioning related parameters */
4046 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
4047 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
4049 TIM_TI2_ConfigInputStage(htim
->Instance
,
4050 sClockSourceConfig
->ClockPolarity
,
4051 sClockSourceConfig
->ClockFilter
);
4052 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_TI2
);
4055 case TIM_CLOCKSOURCE_TI1ED
:
4057 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim
->Instance
));
4058 /* Check TI1 input conditioning related parameters */
4059 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig
->ClockPolarity
));
4060 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig
->ClockFilter
));
4062 TIM_TI1_ConfigInputStage(htim
->Instance
,
4063 sClockSourceConfig
->ClockPolarity
,
4064 sClockSourceConfig
->ClockFilter
);
4065 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_TI1ED
);
4068 case TIM_CLOCKSOURCE_ITR0
:
4070 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4071 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR0
);
4074 case TIM_CLOCKSOURCE_ITR1
:
4076 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4077 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR1
);
4080 case TIM_CLOCKSOURCE_ITR2
:
4082 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4083 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR2
);
4086 case TIM_CLOCKSOURCE_ITR3
:
4088 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim
->Instance
));
4089 TIM_ITRx_SetConfig(htim
->Instance
, TIM_CLOCKSOURCE_ITR3
);
4096 htim
->State
= HAL_TIM_STATE_READY
;
4104 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4105 * or a XOR combination between CH1_input, CH2_input & CH3_input
4106 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4107 * the configuration information for TIM module.
4108 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
4109 * output of a XOR gate.
4110 * This parameter can be one of the following values:
4111 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4112 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4113 * pins are connected to the TI1 input (XOR combination)
4114 * @retval HAL status
4116 HAL_StatusTypeDef
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef
*htim
, uint32_t TI1_Selection
)
4118 uint32_t tmpcr2
= 0;
4120 /* Check the parameters */
4121 assert_param(IS_TIM_XOR_INSTANCE(htim
->Instance
));
4122 assert_param(IS_TIM_TI1SELECTION(TI1_Selection
));
4124 /* Get the TIMx CR2 register value */
4125 tmpcr2
= htim
->Instance
->CR2
;
4127 /* Reset the TI1 selection */
4128 tmpcr2
&= ~TIM_CR2_TI1S
;
4130 /* Set the TI1 selection */
4131 tmpcr2
|= TI1_Selection
;
4133 /* Write to TIMxCR2 */
4134 htim
->Instance
->CR2
= tmpcr2
;
4140 * @brief Configures the TIM in Slave mode
4141 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4142 * the configuration information for TIM module.
4143 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4144 * contains the selected trigger (internal trigger input, filtered
4145 * timer input or external trigger input) and the ) and the Slave
4146 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4147 * @retval HAL status
4149 HAL_StatusTypeDef
HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef
*htim
, TIM_SlaveConfigTypeDef
* sSlaveConfig
)
4151 uint32_t tmpsmcr
= 0;
4152 uint32_t tmpccmr1
= 0;
4153 uint32_t tmpccer
= 0;
4155 /* Check the parameters */
4156 assert_param(IS_TIM_SLAVE_INSTANCE(htim
->Instance
));
4157 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig
->SlaveMode
));
4158 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig
->InputTrigger
));
4162 htim
->State
= HAL_TIM_STATE_BUSY
;
4164 /* Get the TIMx SMCR register value */
4165 tmpsmcr
= htim
->Instance
->SMCR
;
4167 /* Reset the Trigger Selection Bits */
4168 tmpsmcr
&= ~TIM_SMCR_TS
;
4169 /* Set the Input Trigger source */
4170 tmpsmcr
|= sSlaveConfig
->InputTrigger
;
4172 /* Reset the slave mode Bits */
4173 tmpsmcr
&= ~TIM_SMCR_SMS
;
4174 /* Set the slave mode */
4175 tmpsmcr
|= sSlaveConfig
->SlaveMode
;
4177 /* Write to TIMx SMCR */
4178 htim
->Instance
->SMCR
= tmpsmcr
;
4180 /* Configure the trigger prescaler, filter, and polarity */
4181 switch (sSlaveConfig
->InputTrigger
)
4185 /* Check the parameters */
4186 assert_param(IS_TIM_ETR_INSTANCE(htim
->Instance
));
4187 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig
->TriggerPrescaler
));
4188 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
4189 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4190 /* Configure the ETR Trigger source */
4191 TIM_ETR_SetConfig(htim
->Instance
,
4192 sSlaveConfig
->TriggerPrescaler
,
4193 sSlaveConfig
->TriggerPolarity
,
4194 sSlaveConfig
->TriggerFilter
);
4198 case TIM_TS_TI1F_ED
:
4200 /* Check the parameters */
4201 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
4202 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4204 /* Disable the Channel 1: Reset the CC1E Bit */
4205 tmpccer
= htim
->Instance
->CCER
;
4206 htim
->Instance
->CCER
&= ~TIM_CCER_CC1E
;
4207 tmpccmr1
= htim
->Instance
->CCMR1
;
4209 /* Set the filter */
4210 tmpccmr1
&= ~TIM_CCMR1_IC1F
;
4211 tmpccmr1
|= ((sSlaveConfig
->TriggerFilter
) << 4);
4213 /* Write to TIMx CCMR1 and CCER registers */
4214 htim
->Instance
->CCMR1
= tmpccmr1
;
4215 htim
->Instance
->CCER
= tmpccer
;
4222 /* Check the parameters */
4223 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
4224 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
4225 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4227 /* Configure TI1 Filter and Polarity */
4228 TIM_TI1_ConfigInputStage(htim
->Instance
,
4229 sSlaveConfig
->TriggerPolarity
,
4230 sSlaveConfig
->TriggerFilter
);
4236 /* Check the parameters */
4237 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4238 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
4239 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
4241 /* Configure TI2 Filter and Polarity */
4242 TIM_TI2_ConfigInputStage(htim
->Instance
,
4243 sSlaveConfig
->TriggerPolarity
,
4244 sSlaveConfig
->TriggerFilter
);
4250 /* Check the parameter */
4251 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4257 /* Check the parameter */
4258 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4264 /* Check the parameter */
4265 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4271 /* Check the parameter */
4272 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4280 htim
->State
= HAL_TIM_STATE_READY
;
4288 * @brief Configures the TIM in Slave mode in interrupt mode
4289 * @param htim: TIM handle.
4290 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4291 * contains the selected trigger (internal trigger input, filtered
4292 * timer input or external trigger input) and the ) and the Slave
4293 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4294 * @retval HAL status
4296 HAL_StatusTypeDef
HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef
*htim
,
4297 TIM_SlaveConfigTypeDef
* sSlaveConfig
)
4299 /* Check the parameters */
4300 assert_param(IS_TIM_SLAVE_INSTANCE(htim
->Instance
));
4301 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig
->SlaveMode
));
4302 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig
->InputTrigger
));
4306 htim
->State
= HAL_TIM_STATE_BUSY
;
4308 TIM_SlaveTimer_SetConfig(htim
, sSlaveConfig
);
4310 /* Enable Trigger Interrupt */
4311 __HAL_TIM_ENABLE_IT(htim
, TIM_IT_TRIGGER
);
4313 /* Disable Trigger DMA request */
4314 __HAL_TIM_DISABLE_DMA(htim
, TIM_DMA_TRIGGER
);
4316 htim
->State
= HAL_TIM_STATE_READY
;
4324 * @brief Read the captured value from Capture Compare unit
4325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4326 * the configuration information for TIM module.
4327 * @param Channel: TIM Channels to be enabled.
4328 * This parameter can be one of the following values:
4329 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4330 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4331 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4332 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4333 * @retval Captured value
4335 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef
*htim
, uint32_t Channel
)
4337 uint32_t tmpreg
= 0;
4345 /* Check the parameters */
4346 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
4348 /* Return the capture 1 value */
4349 tmpreg
= htim
->Instance
->CCR1
;
4355 /* Check the parameters */
4356 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
4358 /* Return the capture 2 value */
4359 tmpreg
= htim
->Instance
->CCR2
;
4366 /* Check the parameters */
4367 assert_param(IS_TIM_CC3_INSTANCE(htim
->Instance
));
4369 /* Return the capture 3 value */
4370 tmpreg
= htim
->Instance
->CCR3
;
4377 /* Check the parameters */
4378 assert_param(IS_TIM_CC4_INSTANCE(htim
->Instance
));
4380 /* Return the capture 4 value */
4381 tmpreg
= htim
->Instance
->CCR4
;
4398 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4399 * @brief TIM Callbacks functions
4402 ==============================================================================
4403 ##### TIM Callbacks functions #####
4404 ==============================================================================
4406 This section provides TIM callback functions:
4407 (+) Timer Period elapsed callback
4408 (+) Timer Output Compare callback
4409 (+) Timer Input capture callback
4410 (+) Timer Trigger callback
4411 (+) Timer Error callback
4418 * @brief Period elapsed callback in non blocking mode
4419 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4420 * the configuration information for TIM module.
4423 __weak
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef
*htim
)
4425 /* Prevent unused argument(s) compilation warning */
4428 /* NOTE : This function Should not be modified, when the callback is needed,
4429 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4434 * @brief Output Compare callback in non blocking mode
4435 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4436 * the configuration information for TIM module.
4439 __weak
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef
*htim
)
4441 /* Prevent unused argument(s) compilation warning */
4444 /* NOTE : This function Should not be modified, when the callback is needed,
4445 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4449 * @brief Input Capture callback in non blocking mode
4450 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4451 * the configuration information for TIM module.
4454 __weak
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef
*htim
)
4456 /* Prevent unused argument(s) compilation warning */
4459 /* NOTE : This function Should not be modified, when the callback is needed,
4460 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4465 * @brief PWM Pulse finished callback in non blocking mode
4466 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4467 * the configuration information for TIM module.
4470 __weak
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef
*htim
)
4472 /* Prevent unused argument(s) compilation warning */
4475 /* NOTE : This function Should not be modified, when the callback is needed,
4476 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4481 * @brief Hall Trigger detection callback in non blocking mode
4482 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4483 * the configuration information for TIM module.
4486 __weak
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef
*htim
)
4488 /* Prevent unused argument(s) compilation warning */
4491 /* NOTE : This function Should not be modified, when the callback is needed,
4492 the HAL_TIM_TriggerCallback could be implemented in the user file
4497 * @brief Timer error callback in non blocking mode
4498 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4499 * the configuration information for TIM module.
4502 __weak
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef
*htim
)
4504 /* Prevent unused argument(s) compilation warning */
4507 /* NOTE : This function Should not be modified, when the callback is needed,
4508 the HAL_TIM_ErrorCallback could be implemented in the user file
4516 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4517 * @brief Peripheral State functions
4520 ==============================================================================
4521 ##### Peripheral State functions #####
4522 ==============================================================================
4524 This subsection permits to get in run-time the status of the peripheral
4532 * @brief Return the TIM Base state
4533 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4534 * the configuration information for TIM module.
4537 HAL_TIM_StateTypeDef
HAL_TIM_Base_GetState(TIM_HandleTypeDef
*htim
)
4543 * @brief Return the TIM OC state
4544 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4545 * the configuration information for TIM module.
4548 HAL_TIM_StateTypeDef
HAL_TIM_OC_GetState(TIM_HandleTypeDef
*htim
)
4554 * @brief Return the TIM PWM state
4555 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4556 * the configuration information for TIM module.
4559 HAL_TIM_StateTypeDef
HAL_TIM_PWM_GetState(TIM_HandleTypeDef
*htim
)
4565 * @brief Return the TIM Input Capture state
4566 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4567 * the configuration information for TIM module.
4570 HAL_TIM_StateTypeDef
HAL_TIM_IC_GetState(TIM_HandleTypeDef
*htim
)
4576 * @brief Return the TIM One Pulse Mode state
4577 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4578 * the configuration information for TIM module.
4581 HAL_TIM_StateTypeDef
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef
*htim
)
4587 * @brief Return the TIM Encoder Mode state
4588 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4589 * the configuration information for TIM module.
4592 HAL_TIM_StateTypeDef
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef
*htim
)
4602 * @brief TIM DMA error callback
4603 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4604 * the configuration information for the specified DMA module.
4607 void HAL_TIM_DMAError(DMA_HandleTypeDef
*hdma
)
4609 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4611 htim
->State
= HAL_TIM_STATE_READY
;
4613 HAL_TIM_ErrorCallback(htim
);
4617 * @brief TIM DMA Delay Pulse complete callback.
4618 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4619 * the configuration information for the specified DMA module.
4622 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef
*hdma
)
4624 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4626 htim
->State
= HAL_TIM_STATE_READY
;
4628 if (hdma
== htim
->hdma
[TIM_DMA_ID_CC1
])
4630 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_1
;
4632 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC2
])
4634 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_2
;
4636 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC3
])
4638 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_3
;
4640 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC4
])
4642 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_4
;
4645 HAL_TIM_PWM_PulseFinishedCallback(htim
);
4647 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
4650 * @brief TIM DMA Capture complete callback.
4651 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4652 * the configuration information for the specified DMA module.
4655 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef
*hdma
)
4657 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4659 htim
->State
= HAL_TIM_STATE_READY
;
4661 if (hdma
== htim
->hdma
[TIM_DMA_ID_CC1
])
4663 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_1
;
4665 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC2
])
4667 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_2
;
4669 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC3
])
4671 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_3
;
4673 else if (hdma
== htim
->hdma
[TIM_DMA_ID_CC4
])
4675 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_4
;
4678 HAL_TIM_IC_CaptureCallback(htim
);
4680 htim
->Channel
= HAL_TIM_ACTIVE_CHANNEL_CLEARED
;
4685 * @brief TIM DMA Period Elapse complete callback.
4686 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4687 * the configuration information for the specified DMA module.
4690 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef
*hdma
)
4692 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4694 htim
->State
= HAL_TIM_STATE_READY
;
4696 HAL_TIM_PeriodElapsedCallback(htim
);
4700 * @brief TIM DMA Trigger callback.
4701 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4702 * the configuration information for the specified DMA module.
4705 static void TIM_DMATriggerCplt(DMA_HandleTypeDef
*hdma
)
4707 TIM_HandleTypeDef
* htim
= ( TIM_HandleTypeDef
* )((DMA_HandleTypeDef
* )hdma
)->Parent
;
4709 htim
->State
= HAL_TIM_STATE_READY
;
4711 HAL_TIM_TriggerCallback(htim
);
4715 * @brief Time Base configuration
4716 * @param TIMx: TIM peripheral
4717 * @param Structure: pointer on TIM Time Base required parameters
4720 void TIM_Base_SetConfig(TIM_TypeDef
*TIMx
, TIM_Base_InitTypeDef
*Structure
)
4722 uint32_t tmpcr1
= 0;
4725 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4726 if(IS_TIM_CC3_INSTANCE(TIMx
) != RESET
)
4728 /* Select the Counter Mode */
4729 tmpcr1
&= ~(TIM_CR1_DIR
| TIM_CR1_CMS
);
4730 tmpcr1
|= Structure
->CounterMode
;
4733 if(IS_TIM_CC1_INSTANCE(TIMx
) != RESET
)
4735 /* Set the clock division */
4736 tmpcr1
&= ~TIM_CR1_CKD
;
4737 tmpcr1
|= (uint32_t)Structure
->ClockDivision
;
4742 /* Set the Auto-reload value */
4743 TIMx
->ARR
= (uint32_t)Structure
->Period
;
4745 /* Set the Prescaler value */
4746 TIMx
->PSC
= (uint32_t)Structure
->Prescaler
;
4748 if(IS_TIM_ADVANCED_INSTANCE(TIMx
) != RESET
)
4750 /* Set the Repetition Counter value */
4751 TIMx
->RCR
= Structure
->RepetitionCounter
;
4754 /* Generate an update event to reload the Prescaler
4755 and the repetition counter(only for TIM1 and TIM8) value immediately */
4756 TIMx
->EGR
= TIM_EGR_UG
;
4760 * @brief Time Output Compare 1 configuration
4761 * @param TIMx to select the TIM peripheral
4762 * @param OC_Config: The output configuration structure
4765 void TIM_OC1_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4767 uint32_t tmpccmrx
= 0;
4768 uint32_t tmpccer
= 0;
4769 uint32_t tmpcr2
= 0;
4771 /* Disable the Channel 1: Reset the CC1E Bit */
4772 TIMx
->CCER
&= ~TIM_CCER_CC1E
;
4774 /* Get the TIMx CCER register value */
4775 tmpccer
= TIMx
->CCER
;
4776 /* Get the TIMx CR2 register value */
4779 /* Get the TIMx CCMR1 register value */
4780 tmpccmrx
= TIMx
->CCMR1
;
4782 /* Reset the Output Compare Mode Bits */
4783 tmpccmrx
&= ~TIM_CCMR1_OC1M
;
4784 tmpccmrx
&= ~TIM_CCMR1_CC1S
;
4785 /* Select the Output Compare Mode */
4786 tmpccmrx
|= OC_Config
->OCMode
;
4788 /* Reset the Output Polarity level */
4789 tmpccer
&= ~TIM_CCER_CC1P
;
4790 /* Set the Output Compare Polarity */
4791 tmpccer
|= OC_Config
->OCPolarity
;
4794 if(IS_TIM_ADVANCED_INSTANCE(TIMx
) != RESET
)
4796 /* Reset the Output N Polarity level */
4797 tmpccer
&= ~TIM_CCER_CC1NP
;
4798 /* Set the Output N Polarity */
4799 tmpccer
|= OC_Config
->OCNPolarity
;
4800 /* Reset the Output N State */
4801 tmpccer
&= ~TIM_CCER_CC1NE
;
4803 /* Reset the Output Compare and Output Compare N IDLE State */
4804 tmpcr2
&= ~TIM_CR2_OIS1
;
4805 tmpcr2
&= ~TIM_CR2_OIS1N
;
4806 /* Set the Output Idle state */
4807 tmpcr2
|= OC_Config
->OCIdleState
;
4808 /* Set the Output N Idle state */
4809 tmpcr2
|= OC_Config
->OCNIdleState
;
4811 /* Write to TIMx CR2 */
4814 /* Write to TIMx CCMR1 */
4815 TIMx
->CCMR1
= tmpccmrx
;
4817 /* Set the Capture Compare Register value */
4818 TIMx
->CCR1
= OC_Config
->Pulse
;
4820 /* Write to TIMx CCER */
4821 TIMx
->CCER
= tmpccer
;
4825 * @brief Time Output Compare 2 configuration
4826 * @param TIMx to select the TIM peripheral
4827 * @param OC_Config: The output configuration structure
4830 void TIM_OC2_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4832 uint32_t tmpccmrx
= 0;
4833 uint32_t tmpccer
= 0;
4834 uint32_t tmpcr2
= 0;
4836 /* Disable the Channel 2: Reset the CC2E Bit */
4837 TIMx
->CCER
&= ~TIM_CCER_CC2E
;
4839 /* Get the TIMx CCER register value */
4840 tmpccer
= TIMx
->CCER
;
4841 /* Get the TIMx CR2 register value */
4844 /* Get the TIMx CCMR1 register value */
4845 tmpccmrx
= TIMx
->CCMR1
;
4847 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4848 tmpccmrx
&= ~TIM_CCMR1_OC2M
;
4849 tmpccmrx
&= ~TIM_CCMR1_CC2S
;
4851 /* Select the Output Compare Mode */
4852 tmpccmrx
|= (OC_Config
->OCMode
<< 8);
4854 /* Reset the Output Polarity level */
4855 tmpccer
&= ~TIM_CCER_CC2P
;
4856 /* Set the Output Compare Polarity */
4857 tmpccer
|= (OC_Config
->OCPolarity
<< 4);
4859 if(IS_TIM_ADVANCED_INSTANCE(TIMx
) != RESET
)
4861 assert_param(IS_TIM_OCN_POLARITY(OC_Config
->OCNPolarity
));
4863 /* Reset the Output N Polarity level */
4864 tmpccer
&= ~TIM_CCER_CC2NP
;
4865 /* Set the Output N Polarity */
4866 tmpccer
|= (OC_Config
->OCNPolarity
<< 4);
4867 /* Reset the Output N State */
4868 tmpccer
&= ~TIM_CCER_CC2NE
;
4870 /* Reset the Output Compare and Output Compare N IDLE State */
4871 tmpcr2
&= ~TIM_CR2_OIS2
;
4872 tmpcr2
&= ~TIM_CR2_OIS2N
;
4873 /* Set the Output Idle state */
4874 tmpcr2
|= (OC_Config
->OCIdleState
<< 2);
4875 /* Set the Output N Idle state */
4876 tmpcr2
|= (OC_Config
->OCNIdleState
<< 2);
4878 /* Write to TIMx CR2 */
4881 /* Write to TIMx CCMR1 */
4882 TIMx
->CCMR1
= tmpccmrx
;
4884 /* Set the Capture Compare Register value */
4885 TIMx
->CCR2
= OC_Config
->Pulse
;
4887 /* Write to TIMx CCER */
4888 TIMx
->CCER
= tmpccer
;
4892 * @brief Time Output Compare 3 configuration
4893 * @param TIMx to select the TIM peripheral
4894 * @param OC_Config: The output configuration structure
4897 void TIM_OC3_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4899 uint32_t tmpccmrx
= 0;
4900 uint32_t tmpccer
= 0;
4901 uint32_t tmpcr2
= 0;
4903 /* Disable the Channel 3: Reset the CC2E Bit */
4904 TIMx
->CCER
&= ~TIM_CCER_CC3E
;
4906 /* Get the TIMx CCER register value */
4907 tmpccer
= TIMx
->CCER
;
4908 /* Get the TIMx CR2 register value */
4911 /* Get the TIMx CCMR2 register value */
4912 tmpccmrx
= TIMx
->CCMR2
;
4914 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4915 tmpccmrx
&= ~TIM_CCMR2_OC3M
;
4916 tmpccmrx
&= ~TIM_CCMR2_CC3S
;
4917 /* Select the Output Compare Mode */
4918 tmpccmrx
|= OC_Config
->OCMode
;
4920 /* Reset the Output Polarity level */
4921 tmpccer
&= ~TIM_CCER_CC3P
;
4922 /* Set the Output Compare Polarity */
4923 tmpccer
|= (OC_Config
->OCPolarity
<< 8);
4925 if(IS_TIM_ADVANCED_INSTANCE(TIMx
) != RESET
)
4927 assert_param(IS_TIM_OCN_POLARITY(OC_Config
->OCNPolarity
));
4929 /* Reset the Output N Polarity level */
4930 tmpccer
&= ~TIM_CCER_CC3NP
;
4931 /* Set the Output N Polarity */
4932 tmpccer
|= (OC_Config
->OCNPolarity
<< 8);
4933 /* Reset the Output N State */
4934 tmpccer
&= ~TIM_CCER_CC3NE
;
4936 /* Reset the Output Compare and Output Compare N IDLE State */
4937 tmpcr2
&= ~TIM_CR2_OIS3
;
4938 tmpcr2
&= ~TIM_CR2_OIS3N
;
4939 /* Set the Output Idle state */
4940 tmpcr2
|= (OC_Config
->OCIdleState
<< 4);
4941 /* Set the Output N Idle state */
4942 tmpcr2
|= (OC_Config
->OCNIdleState
<< 4);
4944 /* Write to TIMx CR2 */
4947 /* Write to TIMx CCMR2 */
4948 TIMx
->CCMR2
= tmpccmrx
;
4950 /* Set the Capture Compare Register value */
4951 TIMx
->CCR3
= OC_Config
->Pulse
;
4953 /* Write to TIMx CCER */
4954 TIMx
->CCER
= tmpccer
;
4958 * @brief Time Output Compare 4 configuration
4959 * @param TIMx to select the TIM peripheral
4960 * @param OC_Config: The output configuration structure
4963 void TIM_OC4_SetConfig(TIM_TypeDef
*TIMx
, TIM_OC_InitTypeDef
*OC_Config
)
4965 uint32_t tmpccmrx
= 0;
4966 uint32_t tmpccer
= 0;
4967 uint32_t tmpcr2
= 0;
4969 /* Disable the Channel 4: Reset the CC4E Bit */
4970 TIMx
->CCER
&= ~TIM_CCER_CC4E
;
4972 /* Get the TIMx CCER register value */
4973 tmpccer
= TIMx
->CCER
;
4974 /* Get the TIMx CR2 register value */
4977 /* Get the TIMx CCMR2 register value */
4978 tmpccmrx
= TIMx
->CCMR2
;
4980 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4981 tmpccmrx
&= ~TIM_CCMR2_OC4M
;
4982 tmpccmrx
&= ~TIM_CCMR2_CC4S
;
4984 /* Select the Output Compare Mode */
4985 tmpccmrx
|= (OC_Config
->OCMode
<< 8);
4987 /* Reset the Output Polarity level */
4988 tmpccer
&= ~TIM_CCER_CC4P
;
4989 /* Set the Output Compare Polarity */
4990 tmpccer
|= (OC_Config
->OCPolarity
<< 12);
4992 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
4993 if(IS_TIM_ADVANCED_INSTANCE(TIMx
) != RESET
)
4995 assert_param(IS_TIM_OCIDLE_STATE(OC_Config
->OCIdleState
));
4996 /* Reset the Output Compare IDLE State */
4997 tmpcr2
&= ~TIM_CR2_OIS4
;
4998 /* Set the Output Idle state */
4999 tmpcr2
|= (OC_Config
->OCIdleState
<< 6);
5001 /* Write to TIMx CR2 */
5004 /* Write to TIMx CCMR2 */
5005 TIMx
->CCMR2
= tmpccmrx
;
5007 /* Set the Capture Compare Register value */
5008 TIMx
->CCR4
= OC_Config
->Pulse
;
5010 /* Write to TIMx CCER */
5011 TIMx
->CCER
= tmpccer
;
5015 * @brief Time Output Compare 4 configuration
5016 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
5017 * the configuration information for TIM module.
5018 * @param sSlaveConfig: The slave configuration structure
5021 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef
*htim
,
5022 TIM_SlaveConfigTypeDef
* sSlaveConfig
)
5024 uint32_t tmpsmcr
= 0;
5025 uint32_t tmpccmr1
= 0;
5026 uint32_t tmpccer
= 0;
5028 /* Get the TIMx SMCR register value */
5029 tmpsmcr
= htim
->Instance
->SMCR
;
5031 /* Reset the Trigger Selection Bits */
5032 tmpsmcr
&= ~TIM_SMCR_TS
;
5033 /* Set the Input Trigger source */
5034 tmpsmcr
|= sSlaveConfig
->InputTrigger
;
5036 /* Reset the slave mode Bits */
5037 tmpsmcr
&= ~TIM_SMCR_SMS
;
5038 /* Set the slave mode */
5039 tmpsmcr
|= sSlaveConfig
->SlaveMode
;
5041 /* Write to TIMx SMCR */
5042 htim
->Instance
->SMCR
= tmpsmcr
;
5044 /* Configure the trigger prescaler, filter, and polarity */
5045 switch (sSlaveConfig
->InputTrigger
)
5049 /* Check the parameters */
5050 assert_param(IS_TIM_ETR_INSTANCE(htim
->Instance
));
5051 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig
->TriggerPrescaler
));
5052 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
5053 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
5054 /* Configure the ETR Trigger source */
5055 TIM_ETR_SetConfig(htim
->Instance
,
5056 sSlaveConfig
->TriggerPrescaler
,
5057 sSlaveConfig
->TriggerPolarity
,
5058 sSlaveConfig
->TriggerFilter
);
5062 case TIM_TS_TI1F_ED
:
5064 /* Check the parameters */
5065 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
5066 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
5067 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
5069 /* Disable the Channel 1: Reset the CC1E Bit */
5070 tmpccer
= htim
->Instance
->CCER
;
5071 htim
->Instance
->CCER
&= ~TIM_CCER_CC1E
;
5072 tmpccmr1
= htim
->Instance
->CCMR1
;
5074 /* Set the filter */
5075 tmpccmr1
&= ~TIM_CCMR1_IC1F
;
5076 tmpccmr1
|= ((sSlaveConfig
->TriggerFilter
) << 4);
5078 /* Write to TIMx CCMR1 and CCER registers */
5079 htim
->Instance
->CCMR1
= tmpccmr1
;
5080 htim
->Instance
->CCER
= tmpccer
;
5087 /* Check the parameters */
5088 assert_param(IS_TIM_CC1_INSTANCE(htim
->Instance
));
5089 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
5090 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
5092 /* Configure TI1 Filter and Polarity */
5093 TIM_TI1_ConfigInputStage(htim
->Instance
,
5094 sSlaveConfig
->TriggerPolarity
,
5095 sSlaveConfig
->TriggerFilter
);
5101 /* Check the parameters */
5102 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5103 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig
->TriggerPolarity
));
5104 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig
->TriggerFilter
));
5106 /* Configure TI2 Filter and Polarity */
5107 TIM_TI2_ConfigInputStage(htim
->Instance
,
5108 sSlaveConfig
->TriggerPolarity
,
5109 sSlaveConfig
->TriggerFilter
);
5115 /* Check the parameter */
5116 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5122 /* Check the parameter */
5123 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5129 /* Check the parameter */
5130 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5136 /* Check the parameter */
5137 assert_param(IS_TIM_CC2_INSTANCE(htim
->Instance
));
5147 * @brief Configure the TI1 as Input.
5148 * @param TIMx to select the TIM peripheral.
5149 * @param TIM_ICPolarity : The Input Polarity.
5150 * This parameter can be one of the following values:
5151 * @arg TIM_ICPolarity_Rising
5152 * @arg TIM_ICPolarity_Falling
5153 * @arg TIM_ICPolarity_BothEdge
5154 * @param TIM_ICSelection: specifies the input to be used.
5155 * This parameter can be one of the following values:
5156 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
5157 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
5158 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
5159 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5160 * This parameter must be a value between 0x00 and 0x0F.
5162 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
5163 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
5164 * protected against un-initialized filter and polarity values.
5166 void TIM_TI1_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5167 uint32_t TIM_ICFilter
)
5169 uint32_t tmpccmr1
= 0;
5170 uint32_t tmpccer
= 0;
5172 /* Disable the Channel 1: Reset the CC1E Bit */
5173 TIMx
->CCER
&= ~TIM_CCER_CC1E
;
5174 tmpccmr1
= TIMx
->CCMR1
;
5175 tmpccer
= TIMx
->CCER
;
5177 /* Select the Input */
5178 if(IS_TIM_CC2_INSTANCE(TIMx
) != RESET
)
5180 tmpccmr1
&= ~TIM_CCMR1_CC1S
;
5181 tmpccmr1
|= TIM_ICSelection
;
5185 tmpccmr1
|= TIM_CCMR1_CC1S_0
;
5188 /* Set the filter */
5189 tmpccmr1
&= ~TIM_CCMR1_IC1F
;
5190 tmpccmr1
|= ((TIM_ICFilter
<< 4) & TIM_CCMR1_IC1F
);
5192 /* Select the Polarity and set the CC1E Bit */
5193 tmpccer
&= ~(TIM_CCER_CC1P
| TIM_CCER_CC1NP
);
5194 tmpccer
|= (TIM_ICPolarity
& (TIM_CCER_CC1P
| TIM_CCER_CC1NP
));
5196 /* Write to TIMx CCMR1 and CCER registers */
5197 TIMx
->CCMR1
= tmpccmr1
;
5198 TIMx
->CCER
= tmpccer
;
5202 * @brief Configure the Polarity and Filter for TI1.
5203 * @param TIMx to select the TIM peripheral.
5204 * @param TIM_ICPolarity : The Input Polarity.
5205 * This parameter can be one of the following values:
5206 * @arg TIM_ICPolarity_Rising
5207 * @arg TIM_ICPolarity_Falling
5208 * @arg TIM_ICPolarity_BothEdge
5209 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5210 * This parameter must be a value between 0x00 and 0x0F.
5213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
)
5215 uint32_t tmpccmr1
= 0;
5216 uint32_t tmpccer
= 0;
5218 /* Disable the Channel 1: Reset the CC1E Bit */
5219 tmpccer
= TIMx
->CCER
;
5220 TIMx
->CCER
&= ~TIM_CCER_CC1E
;
5221 tmpccmr1
= TIMx
->CCMR1
;
5223 /* Set the filter */
5224 tmpccmr1
&= ~TIM_CCMR1_IC1F
;
5225 tmpccmr1
|= (TIM_ICFilter
<< 4);
5227 /* Select the Polarity and set the CC1E Bit */
5228 tmpccer
&= ~(TIM_CCER_CC1P
| TIM_CCER_CC1NP
);
5229 tmpccer
|= TIM_ICPolarity
;
5231 /* Write to TIMx CCMR1 and CCER registers */
5232 TIMx
->CCMR1
= tmpccmr1
;
5233 TIMx
->CCER
= tmpccer
;
5237 * @brief Configure the TI2 as Input.
5238 * @param TIMx to select the TIM peripheral
5239 * @param TIM_ICPolarity : The Input Polarity.
5240 * This parameter can be one of the following values:
5241 * @arg TIM_ICPolarity_Rising
5242 * @arg TIM_ICPolarity_Falling
5243 * @arg TIM_ICPolarity_BothEdge
5244 * @param TIM_ICSelection: specifies the input to be used.
5245 * This parameter can be one of the following values:
5246 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
5247 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
5248 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
5249 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5250 * This parameter must be a value between 0x00 and 0x0F.
5252 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
5253 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
5254 * protected against un-initialized filter and polarity values.
5256 static void TIM_TI2_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5257 uint32_t TIM_ICFilter
)
5259 uint32_t tmpccmr1
= 0;
5260 uint32_t tmpccer
= 0;
5262 /* Disable the Channel 2: Reset the CC2E Bit */
5263 TIMx
->CCER
&= ~TIM_CCER_CC2E
;
5264 tmpccmr1
= TIMx
->CCMR1
;
5265 tmpccer
= TIMx
->CCER
;
5267 /* Select the Input */
5268 tmpccmr1
&= ~TIM_CCMR1_CC2S
;
5269 tmpccmr1
|= (TIM_ICSelection
<< 8);
5271 /* Set the filter */
5272 tmpccmr1
&= ~TIM_CCMR1_IC2F
;
5273 tmpccmr1
|= ((TIM_ICFilter
<< 12) & TIM_CCMR1_IC2F
);
5275 /* Select the Polarity and set the CC2E Bit */
5276 tmpccer
&= ~(TIM_CCER_CC2P
| TIM_CCER_CC2NP
);
5277 tmpccer
|= ((TIM_ICPolarity
<< 4) & (TIM_CCER_CC2P
| TIM_CCER_CC2NP
));
5279 /* Write to TIMx CCMR1 and CCER registers */
5280 TIMx
->CCMR1
= tmpccmr1
;
5281 TIMx
->CCER
= tmpccer
;
5285 * @brief Configure the Polarity and Filter for TI2.
5286 * @param TIMx to select the TIM peripheral.
5287 * @param TIM_ICPolarity : The Input Polarity.
5288 * This parameter can be one of the following values:
5289 * @arg TIM_ICPolarity_Rising
5290 * @arg TIM_ICPolarity_Falling
5291 * @arg TIM_ICPolarity_BothEdge
5292 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5293 * This parameter must be a value between 0x00 and 0x0F.
5296 static void TIM_TI2_ConfigInputStage(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICFilter
)
5298 uint32_t tmpccmr1
= 0;
5299 uint32_t tmpccer
= 0;
5301 /* Disable the Channel 2: Reset the CC2E Bit */
5302 TIMx
->CCER
&= ~TIM_CCER_CC2E
;
5303 tmpccmr1
= TIMx
->CCMR1
;
5304 tmpccer
= TIMx
->CCER
;
5306 /* Set the filter */
5307 tmpccmr1
&= ~TIM_CCMR1_IC2F
;
5308 tmpccmr1
|= (TIM_ICFilter
<< 12);
5310 /* Select the Polarity and set the CC2E Bit */
5311 tmpccer
&= ~(TIM_CCER_CC2P
| TIM_CCER_CC2NP
);
5312 tmpccer
|= (TIM_ICPolarity
<< 4);
5314 /* Write to TIMx CCMR1 and CCER registers */
5315 TIMx
->CCMR1
= tmpccmr1
;
5316 TIMx
->CCER
= tmpccer
;
5320 * @brief Configure the TI3 as Input.
5321 * @param TIMx to select the TIM peripheral
5322 * @param TIM_ICPolarity : The Input Polarity.
5323 * This parameter can be one of the following values:
5324 * @arg TIM_ICPolarity_Rising
5325 * @arg TIM_ICPolarity_Falling
5326 * @arg TIM_ICPolarity_BothEdge
5327 * @param TIM_ICSelection: specifies the input to be used.
5328 * This parameter can be one of the following values:
5329 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
5330 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
5331 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
5332 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5333 * This parameter must be a value between 0x00 and 0x0F.
5335 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
5336 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5337 * protected against un-initialized filter and polarity values.
5339 static void TIM_TI3_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5340 uint32_t TIM_ICFilter
)
5342 uint32_t tmpccmr2
= 0;
5343 uint32_t tmpccer
= 0;
5345 /* Disable the Channel 3: Reset the CC3E Bit */
5346 TIMx
->CCER
&= ~TIM_CCER_CC3E
;
5347 tmpccmr2
= TIMx
->CCMR2
;
5348 tmpccer
= TIMx
->CCER
;
5350 /* Select the Input */
5351 tmpccmr2
&= ~TIM_CCMR2_CC3S
;
5352 tmpccmr2
|= TIM_ICSelection
;
5354 /* Set the filter */
5355 tmpccmr2
&= ~TIM_CCMR2_IC3F
;
5356 tmpccmr2
|= ((TIM_ICFilter
<< 4) & TIM_CCMR2_IC3F
);
5358 /* Select the Polarity and set the CC3E Bit */
5359 tmpccer
&= ~(TIM_CCER_CC3P
| TIM_CCER_CC3NP
);
5360 tmpccer
|= ((TIM_ICPolarity
<< 8) & (TIM_CCER_CC3P
| TIM_CCER_CC3NP
));
5362 /* Write to TIMx CCMR2 and CCER registers */
5363 TIMx
->CCMR2
= tmpccmr2
;
5364 TIMx
->CCER
= tmpccer
;
5368 * @brief Configure the TI4 as Input.
5369 * @param TIMx to select the TIM peripheral
5370 * @param TIM_ICPolarity : The Input Polarity.
5371 * This parameter can be one of the following values:
5372 * @arg TIM_ICPolarity_Rising
5373 * @arg TIM_ICPolarity_Falling
5374 * @arg TIM_ICPolarity_BothEdge
5375 * @param TIM_ICSelection: specifies the input to be used.
5376 * This parameter can be one of the following values:
5377 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
5378 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
5379 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
5380 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5381 * This parameter must be a value between 0x00 and 0x0F.
5383 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
5384 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5385 * protected against un-initialized filter and polarity values.
5387 static void TIM_TI4_SetConfig(TIM_TypeDef
*TIMx
, uint32_t TIM_ICPolarity
, uint32_t TIM_ICSelection
,
5388 uint32_t TIM_ICFilter
)
5390 uint32_t tmpccmr2
= 0;
5391 uint32_t tmpccer
= 0;
5393 /* Disable the Channel 4: Reset the CC4E Bit */
5394 TIMx
->CCER
&= ~TIM_CCER_CC4E
;
5395 tmpccmr2
= TIMx
->CCMR2
;
5396 tmpccer
= TIMx
->CCER
;
5398 /* Select the Input */
5399 tmpccmr2
&= ~TIM_CCMR2_CC4S
;
5400 tmpccmr2
|= (TIM_ICSelection
<< 8);
5402 /* Set the filter */
5403 tmpccmr2
&= ~TIM_CCMR2_IC4F
;
5404 tmpccmr2
|= ((TIM_ICFilter
<< 12) & TIM_CCMR2_IC4F
);
5406 /* Select the Polarity and set the CC4E Bit */
5407 tmpccer
&= ~(TIM_CCER_CC4P
| TIM_CCER_CC4NP
);
5408 tmpccer
|= ((TIM_ICPolarity
<< 12) & (TIM_CCER_CC4P
| TIM_CCER_CC4NP
));
5410 /* Write to TIMx CCMR2 and CCER registers */
5411 TIMx
->CCMR2
= tmpccmr2
;
5412 TIMx
->CCER
= tmpccer
;
5416 * @brief Selects the Input Trigger source
5417 * @param TIMx to select the TIM peripheral
5418 * @param TIM_ITRx: The Input Trigger source.
5419 * This parameter can be one of the following values:
5420 * @arg TIM_TS_ITR0: Internal Trigger 0
5421 * @arg TIM_TS_ITR1: Internal Trigger 1
5422 * @arg TIM_TS_ITR2: Internal Trigger 2
5423 * @arg TIM_TS_ITR3: Internal Trigger 3
5424 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
5425 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
5426 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
5427 * @arg TIM_TS_ETRF: External Trigger input
5430 static void TIM_ITRx_SetConfig(TIM_TypeDef
*TIMx
, uint16_t TIM_ITRx
)
5432 uint32_t tmpsmcr
= 0;
5434 /* Get the TIMx SMCR register value */
5435 tmpsmcr
= TIMx
->SMCR
;
5436 /* Reset the TS Bits */
5437 tmpsmcr
&= ~TIM_SMCR_TS
;
5438 /* Set the Input Trigger source and the slave mode*/
5439 tmpsmcr
|= TIM_ITRx
| TIM_SLAVEMODE_EXTERNAL1
;
5440 /* Write to TIMx SMCR */
5441 TIMx
->SMCR
= tmpsmcr
;
5445 * @brief Configures the TIMx External Trigger (ETR).
5446 * @param TIMx to select the TIM peripheral
5447 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
5448 * This parameter can be one of the following values:
5449 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
5450 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
5451 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
5452 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
5453 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
5454 * This parameter can be one of the following values:
5455 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
5456 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
5457 * @param ExtTRGFilter: External Trigger Filter.
5458 * This parameter must be a value between 0x00 and 0x0F
5461 void TIM_ETR_SetConfig(TIM_TypeDef
* TIMx
, uint32_t TIM_ExtTRGPrescaler
,
5462 uint32_t TIM_ExtTRGPolarity
, uint32_t ExtTRGFilter
)
5464 uint32_t tmpsmcr
= 0;
5466 tmpsmcr
= TIMx
->SMCR
;
5468 /* Reset the ETR Bits */
5469 tmpsmcr
&= ~(TIM_SMCR_ETF
| TIM_SMCR_ETPS
| TIM_SMCR_ECE
| TIM_SMCR_ETP
);
5471 /* Set the Prescaler, the Filter value and the Polarity */
5472 tmpsmcr
|= (uint32_t)(TIM_ExtTRGPrescaler
| (TIM_ExtTRGPolarity
| (ExtTRGFilter
<< 8)));
5474 /* Write to TIMx SMCR */
5475 TIMx
->SMCR
= tmpsmcr
;
5479 * @brief Enables or disables the TIM Capture Compare Channel x.
5480 * @param TIMx to select the TIM peripheral
5481 * @param Channel: specifies the TIM Channel
5482 * This parameter can be one of the following values:
5483 * @arg TIM_Channel_1: TIM Channel 1
5484 * @arg TIM_Channel_2: TIM Channel 2
5485 * @arg TIM_Channel_3: TIM Channel 3
5486 * @arg TIM_Channel_4: TIM Channel 4
5487 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
5488 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5491 void TIM_CCxChannelCmd(TIM_TypeDef
* TIMx
, uint32_t Channel
, uint32_t ChannelState
)
5495 /* Check the parameters */
5496 assert_param(IS_TIM_CC1_INSTANCE(TIMx
));
5497 assert_param(IS_TIM_CHANNELS(Channel
));
5499 tmp
= TIM_CCER_CC1E
<< Channel
;
5501 /* Reset the CCxE Bit */
5504 /* Set or reset the CCxE Bit */
5505 TIMx
->CCER
|= (uint32_t)(ChannelState
<< Channel
);
5513 #endif /* HAL_TIM_MODULE_ENABLED */
5521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/