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[mTask.git] / int / com / lib / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_tim_ex.c
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 22-April-2016
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer extension peripheral:
10 * + Time Hall Sensor Interface Initialization
11 * + Time Hall Sensor Interface Start
12 * + Time Complementary signal bread and dead time configuration
13 * + Time Master and Slave synchronization configuration
14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
15 * + Time OCRef clear configuration
16 * + Timer remapping capabilities configuration
17 @verbatim
18 ==============================================================================
19 ##### TIMER Extended features #####
20 ==============================================================================
21 [..]
22 The Timer Extension features include:
23 (#) Complementary outputs with programmable dead-time for :
24 (++) Input Capture
25 (++) Output Compare
26 (++) PWM generation (Edge and Center-aligned Mode)
27 (++) One-pulse mode output
28 (#) Synchronization circuit to control the timer with external signals and to
29 interconnect several timers together.
30 (#) Break input to put the timer output signals in reset state or in a known state.
31 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
32 positioning purposes
33
34 ##### How to use this driver #####
35 ==============================================================================
36 [..]
37 (#) Initialize the TIM low level resources by implementing the following functions
38 depending from feature used :
39 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
40 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
41 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
42 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
43
44 (#) Initialize the TIM low level resources :
45 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
46 (##) TIM pins configuration
47 (+++) Enable the clock for the TIM GPIOs using the following function:
48 __GPIOx_CLK_ENABLE();
49 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
50
51 (#) The external Clock can be configured, if needed (the default clock is the
52 internal clock from the APBx), using the following function:
53 HAL_TIM_ConfigClockSource, the clock configuration should be done before
54 any start function.
55
56 (#) Configure the TIM in the desired functioning mode using one of the
57 initialization function of this driver:
58 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
59 Timer Hall Sensor Interface and the commutation event with the corresponding
60 Interrupt and DMA request if needed (Note that One Timer is used to interface
61 with the Hall sensor Interface and another Timer should be used to use
62 the commutation event).
63
64 (#) Activate the TIM peripheral using one of the start functions:
65 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
66 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
67 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
68 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
69
70
71 @endverbatim
72 ******************************************************************************
73 * @attention
74 *
75 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
76 *
77 * Redistribution and use in source and binary forms, with or without modification,
78 * are permitted provided that the following conditions are met:
79 * 1. Redistributions of source code must retain the above copyright notice,
80 * this list of conditions and the following disclaimer.
81 * 2. Redistributions in binary form must reproduce the above copyright notice,
82 * this list of conditions and the following disclaimer in the documentation
83 * and/or other materials provided with the distribution.
84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
85 * may be used to endorse or promote products derived from this software
86 * without specific prior written permission.
87 *
88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
98 *
99 ******************************************************************************
100 */
101
102 /* Includes ------------------------------------------------------------------*/
103 #include "stm32f7xx_hal.h"
104
105 /** @addtogroup STM32F7xx_HAL_Driver
106 * @{
107 */
108
109 /** @defgroup TIMEx TIMEx
110 * @brief TIM Extended HAL module driver
111 * @{
112 */
113
114 #ifdef HAL_TIM_MODULE_ENABLED
115
116 /* Private typedef -----------------------------------------------------------*/
117 /* Private define ------------------------------------------------------------*/
118 #define BDTR_BKF_SHIFT (16)
119 #define BDTR_BK2F_SHIFT (20)
120 /* Private macro -------------------------------------------------------------*/
121 /* Private variables ---------------------------------------------------------*/
122 /* Private function prototypes -----------------------------------------------*/
123 /** @addtogroup TIMEx_Private_Functions
124 * @{
125 */
126 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
127 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
128 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
129 /**
130 * @}
131 */
132 /* Private functions ---------------------------------------------------------*/
133
134 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
135 * @{
136 */
137
138 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
139 * @brief Timer Hall Sensor functions
140 *
141 @verbatim
142 ==============================================================================
143 ##### Timer Hall Sensor functions #####
144 ==============================================================================
145 [..]
146 This section provides functions allowing to:
147 (+) Initialize and configure TIM HAL Sensor.
148 (+) De-initialize TIM HAL Sensor.
149 (+) Start the Hall Sensor Interface.
150 (+) Stop the Hall Sensor Interface.
151 (+) Start the Hall Sensor Interface and enable interrupts.
152 (+) Stop the Hall Sensor Interface and disable interrupts.
153 (+) Start the Hall Sensor Interface and enable DMA transfers.
154 (+) Stop the Hall Sensor Interface and disable DMA transfers.
155
156 @endverbatim
157 * @{
158 */
159 /**
160 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
161 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
162 * the configuration information for TIM module.
163 * @param sConfig: TIM Hall Sensor configuration structure
164 * @retval HAL status
165 */
166 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
167 {
168 TIM_OC_InitTypeDef OC_Config;
169
170 /* Check the TIM handle allocation */
171 if(htim == NULL)
172 {
173 return HAL_ERROR;
174 }
175
176 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
177 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
178 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
179 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
180 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
181 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
182
183 /* Set the TIM state */
184 htim->State= HAL_TIM_STATE_BUSY;
185
186 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
187 HAL_TIMEx_HallSensor_MspInit(htim);
188
189 /* Configure the Time base in the Encoder Mode */
190 TIM_Base_SetConfig(htim->Instance, &htim->Init);
191
192 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
193 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
194
195 /* Reset the IC1PSC Bits */
196 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
197 /* Set the IC1PSC value */
198 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
199
200 /* Enable the Hall sensor interface (XOR function of the three inputs) */
201 htim->Instance->CR2 |= TIM_CR2_TI1S;
202
203 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
204 htim->Instance->SMCR &= ~TIM_SMCR_TS;
205 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
206
207 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
208 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
209 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
210
211 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
212 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
213 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
214 OC_Config.OCMode = TIM_OCMODE_PWM2;
215 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
216 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
217 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
218 OC_Config.Pulse = sConfig->Commutation_Delay;
219
220 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
221
222 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
223 register to 101 */
224 htim->Instance->CR2 &= ~TIM_CR2_MMS;
225 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
226
227 /* Initialize the TIM state*/
228 htim->State= HAL_TIM_STATE_READY;
229
230 return HAL_OK;
231 }
232
233 /**
234 * @brief DeInitializes the TIM Hall Sensor interface
235 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
236 * the configuration information for TIM module.
237 * @retval HAL status
238 */
239 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
240 {
241 /* Check the parameters */
242 assert_param(IS_TIM_INSTANCE(htim->Instance));
243
244 htim->State = HAL_TIM_STATE_BUSY;
245
246 /* Disable the TIM Peripheral Clock */
247 __HAL_TIM_DISABLE(htim);
248
249 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
250 HAL_TIMEx_HallSensor_MspDeInit(htim);
251
252 /* Change TIM state */
253 htim->State = HAL_TIM_STATE_RESET;
254
255 /* Release Lock */
256 __HAL_UNLOCK(htim);
257
258 return HAL_OK;
259 }
260
261 /**
262 * @brief Initializes the TIM Hall Sensor MSP.
263 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
264 * the configuration information for TIM module.
265 * @retval None
266 */
267 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
268 {
269 /* Prevent unused argument(s) compilation warning */
270 UNUSED(htim);
271
272 /* NOTE : This function Should not be modified, when the callback is needed,
273 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
274 */
275 }
276
277 /**
278 * @brief DeInitializes TIM Hall Sensor MSP.
279 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
280 * the configuration information for TIM module.
281 * @retval None
282 */
283 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
284 {
285 /* Prevent unused argument(s) compilation warning */
286 UNUSED(htim);
287
288 /* NOTE : This function Should not be modified, when the callback is needed,
289 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
290 */
291 }
292
293 /**
294 * @brief Starts the TIM Hall Sensor Interface.
295 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
296 * the configuration information for TIM module.
297 * @retval HAL status
298 */
299 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
300 {
301 /* Check the parameters */
302 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
303
304 /* Enable the Input Capture channels 1
305 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
307
308 /* Enable the Peripheral */
309 __HAL_TIM_ENABLE(htim);
310
311 /* Return function status */
312 return HAL_OK;
313 }
314
315 /**
316 * @brief Stops the TIM Hall sensor Interface.
317 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
318 * the configuration information for TIM module.
319 * @retval HAL status
320 */
321 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
322 {
323 /* Check the parameters */
324 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
325
326 /* Disable the Input Capture channels 1, 2 and 3
327 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
328 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
329
330 /* Disable the Peripheral */
331 __HAL_TIM_DISABLE(htim);
332
333 /* Return function status */
334 return HAL_OK;
335 }
336
337 /**
338 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
339 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
340 * the configuration information for TIM module.
341 * @retval HAL status
342 */
343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
344 {
345 /* Check the parameters */
346 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
347
348 /* Enable the capture compare Interrupts 1 event */
349 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
350
351 /* Enable the Input Capture channels 1
352 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
353 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
354
355 /* Enable the Peripheral */
356 __HAL_TIM_ENABLE(htim);
357
358 /* Return function status */
359 return HAL_OK;
360 }
361
362 /**
363 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
364 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
365 * the configuration information for TIM module.
366 * @retval HAL status
367 */
368 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
369 {
370 /* Check the parameters */
371 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
372
373 /* Disable the Input Capture channels 1
374 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
375 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
376
377 /* Disable the capture compare Interrupts event */
378 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
379
380 /* Disable the Peripheral */
381 __HAL_TIM_DISABLE(htim);
382
383 /* Return function status */
384 return HAL_OK;
385 }
386
387 /**
388 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
389 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
390 * the configuration information for TIM module.
391 * @param pData: The destination Buffer address.
392 * @param Length: The length of data to be transferred from TIM peripheral to memory.
393 * @retval HAL status
394 */
395 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
396 {
397 /* Check the parameters */
398 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
399
400 if((htim->State == HAL_TIM_STATE_BUSY))
401 {
402 return HAL_BUSY;
403 }
404 else if((htim->State == HAL_TIM_STATE_READY))
405 {
406 if(((uint32_t)pData == 0 ) && (Length > 0))
407 {
408 return HAL_ERROR;
409 }
410 else
411 {
412 htim->State = HAL_TIM_STATE_BUSY;
413 }
414 }
415 /* Enable the Input Capture channels 1
416 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
417 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
418
419 /* Set the DMA Input Capture 1 Callback */
420 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
421 /* Set the DMA error callback */
422 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
423
424 /* Enable the DMA Stream for Capture 1*/
425 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
426
427 /* Enable the capture compare 1 Interrupt */
428 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
429
430 /* Enable the Peripheral */
431 __HAL_TIM_ENABLE(htim);
432
433 /* Return function status */
434 return HAL_OK;
435 }
436
437 /**
438 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
439 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
440 * the configuration information for TIM module.
441 * @retval HAL status
442 */
443 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
444 {
445 /* Check the parameters */
446 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
447
448 /* Disable the Input Capture channels 1
449 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
451
452
453 /* Disable the capture compare Interrupts 1 event */
454 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
455
456 /* Disable the Peripheral */
457 __HAL_TIM_DISABLE(htim);
458
459 /* Return function status */
460 return HAL_OK;
461 }
462
463 /**
464 * @}
465 */
466
467 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
468 * @brief Timer Complementary Output Compare functions
469 *
470 @verbatim
471 ==============================================================================
472 ##### Timer Complementary Output Compare functions #####
473 ==============================================================================
474 [..]
475 This section provides functions allowing to:
476 (+) Start the Complementary Output Compare/PWM.
477 (+) Stop the Complementary Output Compare/PWM.
478 (+) Start the Complementary Output Compare/PWM and enable interrupts.
479 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
480 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
481 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
482
483 @endverbatim
484 * @{
485 */
486
487 /**
488 * @brief Starts the TIM Output Compare signal generation on the complementary
489 * output.
490 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
491 * the configuration information for TIM module.
492 * @param Channel: TIM Channel to be enabled.
493 * This parameter can be one of the following values:
494 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
495 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
496 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
497 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
498 * @retval HAL status
499 */
500 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
501 {
502 /* Check the parameters */
503 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
504
505 /* Enable the Capture compare channel N */
506 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
507
508 /* Enable the Main Output */
509 __HAL_TIM_MOE_ENABLE(htim);
510
511 /* Enable the Peripheral */
512 __HAL_TIM_ENABLE(htim);
513
514 /* Return function status */
515 return HAL_OK;
516 }
517
518 /**
519 * @brief Stops the TIM Output Compare signal generation on the complementary
520 * output.
521 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
522 * the configuration information for TIM module.
523 * @param Channel: TIM Channel to be disabled.
524 * This parameter can be one of the following values:
525 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
526 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
527 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
528 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
529 * @retval HAL status
530 */
531 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
532 {
533 /* Check the parameters */
534 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
535
536 /* Disable the Capture compare channel N */
537 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
538
539 /* Disable the Main Output */
540 __HAL_TIM_MOE_DISABLE(htim);
541
542 /* Disable the Peripheral */
543 __HAL_TIM_DISABLE(htim);
544
545 /* Return function status */
546 return HAL_OK;
547 }
548
549 /**
550 * @brief Starts the TIM Output Compare signal generation in interrupt mode
551 * on the complementary output.
552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
553 * the configuration information for TIM module.
554 * @param Channel: TIM Channel to be enabled.
555 * This parameter can be one of the following values:
556 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
557 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
558 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
559 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
560 * @retval HAL status
561 */
562 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
563 {
564 /* Check the parameters */
565 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
566
567 switch (Channel)
568 {
569 case TIM_CHANNEL_1:
570 {
571 /* Enable the TIM Output Compare interrupt */
572 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
573 }
574 break;
575
576 case TIM_CHANNEL_2:
577 {
578 /* Enable the TIM Output Compare interrupt */
579 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
580 }
581 break;
582
583 case TIM_CHANNEL_3:
584 {
585 /* Enable the TIM Output Compare interrupt */
586 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
587 }
588 break;
589
590 case TIM_CHANNEL_4:
591 {
592 /* Enable the TIM Output Compare interrupt */
593 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
594 }
595 break;
596
597 default:
598 break;
599 }
600
601 /* Enable the TIM Break interrupt */
602 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
603
604 /* Enable the Capture compare channel N */
605 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
606
607 /* Enable the Main Output */
608 __HAL_TIM_MOE_ENABLE(htim);
609
610 /* Enable the Peripheral */
611 __HAL_TIM_ENABLE(htim);
612
613 /* Return function status */
614 return HAL_OK;
615 }
616
617 /**
618 * @brief Stops the TIM Output Compare signal generation in interrupt mode
619 * on the complementary output.
620 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
621 * the configuration information for TIM module.
622 * @param Channel: TIM Channel to be disabled.
623 * This parameter can be one of the following values:
624 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
625 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
626 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
627 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
628 * @retval HAL status
629 */
630 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
631 {
632 uint32_t tmpccer = 0;
633
634 /* Check the parameters */
635 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
636
637 switch (Channel)
638 {
639 case TIM_CHANNEL_1:
640 {
641 /* Disable the TIM Output Compare interrupt */
642 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
643 }
644 break;
645
646 case TIM_CHANNEL_2:
647 {
648 /* Disable the TIM Output Compare interrupt */
649 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
650 }
651 break;
652
653 case TIM_CHANNEL_3:
654 {
655 /* Disable the TIM Output Compare interrupt */
656 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
657 }
658 break;
659
660 case TIM_CHANNEL_4:
661 {
662 /* Disable the TIM Output Compare interrupt */
663 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
664 }
665 break;
666
667 default:
668 break;
669 }
670
671 /* Disable the Capture compare channel N */
672 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
673
674 /* Disable the TIM Break interrupt (only if no more channel is active) */
675 tmpccer = htim->Instance->CCER;
676 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
677 {
678 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
679 }
680
681 /* Disable the Main Output */
682 __HAL_TIM_MOE_DISABLE(htim);
683
684 /* Disable the Peripheral */
685 __HAL_TIM_DISABLE(htim);
686
687 /* Return function status */
688 return HAL_OK;
689 }
690
691 /**
692 * @brief Starts the TIM Output Compare signal generation in DMA mode
693 * on the complementary output.
694 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
695 * the configuration information for TIM module.
696 * @param Channel: TIM Channel to be enabled.
697 * This parameter can be one of the following values:
698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
701 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
702 * @param pData: The source Buffer address.
703 * @param Length: The length of data to be transferred from memory to TIM peripheral
704 * @retval HAL status
705 */
706 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
707 {
708 /* Check the parameters */
709 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
710
711 if((htim->State == HAL_TIM_STATE_BUSY))
712 {
713 return HAL_BUSY;
714 }
715 else if((htim->State == HAL_TIM_STATE_READY))
716 {
717 if(((uint32_t)pData == 0 ) && (Length > 0))
718 {
719 return HAL_ERROR;
720 }
721 else
722 {
723 htim->State = HAL_TIM_STATE_BUSY;
724 }
725 }
726 switch (Channel)
727 {
728 case TIM_CHANNEL_1:
729 {
730 /* Set the DMA Period elapsed callback */
731 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
732
733 /* Set the DMA error callback */
734 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
735
736 /* Enable the DMA Stream */
737 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
738
739 /* Enable the TIM Output Compare DMA request */
740 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
741 }
742 break;
743
744 case TIM_CHANNEL_2:
745 {
746 /* Set the DMA Period elapsed callback */
747 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
748
749 /* Set the DMA error callback */
750 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
751
752 /* Enable the DMA Stream */
753 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
754
755 /* Enable the TIM Output Compare DMA request */
756 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
757 }
758 break;
759
760 case TIM_CHANNEL_3:
761 {
762 /* Set the DMA Period elapsed callback */
763 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
764
765 /* Set the DMA error callback */
766 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
767
768 /* Enable the DMA Stream */
769 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
770
771 /* Enable the TIM Output Compare DMA request */
772 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
773 }
774 break;
775
776 case TIM_CHANNEL_4:
777 {
778 /* Set the DMA Period elapsed callback */
779 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
780
781 /* Set the DMA error callback */
782 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
783
784 /* Enable the DMA Stream */
785 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
786
787 /* Enable the TIM Output Compare DMA request */
788 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
789 }
790 break;
791
792 default:
793 break;
794 }
795
796 /* Enable the Capture compare channel N */
797 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
798
799 /* Enable the Main Output */
800 __HAL_TIM_MOE_ENABLE(htim);
801
802 /* Enable the Peripheral */
803 __HAL_TIM_ENABLE(htim);
804
805 /* Return function status */
806 return HAL_OK;
807 }
808
809 /**
810 * @brief Stops the TIM Output Compare signal generation in DMA mode
811 * on the complementary output.
812 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
813 * the configuration information for TIM module.
814 * @param Channel: TIM Channel to be disabled.
815 * This parameter can be one of the following values:
816 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
817 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
818 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
819 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
820 * @retval HAL status
821 */
822 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
823 {
824 /* Check the parameters */
825 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
826
827 switch (Channel)
828 {
829 case TIM_CHANNEL_1:
830 {
831 /* Disable the TIM Output Compare DMA request */
832 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
833 }
834 break;
835
836 case TIM_CHANNEL_2:
837 {
838 /* Disable the TIM Output Compare DMA request */
839 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
840 }
841 break;
842
843 case TIM_CHANNEL_3:
844 {
845 /* Disable the TIM Output Compare DMA request */
846 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
847 }
848 break;
849
850 case TIM_CHANNEL_4:
851 {
852 /* Disable the TIM Output Compare interrupt */
853 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
854 }
855 break;
856
857 default:
858 break;
859 }
860
861 /* Disable the Capture compare channel N */
862 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
863
864 /* Disable the Main Output */
865 __HAL_TIM_MOE_DISABLE(htim);
866
867 /* Disable the Peripheral */
868 __HAL_TIM_DISABLE(htim);
869
870 /* Change the htim state */
871 htim->State = HAL_TIM_STATE_READY;
872
873 /* Return function status */
874 return HAL_OK;
875 }
876
877 /**
878 * @}
879 */
880
881 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
882 * @brief Timer Complementary PWM functions
883 *
884 @verbatim
885 ==============================================================================
886 ##### Timer Complementary PWM functions #####
887 ==============================================================================
888 [..]
889 This section provides functions allowing to:
890 (+) Start the Complementary PWM.
891 (+) Stop the Complementary PWM.
892 (+) Start the Complementary PWM and enable interrupts.
893 (+) Stop the Complementary PWM and disable interrupts.
894 (+) Start the Complementary PWM and enable DMA transfers.
895 (+) Stop the Complementary PWM and disable DMA transfers.
896 (+) Start the Complementary Input Capture measurement.
897 (+) Stop the Complementary Input Capture.
898 (+) Start the Complementary Input Capture and enable interrupts.
899 (+) Stop the Complementary Input Capture and disable interrupts.
900 (+) Start the Complementary Input Capture and enable DMA transfers.
901 (+) Stop the Complementary Input Capture and disable DMA transfers.
902 (+) Start the Complementary One Pulse generation.
903 (+) Stop the Complementary One Pulse.
904 (+) Start the Complementary One Pulse and enable interrupts.
905 (+) Stop the Complementary One Pulse and disable interrupts.
906
907 @endverbatim
908 * @{
909 */
910
911 /**
912 * @brief Starts the PWM signal generation on the complementary output.
913 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
914 * the configuration information for TIM module.
915 * @param Channel: TIM Channel to be enabled.
916 * This parameter can be one of the following values:
917 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
918 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
919 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
920 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
921 * @retval HAL status
922 */
923 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
924 {
925 /* Check the parameters */
926 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
927
928 /* Enable the complementary PWM output */
929 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
930
931 /* Enable the Main Output */
932 __HAL_TIM_MOE_ENABLE(htim);
933
934 /* Enable the Peripheral */
935 __HAL_TIM_ENABLE(htim);
936
937 /* Return function status */
938 return HAL_OK;
939 }
940
941 /**
942 * @brief Stops the PWM signal generation on the complementary output.
943 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
944 * the configuration information for TIM module.
945 * @param Channel: TIM Channel to be disabled.
946 * This parameter can be one of the following values:
947 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
948 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
949 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
950 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
951 * @retval HAL status
952 */
953 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
954 {
955 /* Check the parameters */
956 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
957
958 /* Disable the complementary PWM output */
959 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
960
961 /* Disable the Main Output */
962 __HAL_TIM_MOE_DISABLE(htim);
963
964 /* Disable the Peripheral */
965 __HAL_TIM_DISABLE(htim);
966
967 /* Return function status */
968 return HAL_OK;
969 }
970
971 /**
972 * @brief Starts the PWM signal generation in interrupt mode on the
973 * complementary output.
974 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
975 * the configuration information for TIM module.
976 * @param Channel: TIM Channel to be disabled.
977 * This parameter can be one of the following values:
978 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
979 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
980 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
981 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
982 * @retval HAL status
983 */
984 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
985 {
986 /* Check the parameters */
987 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
988
989 switch (Channel)
990 {
991 case TIM_CHANNEL_1:
992 {
993 /* Enable the TIM Capture/Compare 1 interrupt */
994 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
995 }
996 break;
997
998 case TIM_CHANNEL_2:
999 {
1000 /* Enable the TIM Capture/Compare 2 interrupt */
1001 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1002 }
1003 break;
1004
1005 case TIM_CHANNEL_3:
1006 {
1007 /* Enable the TIM Capture/Compare 3 interrupt */
1008 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1009 }
1010 break;
1011
1012 case TIM_CHANNEL_4:
1013 {
1014 /* Enable the TIM Capture/Compare 4 interrupt */
1015 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1016 }
1017 break;
1018
1019 default:
1020 break;
1021 }
1022
1023 /* Enable the TIM Break interrupt */
1024 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1025
1026 /* Enable the complementary PWM output */
1027 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1028
1029 /* Enable the Main Output */
1030 __HAL_TIM_MOE_ENABLE(htim);
1031
1032 /* Enable the Peripheral */
1033 __HAL_TIM_ENABLE(htim);
1034
1035 /* Return function status */
1036 return HAL_OK;
1037 }
1038
1039 /**
1040 * @brief Stops the PWM signal generation in interrupt mode on the
1041 * complementary output.
1042 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1043 * the configuration information for TIM module.
1044 * @param Channel: TIM Channel to be disabled.
1045 * This parameter can be one of the following values:
1046 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1047 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1048 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1049 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1050 * @retval HAL status
1051 */
1052 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1053 {
1054 uint32_t tmpccer = 0;
1055
1056 /* Check the parameters */
1057 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1058
1059 switch (Channel)
1060 {
1061 case TIM_CHANNEL_1:
1062 {
1063 /* Disable the TIM Capture/Compare 1 interrupt */
1064 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1065 }
1066 break;
1067
1068 case TIM_CHANNEL_2:
1069 {
1070 /* Disable the TIM Capture/Compare 2 interrupt */
1071 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1072 }
1073 break;
1074
1075 case TIM_CHANNEL_3:
1076 {
1077 /* Disable the TIM Capture/Compare 3 interrupt */
1078 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1079 }
1080 break;
1081
1082 case TIM_CHANNEL_4:
1083 {
1084 /* Disable the TIM Capture/Compare 3 interrupt */
1085 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1086 }
1087 break;
1088
1089 default:
1090 break;
1091 }
1092
1093 /* Disable the complementary PWM output */
1094 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1095
1096 /* Disable the TIM Break interrupt (only if no more channel is active) */
1097 tmpccer = htim->Instance->CCER;
1098 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
1099 {
1100 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1101 }
1102
1103 /* Disable the Main Output */
1104 __HAL_TIM_MOE_DISABLE(htim);
1105
1106 /* Disable the Peripheral */
1107 __HAL_TIM_DISABLE(htim);
1108
1109 /* Return function status */
1110 return HAL_OK;
1111 }
1112
1113 /**
1114 * @brief Starts the TIM PWM signal generation in DMA mode on the
1115 * complementary output
1116 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1117 * the configuration information for TIM module.
1118 * @param Channel: TIM Channel to be enabled.
1119 * This parameter can be one of the following values:
1120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1122 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1123 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1124 * @param pData: The source Buffer address.
1125 * @param Length: The length of data to be transferred from memory to TIM peripheral
1126 * @retval HAL status
1127 */
1128 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1129 {
1130 /* Check the parameters */
1131 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1132
1133 if((htim->State == HAL_TIM_STATE_BUSY))
1134 {
1135 return HAL_BUSY;
1136 }
1137 else if((htim->State == HAL_TIM_STATE_READY))
1138 {
1139 if(((uint32_t)pData == 0 ) && (Length > 0))
1140 {
1141 return HAL_ERROR;
1142 }
1143 else
1144 {
1145 htim->State = HAL_TIM_STATE_BUSY;
1146 }
1147 }
1148 switch (Channel)
1149 {
1150 case TIM_CHANNEL_1:
1151 {
1152 /* Set the DMA Period elapsed callback */
1153 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1154
1155 /* Set the DMA error callback */
1156 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1157
1158 /* Enable the DMA Stream */
1159 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1160
1161 /* Enable the TIM Capture/Compare 1 DMA request */
1162 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1163 }
1164 break;
1165
1166 case TIM_CHANNEL_2:
1167 {
1168 /* Set the DMA Period elapsed callback */
1169 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1170
1171 /* Set the DMA error callback */
1172 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1173
1174 /* Enable the DMA Stream */
1175 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1176
1177 /* Enable the TIM Capture/Compare 2 DMA request */
1178 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1179 }
1180 break;
1181
1182 case TIM_CHANNEL_3:
1183 {
1184 /* Set the DMA Period elapsed callback */
1185 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1186
1187 /* Set the DMA error callback */
1188 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1189
1190 /* Enable the DMA Stream */
1191 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1192
1193 /* Enable the TIM Capture/Compare 3 DMA request */
1194 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1195 }
1196 break;
1197
1198 case TIM_CHANNEL_4:
1199 {
1200 /* Set the DMA Period elapsed callback */
1201 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1202
1203 /* Set the DMA error callback */
1204 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1205
1206 /* Enable the DMA Stream */
1207 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1208
1209 /* Enable the TIM Capture/Compare 4 DMA request */
1210 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1211 }
1212 break;
1213
1214 default:
1215 break;
1216 }
1217
1218 /* Enable the complementary PWM output */
1219 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1220
1221 /* Enable the Main Output */
1222 __HAL_TIM_MOE_ENABLE(htim);
1223
1224 /* Enable the Peripheral */
1225 __HAL_TIM_ENABLE(htim);
1226
1227 /* Return function status */
1228 return HAL_OK;
1229 }
1230
1231 /**
1232 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1233 * output
1234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1235 * the configuration information for TIM module.
1236 * @param Channel: TIM Channel to be disabled.
1237 * This parameter can be one of the following values:
1238 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1239 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1240 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1241 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1242 * @retval HAL status
1243 */
1244 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1245 {
1246 /* Check the parameters */
1247 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1248
1249 switch (Channel)
1250 {
1251 case TIM_CHANNEL_1:
1252 {
1253 /* Disable the TIM Capture/Compare 1 DMA request */
1254 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1255 }
1256 break;
1257
1258 case TIM_CHANNEL_2:
1259 {
1260 /* Disable the TIM Capture/Compare 2 DMA request */
1261 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1262 }
1263 break;
1264
1265 case TIM_CHANNEL_3:
1266 {
1267 /* Disable the TIM Capture/Compare 3 DMA request */
1268 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1269 }
1270 break;
1271
1272 case TIM_CHANNEL_4:
1273 {
1274 /* Disable the TIM Capture/Compare 4 DMA request */
1275 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1276 }
1277 break;
1278
1279 default:
1280 break;
1281 }
1282
1283 /* Disable the complementary PWM output */
1284 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1285
1286 /* Disable the Main Output */
1287 __HAL_TIM_MOE_DISABLE(htim);
1288
1289 /* Disable the Peripheral */
1290 __HAL_TIM_DISABLE(htim);
1291
1292 /* Change the htim state */
1293 htim->State = HAL_TIM_STATE_READY;
1294
1295 /* Return function status */
1296 return HAL_OK;
1297 }
1298
1299 /**
1300 * @}
1301 */
1302
1303 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1304 * @brief Timer Complementary One Pulse functions
1305 *
1306 @verbatim
1307 ==============================================================================
1308 ##### Timer Complementary One Pulse functions #####
1309 ==============================================================================
1310 [..]
1311 This section provides functions allowing to:
1312 (+) Start the Complementary One Pulse generation.
1313 (+) Stop the Complementary One Pulse.
1314 (+) Start the Complementary One Pulse and enable interrupts.
1315 (+) Stop the Complementary One Pulse and disable interrupts.
1316
1317 @endverbatim
1318 * @{
1319 */
1320
1321 /**
1322 * @brief Starts the TIM One Pulse signal generation on the complemetary
1323 * output.
1324 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1325 * the configuration information for TIM module.
1326 * @param OutputChannel: TIM Channel to be enabled.
1327 * This parameter can be one of the following values:
1328 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1329 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1330 * @retval HAL status
1331 */
1332 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1333 {
1334 /* Check the parameters */
1335 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1336
1337 /* Enable the complementary One Pulse output */
1338 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1339
1340 /* Enable the Main Output */
1341 __HAL_TIM_MOE_ENABLE(htim);
1342
1343 /* Return function status */
1344 return HAL_OK;
1345 }
1346
1347 /**
1348 * @brief Stops the TIM One Pulse signal generation on the complementary
1349 * output.
1350 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1351 * the configuration information for TIM module.
1352 * @param OutputChannel: TIM Channel to be disabled.
1353 * This parameter can be one of the following values:
1354 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1355 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1356 * @retval HAL status
1357 */
1358 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1359 {
1360
1361 /* Check the parameters */
1362 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1363
1364 /* Disable the complementary One Pulse output */
1365 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1366
1367 /* Disable the Main Output */
1368 __HAL_TIM_MOE_DISABLE(htim);
1369
1370 /* Disable the Peripheral */
1371 __HAL_TIM_DISABLE(htim);
1372
1373 /* Return function status */
1374 return HAL_OK;
1375 }
1376
1377 /**
1378 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1379 * complementary channel.
1380 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1381 * the configuration information for TIM module.
1382 * @param OutputChannel: TIM Channel to be enabled.
1383 * This parameter can be one of the following values:
1384 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1385 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1386 * @retval HAL status
1387 */
1388 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1389 {
1390 /* Check the parameters */
1391 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1392
1393 /* Enable the TIM Capture/Compare 1 interrupt */
1394 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1395
1396 /* Enable the TIM Capture/Compare 2 interrupt */
1397 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1398
1399 /* Enable the complementary One Pulse output */
1400 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1401
1402 /* Enable the Main Output */
1403 __HAL_TIM_MOE_ENABLE(htim);
1404
1405 /* Return function status */
1406 return HAL_OK;
1407 }
1408
1409 /**
1410 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1411 * complementary channel.
1412 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1413 * the configuration information for TIM module.
1414 * @param OutputChannel: TIM Channel to be disabled.
1415 * This parameter can be one of the following values:
1416 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1417 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1418 * @retval HAL status
1419 */
1420 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1421 {
1422 /* Check the parameters */
1423 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1424
1425 /* Disable the TIM Capture/Compare 1 interrupt */
1426 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1427
1428 /* Disable the TIM Capture/Compare 2 interrupt */
1429 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1430
1431 /* Disable the complementary One Pulse output */
1432 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1433
1434 /* Disable the Main Output */
1435 __HAL_TIM_MOE_DISABLE(htim);
1436
1437 /* Disable the Peripheral */
1438 __HAL_TIM_DISABLE(htim);
1439
1440 /* Return function status */
1441 return HAL_OK;
1442 }
1443
1444 /**
1445 * @}
1446 */
1447
1448 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1449 * @brief Peripheral Control functions
1450 *
1451 @verbatim
1452 ==============================================================================
1453 ##### Peripheral Control functions #####
1454 ==============================================================================
1455 [..]
1456 This section provides functions allowing to:
1457 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
1458 (+) Configure External Clock source.
1459 (+) Configure Complementary channels, break features and dead time.
1460 (+) Configure Master and the Slave synchronization.
1461 (+) Configure the commutation event in case of use of the Hall sensor interface.
1462 (+) Configure the DMA Burst Mode.
1463
1464 @endverbatim
1465 * @{
1466 */
1467 /**
1468 * @brief Configure the TIM commutation event sequence.
1469 * @note This function is mandatory to use the commutation event in order to
1470 * update the configuration at each commutation detection on the TRGI input of the Timer,
1471 * the typical use of this feature is with the use of another Timer(interface Timer)
1472 * configured in Hall sensor interface, this interface Timer will generate the
1473 * commutation at its TRGO output (connected to Timer used in this function) each time
1474 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1475 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1476 * the configuration information for TIM module.
1477 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
1478 * This parameter can be one of the following values:
1479 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1480 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1481 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1482 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1483 * @arg TIM_TS_NONE: No trigger is needed
1484 * @param CommutationSource: the Commutation Event source.
1485 * This parameter can be one of the following values:
1486 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1487 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1488 * @retval HAL status
1489 */
1490 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1491 {
1492 /* Check the parameters */
1493 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
1494 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1495
1496 __HAL_LOCK(htim);
1497
1498 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1499 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1500 {
1501 /* Select the Input trigger */
1502 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1503 htim->Instance->SMCR |= InputTrigger;
1504 }
1505
1506 /* Select the Capture Compare preload feature */
1507 htim->Instance->CR2 |= TIM_CR2_CCPC;
1508 /* Select the Commutation event source */
1509 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1510 htim->Instance->CR2 |= CommutationSource;
1511
1512 __HAL_UNLOCK(htim);
1513
1514 return HAL_OK;
1515 }
1516
1517 /**
1518 * @brief Configure the TIM commutation event sequence with interrupt.
1519 * @note This function is mandatory to use the commutation event in order to
1520 * update the configuration at each commutation detection on the TRGI input of the Timer,
1521 * the typical use of this feature is with the use of another Timer(interface Timer)
1522 * configured in Hall sensor interface, this interface Timer will generate the
1523 * commutation at its TRGO output (connected to Timer used in this function) each time
1524 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1525 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1526 * the configuration information for TIM module.
1527 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
1528 * This parameter can be one of the following values:
1529 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1530 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1531 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1532 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1533 * @arg TIM_TS_NONE: No trigger is needed
1534 * @param CommutationSource: the Commutation Event source.
1535 * This parameter can be one of the following values:
1536 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1537 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1538 * @retval HAL status
1539 */
1540 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1541 {
1542 /* Check the parameters */
1543 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
1544 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1545
1546 __HAL_LOCK(htim);
1547
1548 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1549 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1550 {
1551 /* Select the Input trigger */
1552 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1553 htim->Instance->SMCR |= InputTrigger;
1554 }
1555
1556 /* Select the Capture Compare preload feature */
1557 htim->Instance->CR2 |= TIM_CR2_CCPC;
1558 /* Select the Commutation event source */
1559 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1560 htim->Instance->CR2 |= CommutationSource;
1561
1562 /* Enable the Commutation Interrupt Request */
1563 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
1564
1565 __HAL_UNLOCK(htim);
1566
1567 return HAL_OK;
1568 }
1569
1570 /**
1571 * @brief Configure the TIM commutation event sequence with DMA.
1572 * @note This function is mandatory to use the commutation event in order to
1573 * update the configuration at each commutation detection on the TRGI input of the Timer,
1574 * the typical use of this feature is with the use of another Timer(interface Timer)
1575 * configured in Hall sensor interface, this interface Timer will generate the
1576 * commutation at its TRGO output (connected to Timer used in this function) each time
1577 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1578 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
1579 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1580 * the configuration information for TIM module.
1581 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
1582 * This parameter can be one of the following values:
1583 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1584 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1585 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1586 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1587 * @arg TIM_TS_NONE: No trigger is needed
1588 * @param CommutationSource: the Commutation Event source.
1589 * This parameter can be one of the following values:
1590 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1591 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1592 * @retval HAL status
1593 */
1594 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1595 {
1596 /* Check the parameters */
1597 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
1598 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1599
1600 __HAL_LOCK(htim);
1601
1602 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1603 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1604 {
1605 /* Select the Input trigger */
1606 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1607 htim->Instance->SMCR |= InputTrigger;
1608 }
1609
1610 /* Select the Capture Compare preload feature */
1611 htim->Instance->CR2 |= TIM_CR2_CCPC;
1612 /* Select the Commutation event source */
1613 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1614 htim->Instance->CR2 |= CommutationSource;
1615
1616 /* Enable the Commutation DMA Request */
1617 /* Set the DMA Commutation Callback */
1618 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
1619 /* Set the DMA error callback */
1620 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
1621
1622 /* Enable the Commutation DMA Request */
1623 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
1624
1625 __HAL_UNLOCK(htim);
1626
1627 return HAL_OK;
1628 }
1629
1630 /**
1631 * @brief Initializes the TIM Output Compare Channels according to the specified
1632 * parameters in the TIM_OC_InitTypeDef.
1633 * @param htim: TIM Output Compare handle
1634 * @param sConfig: TIM Output Compare configuration structure
1635 * @param Channel : TIM Channels to configure
1636 * This parameter can be one of the following values:
1637 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1638 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1639 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1640 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1641 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1642 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1643 * @retval HAL status
1644 */
1645 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
1646 {
1647 /* Check the parameters */
1648 assert_param(IS_TIM_CHANNELS(Channel));
1649 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
1650 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
1651
1652 /* Check input state */
1653 __HAL_LOCK(htim);
1654
1655 htim->State = HAL_TIM_STATE_BUSY;
1656
1657 switch (Channel)
1658 {
1659 case TIM_CHANNEL_1:
1660 {
1661 /* Check the parameters */
1662 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
1663
1664 /* Configure the TIM Channel 1 in Output Compare */
1665 TIM_OC1_SetConfig(htim->Instance, sConfig);
1666 }
1667 break;
1668
1669 case TIM_CHANNEL_2:
1670 {
1671 /* Check the parameters */
1672 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1673
1674 /* Configure the TIM Channel 2 in Output Compare */
1675 TIM_OC2_SetConfig(htim->Instance, sConfig);
1676 }
1677 break;
1678
1679 case TIM_CHANNEL_3:
1680 {
1681 /* Check the parameters */
1682 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
1683
1684 /* Configure the TIM Channel 3 in Output Compare */
1685 TIM_OC3_SetConfig(htim->Instance, sConfig);
1686 }
1687 break;
1688
1689 case TIM_CHANNEL_4:
1690 {
1691 /* Check the parameters */
1692 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
1693
1694 /* Configure the TIM Channel 4 in Output Compare */
1695 TIM_OC4_SetConfig(htim->Instance, sConfig);
1696 }
1697 break;
1698
1699 case TIM_CHANNEL_5:
1700 {
1701 /* Check the parameters */
1702 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
1703
1704 /* Configure the TIM Channel 5 in Output Compare */
1705 TIM_OC5_SetConfig(htim->Instance, sConfig);
1706 }
1707 break;
1708
1709 case TIM_CHANNEL_6:
1710 {
1711 /* Check the parameters */
1712 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
1713
1714 /* Configure the TIM Channel 6 in Output Compare */
1715 TIM_OC6_SetConfig(htim->Instance, sConfig);
1716 }
1717 break;
1718
1719 default:
1720 break;
1721 }
1722
1723 htim->State = HAL_TIM_STATE_READY;
1724
1725 __HAL_UNLOCK(htim);
1726
1727 return HAL_OK;
1728 }
1729
1730 /**
1731 * @brief Initializes the TIM PWM channels according to the specified
1732 * parameters in the TIM_OC_InitTypeDef.
1733 * @param htim: TIM PWM handle
1734 * @param sConfig: TIM PWM configuration structure
1735 * @param Channel : TIM Channels to be configured
1736 * This parameter can be one of the following values:
1737 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1738 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1739 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1740 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1741 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1742 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1743 * @retval HAL status
1744 */
1745 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
1746 TIM_OC_InitTypeDef* sConfig,
1747 uint32_t Channel)
1748 {
1749 /* Check the parameters */
1750 assert_param(IS_TIM_CHANNELS(Channel));
1751 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
1752 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
1753 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
1754
1755 /* Check input state */
1756 __HAL_LOCK(htim);
1757
1758 htim->State = HAL_TIM_STATE_BUSY;
1759
1760 switch (Channel)
1761 {
1762 case TIM_CHANNEL_1:
1763 {
1764 /* Check the parameters */
1765 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
1766
1767 /* Configure the Channel 1 in PWM mode */
1768 TIM_OC1_SetConfig(htim->Instance, sConfig);
1769
1770 /* Set the Preload enable bit for channel1 */
1771 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
1772
1773 /* Configure the Output Fast mode */
1774 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
1775 htim->Instance->CCMR1 |= sConfig->OCFastMode;
1776 }
1777 break;
1778
1779 case TIM_CHANNEL_2:
1780 {
1781 /* Check the parameters */
1782 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1783
1784 /* Configure the Channel 2 in PWM mode */
1785 TIM_OC2_SetConfig(htim->Instance, sConfig);
1786
1787 /* Set the Preload enable bit for channel2 */
1788 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
1789
1790 /* Configure the Output Fast mode */
1791 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
1792 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
1793 }
1794 break;
1795
1796 case TIM_CHANNEL_3:
1797 {
1798 /* Check the parameters */
1799 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
1800
1801 /* Configure the Channel 3 in PWM mode */
1802 TIM_OC3_SetConfig(htim->Instance, sConfig);
1803
1804 /* Set the Preload enable bit for channel3 */
1805 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
1806
1807 /* Configure the Output Fast mode */
1808 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
1809 htim->Instance->CCMR2 |= sConfig->OCFastMode;
1810 }
1811 break;
1812
1813 case TIM_CHANNEL_4:
1814 {
1815 /* Check the parameters */
1816 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
1817
1818 /* Configure the Channel 4 in PWM mode */
1819 TIM_OC4_SetConfig(htim->Instance, sConfig);
1820
1821 /* Set the Preload enable bit for channel4 */
1822 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
1823
1824 /* Configure the Output Fast mode */
1825 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
1826 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
1827 }
1828 break;
1829
1830 case TIM_CHANNEL_5:
1831 {
1832 /* Check the parameters */
1833 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
1834
1835 /* Configure the Channel 5 in PWM mode */
1836 TIM_OC5_SetConfig(htim->Instance, sConfig);
1837
1838 /* Set the Preload enable bit for channel5*/
1839 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
1840
1841 /* Configure the Output Fast mode */
1842 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
1843 htim->Instance->CCMR3 |= sConfig->OCFastMode;
1844 }
1845 break;
1846
1847 case TIM_CHANNEL_6:
1848 {
1849 /* Check the parameters */
1850 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
1851
1852 /* Configure the Channel 5 in PWM mode */
1853 TIM_OC6_SetConfig(htim->Instance, sConfig);
1854
1855 /* Set the Preload enable bit for channel6 */
1856 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
1857
1858 /* Configure the Output Fast mode */
1859 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
1860 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
1861 }
1862 break;
1863
1864 default:
1865 break;
1866 }
1867
1868 htim->State = HAL_TIM_STATE_READY;
1869
1870 __HAL_UNLOCK(htim);
1871
1872 return HAL_OK;
1873 }
1874
1875 /**
1876 * @brief Configures the OCRef clear feature
1877 * @param htim: TIM handle
1878 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
1879 * contains the OCREF clear feature and parameters for the TIM peripheral.
1880 * @param Channel: specifies the TIM Channel
1881 * This parameter can be one of the following values:
1882 * @arg TIM_Channel_1: TIM Channel 1
1883 * @arg TIM_Channel_2: TIM Channel 2
1884 * @arg TIM_Channel_3: TIM Channel 3
1885 * @arg TIM_Channel_4: TIM Channel 4
1886 * @arg TIM_Channel_5: TIM Channel 5
1887 * @arg TIM_Channel_6: TIM Channel 6
1888 * @retval None
1889 */
1890 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
1891 TIM_ClearInputConfigTypeDef *sClearInputConfig,
1892 uint32_t Channel)
1893 {
1894 uint32_t tmpsmcr = 0;
1895
1896 /* Check the parameters */
1897 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
1898 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
1899
1900 /* Check input state */
1901 __HAL_LOCK(htim);
1902
1903 switch (sClearInputConfig->ClearInputSource)
1904 {
1905 case TIM_CLEARINPUTSOURCE_NONE:
1906 {
1907 /* Get the TIMx SMCR register value */
1908 tmpsmcr = htim->Instance->SMCR;
1909
1910 /* Clear the OCREF clear selection bit */
1911 tmpsmcr &= ~TIM_SMCR_OCCS;
1912
1913 /* Clear the ETR Bits */
1914 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
1915
1916 /* Set TIMx_SMCR */
1917 htim->Instance->SMCR = tmpsmcr;
1918 }
1919 break;
1920
1921 case TIM_CLEARINPUTSOURCE_OCREFCLR:
1922 {
1923 /* Clear the OCREF clear selection bit */
1924 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
1925 }
1926 break;
1927
1928 case TIM_CLEARINPUTSOURCE_ETR:
1929 {
1930 /* Check the parameters */
1931 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
1932 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
1933 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
1934
1935 TIM_ETR_SetConfig(htim->Instance,
1936 sClearInputConfig->ClearInputPrescaler,
1937 sClearInputConfig->ClearInputPolarity,
1938 sClearInputConfig->ClearInputFilter);
1939
1940 /* Set the OCREF clear selection bit */
1941 htim->Instance->SMCR |= TIM_SMCR_OCCS;
1942 }
1943 break;
1944 default:
1945 break;
1946 }
1947
1948 switch (Channel)
1949 {
1950 case TIM_CHANNEL_1:
1951 {
1952 if(sClearInputConfig->ClearInputState != RESET)
1953 {
1954 /* Enable the Ocref clear feature for Channel 1 */
1955 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
1956 }
1957 else
1958 {
1959 /* Disable the Ocref clear feature for Channel 1 */
1960 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
1961 }
1962 }
1963 break;
1964 case TIM_CHANNEL_2:
1965 {
1966 if(sClearInputConfig->ClearInputState != RESET)
1967 {
1968 /* Enable the Ocref clear feature for Channel 2 */
1969 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
1970 }
1971 else
1972 {
1973 /* Disable the Ocref clear feature for Channel 2 */
1974 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
1975 }
1976 }
1977 break;
1978 case TIM_CHANNEL_3:
1979 {
1980 if(sClearInputConfig->ClearInputState != RESET)
1981 {
1982 /* Enable the Ocref clear feature for Channel 3 */
1983 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
1984 }
1985 else
1986 {
1987 /* Disable the Ocref clear feature for Channel 3 */
1988 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
1989 }
1990 }
1991 break;
1992 case TIM_CHANNEL_4:
1993 {
1994 if(sClearInputConfig->ClearInputState != RESET)
1995 {
1996 /* Enable the Ocref clear feature for Channel 4 */
1997 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
1998 }
1999 else
2000 {
2001 /* Disable the Ocref clear feature for Channel 4 */
2002 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
2003 }
2004 }
2005 break;
2006 case TIM_CHANNEL_5:
2007 {
2008 if(sClearInputConfig->ClearInputState != RESET)
2009 {
2010 /* Enable the Ocref clear feature for Channel 1 */
2011 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
2012 }
2013 else
2014 {
2015 /* Disable the Ocref clear feature for Channel 1 */
2016 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
2017 }
2018 }
2019 break;
2020 case TIM_CHANNEL_6:
2021 {
2022 if(sClearInputConfig->ClearInputState != RESET)
2023 {
2024 /* Enable the Ocref clear feature for Channel 1 */
2025 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
2026 }
2027 else
2028 {
2029 /* Disable the Ocref clear feature for Channel 1 */
2030 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
2031 }
2032 }
2033 break;
2034 default:
2035 break;
2036 }
2037
2038 __HAL_UNLOCK(htim);
2039
2040 return HAL_OK;
2041 }
2042
2043 /**
2044 * @brief Configures the TIM in master mode.
2045 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2046 * the configuration information for TIM module.
2047 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
2048 * contains the selected trigger output (TRGO) and the Master/Slave
2049 * mode.
2050 * @retval HAL status
2051 */
2052 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
2053 {
2054 uint32_t tmpcr2;
2055 uint32_t tmpsmcr;
2056
2057 /* Check the parameters */
2058 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
2059 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2060 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2061
2062 /* Check input state */
2063 __HAL_LOCK(htim);
2064
2065 /* Get the TIMx CR2 register value */
2066 tmpcr2 = htim->Instance->CR2;
2067
2068 /* Get the TIMx SMCR register value */
2069 tmpsmcr = htim->Instance->SMCR;
2070
2071 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2072 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2073 {
2074 /* Check the parameters */
2075 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2076
2077 /* Clear the MMS2 bits */
2078 tmpcr2 &= ~TIM_CR2_MMS2;
2079 /* Select the TRGO2 source*/
2080 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2081 }
2082
2083 /* Reset the MMS Bits */
2084 tmpcr2 &= ~TIM_CR2_MMS;
2085 /* Select the TRGO source */
2086 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2087
2088 /* Reset the MSM Bit */
2089 tmpsmcr &= ~TIM_SMCR_MSM;
2090 /* Set master mode */
2091 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2092
2093 /* Update TIMx CR2 */
2094 htim->Instance->CR2 = tmpcr2;
2095
2096 /* Update TIMx SMCR */
2097 htim->Instance->SMCR = tmpsmcr;
2098
2099 __HAL_UNLOCK(htim);
2100
2101 return HAL_OK;
2102 }
2103
2104 /**
2105 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2106 * and the AOE(automatic output enable).
2107 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2108 * the configuration information for TIM module.
2109 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
2110 * contains the BDTR Register configuration information for the TIM peripheral.
2111 * @retval HAL status
2112 */
2113 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2114 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
2115 {
2116 uint32_t tmpbdtr = 0;
2117
2118 /* Check the parameters */
2119 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2120 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2121 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2122 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2123 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2124 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2125 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2126 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2127 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2128 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2129 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2130 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2131
2132 /* Check input state */
2133 __HAL_LOCK(htim);
2134
2135 htim->State = HAL_TIM_STATE_BUSY;
2136
2137 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2138 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2139
2140 /* Clear the BDTR bits */
2141 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
2142 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
2143 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
2144 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
2145
2146 /* Set the BDTR bits */
2147 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
2148 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
2149 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
2150 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
2151 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
2152 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
2153 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
2154 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
2155 tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
2156 tmpbdtr |= sBreakDeadTimeConfig->Break2State;
2157 tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
2158
2159 /* Set TIMx_BDTR */
2160 htim->Instance->BDTR = tmpbdtr;
2161
2162 __HAL_UNLOCK(htim);
2163
2164 return HAL_OK;
2165 }
2166 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
2167 /**
2168 * @brief Configures the break input source.
2169 * @param htim: TIM handle.
2170 * @param BreakInput: Break input to configure
2171 * This parameter can be one of the following values:
2172 * @arg TIM_BREAKINPUT_BRK: Timer break input
2173 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2174 * @param sBreakInputConfig: Break input source configuration
2175 * @retval HAL status
2176 */
2177 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2178 uint32_t BreakInput,
2179 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2180
2181 {
2182 uint32_t tmporx = 0;
2183 uint32_t bkin_enable_mask = 0;
2184 uint32_t bkin_enable_bitpos = 0;
2185
2186 /* Check the parameters */
2187 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2188 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2189 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2190 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2191
2192 /* Check input state */
2193 __HAL_LOCK(htim);
2194
2195 switch(sBreakInputConfig->Source)
2196 {
2197 case TIM_BREAKINPUTSOURCE_BKIN:
2198 {
2199 bkin_enable_mask = TIM1_AF1_BKINE;
2200 bkin_enable_bitpos = 0;
2201 }
2202 break;
2203
2204 case TIM_BREAKINPUTSOURCE_DFSDM1:
2205 {
2206 bkin_enable_mask = TIM1_AF1_BKDF1BKE;
2207 bkin_enable_bitpos = 8;
2208 }
2209 break;
2210
2211 default:
2212 break;
2213 }
2214
2215 switch(BreakInput)
2216 {
2217 case TIM_BREAKINPUT_BRK:
2218 {
2219 /* Get the TIMx_AF1 register value */
2220 tmporx = htim->Instance->AF1;
2221
2222 /* Enable the break input */
2223 tmporx &= ~bkin_enable_mask;
2224 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2225
2226 /* Set TIMx_AF1 */
2227 htim->Instance->AF1 = tmporx;
2228 }
2229 break;
2230 case TIM_BREAKINPUT_BRK2:
2231 {
2232 /* Get the TIMx_AF2 register value */
2233 tmporx = htim->Instance->AF2;
2234
2235 /* Enable the break input */
2236 tmporx &= ~bkin_enable_mask;
2237 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2238
2239 /* Set TIMx_AF2 */
2240 htim->Instance->AF2 = tmporx;
2241 }
2242 break;
2243 default:
2244 break;
2245 }
2246
2247 __HAL_UNLOCK(htim);
2248
2249 return HAL_OK;
2250 }
2251 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2252
2253 /**
2254 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
2255 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2256 * the configuration information for TIM module.
2257 * @param Remap: specifies the TIM input remapping source.
2258 * This parameter can be one of the following values:
2259 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
2260 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
2261 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
2262 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
2263 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
2264 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
2265 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
2266 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
2267 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
2268 * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous
2269 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
2270 * (HSE divided by a programmable prescaler)
2271 * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
2272 * @retval HAL status
2273 */
2274 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2275 {
2276 __HAL_LOCK(htim);
2277
2278 /* Check parameters */
2279 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2280 assert_param(IS_TIM_REMAP(Remap));
2281
2282 /* Set the Timer remapping configuration */
2283 htim->Instance->OR = Remap;
2284
2285 htim->State = HAL_TIM_STATE_READY;
2286
2287 __HAL_UNLOCK(htim);
2288
2289 return HAL_OK;
2290 }
2291
2292 /**
2293 * @brief Group channel 5 and channel 1, 2 or 3
2294 * @param htim: TIM handle.
2295 * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
2296 * This parameter can be any combination of the following values:
2297 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2298 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2299 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2300 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2301 * @retval HAL status
2302 */
2303 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
2304 {
2305 /* Check parameters */
2306 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2307 assert_param(IS_TIM_GROUPCH5(OCRef));
2308
2309 /* Process Locked */
2310 __HAL_LOCK(htim);
2311
2312 htim->State = HAL_TIM_STATE_BUSY;
2313
2314 /* Clear GC5Cx bit fields */
2315 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
2316
2317 /* Set GC5Cx bit fields */
2318 htim->Instance->CCR5 |= OCRef;
2319
2320 htim->State = HAL_TIM_STATE_READY;
2321
2322 __HAL_UNLOCK(htim);
2323
2324 return HAL_OK;
2325 }
2326
2327 /**
2328 * @}
2329 */
2330
2331 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2332 * @brief Extended Callbacks functions
2333 *
2334 @verbatim
2335 ==============================================================================
2336 ##### Extension Callbacks functions #####
2337 ==============================================================================
2338 [..]
2339 This section provides Extension TIM callback functions:
2340 (+) Timer Commutation callback
2341 (+) Timer Break callback
2342
2343 @endverbatim
2344 * @{
2345 */
2346
2347 /**
2348 * @brief Hall commutation changed callback in non blocking mode
2349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2350 * the configuration information for TIM module.
2351 * @retval None
2352 */
2353 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
2354 {
2355 /* Prevent unused argument(s) compilation warning */
2356 UNUSED(htim);
2357
2358 /* NOTE : This function Should not be modified, when the callback is needed,
2359 the HAL_TIMEx_CommutationCallback could be implemented in the user file
2360 */
2361 }
2362
2363 /**
2364 * @brief Hall Break detection callback in non blocking mode
2365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2366 * the configuration information for TIM module.
2367 * @retval None
2368 */
2369 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
2370 {
2371 /* Prevent unused argument(s) compilation warning */
2372 UNUSED(htim);
2373
2374 /* NOTE : This function Should not be modified, when the callback is needed,
2375 the HAL_TIMEx_BreakCallback could be implemented in the user file
2376 */
2377 }
2378
2379 /**
2380 * @}
2381 */
2382
2383 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
2384 * @brief Extended Peripheral State functions
2385 *
2386 @verbatim
2387 ==============================================================================
2388 ##### Extension Peripheral State functions #####
2389 ==============================================================================
2390 [..]
2391 This subsection permits to get in run-time the status of the peripheral
2392 and the data flow.
2393
2394 @endverbatim
2395 * @{
2396 */
2397
2398 /**
2399 * @brief Return the TIM Hall Sensor interface state
2400 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2401 * the configuration information for TIM module.
2402 * @retval HAL state
2403 */
2404 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
2405 {
2406 return htim->State;
2407 }
2408
2409 /**
2410 * @}
2411 */
2412
2413 /**
2414 * @brief TIM DMA Commutation callback.
2415 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2416 * the configuration information for the specified DMA module.
2417 * @retval None
2418 */
2419 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
2420 {
2421 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2422
2423 htim->State= HAL_TIM_STATE_READY;
2424
2425 HAL_TIMEx_CommutationCallback(htim);
2426 }
2427
2428 /**
2429 * @brief Enables or disables the TIM Capture Compare Channel xN.
2430 * @param TIMx to select the TIM peripheral
2431 * @param Channel: specifies the TIM Channel
2432 * This parameter can be one of the following values:
2433 * @arg TIM_Channel_1: TIM Channel 1
2434 * @arg TIM_Channel_2: TIM Channel 2
2435 * @arg TIM_Channel_3: TIM Channel 3
2436 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
2437 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
2438 * @retval None
2439 */
2440 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
2441 {
2442 uint32_t tmp = 0;
2443
2444 /* Check the parameters */
2445 assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
2446 assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
2447
2448 tmp = TIM_CCER_CC1NE << Channel;
2449
2450 /* Reset the CCxNE Bit */
2451 TIMx->CCER &= ~tmp;
2452
2453 /* Set or reset the CCxNE Bit */
2454 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
2455 }
2456
2457 /**
2458 * @brief Timer Output Compare 5 configuration
2459 * @param TIMx to select the TIM peripheral
2460 * @param OC_Config: The output configuration structure
2461 * @retval None
2462 */
2463 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
2464 {
2465 uint32_t tmpccmrx = 0;
2466 uint32_t tmpccer = 0;
2467 uint32_t tmpcr2 = 0;
2468
2469 /* Disable the output: Reset the CCxE Bit */
2470 TIMx->CCER &= ~TIM_CCER_CC5E;
2471
2472 /* Get the TIMx CCER register value */
2473 tmpccer = TIMx->CCER;
2474 /* Get the TIMx CR2 register value */
2475 tmpcr2 = TIMx->CR2;
2476 /* Get the TIMx CCMR1 register value */
2477 tmpccmrx = TIMx->CCMR3;
2478
2479 /* Reset the Output Compare Mode Bits */
2480 tmpccmrx &= ~(TIM_CCMR3_OC5M);
2481 /* Select the Output Compare Mode */
2482 tmpccmrx |= OC_Config->OCMode;
2483
2484 /* Reset the Output Polarity level */
2485 tmpccer &= ~TIM_CCER_CC5P;
2486 /* Set the Output Compare Polarity */
2487 tmpccer |= (OC_Config->OCPolarity << 16);
2488
2489 if(IS_TIM_BREAK_INSTANCE(TIMx))
2490 {
2491 /* Reset the Output Compare IDLE State */
2492 tmpcr2 &= ~TIM_CR2_OIS5;
2493 /* Set the Output Idle state */
2494 tmpcr2 |= (OC_Config->OCIdleState << 8);
2495 }
2496 /* Write to TIMx CR2 */
2497 TIMx->CR2 = tmpcr2;
2498
2499 /* Write to TIMx CCMR3 */
2500 TIMx->CCMR3 = tmpccmrx;
2501
2502 /* Set the Capture Compare Register value */
2503 TIMx->CCR5 = OC_Config->Pulse;
2504
2505 /* Write to TIMx CCER */
2506 TIMx->CCER = tmpccer;
2507 }
2508
2509 /**
2510 * @brief Timer Output Compare 6 configuration
2511 * @param TIMx to select the TIM peripheral
2512 * @param OC_Config: The output configuration structure
2513 * @retval None
2514 */
2515 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
2516 {
2517 uint32_t tmpccmrx = 0;
2518 uint32_t tmpccer = 0;
2519 uint32_t tmpcr2 = 0;
2520
2521 /* Disable the output: Reset the CCxE Bit */
2522 TIMx->CCER &= ~TIM_CCER_CC6E;
2523
2524 /* Get the TIMx CCER register value */
2525 tmpccer = TIMx->CCER;
2526 /* Get the TIMx CR2 register value */
2527 tmpcr2 = TIMx->CR2;
2528 /* Get the TIMx CCMR1 register value */
2529 tmpccmrx = TIMx->CCMR3;
2530
2531 /* Reset the Output Compare Mode Bits */
2532 tmpccmrx &= ~(TIM_CCMR3_OC6M);
2533 /* Select the Output Compare Mode */
2534 tmpccmrx |= (OC_Config->OCMode << 8);
2535
2536 /* Reset the Output Polarity level */
2537 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
2538 /* Set the Output Compare Polarity */
2539 tmpccer |= (OC_Config->OCPolarity << 20);
2540
2541 if(IS_TIM_BREAK_INSTANCE(TIMx))
2542 {
2543 /* Reset the Output Compare IDLE State */
2544 tmpcr2 &= ~TIM_CR2_OIS6;
2545 /* Set the Output Idle state */
2546 tmpcr2 |= (OC_Config->OCIdleState << 10);
2547 }
2548
2549 /* Write to TIMx CR2 */
2550 TIMx->CR2 = tmpcr2;
2551
2552 /* Write to TIMx CCMR3 */
2553 TIMx->CCMR3 = tmpccmrx;
2554
2555 /* Set the Capture Compare Register value */
2556 TIMx->CCR6 = OC_Config->Pulse;
2557
2558 /* Write to TIMx CCER */
2559 TIMx->CCER = tmpccer;
2560 }
2561
2562 /**
2563 * @}
2564 */
2565
2566 #endif /* HAL_TIM_MODULE_ENABLED */
2567 /**
2568 * @}
2569 */
2570
2571 /**
2572 * @}
2573 */
2574 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Repo containing the code for the mTask system (see msc-thesis1617)