3 % Definition of logical gates
, used
in the examples below
.
4 and_gate
(all X
:(and(X
) , ~ab
(X
) => (in1
(X
), in2
(X
) <=> out
(X
)))).
5 or_gate
( all X
:(or(X
) , ~ab
(X
) => (in1
(X
) ; in2
(X
) <=> out
(X
)))).
6 xor_gate
(all X
:(xor(X
) , ~ab
(X
) => (out
(X
) <=> in1
(X
),~in2
(X
);~in1
(X
),in2
(X
)))).
8 % Two unconnected AND gates with two inputs
. It is observed that the
9 % inputs are true
and the outputs are false
.
10 problem1
(SD
, COMP
, OBS
) :-
12 SD
= [ AND
, and(a1
), and(a2
) ],
14 OBS
= [in1
(a1
), in2
(a1
), ~out
(a1
), in1
(a2
), in2
(a2
), ~out
(a2
)].
16 % Example of wwo AND gates where the output of the first gate
(a1
) is
17 % connected to the first input
(in1
) of the second gate
(a2
). It is
18 % easy to see that the observations are inconsistent with the
20 problem2
(SD
, COMP
, OBS
) :-
22 SD
= [ AND
, and(a1
), and(a2
), out
(a1
) <=> in1
(a2
) ],
24 OBS
= [in1
(a1
), ~in2
(a1
), out
(a2
)].
26 % Another wiring example
, now with two AND gates
and an OR gate
.
27 problem3
(SD
, COMP
, OBS
) :-
28 and_gate
(AND
), or_gate
(OR
),
29 SD
= [ AND
, OR
, and(a1
), and(a2
), or(o1
),
30 out
(a1
) <=> in1
(o1
), out
(a2
) <=> in2
(o1
)],
32 OBS
= [in1
(a1
), in2
(a1
), in1
(a2
), in2
(a2
), ~out
(o1
)].
34 % The following represents a
(one
-bit
) full adder
: a
35 % circuit that can be used
for the addition of two bits with
36 % carry
-in and carry
-out bits
.
38 % in1
(fa
), in2
(fa
): input bits
39 % carryin
(fa
): carry
-in bit
41 % carryout
(fa
): carry
-out bit
43 % returns the sum of in1
(fa
) + in2
(fa
) + carryin
(fa
)
44 % as
2 * carryout
(fa
) + out
(fa
) (i
.e
., as
2 bits
)
45 fulladder
(SD
, COMP
, OBS
) :-
46 and_gate
(AND
), or_gate
(OR
), xor_gate
(XOR
),
48 and(a1
), and(a2
), xor(x1
), xor(x2
), or(r1
),
49 in1
(fa
) <=> in1
(x1
), in2
(fa
) <=> in1
(a1
),
50 carryin
(fa
) <=> in1
(a2
), carryin
(fa
) <=> in2
(x2
),
51 out
(fa
) <=> out
(x2
), carryout
(fa
) <=> out
(r1
),
52 in2
(fa
) <=> in2
(x1
), in2
(fa
) <=> in2
(a1
),
53 out
(x1
) <=> in2
(a2
), out
(x1
) <=> in1
(x2
),
54 out
(a2
) <=> in1
(r1
), out
(a1
) <=> in2
(r1
) ],
55 COMP
= [a1
, a2
, x1
, x2
, r1
],
56 OBS
= [in1
(fa
), ~in2
(fa
), carryin
(fa
), out
(fa
), ~carryout
(fa
)]. %1+1=1?