+++ /dev/null
-BOARD_TAG = uno
-ARDUINO_LIBS = LiquidCrystal
-CPPFLAGS += -std=gnu11
-
-include /usr/share/arduino/Arduino.mk
-
--- /dev/null
+/*
+*****************************************************************************
+**
+
+** File : LinkerScript.ld
+**
+** Abstract : Linker script for STM32F746ZGTx Device with
+** 1024KByte FLASH, 320KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of Ac6 nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20050000; /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x400; /* required amount of heap */
+_Min_Stack_Size = 0x200; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 2048K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f767xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.\r
+ *\r
+ * This file contains:\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral\92s registers hardware\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS_Device\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f767xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F767xx_H\r
+#define __STM32F767xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+typedef enum\r
+{\r
+/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ \r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ \r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+ FMC_IRQn = 48, /*!< FMC global Interrupt */\r
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */\r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
+ RNG_IRQn = 80, /*!< RNG global interrupt */\r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */\r
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */\r
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */\r
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */\r
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */\r
+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */\r
+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */\r
+ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */\r
+ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */\r
+ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */\r
+ SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */\r
+ DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */\r
+ DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */\r
+ DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */\r
+ DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */\r
+ SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */\r
+ CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */\r
+ CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */\r
+ CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */\r
+ CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */\r
+ JPEG_IRQn = 108, /*!< JPEG global Interrupt */\r
+ MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals \r
+ */\r
+#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */\r
+#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */\r
+#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */\r
+#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */\r
+ \r
+ \r
+#include "system_stm32f7xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ \r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
+ AND triple modes, Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Controller Area Network TxMailBox \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FIFOMailBox \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FilterRegister \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ \r
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
+} CAN_TypeDef;\r
+\r
+/** \r
+ * @brief HDMI-CEC \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */\r
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */\r
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */\r
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */\r
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */\r
+}CEC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */\r
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\r
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/**\r
+ * @brief DFSDM module registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */\r
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */\r
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */\r
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */\r
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */\r
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */\r
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */\r
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */\r
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */\r
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */\r
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */\r
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */\r
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */\r
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */\r
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */\r
+} DFSDM_Filter_TypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel configuration registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */\r
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */\r
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and\r
+ short circuit detector register, Address offset: 0x08 */\r
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */\r
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */\r
+} DFSDM_Channel_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DCMI\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief DMA2D Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */\r
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */\r
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */\r
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */\r
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */\r
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */\r
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */\r
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */\r
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */\r
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */\r
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */\r
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */\r
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */\r
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */\r
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */\r
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */\r
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */\r
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */\r
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */\r
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */\r
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */\r
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */\r
+} DMA2D_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Ethernet MAC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACFFR;\r
+ __IO uint32_t MACHTHR;\r
+ __IO uint32_t MACHTLR;\r
+ __IO uint32_t MACMIIAR;\r
+ __IO uint32_t MACMIIDR;\r
+ __IO uint32_t MACFCR;\r
+ __IO uint32_t MACVLANTR; /* 8 */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t MACRWUFFR; /* 11 */\r
+ __IO uint32_t MACPMTCSR;\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t MACSR; /* 15 */\r
+ __IO uint32_t MACIMR;\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR; /* 24 */\r
+ uint32_t RESERVED2[40];\r
+ __IO uint32_t MMCCR; /* 65 */\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR; /* 69 */\r
+ uint32_t RESERVED3[14];\r
+ __IO uint32_t MMCTGFSCCR; /* 84 */\r
+ __IO uint32_t MMCTGFMSCCR;\r
+ uint32_t RESERVED4[5];\r
+ __IO uint32_t MMCTGFCR;\r
+ uint32_t RESERVED5[10];\r
+ __IO uint32_t MMCRFCECR;\r
+ __IO uint32_t MMCRFAECR;\r
+ uint32_t RESERVED6[10];\r
+ __IO uint32_t MMCRGUFCR;\r
+ uint32_t RESERVED7[334];\r
+ __IO uint32_t PTPTSCR;\r
+ __IO uint32_t PTPSSIR;\r
+ __IO uint32_t PTPTSHR;\r
+ __IO uint32_t PTPTSLR;\r
+ __IO uint32_t PTPTSHUR;\r
+ __IO uint32_t PTPTSLUR;\r
+ __IO uint32_t PTPTSAR;\r
+ __IO uint32_t PTPTTHR;\r
+ __IO uint32_t PTPTTLR;\r
+ __IO uint32_t RESERVED8;\r
+ __IO uint32_t PTPTSSR;\r
+ uint32_t RESERVED9[565];\r
+ __IO uint32_t DMABMR;\r
+ __IO uint32_t DMATPDR;\r
+ __IO uint32_t DMARPDR;\r
+ __IO uint32_t DMARDLAR;\r
+ __IO uint32_t DMATDLAR;\r
+ __IO uint32_t DMASR;\r
+ __IO uint32_t DMAOMR;\r
+ __IO uint32_t DMAIER;\r
+ __IO uint32_t DMAMFBOCR;\r
+ __IO uint32_t DMARSWTR;\r
+ uint32_t RESERVED10[8];\r
+ __IO uint32_t DMACHTDR;\r
+ __IO uint32_t DMACHRDR;\r
+ __IO uint32_t DMACHTBAR;\r
+ __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */\r
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */\r
+} FLASH_TypeDef;\r
+\r
+\r
+\r
+/** \r
+ * @brief Flexible Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
+} FMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank3\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */\r
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */\r
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */\r
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+ \r
+/** \r
+ * @brief Flexible Memory Controller Bank5_6\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
+} FMC_Bank5_6_TypeDef; \r
+\r
+\r
+/** \r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief System configuration controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ uint32_t RESERVED; /*!< Reserved, 0x18 */\r
+ __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */\r
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ \r
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\r
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\r
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\r
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\r
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\r
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\r
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ \r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief LCD-TFT Display Controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */\r
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */\r
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */\r
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */\r
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */\r
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */\r
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */\r
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */\r
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */\r
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */\r
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */\r
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */\r
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */\r
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */\r
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */\r
+} LTDC_TypeDef; \r
+\r
+/** \r
+ * @brief LCD-TFT Display layer x Controller\r
+ */\r
+ \r
+typedef struct\r
+{ \r
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */\r
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */\r
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */\r
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */\r
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */\r
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */\r
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */\r
+ uint32_t RESERVED0[2]; /*!< Reserved */\r
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */\r
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */\r
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */\r
+ uint32_t RESERVED1[3]; /*!< Reserved */\r
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */\r
+\r
+} LTDC_Layer_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */\r
+ __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */\r
+} PWR_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */\r
+ __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */\r
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */\r
+\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ \r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ uint32_t reserved; /*!< Reserved */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Serial Audio Interface\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+\r
+/** \r
+ * @brief SPDIF-RX Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */\r
+ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ \r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */\r
+ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ \r
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */\r
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */\r
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */\r
+} SPDIFRX_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */\r
+} SDMMC_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief QUAD Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */\r
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */\r
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */\r
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */\r
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */\r
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */\r
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */\r
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ \r
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */\r
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ \r
+} QUADSPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */\r
+ __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */\r
+ __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */\r
+ __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */\r
+ __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */\r
+\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief LPTIMIMER\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\r
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\r
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\r
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\r
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\r
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\r
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\r
+} LPTIM_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ \r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ \r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\r
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ \r
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ \r
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\r
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\r
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\r
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\r
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\r
+} USART_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief RNG\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** \r
+ * @brief USB_OTG_Core_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */\r
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */\r
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */\r
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */\r
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */\r
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */\r
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */\r
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */\r
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */\r
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */\r
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */\r
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */\r
+ uint32_t Reserved30[2]; /*!< Reserved 030h */\r
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */\r
+ __IO uint32_t CID; /*!< User ID Register 03Ch */\r
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */\r
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */\r
+ uint32_t Reserved6; /*!< Reserved 050h */ \r
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */\r
+ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */\r
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */\r
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */\r
+ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */\r
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */\r
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */\r
+} USB_OTG_GlobalTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_device_Registers\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */\r
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */\r
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */\r
+ uint32_t Reserved0C; /*!< Reserved 80Ch */\r
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */\r
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */\r
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */\r
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */\r
+ uint32_t Reserved20; /*!< Reserved 820h */\r
+ uint32_t Reserved9; /*!< Reserved 824h */\r
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */\r
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */\r
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */\r
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */\r
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */\r
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ \r
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */\r
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */\r
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */\r
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ \r
+} USB_OTG_DeviceTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_IN_Endpoint-Specific_Register\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */\r
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r
+} USB_OTG_INEndpointTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */\r
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r
+} USB_OTG_OUTEndpointTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_Host_Mode_Register_Structures\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */\r
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */\r
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */\r
+ uint32_t Reserved40C; /*!< Reserved 40Ch */\r
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */\r
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */\r
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */\r
+} USB_OTG_HostTypeDef;\r
+\r
+/** \r
+ * @brief USB_OTG_Host_Channel_Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */\r
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */\r
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */\r
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */\r
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */\r
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */\r
+ uint32_t Reserved[2]; /*!< Reserved */\r
+} USB_OTG_HostChannelTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief JPEG Codec\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */\r
+ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */\r
+ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */\r
+ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ \r
+ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ \r
+ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ \r
+ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ \r
+ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */\r
+ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */\r
+ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ \r
+ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ \r
+ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ \r
+ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */\r
+ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */\r
+ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */\r
+ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */\r
+ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */\r
+ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */\r
+ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */\r
+ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */\r
+ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */\r
+ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */\r
+ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */\r
+ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */\r
+ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */\r
+ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */\r
+ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */\r
+ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */\r
+ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */\r
+\r
+} JPEG_TypeDef;\r
+\r
+/**\r
+ * @brief MDIOS\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */\r
+ __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */\r
+ __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */\r
+ __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ \r
+ __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ \r
+ __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */\r
+ __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ \r
+ uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ \r
+ __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ \r
+ __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ \r
+ __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ \r
+ __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ \r
+ __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ \r
+ __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ \r
+ __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ \r
+ __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ \r
+ __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ \r
+ __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ \r
+ __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ \r
+ __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ \r
+ __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ \r
+ __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ \r
+ __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ \r
+ __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ \r
+ __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ \r
+ __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ \r
+ __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ \r
+ __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ \r
+ __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ \r
+ __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ \r
+ __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ \r
+ __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ \r
+ __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ \r
+ __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ \r
+ __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ \r
+ __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ \r
+ __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ \r
+ __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ \r
+ __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ \r
+ __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ \r
+ __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ \r
+ __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ \r
+ __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ \r
+ __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ \r
+ __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ \r
+ __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ \r
+ __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ \r
+ __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */\r
+ __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */\r
+ __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */\r
+ __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */\r
+ __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */\r
+ __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */\r
+ __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */\r
+ __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */\r
+ __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */\r
+ __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */\r
+ __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */\r
+ __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */\r
+ __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */\r
+ __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */\r
+ __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */\r
+ __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */\r
+ __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */\r
+ __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */\r
+ __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */\r
+ __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */\r
+ __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */\r
+ __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */\r
+ __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */\r
+ __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */\r
+ __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */\r
+} MDIOS_TypeDef;\r
+\r
+\r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */\r
+#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ \r
+#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ \r
+#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */\r
+#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */\r
+#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */\r
+#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */\r
+#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */\r
+#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */\r
+#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */\r
+#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */\r
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */\r
+\r
+/* Legacy define */\r
+#define FLASH_BASE FLASHAXI_BASE\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)\r
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)\r
+#define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)\r
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)\r
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)\r
+#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)\r
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)\r
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)\r
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)\r
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)\r
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)\r
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)\r
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)\r
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)\r
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)\r
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)\r
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)\r
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)\r
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)\r
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)\r
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)\r
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)\r
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)\r
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)\r
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)\r
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)\r
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)\r
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)\r
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)\r
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)\r
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)\r
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)\r
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)\r
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)\r
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)\r
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)\r
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)\r
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)\r
+#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)\r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)\r
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)\r
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)\r
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)\r
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)\r
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)\r
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)\r
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)\r
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)\r
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)\r
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)\r
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)\r
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)\r
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)\r
+#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */\r
+#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */\r
+#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */\r
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)\r
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)\r
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)\r
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)\r
+/*!< AHB2 peripherals */\r
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)\r
+#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)\r
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)\r
+/*!< FMC Bankx registers base address */\r
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)\r
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)\r
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)\r
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE 0xE0042000U\r
+\r
+/*!< USB registers base address */\r
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U\r
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U\r
+\r
+#define USB_OTG_GLOBAL_BASE 0x000U\r
+#define USB_OTG_DEVICE_BASE 0x800U\r
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U\r
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U\r
+#define USB_OTG_EP_REG_SIZE 0x20U\r
+#define USB_OTG_HOST_BASE 0x400U\r
+#define USB_OTG_HOST_PORT_BASE 0x440U\r
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U\r
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U\r
+#define USB_OTG_PCGCCTL_BASE 0xE00U\r
+#define USB_OTG_FIFO_BASE 0x1000U\r
+#define USB_OTG_FIFO_SIZE 0x1000U\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) \r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define UART7 ((USART_TypeDef *) UART7_BASE)\r
+#define UART8 ((USART_TypeDef *) UART8_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE) \r
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)\r
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)\r
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)\r
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)\r
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define ETH ((ETH_TypeDef *) ETH_BASE) \r
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)\r
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\r
+#define CAN3 ((CAN_TypeDef *) CAN3_BASE)\r
+#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)\r
+#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)\r
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\r
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\r
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\r
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\r
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\r
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\r
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\r
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\r
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\r
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\r
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\r
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\r
+#define JPEG ((JPEG_TypeDef *) JPEG_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */\r
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */\r
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */\r
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */\r
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */\r
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */\r
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */\r
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */\r
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */\r
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */\r
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */\r
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */\r
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */\r
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */\r
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */\r
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */\r
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */\r
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */\r
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */\r
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */\r
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */\r
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */\r
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */\r
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */\r
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */\r
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */\r
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */\r
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */\r
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */\r
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */\r
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */\r
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */\r
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */\r
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */\r
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */\r
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */\r
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */\r
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */\r
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */\r
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */\r
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */\r
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */\r
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */\r
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */\r
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */\r
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */\r
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */\r
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */\r
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */\r
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */\r
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */\r
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */\r
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */\r
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */\r
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */\r
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */\r
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */\r
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */\r
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */\r
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */\r
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */\r
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */\r
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */\r
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */\r
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */\r
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */\r
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */\r
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */\r
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */\r
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */\r
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */\r
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */\r
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */\r
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */\r
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */\r
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */\r
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */\r
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */\r
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */\r
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */\r
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */\r
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */\r
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */\r
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */\r
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */\r
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */\r
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */\r
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */\r
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */\r
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */\r
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */\r
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */\r
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */\r
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */\r
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 Overrun flag */\r
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */\r
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */\r
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */\r
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */\r
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 Overrun flag */\r
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */\r
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */\r
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */\r
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */\r
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 Overrun flag */\r
+\r
+/* Legacy defines */\r
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1\r
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2\r
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3\r
+\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ \r
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */\r
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */\r
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */\r
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */\r
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */\r
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ \r
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */\r
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */\r
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */\r
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */\r
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */\r
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ \r
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */\r
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */\r
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */ \r
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */\r
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */\r
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************* Bit definition for ADC_CDR register ********************/\r
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */\r
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */\r
+ \r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */\r
+#define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */\r
+#define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */\r
+#define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */\r
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */\r
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */\r
+\r
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */\r
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */\r
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */\r
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */\r
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */\r
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */\r
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */\r
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */\r
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */\r
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */\r
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */\r
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */\r
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */\r
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */\r
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/ \r
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */\r
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */\r
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */\r
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM 0x3FFFU /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0 0x0001U /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1 0x0002U /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2 0x0004U /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3 0x0008U /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4 0x0010U /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5 0x0020U /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6 0x0040U /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7 0x0080U /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8 0x0100U /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9 0x0200U /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10 0x0400U /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11 0x0800U /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12 0x1000U /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13 0x2000U /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC 0x00003FFFU /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA 0x00003FFFU /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT 0x00003FFFU /*!<Filter Active */\r
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HDMI-CEC (CEC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CEC_CR register *********************/\r
+#define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */\r
+#define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */\r
+#define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */\r
+\r
+/******************* Bit definition for CEC_CFGR register *******************/\r
+#define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */\r
+#define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */\r
+#define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */\r
+#define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */\r
+#define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Period Error generation */\r
+#define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast no Error generation */\r
+#define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */\r
+#define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */\r
+#define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */\r
+\r
+/******************* Bit definition for CEC_TXDR register *******************/\r
+#define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */\r
+\r
+/******************* Bit definition for CEC_RXDR register *******************/\r
+#define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */\r
+\r
+/******************* Bit definition for CEC_ISR register ********************/\r
+#define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */\r
+#define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */\r
+#define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */\r
+#define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */\r
+#define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */\r
+#define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */\r
+#define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */\r
+#define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */\r
+#define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */\r
+#define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */\r
+#define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */\r
+#define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */\r
+#define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */\r
+\r
+/******************* Bit definition for CEC_IER register ********************/\r
+#define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */\r
+#define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */\r
+#define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */\r
+#define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */\r
+#define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable*/\r
+#define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */\r
+#define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */\r
+#define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */\r
+#define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */\r
+#define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */\r
+#define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */\r
+#define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */\r
+#define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET 0x00000001U /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_POLYSIZE 0x00000018U /*!< Polynomial size bits */\r
+#define CRC_CR_POLYSIZE_0 0x00000008U /*!< Polynomial size bit 0 */\r
+#define CRC_CR_POLYSIZE_1 0x00000010U /*!< Polynomial size bit 1 */\r
+#define CRC_CR_REV_IN 0x00000060U /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0 0x00000020U /*!< Bit 0 */\r
+#define CRC_CR_REV_IN_1 0x00000040U /*!< Bit 1 */\r
+#define CRC_CR_REV_OUT 0x00000080U /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/******************* Bit definition for CRC_INIT register *******************/\r
+#define CRC_INIT_INIT 0xFFFFFFFFU /*!< Initial CRC value bits */\r
+\r
+/******************* Bit definition for CRC_POL register ********************/\r
+#define CRC_POL_POL 0xFFFFFFFFU /*!< Coefficients of the polynomial */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */\r
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */\r
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */\r
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */\r
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */\r
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable */\r
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */\r
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */\r
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */\r
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */\r
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enable */\r
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital Filter for Sigma Delta Modulators */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** DFSDM channel configuration registers ********************/\r
+\r
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/\r
+#define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */\r
+#define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */\r
+#define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */\r
+#define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */\r
+#define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */\r
+#define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */\r
+#define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */\r
+#define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */\r
+#define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */\r
+#define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */\r
+#define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */\r
+#define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */\r
+#define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */\r
+#define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */\r
+#define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */\r
+#define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */\r
+\r
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/\r
+#define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\r
+#define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */\r
+\r
+/****************** Bit definition for DFSDM_CHAWSCDR register *****************/\r
+#define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\r
+#define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */\r
+#define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */\r
+#define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\r
+#define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\r
+#define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */\r
+\r
+/**************** Bit definition for DFSDM_CHWDATR register *******************/\r
+#define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */\r
+\r
+/**************** Bit definition for DFSDM_CHDATINR register *****************/\r
+#define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\r
+#define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */\r
+\r
+/************************ DFSDM module registers ****************************/\r
+\r
+/******************** Bit definition for DFSDM_FLTCR1 register *******************/\r
+#define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */\r
+#define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */\r
+#define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */\r
+#define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */\r
+#define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */\r
+#define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */\r
+#define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */\r
+#define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\r
+#define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */\r
+#define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */\r
+#define DFSDM_FLTCR1_JEXTSEL 0x00001F00U /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */\r
+#define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */\r
+#define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */\r
+#define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */\r
+#define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U /*!< Trigger signal selection for launching injected conversions, Bit 3 */\r
+#define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U /*!< Trigger signal selection for launching injected conversions, Bit 4 */\r
+#define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */\r
+#define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */\r
+#define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */\r
+#define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */\r
+#define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */\r
+\r
+/******************** Bit definition for DFSDM_FLTCR2 register *******************/\r
+#define DFSDM_FLTCR2_AWDCH 0x00FF0000U /*!< AWDCH[7:0] Analog watchdog channel selection */\r
+#define DFSDM_FLTCR2_EXCH 0x0000FF00U /*!< EXCH[7:0] Extreme detector channel selection */\r
+#define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */\r
+#define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */\r
+#define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */\r
+#define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */\r
+#define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */\r
+\r
+/******************** Bit definition for DFSDM_FLTISR register *******************/\r
+#define DFSDM_FLTISR_SCDF 0xFF000000U /*!< SCDF[7:0] Short circuit detector flag */\r
+#define DFSDM_FLTISR_CKABF 0x00FF0000U /*!< CKABF[7:0] Clock absence flag */\r
+#define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */\r
+#define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */\r
+#define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */\r
+#define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */\r
+#define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */\r
+#define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */\r
+#define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */\r
+\r
+/******************** Bit definition for DFSDM_FLTICR register *******************/\r
+#define DFSDM_FLTICR_CLRSCSDF 0xFF000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\r
+#define DFSDM_FLTICR_CLRCKABF 0x00FF0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */\r
+#define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */\r
+#define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */\r
+\r
+/******************* Bit definition for DFSDM_FLTJCHGR register ******************/\r
+#define DFSDM_FLTJCHGR_JCHG 0x000000FFU /*!< JCHG[7:0] Injected channel group selection */\r
+\r
+/******************** Bit definition for DFSDM_FLTFCR register *******************/\r
+#define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */\r
+#define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */\r
+#define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */\r
+#define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */\r
+#define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\r
+#define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\r
+\r
+/****************** Bit definition for DFSDM_FLTJDATAR register *****************/\r
+#define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */\r
+#define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */\r
+\r
+/****************** Bit definition for DFSDM_FLTRDATAR register *****************/\r
+#define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */\r
+#define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */\r
+#define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWHTR register ******************/\r
+#define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */\r
+#define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWLTR register ******************/\r
+#define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */\r
+#define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWSR register ******************/\r
+#define DFSDM_FLTAWSR_AWHTF 0x0000FF00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\r
+#define DFSDM_FLTAWSR_AWLTF 0x000000FFU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWCFR register *****************/\r
+#define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\r
+#define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\r
+\r
+/****************** Bit definition for DFSDM_FLTEXMAX register ******************/\r
+#define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */\r
+#define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\r
+\r
+/****************** Bit definition for DFSDM_FLTEXMIN register ******************/\r
+#define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */\r
+#define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */\r
+\r
+/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/\r
+#define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DCMI */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DCMI_CR register ******************/\r
+#define DCMI_CR_CAPTURE 0x00000001U\r
+#define DCMI_CR_CM 0x00000002U\r
+#define DCMI_CR_CROP 0x00000004U\r
+#define DCMI_CR_JPEG 0x00000008U\r
+#define DCMI_CR_ESS 0x00000010U\r
+#define DCMI_CR_PCKPOL 0x00000020U\r
+#define DCMI_CR_HSPOL 0x00000040U\r
+#define DCMI_CR_VSPOL 0x00000080U\r
+#define DCMI_CR_FCRC_0 0x00000100U\r
+#define DCMI_CR_FCRC_1 0x00000200U\r
+#define DCMI_CR_EDM_0 0x00000400U\r
+#define DCMI_CR_EDM_1 0x00000800U\r
+#define DCMI_CR_CRE 0x00001000U\r
+#define DCMI_CR_ENABLE 0x00004000U\r
+#define DCMI_CR_BSM 0x00030000U\r
+#define DCMI_CR_BSM_0 0x00010000U\r
+#define DCMI_CR_BSM_1 0x00020000U\r
+#define DCMI_CR_OEBS 0x00040000U\r
+#define DCMI_CR_LSM 0x00080000U\r
+#define DCMI_CR_OELS 0x00100000U\r
+\r
+/******************** Bits definition for DCMI_SR register ******************/\r
+#define DCMI_SR_HSYNC 0x00000001U\r
+#define DCMI_SR_VSYNC 0x00000002U\r
+#define DCMI_SR_FNE 0x00000004U\r
+\r
+/******************** Bits definition for DCMI_RIS register ****************/\r
+#define DCMI_RIS_FRAME_RIS 0x00000001U\r
+#define DCMI_RIS_OVR_RIS 0x00000002U\r
+#define DCMI_RIS_ERR_RIS 0x00000004U\r
+#define DCMI_RIS_VSYNC_RIS 0x00000008U\r
+#define DCMI_RIS_LINE_RIS 0x00000010U\r
+\r
+/* Legacy defines */\r
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS\r
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS\r
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS\r
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS\r
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS\r
+\r
+/******************** Bits definition for DCMI_IER register *****************/\r
+#define DCMI_IER_FRAME_IE 0x00000001U\r
+#define DCMI_IER_OVR_IE 0x00000002U\r
+#define DCMI_IER_ERR_IE 0x00000004U\r
+#define DCMI_IER_VSYNC_IE 0x00000008U\r
+#define DCMI_IER_LINE_IE 0x00000010U\r
+\r
+\r
+/******************** Bits definition for DCMI_MIS register *****************/\r
+#define DCMI_MIS_FRAME_MIS 0x00000001U\r
+#define DCMI_MIS_OVR_MIS 0x00000002U\r
+#define DCMI_MIS_ERR_MIS 0x00000004U\r
+#define DCMI_MIS_VSYNC_MIS 0x00000008U\r
+#define DCMI_MIS_LINE_MIS 0x00000010U\r
+\r
+\r
+/******************** Bits definition for DCMI_ICR register *****************/\r
+#define DCMI_ICR_FRAME_ISC 0x00000001U\r
+#define DCMI_ICR_OVR_ISC 0x00000002U\r
+#define DCMI_ICR_ERR_ISC 0x00000004U\r
+#define DCMI_ICR_VSYNC_ISC 0x00000008U\r
+#define DCMI_ICR_LINE_ISC 0x00000010U\r
+\r
+\r
+/******************** Bits definition for DCMI_ESCR register ******************/\r
+#define DCMI_ESCR_FSC 0x000000FFU\r
+#define DCMI_ESCR_LSC 0x0000FF00U\r
+#define DCMI_ESCR_LEC 0x00FF0000U\r
+#define DCMI_ESCR_FEC 0xFF000000U\r
+\r
+/******************** Bits definition for DCMI_ESUR register ******************/\r
+#define DCMI_ESUR_FSU 0x000000FFU\r
+#define DCMI_ESUR_LSU 0x0000FF00U\r
+#define DCMI_ESUR_LEU 0x00FF0000U\r
+#define DCMI_ESUR_FEU 0xFF000000U\r
+\r
+/******************** Bits definition for DCMI_CWSTRT register ******************/\r
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU\r
+#define DCMI_CWSTRT_VST 0x1FFF0000U\r
+\r
+/******************** Bits definition for DCMI_CWSIZE register ******************/\r
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU\r
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U\r
+\r
+/******************** Bits definition for DCMI_DR register ******************/\r
+#define DCMI_DR_BYTE0 0x000000FFU\r
+#define DCMI_DR_BYTE1 0x0000FF00U\r
+#define DCMI_DR_BYTE2 0x00FF0000U\r
+#define DCMI_DR_BYTE3 0xFF000000U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/ \r
+#define DMA_SxCR_CHSEL 0x1E000000U\r
+#define DMA_SxCR_CHSEL_0 0x02000000U\r
+#define DMA_SxCR_CHSEL_1 0x04000000U\r
+#define DMA_SxCR_CHSEL_2 0x08000000U \r
+#define DMA_SxCR_CHSEL_3 0x10000000U\r
+#define DMA_SxCR_MBURST 0x01800000U\r
+#define DMA_SxCR_MBURST_0 0x00800000U\r
+#define DMA_SxCR_MBURST_1 0x01000000U\r
+#define DMA_SxCR_PBURST 0x00600000U\r
+#define DMA_SxCR_PBURST_0 0x00200000U\r
+#define DMA_SxCR_PBURST_1 0x00400000U\r
+#define DMA_SxCR_CT 0x00080000U \r
+#define DMA_SxCR_DBM 0x00040000U\r
+#define DMA_SxCR_PL 0x00030000U\r
+#define DMA_SxCR_PL_0 0x00010000U\r
+#define DMA_SxCR_PL_1 0x00020000U\r
+#define DMA_SxCR_PINCOS 0x00008000U\r
+#define DMA_SxCR_MSIZE 0x00006000U\r
+#define DMA_SxCR_MSIZE_0 0x00002000U\r
+#define DMA_SxCR_MSIZE_1 0x00004000U\r
+#define DMA_SxCR_PSIZE 0x00001800U\r
+#define DMA_SxCR_PSIZE_0 0x00000800U\r
+#define DMA_SxCR_PSIZE_1 0x00001000U\r
+#define DMA_SxCR_MINC 0x00000400U\r
+#define DMA_SxCR_PINC 0x00000200U\r
+#define DMA_SxCR_CIRC 0x00000100U\r
+#define DMA_SxCR_DIR 0x000000C0U\r
+#define DMA_SxCR_DIR_0 0x00000040U\r
+#define DMA_SxCR_DIR_1 0x00000080U\r
+#define DMA_SxCR_PFCTRL 0x00000020U\r
+#define DMA_SxCR_TCIE 0x00000010U\r
+#define DMA_SxCR_HTIE 0x00000008U\r
+#define DMA_SxCR_TEIE 0x00000004U\r
+#define DMA_SxCR_DMEIE 0x00000002U\r
+#define DMA_SxCR_EN 0x00000001U\r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT 0x0000FFFFU\r
+#define DMA_SxNDT_0 0x00000001U\r
+#define DMA_SxNDT_1 0x00000002U\r
+#define DMA_SxNDT_2 0x00000004U\r
+#define DMA_SxNDT_3 0x00000008U\r
+#define DMA_SxNDT_4 0x00000010U\r
+#define DMA_SxNDT_5 0x00000020U\r
+#define DMA_SxNDT_6 0x00000040U\r
+#define DMA_SxNDT_7 0x00000080U\r
+#define DMA_SxNDT_8 0x00000100U\r
+#define DMA_SxNDT_9 0x00000200U\r
+#define DMA_SxNDT_10 0x00000400U\r
+#define DMA_SxNDT_11 0x00000800U\r
+#define DMA_SxNDT_12 0x00001000U\r
+#define DMA_SxNDT_13 0x00002000U\r
+#define DMA_SxNDT_14 0x00004000U\r
+#define DMA_SxNDT_15 0x00008000U\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/ \r
+#define DMA_SxFCR_FEIE 0x00000080U\r
+#define DMA_SxFCR_FS 0x00000038U\r
+#define DMA_SxFCR_FS_0 0x00000008U\r
+#define DMA_SxFCR_FS_1 0x00000010U\r
+#define DMA_SxFCR_FS_2 0x00000020U\r
+#define DMA_SxFCR_DMDIS 0x00000004U\r
+#define DMA_SxFCR_FTH 0x00000003U\r
+#define DMA_SxFCR_FTH_0 0x00000001U\r
+#define DMA_SxFCR_FTH_1 0x00000002U\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/ \r
+#define DMA_LISR_TCIF3 0x08000000U\r
+#define DMA_LISR_HTIF3 0x04000000U\r
+#define DMA_LISR_TEIF3 0x02000000U\r
+#define DMA_LISR_DMEIF3 0x01000000U\r
+#define DMA_LISR_FEIF3 0x00400000U\r
+#define DMA_LISR_TCIF2 0x00200000U\r
+#define DMA_LISR_HTIF2 0x00100000U\r
+#define DMA_LISR_TEIF2 0x00080000U\r
+#define DMA_LISR_DMEIF2 0x00040000U\r
+#define DMA_LISR_FEIF2 0x00010000U\r
+#define DMA_LISR_TCIF1 0x00000800U\r
+#define DMA_LISR_HTIF1 0x00000400U\r
+#define DMA_LISR_TEIF1 0x00000200U\r
+#define DMA_LISR_DMEIF1 0x00000100U\r
+#define DMA_LISR_FEIF1 0x00000040U\r
+#define DMA_LISR_TCIF0 0x00000020U\r
+#define DMA_LISR_HTIF0 0x00000010U\r
+#define DMA_LISR_TEIF0 0x00000008U\r
+#define DMA_LISR_DMEIF0 0x00000004U\r
+#define DMA_LISR_FEIF0 0x00000001U\r
+\r
+/******************** Bits definition for DMA_HISR register *****************/ \r
+#define DMA_HISR_TCIF7 0x08000000U\r
+#define DMA_HISR_HTIF7 0x04000000U\r
+#define DMA_HISR_TEIF7 0x02000000U\r
+#define DMA_HISR_DMEIF7 0x01000000U\r
+#define DMA_HISR_FEIF7 0x00400000U\r
+#define DMA_HISR_TCIF6 0x00200000U\r
+#define DMA_HISR_HTIF6 0x00100000U\r
+#define DMA_HISR_TEIF6 0x00080000U\r
+#define DMA_HISR_DMEIF6 0x00040000U\r
+#define DMA_HISR_FEIF6 0x00010000U\r
+#define DMA_HISR_TCIF5 0x00000800U\r
+#define DMA_HISR_HTIF5 0x00000400U\r
+#define DMA_HISR_TEIF5 0x00000200U\r
+#define DMA_HISR_DMEIF5 0x00000100U\r
+#define DMA_HISR_FEIF5 0x00000040U\r
+#define DMA_HISR_TCIF4 0x00000020U\r
+#define DMA_HISR_HTIF4 0x00000010U\r
+#define DMA_HISR_TEIF4 0x00000008U\r
+#define DMA_HISR_DMEIF4 0x00000004U\r
+#define DMA_HISR_FEIF4 0x00000001U\r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/ \r
+#define DMA_LIFCR_CTCIF3 0x08000000U\r
+#define DMA_LIFCR_CHTIF3 0x04000000U\r
+#define DMA_LIFCR_CTEIF3 0x02000000U\r
+#define DMA_LIFCR_CDMEIF3 0x01000000U\r
+#define DMA_LIFCR_CFEIF3 0x00400000U\r
+#define DMA_LIFCR_CTCIF2 0x00200000U\r
+#define DMA_LIFCR_CHTIF2 0x00100000U\r
+#define DMA_LIFCR_CTEIF2 0x00080000U\r
+#define DMA_LIFCR_CDMEIF2 0x00040000U\r
+#define DMA_LIFCR_CFEIF2 0x00010000U\r
+#define DMA_LIFCR_CTCIF1 0x00000800U\r
+#define DMA_LIFCR_CHTIF1 0x00000400U\r
+#define DMA_LIFCR_CTEIF1 0x00000200U\r
+#define DMA_LIFCR_CDMEIF1 0x00000100U\r
+#define DMA_LIFCR_CFEIF1 0x00000040U\r
+#define DMA_LIFCR_CTCIF0 0x00000020U\r
+#define DMA_LIFCR_CHTIF0 0x00000010U\r
+#define DMA_LIFCR_CTEIF0 0x00000008U\r
+#define DMA_LIFCR_CDMEIF0 0x00000004U\r
+#define DMA_LIFCR_CFEIF0 0x00000001U\r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/ \r
+#define DMA_HIFCR_CTCIF7 0x08000000U\r
+#define DMA_HIFCR_CHTIF7 0x04000000U\r
+#define DMA_HIFCR_CTEIF7 0x02000000U\r
+#define DMA_HIFCR_CDMEIF7 0x01000000U\r
+#define DMA_HIFCR_CFEIF7 0x00400000U\r
+#define DMA_HIFCR_CTCIF6 0x00200000U\r
+#define DMA_HIFCR_CHTIF6 0x00100000U\r
+#define DMA_HIFCR_CTEIF6 0x00080000U\r
+#define DMA_HIFCR_CDMEIF6 0x00040000U\r
+#define DMA_HIFCR_CFEIF6 0x00010000U\r
+#define DMA_HIFCR_CTCIF5 0x00000800U\r
+#define DMA_HIFCR_CHTIF5 0x00000400U\r
+#define DMA_HIFCR_CTEIF5 0x00000200U\r
+#define DMA_HIFCR_CDMEIF5 0x00000100U\r
+#define DMA_HIFCR_CFEIF5 0x00000040U\r
+#define DMA_HIFCR_CTCIF4 0x00000020U\r
+#define DMA_HIFCR_CHTIF4 0x00000010U\r
+#define DMA_HIFCR_CTEIF4 0x00000008U\r
+#define DMA_HIFCR_CDMEIF4 0x00000004U\r
+#define DMA_HIFCR_CFEIF4 0x00000001U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* AHB Master DMA2D Controller (DMA2D) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DMA2D_CR register ******************/\r
+\r
+#define DMA2D_CR_START 0x00000001U /*!< Start transfer */\r
+#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */\r
+#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */\r
+#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */\r
+#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */\r
+#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */\r
+#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */\r
+#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */\r
+#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */\r
+#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */\r
+\r
+/******************** Bit definition for DMA2D_ISR register *****************/\r
+\r
+#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */\r
+#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */\r
+#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_IFCR register ****************/\r
+\r
+#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/* Legacy defines */\r
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_FGMAR register ***************/\r
+\r
+#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_FGOR register ****************/\r
+\r
+#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_BGMAR register ***************/\r
+\r
+#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGOR register ****************/\r
+\r
+#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_FGPFCCR register *************/\r
+\r
+#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */\r
+#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */\r
+#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */\r
+#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */\r
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */\r
+#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */\r
+#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */\r
+#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */\r
+#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */\r
+#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */\r
+#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */\r
+#define DMA2D_FGPFCCR_AI 0x00100000U /*!< Foreground Input Alpha Inverted */\r
+#define DMA2D_FGPFCCR_RBS 0x00200000U /*!< Foreground Input Red Blue Swap */\r
+#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_FGCOLR register **************/\r
+\r
+#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */\r
+#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */\r
+#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */ \r
+\r
+/******************** Bit definition for DMA2D_BGPFCCR register *************/\r
+\r
+#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */\r
+#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */\r
+#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */\r
+#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */\r
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */\r
+#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */\r
+#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */\r
+#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */\r
+#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */\r
+#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */\r
+#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */\r
+#define DMA2D_BGPFCCR_AI 0x00100000U /*!< background Input Alpha Inverted */\r
+#define DMA2D_BGPFCCR_RBS 0x00200000U /*!< Background Input Red Blue Swap */\r
+#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_BGCOLR register **************/\r
+\r
+#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */\r
+#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */\r
+#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */\r
+\r
+/******************** Bit definition for DMA2D_FGCMAR register **************/\r
+\r
+#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGCMAR register **************/\r
+\r
+#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OPFCCR register **************/\r
+\r
+#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */\r
+#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */\r
+#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */\r
+#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */\r
+#define DMA2D_OPFCCR_AI 0x00100000U /*!< Output Alpha Inverted */\r
+#define DMA2D_OPFCCR_RBS 0x00200000U /*!< Output Red Blue Swap */\r
+\r
+/******************** Bit definition for DMA2D_OCOLR register ***************/\r
+\r
+/*!<Mode_ARGB8888/RGB888 */\r
+\r
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_RGB565 */\r
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */\r
+\r
+/*!<Mode_ARGB1555 */\r
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_ARGB4444 */\r
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */\r
+\r
+/******************** Bit definition for DMA2D_OMAR register ****************/\r
+\r
+#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OOR register *****************/\r
+\r
+#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_NLR register *****************/\r
+\r
+#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */\r
+#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */\r
+\r
+/******************** Bit definition for DMA2D_LWR register *****************/\r
+\r
+#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */\r
+\r
+/******************** Bit definition for DMA2D_AMTCR register ***************/\r
+\r
+#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */\r
+#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */\r
+\r
+\r
+/******************** Bit definition for DMA2D_FGCLUT register **************/\r
+ \r
+/******************** Bit definition for DMA2D_BGCLUT register **************/\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */\r
+#define EXTI_IMR_MR24 0x01000000U /*!< Interrupt Mask on line 24 */\r
+\r
+/* Reference Defines */\r
+#define EXTI_IMR_IM0 EXTI_IMR_MR0 \r
+#define EXTI_IMR_IM1 EXTI_IMR_MR1 \r
+#define EXTI_IMR_IM2 EXTI_IMR_MR2 \r
+#define EXTI_IMR_IM3 EXTI_IMR_MR3 \r
+#define EXTI_IMR_IM4 EXTI_IMR_MR4 \r
+#define EXTI_IMR_IM5 EXTI_IMR_MR5 \r
+#define EXTI_IMR_IM6 EXTI_IMR_MR6 \r
+#define EXTI_IMR_IM7 EXTI_IMR_MR7 \r
+#define EXTI_IMR_IM8 EXTI_IMR_MR8 \r
+#define EXTI_IMR_IM9 EXTI_IMR_MR9 \r
+#define EXTI_IMR_IM10 EXTI_IMR_MR10\r
+#define EXTI_IMR_IM11 EXTI_IMR_MR11\r
+#define EXTI_IMR_IM12 EXTI_IMR_MR12\r
+#define EXTI_IMR_IM13 EXTI_IMR_MR13\r
+#define EXTI_IMR_IM14 EXTI_IMR_MR14\r
+#define EXTI_IMR_IM15 EXTI_IMR_MR15\r
+#define EXTI_IMR_IM16 EXTI_IMR_MR16\r
+#define EXTI_IMR_IM17 EXTI_IMR_MR17\r
+#define EXTI_IMR_IM18 EXTI_IMR_MR18\r
+#define EXTI_IMR_IM19 EXTI_IMR_MR19\r
+#define EXTI_IMR_IM20 EXTI_IMR_MR20\r
+#define EXTI_IMR_IM21 EXTI_IMR_MR21\r
+#define EXTI_IMR_IM22 EXTI_IMR_MR22\r
+#define EXTI_IMR_IM23 EXTI_IMR_MR23\r
+#define EXTI_IMR_IM24 EXTI_IMR_MR24\r
+\r
+#define EXTI_IMR_IM 0x01FFFFFFU /*!< Interrupt Mask All */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */\r
+#define EXTI_EMR_MR24 0x01000000U /*!< Event Mask on line 24 */\r
+\r
+/* Reference Defines */\r
+#define EXTI_EMR_EM0 EXTI_EMR_MR0 \r
+#define EXTI_EMR_EM1 EXTI_EMR_MR1 \r
+#define EXTI_EMR_EM2 EXTI_EMR_MR2 \r
+#define EXTI_EMR_EM3 EXTI_EMR_MR3 \r
+#define EXTI_EMR_EM4 EXTI_EMR_MR4 \r
+#define EXTI_EMR_EM5 EXTI_EMR_MR5 \r
+#define EXTI_EMR_EM6 EXTI_EMR_MR6 \r
+#define EXTI_EMR_EM7 EXTI_EMR_MR7 \r
+#define EXTI_EMR_EM8 EXTI_EMR_MR8 \r
+#define EXTI_EMR_EM9 EXTI_EMR_MR9 \r
+#define EXTI_EMR_EM10 EXTI_EMR_MR10\r
+#define EXTI_EMR_EM11 EXTI_EMR_MR11\r
+#define EXTI_EMR_EM12 EXTI_EMR_MR12\r
+#define EXTI_EMR_EM13 EXTI_EMR_MR13\r
+#define EXTI_EMR_EM14 EXTI_EMR_MR14\r
+#define EXTI_EMR_EM15 EXTI_EMR_MR15\r
+#define EXTI_EMR_EM16 EXTI_EMR_MR16\r
+#define EXTI_EMR_EM17 EXTI_EMR_MR17\r
+#define EXTI_EMR_EM18 EXTI_EMR_MR18\r
+#define EXTI_EMR_EM19 EXTI_EMR_MR19\r
+#define EXTI_EMR_EM20 EXTI_EMR_MR20\r
+#define EXTI_EMR_EM21 EXTI_EMR_MR21\r
+#define EXTI_EMR_EM22 EXTI_EMR_MR22\r
+#define EXTI_EMR_EM23 EXTI_EMR_MR23\r
+#define EXTI_EMR_EM24 EXTI_EMR_MR24\r
+\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */\r
+#define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */\r
+#define EXTI_RTSR_TR24 0x01000000U /*!< Rising trigger event configuration bit of line 24 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */\r
+#define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */\r
+#define EXTI_FTSR_TR24 0x01000000U /*!< Falling trigger event configuration bit of line 24 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */\r
+#define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */\r
+#define EXTI_SWIER_SWIER24 0x01000000U /*!< Software Interrupt on line 24 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */\r
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */\r
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */\r
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */\r
+#define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */\r
+#define EXTI_PR_PR24 0x01000000U /*!< Pending bit for line 24 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+* @brief FLASH Total Sectors Number\r
+*/\r
+#define FLASH_SECTOR_TOTAL 24\r
+\r
+/******************* Bits definition for FLASH_ACR register *****************/\r
+#define FLASH_ACR_LATENCY 0x0000000FU\r
+#define FLASH_ACR_LATENCY_0WS 0x00000000U\r
+#define FLASH_ACR_LATENCY_1WS 0x00000001U\r
+#define FLASH_ACR_LATENCY_2WS 0x00000002U\r
+#define FLASH_ACR_LATENCY_3WS 0x00000003U\r
+#define FLASH_ACR_LATENCY_4WS 0x00000004U\r
+#define FLASH_ACR_LATENCY_5WS 0x00000005U\r
+#define FLASH_ACR_LATENCY_6WS 0x00000006U\r
+#define FLASH_ACR_LATENCY_7WS 0x00000007U\r
+#define FLASH_ACR_LATENCY_8WS 0x00000008U\r
+#define FLASH_ACR_LATENCY_9WS 0x00000009U\r
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU\r
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU\r
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU\r
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU\r
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU\r
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU\r
+#define FLASH_ACR_PRFTEN 0x00000100U\r
+#define FLASH_ACR_ARTEN 0x00000200U\r
+#define FLASH_ACR_ARTRST 0x00000800U\r
+\r
+/******************* Bits definition for FLASH_SR register ******************/\r
+#define FLASH_SR_EOP 0x00000001U\r
+#define FLASH_SR_OPERR 0x00000002U\r
+#define FLASH_SR_WRPERR 0x00000010U\r
+#define FLASH_SR_PGAERR 0x00000020U\r
+#define FLASH_SR_PGPERR 0x00000040U\r
+#define FLASH_SR_ERSERR 0x00000080U\r
+#define FLASH_SR_BSY 0x00010000U\r
+\r
+/******************* Bits definition for FLASH_CR register ******************/\r
+#define FLASH_CR_PG 0x00000001U\r
+#define FLASH_CR_SER 0x00000002U\r
+#define FLASH_CR_MER 0x00000004U\r
+#define FLASH_CR_MER1 FLASH_CR_MER\r
+#define FLASH_CR_SNB 0x000000F8U\r
+#define FLASH_CR_SNB_0 0x00000008U\r
+#define FLASH_CR_SNB_1 0x00000010U\r
+#define FLASH_CR_SNB_2 0x00000020U\r
+#define FLASH_CR_SNB_3 0x00000040U\r
+#define FLASH_CR_SNB_4 0x00000080U\r
+#define FLASH_CR_PSIZE 0x00000300U\r
+#define FLASH_CR_PSIZE_0 0x00000100U\r
+#define FLASH_CR_PSIZE_1 0x00000200U\r
+#define FLASH_CR_MER2 0x00008000U\r
+#define FLASH_CR_STRT 0x00010000U\r
+#define FLASH_CR_EOPIE 0x01000000U\r
+#define FLASH_CR_ERRIE 0x02000000U\r
+#define FLASH_CR_LOCK 0x80000000U\r
+\r
+/******************* Bits definition for FLASH_OPTCR register ***************/\r
+#define FLASH_OPTCR_OPTLOCK 0x00000001U\r
+#define FLASH_OPTCR_OPTSTRT 0x00000002U\r
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU\r
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U\r
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U\r
+#define FLASH_OPTCR_WWDG_SW 0x00000010U\r
+#define FLASH_OPTCR_IWDG_SW 0x00000020U\r
+#define FLASH_OPTCR_nRST_STOP 0x00000040U\r
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U\r
+#define FLASH_OPTCR_RDP 0x0000FF00U\r
+#define FLASH_OPTCR_RDP_0 0x00000100U\r
+#define FLASH_OPTCR_RDP_1 0x00000200U\r
+#define FLASH_OPTCR_RDP_2 0x00000400U\r
+#define FLASH_OPTCR_RDP_3 0x00000800U\r
+#define FLASH_OPTCR_RDP_4 0x00001000U\r
+#define FLASH_OPTCR_RDP_5 0x00002000U\r
+#define FLASH_OPTCR_RDP_6 0x00004000U\r
+#define FLASH_OPTCR_RDP_7 0x00008000U\r
+#define FLASH_OPTCR_nWRP 0x0FFF0000U\r
+#define FLASH_OPTCR_nWRP_0 0x00010000U\r
+#define FLASH_OPTCR_nWRP_1 0x00020000U\r
+#define FLASH_OPTCR_nWRP_2 0x00040000U\r
+#define FLASH_OPTCR_nWRP_3 0x00080000U\r
+#define FLASH_OPTCR_nWRP_4 0x00100000U\r
+#define FLASH_OPTCR_nWRP_5 0x00200000U\r
+#define FLASH_OPTCR_nWRP_6 0x00400000U\r
+#define FLASH_OPTCR_nWRP_7 0x00800000U\r
+#define FLASH_OPTCR_nWRP_8 0x01000000U\r
+#define FLASH_OPTCR_nWRP_9 0x02000000U\r
+#define FLASH_OPTCR_nWRP_10 0x04000000U\r
+#define FLASH_OPTCR_nWRP_11 0x08000000U\r
+#define FLASH_OPTCR_nDBOOT 0x10000000U\r
+#define FLASH_OPTCR_nDBANK 0x20000000U\r
+#define FLASH_OPTCR_IWDG_STDBY 0x40000000U\r
+#define FLASH_OPTCR_IWDG_STOP 0x80000000U\r
+\r
+/******************* Bits definition for FLASH_OPTCR1 register ***************/\r
+#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU\r
+#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FMC_BCR1 register *******************/\r
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */\r
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */\r
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */\r
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */\r
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */\r
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */\r
+#define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */\r
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */\r
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */\r
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */\r
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */\r
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */\r
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */\r
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */\r
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */\r
+#define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */\r
+\r
+/****************** Bit definition for FMC_BCR2 register *******************/\r
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */\r
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */\r
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */\r
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */\r
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */\r
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */\r
+#define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */\r
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */\r
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */\r
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */\r
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */\r
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */\r
+#define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */\r
+#define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR3 register *******************/\r
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */\r
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */\r
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */\r
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */\r
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */\r
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */\r
+#define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */\r
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */\r
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */\r
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */\r
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */\r
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */\r
+#define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */\r
+#define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR4 register *******************/\r
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */\r
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */\r
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */\r
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */\r
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */\r
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */\r
+#define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */\r
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */\r
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */\r
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */\r
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */\r
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */\r
+#define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */\r
+#define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BTR1 register ******************/\r
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */\r
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */\r
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */\r
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */\r
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */\r
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */\r
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR2 register *******************/\r
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */\r
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */\r
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */\r
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */\r
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */\r
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */\r
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/******************* Bit definition for FMC_BTR3 register *******************/\r
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */\r
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */\r
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */\r
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */\r
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */\r
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */\r
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR4 register *******************/\r
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */\r
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */\r
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */\r
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */\r
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */\r
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */\r
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR1 register ******************/\r
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR2 register ******************/\r
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR3 register ******************/\r
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR4 register ******************/\r
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */\r
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_PCR register *******************/\r
+#define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */\r
+#define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR_PTYP 0x00000008U /*!<Memory type */\r
+#define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */\r
+#define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */\r
+#define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */\r
+#define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */\r
+#define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */\r
+#define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */\r
+#define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */\r
+#define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */\r
+#define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */\r
+#define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */\r
+#define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */\r
+#define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */\r
+\r
+/******************* Bit definition for FMC_SR register *******************/\r
+#define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */\r
+#define FMC_SR_ILS 0x02U /*!<Interrupt Level status */\r
+#define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */\r
+#define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR_FEMPT 0x40U /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FMC_PMEM register ******************/\r
+#define FMC_PMEM_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FMC_PMEM_MEMSET3_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_PMEM_MEMSET3_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_PMEM_MEMSET3_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_PMEM_MEMSET3_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_PMEM_MEMSET3_4 0x00000010U /*!<Bit 4 */\r
+#define FMC_PMEM_MEMSET3_5 0x00000020U /*!<Bit 5 */\r
+#define FMC_PMEM_MEMSET3_6 0x00000040U /*!<Bit 6 */\r
+#define FMC_PMEM_MEMSET3_7 0x00000080U /*!<Bit 7 */\r
+#define FMC_PMEM_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FMC_PMEM_MEMWAIT3_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_PMEM_MEMWAIT3_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_PMEM_MEMWAIT3_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_PMEM_MEMWAIT3_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_PMEM_MEMWAIT3_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_PMEM_MEMWAIT3_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_PMEM_MEMWAIT3_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_PMEM_MEMWAIT3_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_PMEM_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FMC_PMEM_MEMHOLD3_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_PMEM_MEMHOLD3_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_PMEM_MEMHOLD3_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_PMEM_MEMHOLD3_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_PMEM_MEMHOLD3_4 0x00100000U /*!<Bit 4 */\r
+#define FMC_PMEM_MEMHOLD3_5 0x00200000U /*!<Bit 5 */\r
+#define FMC_PMEM_MEMHOLD3_6 0x00400000U /*!<Bit 6 */\r
+#define FMC_PMEM_MEMHOLD3_7 0x00800000U /*!<Bit 7 */\r
+#define FMC_PMEM_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FMC_PMEM_MEMHIZ3_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_PMEM_MEMHIZ3_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_PMEM_MEMHIZ3_2 0x04000000U /*!<Bit 2 */\r
+#define FMC_PMEM_MEMHIZ3_3 0x08000000U /*!<Bit 3 */\r
+#define FMC_PMEM_MEMHIZ3_4 0x10000000U /*!<Bit 4 */\r
+#define FMC_PMEM_MEMHIZ3_5 0x20000000U /*!<Bit 5 */\r
+#define FMC_PMEM_MEMHIZ3_6 0x40000000U /*!<Bit 6 */\r
+#define FMC_PMEM_MEMHIZ3_7 0x80000000U /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PATT register ******************/\r
+#define FMC_PATT_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FMC_PATT_ATTSET3_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_PATT_ATTSET3_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_PATT_ATTSET3_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_PATT_ATTSET3_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_PATT_ATTSET3_4 0x00000010U /*!<Bit 4 */\r
+#define FMC_PATT_ATTSET3_5 0x00000020U /*!<Bit 5 */\r
+#define FMC_PATT_ATTSET3_6 0x00000040U /*!<Bit 6 */\r
+#define FMC_PATT_ATTSET3_7 0x00000080U /*!<Bit 7 */\r
+#define FMC_PATT_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FMC_PATT_ATTWAIT3_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_PATT_ATTWAIT3_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_PATT_ATTWAIT3_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_PATT_ATTWAIT3_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_PATT_ATTWAIT3_4 0x00001000U /*!<Bit 4 */\r
+#define FMC_PATT_ATTWAIT3_5 0x00002000U /*!<Bit 5 */\r
+#define FMC_PATT_ATTWAIT3_6 0x00004000U /*!<Bit 6 */\r
+#define FMC_PATT_ATTWAIT3_7 0x00008000U /*!<Bit 7 */\r
+#define FMC_PATT_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FMC_PATT_ATTHOLD3_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_PATT_ATTHOLD3_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_PATT_ATTHOLD3_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_PATT_ATTHOLD3_3 0x00080000U /*!<Bit 3 */\r
+#define FMC_PATT_ATTHOLD3_4 0x00100000U /*!<Bit 4 */\r
+#define FMC_PATT_ATTHOLD3_5 0x00200000U /*!<Bit 5 */\r
+#define FMC_PATT_ATTHOLD3_6 0x00400000U /*!<Bit 6 */\r
+#define FMC_PATT_ATTHOLD3_7 0x00800000U /*!<Bit 7 */\r
+#define FMC_PATT_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FMC_PATT_ATTHIZ3_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_PATT_ATTHIZ3_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_PATT_ATTHIZ3_2 0x04000000U /*!<Bit 2 */\r
+#define FMC_PATT_ATTHIZ3_3 0x08000000U /*!<Bit 3 */\r
+#define FMC_PATT_ATTHIZ3_4 0x10000000U /*!<Bit 4 */\r
+#define FMC_PATT_ATTHIZ3_5 0x20000000U /*!<Bit 5 */\r
+#define FMC_PATT_ATTHIZ3_6 0x40000000U /*!<Bit 6 */\r
+#define FMC_PATT_ATTHIZ3_7 0x80000000U /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_ECCR register ******************/\r
+#define FMC_ECCR_ECC3 0xFFFFFFFFU /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_SDCR1 register ******************/\r
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */\r
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */\r
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */\r
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */\r
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */\r
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */\r
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */\r
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */\r
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */\r
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */\r
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */\r
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */\r
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDCR2 register ******************/\r
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */\r
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */\r
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */\r
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */\r
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */\r
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */\r
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */\r
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */\r
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */\r
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */\r
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */\r
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDTR1 register ******************/\r
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */\r
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */\r
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */\r
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */\r
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */\r
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */\r
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDTR2 register ******************/\r
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */\r
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */\r
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */\r
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */\r
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */\r
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */\r
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */\r
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */\r
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */\r
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */\r
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */\r
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */\r
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */\r
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */\r
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */\r
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */\r
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */\r
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */\r
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */\r
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */\r
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */\r
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDCMR register ******************/\r
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */\r
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */\r
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */\r
+#define FMC_SDCMR_MODE_2 0x00000003U /*!<Bit 2 */\r
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */\r
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */\r
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */\r
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */\r
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */\r
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */\r
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/****************** Bit definition for FMC_SDRTR register ******************/\r
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */\r
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */\r
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */\r
+\r
+/****************** Bit definition for FMC_SDSR register ******************/\r
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */\r
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */\r
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */\r
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */\r
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */\r
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0 0x00000003U\r
+#define GPIO_MODER_MODER0_0 0x00000001U\r
+#define GPIO_MODER_MODER0_1 0x00000002U\r
+#define GPIO_MODER_MODER1 0x0000000CU\r
+#define GPIO_MODER_MODER1_0 0x00000004U\r
+#define GPIO_MODER_MODER1_1 0x00000008U\r
+#define GPIO_MODER_MODER2 0x00000030U\r
+#define GPIO_MODER_MODER2_0 0x00000010U\r
+#define GPIO_MODER_MODER2_1 0x00000020U\r
+#define GPIO_MODER_MODER3 0x000000C0U\r
+#define GPIO_MODER_MODER3_0 0x00000040U\r
+#define GPIO_MODER_MODER3_1 0x00000080U\r
+#define GPIO_MODER_MODER4 0x00000300U\r
+#define GPIO_MODER_MODER4_0 0x00000100U\r
+#define GPIO_MODER_MODER4_1 0x00000200U\r
+#define GPIO_MODER_MODER5 0x00000C00U\r
+#define GPIO_MODER_MODER5_0 0x00000400U\r
+#define GPIO_MODER_MODER5_1 0x00000800U\r
+#define GPIO_MODER_MODER6 0x00003000U\r
+#define GPIO_MODER_MODER6_0 0x00001000U\r
+#define GPIO_MODER_MODER6_1 0x00002000U\r
+#define GPIO_MODER_MODER7 0x0000C000U\r
+#define GPIO_MODER_MODER7_0 0x00004000U\r
+#define GPIO_MODER_MODER7_1 0x00008000U\r
+#define GPIO_MODER_MODER8 0x00030000U\r
+#define GPIO_MODER_MODER8_0 0x00010000U\r
+#define GPIO_MODER_MODER8_1 0x00020000U\r
+#define GPIO_MODER_MODER9 0x000C0000U\r
+#define GPIO_MODER_MODER9_0 0x00040000U\r
+#define GPIO_MODER_MODER9_1 0x00080000U\r
+#define GPIO_MODER_MODER10 0x00300000U\r
+#define GPIO_MODER_MODER10_0 0x00100000U\r
+#define GPIO_MODER_MODER10_1 0x00200000U\r
+#define GPIO_MODER_MODER11 0x00C00000U\r
+#define GPIO_MODER_MODER11_0 0x00400000U\r
+#define GPIO_MODER_MODER11_1 0x00800000U\r
+#define GPIO_MODER_MODER12 0x03000000U\r
+#define GPIO_MODER_MODER12_0 0x01000000U\r
+#define GPIO_MODER_MODER12_1 0x02000000U\r
+#define GPIO_MODER_MODER13 0x0C000000U\r
+#define GPIO_MODER_MODER13_0 0x04000000U\r
+#define GPIO_MODER_MODER13_1 0x08000000U\r
+#define GPIO_MODER_MODER14 0x30000000U\r
+#define GPIO_MODER_MODER14_0 0x10000000U\r
+#define GPIO_MODER_MODER14_1 0x20000000U\r
+#define GPIO_MODER_MODER15 0xC0000000U\r
+#define GPIO_MODER_MODER15_0 0x40000000U\r
+#define GPIO_MODER_MODER15_1 0x80000000U\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT_0 0x00000001U\r
+#define GPIO_OTYPER_OT_1 0x00000002U\r
+#define GPIO_OTYPER_OT_2 0x00000004U\r
+#define GPIO_OTYPER_OT_3 0x00000008U\r
+#define GPIO_OTYPER_OT_4 0x00000010U\r
+#define GPIO_OTYPER_OT_5 0x00000020U\r
+#define GPIO_OTYPER_OT_6 0x00000040U\r
+#define GPIO_OTYPER_OT_7 0x00000080U\r
+#define GPIO_OTYPER_OT_8 0x00000100U\r
+#define GPIO_OTYPER_OT_9 0x00000200U\r
+#define GPIO_OTYPER_OT_10 0x00000400U\r
+#define GPIO_OTYPER_OT_11 0x00000800U\r
+#define GPIO_OTYPER_OT_12 0x00001000U\r
+#define GPIO_OTYPER_OT_13 0x00002000U\r
+#define GPIO_OTYPER_OT_14 0x00004000U\r
+#define GPIO_OTYPER_OT_15 0x00008000U\r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U\r
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U\r
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U\r
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U\r
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U\r
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U\r
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U\r
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U\r
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U\r
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U\r
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U\r
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U\r
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U\r
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U\r
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U\r
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0 0x00000003U\r
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U\r
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U\r
+#define GPIO_PUPDR_PUPDR1 0x0000000CU\r
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U\r
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U\r
+#define GPIO_PUPDR_PUPDR2 0x00000030U\r
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U\r
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U\r
+#define GPIO_PUPDR_PUPDR3 0x000000C0U\r
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U\r
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U\r
+#define GPIO_PUPDR_PUPDR4 0x00000300U\r
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U\r
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U\r
+#define GPIO_PUPDR_PUPDR5 0x00000C00U\r
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U\r
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U\r
+#define GPIO_PUPDR_PUPDR6 0x00003000U\r
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U\r
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U\r
+#define GPIO_PUPDR_PUPDR7 0x0000C000U\r
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U\r
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U\r
+#define GPIO_PUPDR_PUPDR8 0x00030000U\r
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U\r
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U\r
+#define GPIO_PUPDR_PUPDR9 0x000C0000U\r
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U\r
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U\r
+#define GPIO_PUPDR_PUPDR10 0x00300000U\r
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U\r
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U\r
+#define GPIO_PUPDR_PUPDR11 0x00C00000U\r
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U\r
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U\r
+#define GPIO_PUPDR_PUPDR12 0x03000000U\r
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U\r
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U\r
+#define GPIO_PUPDR_PUPDR13 0x0C000000U\r
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U\r
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U\r
+#define GPIO_PUPDR_PUPDR14 0x30000000U\r
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U\r
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U\r
+#define GPIO_PUPDR_PUPDR15 0xC0000000U\r
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U\r
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 0x00000001U\r
+#define GPIO_IDR_IDR_1 0x00000002U\r
+#define GPIO_IDR_IDR_2 0x00000004U\r
+#define GPIO_IDR_IDR_3 0x00000008U\r
+#define GPIO_IDR_IDR_4 0x00000010U\r
+#define GPIO_IDR_IDR_5 0x00000020U\r
+#define GPIO_IDR_IDR_6 0x00000040U\r
+#define GPIO_IDR_IDR_7 0x00000080U\r
+#define GPIO_IDR_IDR_8 0x00000100U\r
+#define GPIO_IDR_IDR_9 0x00000200U\r
+#define GPIO_IDR_IDR_10 0x00000400U\r
+#define GPIO_IDR_IDR_11 0x00000800U\r
+#define GPIO_IDR_IDR_12 0x00001000U\r
+#define GPIO_IDR_IDR_13 0x00002000U\r
+#define GPIO_IDR_IDR_14 0x00004000U\r
+#define GPIO_IDR_IDR_15 0x00008000U\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 0x00000001U\r
+#define GPIO_ODR_ODR_1 0x00000002U\r
+#define GPIO_ODR_ODR_2 0x00000004U\r
+#define GPIO_ODR_ODR_3 0x00000008U\r
+#define GPIO_ODR_ODR_4 0x00000010U\r
+#define GPIO_ODR_ODR_5 0x00000020U\r
+#define GPIO_ODR_ODR_6 0x00000040U\r
+#define GPIO_ODR_ODR_7 0x00000080U\r
+#define GPIO_ODR_ODR_8 0x00000100U\r
+#define GPIO_ODR_ODR_9 0x00000200U\r
+#define GPIO_ODR_ODR_10 0x00000400U\r
+#define GPIO_ODR_ODR_11 0x00000800U\r
+#define GPIO_ODR_ODR_12 0x00001000U\r
+#define GPIO_ODR_ODR_13 0x00002000U\r
+#define GPIO_ODR_ODR_14 0x00004000U\r
+#define GPIO_ODR_ODR_15 0x00008000U\r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS_0 0x00000001U\r
+#define GPIO_BSRR_BS_1 0x00000002U\r
+#define GPIO_BSRR_BS_2 0x00000004U\r
+#define GPIO_BSRR_BS_3 0x00000008U\r
+#define GPIO_BSRR_BS_4 0x00000010U\r
+#define GPIO_BSRR_BS_5 0x00000020U\r
+#define GPIO_BSRR_BS_6 0x00000040U\r
+#define GPIO_BSRR_BS_7 0x00000080U\r
+#define GPIO_BSRR_BS_8 0x00000100U\r
+#define GPIO_BSRR_BS_9 0x00000200U\r
+#define GPIO_BSRR_BS_10 0x00000400U\r
+#define GPIO_BSRR_BS_11 0x00000800U\r
+#define GPIO_BSRR_BS_12 0x00001000U\r
+#define GPIO_BSRR_BS_13 0x00002000U\r
+#define GPIO_BSRR_BS_14 0x00004000U\r
+#define GPIO_BSRR_BS_15 0x00008000U\r
+#define GPIO_BSRR_BR_0 0x00010000U\r
+#define GPIO_BSRR_BR_1 0x00020000U\r
+#define GPIO_BSRR_BR_2 0x00040000U\r
+#define GPIO_BSRR_BR_3 0x00080000U\r
+#define GPIO_BSRR_BR_4 0x00100000U\r
+#define GPIO_BSRR_BR_5 0x00200000U\r
+#define GPIO_BSRR_BR_6 0x00400000U\r
+#define GPIO_BSRR_BR_7 0x00800000U\r
+#define GPIO_BSRR_BR_8 0x01000000U\r
+#define GPIO_BSRR_BR_9 0x02000000U\r
+#define GPIO_BSRR_BR_10 0x04000000U\r
+#define GPIO_BSRR_BR_11 0x08000000U\r
+#define GPIO_BSRR_BR_12 0x10000000U\r
+#define GPIO_BSRR_BR_13 0x20000000U\r
+#define GPIO_BSRR_BR_14 0x40000000U\r
+#define GPIO_BSRR_BR_15 0x80000000U\r
+\r
+/****************** Bit definition for GPIO_LCKR register *********************/\r
+#define GPIO_LCKR_LCK0 0x00000001U\r
+#define GPIO_LCKR_LCK1 0x00000002U\r
+#define GPIO_LCKR_LCK2 0x00000004U\r
+#define GPIO_LCKR_LCK3 0x00000008U\r
+#define GPIO_LCKR_LCK4 0x00000010U\r
+#define GPIO_LCKR_LCK5 0x00000020U\r
+#define GPIO_LCKR_LCK6 0x00000040U\r
+#define GPIO_LCKR_LCK7 0x00000080U\r
+#define GPIO_LCKR_LCK8 0x00000100U\r
+#define GPIO_LCKR_LCK9 0x00000200U\r
+#define GPIO_LCKR_LCK10 0x00000400U\r
+#define GPIO_LCKR_LCK11 0x00000800U\r
+#define GPIO_LCKR_LCK12 0x00001000U\r
+#define GPIO_LCKR_LCK13 0x00002000U\r
+#define GPIO_LCKR_LCK14 0x00004000U\r
+#define GPIO_LCKR_LCK15 0x00008000U\r
+#define GPIO_LCKR_LCKK 0x00010000U\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register *******************/\r
+#define I2C_CR1_PE 0x00000001U /*!< Peripheral enable */\r
+#define I2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */\r
+#define I2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */\r
+#define I2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */\r
+#define I2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */\r
+#define I2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */\r
+#define I2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */\r
+#define I2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */\r
+#define I2C_CR1_DNF 0x00000F00U /*!< Digital noise filter */\r
+#define I2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */\r
+#define I2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */\r
+#define I2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */\r
+#define I2C_CR1_SBC 0x00010000U /*!< Slave byte control */\r
+#define I2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */\r
+#define I2C_CR1_GCEN 0x00080000U /*!< General call enable */\r
+#define I2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */\r
+#define I2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */\r
+#define I2C_CR1_PECEN 0x00800000U /*!< PEC enable */\r
+\r
+\r
+/****************** Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */\r
+#define I2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */\r
+#define I2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */\r
+#define I2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START 0x00002000U /*!< START generation */\r
+#define I2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */\r
+#define I2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */\r
+#define I2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */\r
+#define I2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */\r
+#define I2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */\r
+#define I2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */\r
+\r
+/******************* Bit definition for I2C_OAR1 register ******************/\r
+#define I2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */\r
+#define I2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */\r
+\r
+/******************* Bit definition for I2C_OAR2 register ******************/\r
+#define I2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */\r
+#define I2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */\r
+#define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */\r
+#define I2C_OAR2_OA2MASK01 0x00000100U /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r
+#define I2C_OAR2_OA2MASK02 0x00000200U /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r
+#define I2C_OAR2_OA2MASK03 0x00000300U /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r
+#define I2C_OAR2_OA2MASK04 0x00000400U /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r
+#define I2C_OAR2_OA2MASK05 0x00000500U /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r
+#define I2C_OAR2_OA2MASK06 0x00000600U /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r
+#define I2C_OAR2_OA2MASK07 0x00000700U /*!< OA2[7:1] is masked, No comparison is done */\r
+#define I2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */\r
+\r
+/******************* Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */\r
+#define I2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */\r
+#define I2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */\r
+#define I2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */\r
+#define I2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */\r
+#define I2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */\r
+#define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */\r
+#define I2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */\r
+\r
+/****************** Bit definition for I2C_ISR register *********************/\r
+#define I2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */\r
+#define I2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */\r
+#define I2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */\r
+#define I2C_ISR_NACKF 0x00000010U /*!< NACK received flag */\r
+#define I2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */\r
+#define I2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */\r
+#define I2C_ISR_BERR 0x00000100U /*!< Bus error */\r
+#define I2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */\r
+#define I2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */\r
+#define I2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */\r
+#define I2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */\r
+#define I2C_ISR_ALERT 0x00002000U /*!< SMBus alert */\r
+#define I2C_ISR_BUSY 0x00008000U /*!< Bus busy */\r
+#define I2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */\r
+\r
+/****************** Bit definition for I2C_ICR register *********************/\r
+#define I2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */\r
+#define I2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */\r
+#define I2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */\r
+#define I2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */\r
+#define I2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */\r
+#define I2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */\r
+#define I2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */\r
+\r
+/****************** Bit definition for I2C_PECR register *********************/\r
+#define I2C_PECR_PEC 0x000000FFU /*!< PEC register */\r
+\r
+/****************** Bit definition for I2C_RXDR register *********************/\r
+#define I2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */\r
+\r
+/****************** Bit definition for I2C_TXDR register *********************/\r
+#define I2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */\r
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */\r
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU 0x01U /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU 0x02U /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU 0x04U /*!< Watchdog counter window value update */\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_WINR_WIN 0x0FFFU /*!< Watchdog counter window value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD-TFT Display Controller (LTDC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for LTDC_SSCR register *****************/\r
+\r
+#define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */\r
+#define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */\r
+\r
+/******************** Bit definition for LTDC_BPCR register *****************/\r
+\r
+#define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */\r
+#define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */\r
+\r
+/******************** Bit definition for LTDC_AWCR register *****************/\r
+\r
+#define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */\r
+#define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */\r
+\r
+/******************** Bit definition for LTDC_TWCR register *****************/\r
+\r
+#define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */\r
+#define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */\r
+\r
+/******************** Bit definition for LTDC_GCR register ******************/\r
+\r
+#define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */\r
+#define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */\r
+#define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */\r
+#define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */\r
+#define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */\r
+#define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */\r
+#define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */\r
+#define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */\r
+#define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */\r
+\r
+\r
+/******************** Bit definition for LTDC_SRCR register *****************/\r
+\r
+#define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */\r
+#define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */\r
+\r
+/******************** Bit definition for LTDC_BCCR register *****************/\r
+\r
+#define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */\r
+#define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */\r
+#define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */\r
+\r
+/******************** Bit definition for LTDC_IER register ******************/\r
+\r
+#define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */\r
+#define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */\r
+#define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */\r
+#define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */\r
+\r
+/******************** Bit definition for LTDC_ISR register ******************/\r
+\r
+#define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */\r
+#define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */\r
+#define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */\r
+#define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_ICR register ******************/\r
+\r
+#define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */\r
+#define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */\r
+#define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */\r
+#define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_LIPCR register ****************/\r
+\r
+#define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */\r
+\r
+/******************** Bit definition for LTDC_CPSR register *****************/\r
+\r
+#define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */\r
+#define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */\r
+\r
+/******************** Bit definition for LTDC_CDSR register *****************/\r
+\r
+#define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */\r
+#define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */\r
+#define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */\r
+#define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */\r
+\r
+/******************** Bit definition for LTDC_LxCR register *****************/\r
+\r
+#define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */\r
+#define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */\r
+#define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */\r
+\r
+/******************** Bit definition for LTDC_LxWHPCR register **************/\r
+\r
+#define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */\r
+#define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxWVPCR register **************/\r
+\r
+#define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */\r
+#define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxCKCR register ***************/\r
+\r
+#define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */\r
+#define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */\r
+#define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */\r
+\r
+/******************** Bit definition for LTDC_LxPFCR register ***************/\r
+\r
+#define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */\r
+\r
+/******************** Bit definition for LTDC_LxCACR register ***************/\r
+\r
+#define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxDCCR register ***************/\r
+\r
+#define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */\r
+#define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */\r
+#define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */\r
+#define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */\r
+ \r
+/******************** Bit definition for LTDC_LxBFCR register ***************/\r
+\r
+#define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */\r
+#define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */\r
+\r
+/******************** Bit definition for LTDC_LxCFBAR register **************/\r
+\r
+#define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLR register **************/\r
+\r
+#define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */\r
+#define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLNR register *************/\r
+\r
+#define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */\r
+\r
+/******************** Bit definition for LTDC_LxCLUTWR register *************/\r
+\r
+#define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */\r
+#define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */\r
+#define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */\r
+#define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for PWR_CR1 register ********************/\r
+#define PWR_CR1_LPDS 0x00000001U /*!< Low-Power Deepsleep */\r
+#define PWR_CR1_PDDS 0x00000002U /*!< Power Down Deepsleep */\r
+#define PWR_CR1_CSBF 0x00000008U /*!< Clear Standby Flag */\r
+#define PWR_CR1_PVDE 0x00000010U /*!< Power Voltage Detector Enable */\r
+#define PWR_CR1_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR1_PLS_0 0x00000020U /*!< Bit 0 */\r
+#define PWR_CR1_PLS_1 0x00000040U /*!< Bit 1 */\r
+#define PWR_CR1_PLS_2 0x00000080U /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */\r
+#define PWR_CR1_PLS_LEV1 0x00000020U /*!< PVD level 1 */\r
+#define PWR_CR1_PLS_LEV2 0x00000040U /*!< PVD level 2 */\r
+#define PWR_CR1_PLS_LEV3 0x00000060U /*!< PVD level 3 */\r
+#define PWR_CR1_PLS_LEV4 0x00000080U /*!< PVD level 4 */\r
+#define PWR_CR1_PLS_LEV5 0x000000A0U /*!< PVD level 5 */\r
+#define PWR_CR1_PLS_LEV6 0x000000C0U /*!< PVD level 6 */\r
+#define PWR_CR1_PLS_LEV7 0x000000E0U /*!< PVD level 7 */\r
+#define PWR_CR1_DBP 0x00000100U /*!< Disable Backup Domain write protection */\r
+#define PWR_CR1_FPDS 0x00000200U /*!< Flash power down in Stop mode */\r
+#define PWR_CR1_LPUDS 0x00000400U /*!< Low-power regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_MRUDS 0x00000800U /*!< Main regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */ \r
+#define PWR_CR1_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define PWR_CR1_VOS_0 0x00004000U /*!< Bit 0 */\r
+#define PWR_CR1_VOS_1 0x00008000U /*!< Bit 1 */\r
+#define PWR_CR1_ODEN 0x00010000U /*!< Over Drive enable */\r
+#define PWR_CR1_ODSWEN 0x00020000U /*!< Over Drive switch enabled */\r
+#define PWR_CR1_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */\r
+#define PWR_CR1_UDEN_0 0x00040000U /*!< Bit 0 */\r
+#define PWR_CR1_UDEN_1 0x00080000U /*!< Bit 1 */\r
+\r
+/******************* Bit definition for PWR_CSR1 register ********************/\r
+#define PWR_CSR1_WUIF 0x00000001U /*!< Wake up internal Flag */\r
+#define PWR_CSR1_SBF 0x00000002U /*!< Standby Flag */\r
+#define PWR_CSR1_PVDO 0x00000004U /*!< PVD Output */\r
+#define PWR_CSR1_BRR 0x00000008U /*!< Backup regulator ready */\r
+#define PWR_CSR1_EIWUP 0x00000100U /*!< Enable internal wakeup */\r
+#define PWR_CSR1_BRE 0x00000200U /*!< Backup regulator enable */\r
+#define PWR_CSR1_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */\r
+#define PWR_CSR1_ODRDY 0x00010000U /*!< Over Drive generator ready */\r
+#define PWR_CSR1_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */\r
+#define PWR_CSR1_UDRDY 0x000C0000U /*!< Under Drive ready */\r
+\r
+\r
+/******************** Bit definition for PWR_CR2 register ********************/\r
+#define PWR_CR2_CWUPF1 0x00000001U /*!< Clear Wakeup Pin Flag for PA0 */\r
+#define PWR_CR2_CWUPF2 0x00000002U /*!< Clear Wakeup Pin Flag for PA2 */\r
+#define PWR_CR2_CWUPF3 0x00000004U /*!< Clear Wakeup Pin Flag for PC1 */\r
+#define PWR_CR2_CWUPF4 0x00000008U /*!< Clear Wakeup Pin Flag for PC13 */\r
+#define PWR_CR2_CWUPF5 0x00000010U /*!< Clear Wakeup Pin Flag for PI8 */\r
+#define PWR_CR2_CWUPF6 0x00000020U /*!< Clear Wakeup Pin Flag for PI11 */\r
+#define PWR_CR2_WUPP1 0x00000100U /*!< Wakeup Pin Polarity bit for PA0 */\r
+#define PWR_CR2_WUPP2 0x00000200U /*!< Wakeup Pin Polarity bit for PA2 */\r
+#define PWR_CR2_WUPP3 0x00000400U /*!< Wakeup Pin Polarity bit for PC1 */\r
+#define PWR_CR2_WUPP4 0x00000800U /*!< Wakeup Pin Polarity bit for PC13 */\r
+#define PWR_CR2_WUPP5 0x00001000U /*!< Wakeup Pin Polarity bit for PI8 */\r
+#define PWR_CR2_WUPP6 0x00002000U /*!< Wakeup Pin Polarity bit for PI11 */\r
+\r
+/******************* Bit definition for PWR_CSR2 register ********************/\r
+#define PWR_CSR2_WUPF1 0x00000001U /*!< Wakeup Pin Flag for PA0 */\r
+#define PWR_CSR2_WUPF2 0x00000002U /*!< Wakeup Pin Flag for PA2 */\r
+#define PWR_CSR2_WUPF3 0x00000004U /*!< Wakeup Pin Flag for PC1 */\r
+#define PWR_CSR2_WUPF4 0x00000008U /*!< Wakeup Pin Flag for PC13 */\r
+#define PWR_CSR2_WUPF5 0x00000010U /*!< Wakeup Pin Flag for PI8 */\r
+#define PWR_CSR2_WUPF6 0x00000020U /*!< Wakeup Pin Flag for PI11 */\r
+#define PWR_CSR2_EWUP1 0x00000100U /*!< Enable Wakeup Pin PA0 */\r
+#define PWR_CSR2_EWUP2 0x00000200U /*!< Enable Wakeup Pin PA2 */\r
+#define PWR_CSR2_EWUP3 0x00000400U /*!< Enable Wakeup Pin PC1 */\r
+#define PWR_CSR2_EWUP4 0x00000800U /*!< Enable Wakeup Pin PC13 */\r
+#define PWR_CSR2_EWUP5 0x00001000U /*!< Enable Wakeup Pin PI8 */\r
+#define PWR_CSR2_EWUP6 0x00002000U /*!< Enable Wakeup Pin PI11 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* QUADSPI */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for QUADSPI_CR register *******************/\r
+#define QUADSPI_CR_EN 0x00000001U /*!< Enable */\r
+#define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */\r
+#define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */\r
+#define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */\r
+#define QUADSPI_CR_SSHIFT 0x00000010U /*!< Sample Shift */\r
+#define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */\r
+#define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */\r
+#define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[4:0] FIFO Level */\r
+#define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */\r
+#define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */\r
+#define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */\r
+#define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */\r
+#define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */\r
+#define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */\r
+#define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */\r
+#define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */\r
+#define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */\r
+#define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */\r
+#define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */\r
+#define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */\r
+#define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */\r
+#define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */\r
+#define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */\r
+#define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */\r
+#define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */\r
+#define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */\r
+#define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */\r
+#define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */\r
+#define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */\r
+\r
+/***************** Bit definition for QUADSPI_DCR register ******************/\r
+#define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */\r
+#define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */\r
+#define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */\r
+#define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */\r
+#define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */\r
+#define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */\r
+#define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */\r
+#define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */\r
+#define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */\r
+#define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */\r
+#define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */\r
+\r
+/****************** Bit definition for QUADSPI_SR register *******************/\r
+#define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */\r
+#define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */\r
+#define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */\r
+#define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */\r
+#define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */\r
+#define QUADSPI_SR_FLEVEL 0x00001F00U /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */\r
+#define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */\r
+#define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */\r
+#define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */\r
+#define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */\r
+\r
+/****************** Bit definition for QUADSPI_FCR register ******************/\r
+#define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */\r
+#define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */\r
+#define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */\r
+#define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */\r
+\r
+/****************** Bit definition for QUADSPI_DLR register ******************/\r
+#define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */\r
+\r
+/****************** Bit definition for QUADSPI_CCR register ******************/\r
+#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */\r
+#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */\r
+#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */\r
+#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */\r
+#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */\r
+#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */\r
+#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */\r
+#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */\r
+#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */\r
+#define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */\r
+#define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */\r
+#define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */\r
+#define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */\r
+#define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */\r
+#define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */\r
+#define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */\r
+#define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */\r
+#define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
+#define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */\r
+#define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */\r
+#define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */\r
+#define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */\r
+#define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */\r
+#define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */\r
+#define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */\r
+#define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */\r
+#define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */\r
+#define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */\r
+#define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */\r
+#define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */\r
+#define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */\r
+#define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */\r
+#define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */\r
+#define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */\r
+#define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */\r
+#define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */\r
+#define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */ \r
+/****************** Bit definition for QUADSPI_AR register *******************/\r
+#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */\r
+\r
+/****************** Bit definition for QUADSPI_ABR register ******************/\r
+#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */\r
+\r
+/****************** Bit definition for QUADSPI_DR register *******************/\r
+#define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */\r
+\r
+/****************** Bit definition for QUADSPI_PSMKR register ****************/\r
+#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */\r
+\r
+/****************** Bit definition for QUADSPI_PSMAR register ****************/\r
+#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */\r
+\r
+/****************** Bit definition for QUADSPI_PIR register *****************/\r
+#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */\r
+\r
+/****************** Bit definition for QUADSPI_LPTR register *****************/\r
+#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION 0x00000001U\r
+#define RCC_CR_HSIRDY 0x00000002U\r
+#define RCC_CR_HSITRIM 0x000000F8U\r
+#define RCC_CR_HSITRIM_0 0x00000008U /*!<Bit 0 */\r
+#define RCC_CR_HSITRIM_1 0x00000010U /*!<Bit 1 */\r
+#define RCC_CR_HSITRIM_2 0x00000020U /*!<Bit 2 */\r
+#define RCC_CR_HSITRIM_3 0x00000040U /*!<Bit 3 */\r
+#define RCC_CR_HSITRIM_4 0x00000080U /*!<Bit 4 */\r
+#define RCC_CR_HSICAL 0x0000FF00U\r
+#define RCC_CR_HSICAL_0 0x00000100U /*!<Bit 0 */\r
+#define RCC_CR_HSICAL_1 0x00000200U /*!<Bit 1 */\r
+#define RCC_CR_HSICAL_2 0x00000400U /*!<Bit 2 */\r
+#define RCC_CR_HSICAL_3 0x00000800U /*!<Bit 3 */\r
+#define RCC_CR_HSICAL_4 0x00001000U /*!<Bit 4 */\r
+#define RCC_CR_HSICAL_5 0x00002000U /*!<Bit 5 */\r
+#define RCC_CR_HSICAL_6 0x00004000U /*!<Bit 6 */\r
+#define RCC_CR_HSICAL_7 0x00008000U /*!<Bit 7 */\r
+#define RCC_CR_HSEON 0x00010000U\r
+#define RCC_CR_HSERDY 0x00020000U\r
+#define RCC_CR_HSEBYP 0x00040000U\r
+#define RCC_CR_CSSON 0x00080000U\r
+#define RCC_CR_PLLON 0x01000000U\r
+#define RCC_CR_PLLRDY 0x02000000U\r
+#define RCC_CR_PLLI2SON 0x04000000U\r
+#define RCC_CR_PLLI2SRDY 0x08000000U\r
+#define RCC_CR_PLLSAION 0x10000000U\r
+#define RCC_CR_PLLSAIRDY 0x20000000U\r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+#define RCC_PLLCFGR_PLLM 0x0000003FU\r
+#define RCC_PLLCFGR_PLLM_0 0x00000001U\r
+#define RCC_PLLCFGR_PLLM_1 0x00000002U\r
+#define RCC_PLLCFGR_PLLM_2 0x00000004U\r
+#define RCC_PLLCFGR_PLLM_3 0x00000008U\r
+#define RCC_PLLCFGR_PLLM_4 0x00000010U\r
+#define RCC_PLLCFGR_PLLM_5 0x00000020U\r
+#define RCC_PLLCFGR_PLLN 0x00007FC0U\r
+#define RCC_PLLCFGR_PLLN_0 0x00000040U\r
+#define RCC_PLLCFGR_PLLN_1 0x00000080U\r
+#define RCC_PLLCFGR_PLLN_2 0x00000100U\r
+#define RCC_PLLCFGR_PLLN_3 0x00000200U\r
+#define RCC_PLLCFGR_PLLN_4 0x00000400U\r
+#define RCC_PLLCFGR_PLLN_5 0x00000800U\r
+#define RCC_PLLCFGR_PLLN_6 0x00001000U\r
+#define RCC_PLLCFGR_PLLN_7 0x00002000U\r
+#define RCC_PLLCFGR_PLLN_8 0x00004000U\r
+#define RCC_PLLCFGR_PLLP 0x00030000U\r
+#define RCC_PLLCFGR_PLLP_0 0x00010000U\r
+#define RCC_PLLCFGR_PLLP_1 0x00020000U\r
+#define RCC_PLLCFGR_PLLSRC 0x00400000U\r
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U\r
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U\r
+#define RCC_PLLCFGR_PLLQ 0x0F000000U\r
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U\r
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U\r
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U\r
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U\r
+\r
+#define RCC_PLLCFGR_PLLR 0x70000000U\r
+#define RCC_PLLCFGR_PLLR_0 0x10000000U\r
+#define RCC_PLLCFGR_PLLR_1 0x20000000U\r
+#define RCC_PLLCFGR_PLLR_2 0x40000000U\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */\r
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */\r
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE 0x001F0000U\r
+#define RCC_CFGR_RTCPRE_0 0x00010000U\r
+#define RCC_CFGR_RTCPRE_1 0x00020000U\r
+#define RCC_CFGR_RTCPRE_2 0x00040000U\r
+#define RCC_CFGR_RTCPRE_3 0x00080000U\r
+#define RCC_CFGR_RTCPRE_4 0x00100000U\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1 0x00600000U\r
+#define RCC_CFGR_MCO1_0 0x00200000U\r
+#define RCC_CFGR_MCO1_1 0x00400000U\r
+\r
+#define RCC_CFGR_I2SSRC 0x00800000U\r
+\r
+#define RCC_CFGR_MCO1PRE 0x07000000U\r
+#define RCC_CFGR_MCO1PRE_0 0x01000000U\r
+#define RCC_CFGR_MCO1PRE_1 0x02000000U\r
+#define RCC_CFGR_MCO1PRE_2 0x04000000U\r
+\r
+#define RCC_CFGR_MCO2PRE 0x38000000U\r
+#define RCC_CFGR_MCO2PRE_0 0x08000000U\r
+#define RCC_CFGR_MCO2PRE_1 0x10000000U\r
+#define RCC_CFGR_MCO2PRE_2 0x20000000U\r
+\r
+#define RCC_CFGR_MCO2 0xC0000000U\r
+#define RCC_CFGR_MCO2_0 0x40000000U\r
+#define RCC_CFGR_MCO2_1 0x80000000U\r
+\r
+/******************** Bit definition for RCC_CIR register *******************/\r
+#define RCC_CIR_LSIRDYF 0x00000001U\r
+#define RCC_CIR_LSERDYF 0x00000002U\r
+#define RCC_CIR_HSIRDYF 0x00000004U\r
+#define RCC_CIR_HSERDYF 0x00000008U\r
+#define RCC_CIR_PLLRDYF 0x00000010U\r
+#define RCC_CIR_PLLI2SRDYF 0x00000020U\r
+#define RCC_CIR_PLLSAIRDYF 0x00000040U\r
+#define RCC_CIR_CSSF 0x00000080U\r
+#define RCC_CIR_LSIRDYIE 0x00000100U\r
+#define RCC_CIR_LSERDYIE 0x00000200U\r
+#define RCC_CIR_HSIRDYIE 0x00000400U\r
+#define RCC_CIR_HSERDYIE 0x00000800U\r
+#define RCC_CIR_PLLRDYIE 0x00001000U\r
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U\r
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U\r
+#define RCC_CIR_LSIRDYC 0x00010000U\r
+#define RCC_CIR_LSERDYC 0x00020000U\r
+#define RCC_CIR_HSIRDYC 0x00040000U\r
+#define RCC_CIR_HSERDYC 0x00080000U\r
+#define RCC_CIR_PLLRDYC 0x00100000U\r
+#define RCC_CIR_PLLI2SRDYC 0x00200000U\r
+#define RCC_CIR_PLLSAIRDYC 0x00400000U\r
+#define RCC_CIR_CSSC 0x00800000U\r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register **************/\r
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U\r
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U\r
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U\r
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U\r
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U\r
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U\r
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U\r
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U\r
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U\r
+#define RCC_AHB1RSTR_GPIOJRST 0x00000200U\r
+#define RCC_AHB1RSTR_GPIOKRST 0x00000400U\r
+#define RCC_AHB1RSTR_CRCRST 0x00001000U\r
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U\r
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U\r
+#define RCC_AHB1RSTR_DMA2DRST 0x00800000U\r
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U\r
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U\r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register **************/\r
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U\r
+#define RCC_AHB2RSTR_JPEGRST 0x00000002U\r
+#define RCC_AHB2RSTR_RNGRST 0x00000040U\r
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U\r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register **************/\r
+\r
+#define RCC_AHB3RSTR_FMCRST 0x00000001U\r
+#define RCC_AHB3RSTR_QSPIRST 0x00000002U\r
+\r
+/******************** Bit definition for RCC_APB1RSTR register **************/\r
+#define RCC_APB1RSTR_TIM2RST 0x00000001U\r
+#define RCC_APB1RSTR_TIM3RST 0x00000002U\r
+#define RCC_APB1RSTR_TIM4RST 0x00000004U\r
+#define RCC_APB1RSTR_TIM5RST 0x00000008U\r
+#define RCC_APB1RSTR_TIM6RST 0x00000010U\r
+#define RCC_APB1RSTR_TIM7RST 0x00000020U\r
+#define RCC_APB1RSTR_TIM12RST 0x00000040U\r
+#define RCC_APB1RSTR_TIM13RST 0x00000080U\r
+#define RCC_APB1RSTR_TIM14RST 0x00000100U\r
+#define RCC_APB1RSTR_LPTIM1RST 0x00000200U\r
+#define RCC_APB1RSTR_WWDGRST 0x00000800U\r
+#define RCC_APB1RSTR_CAN3RST 0x00002000U\r
+#define RCC_APB1RSTR_SPI2RST 0x00004000U\r
+#define RCC_APB1RSTR_SPI3RST 0x00008000U\r
+#define RCC_APB1RSTR_SPDIFRXRST 0x00010000U\r
+#define RCC_APB1RSTR_USART2RST 0x00020000U\r
+#define RCC_APB1RSTR_USART3RST 0x00040000U\r
+#define RCC_APB1RSTR_UART4RST 0x00080000U\r
+#define RCC_APB1RSTR_UART5RST 0x00100000U\r
+#define RCC_APB1RSTR_I2C1RST 0x00200000U\r
+#define RCC_APB1RSTR_I2C2RST 0x00400000U\r
+#define RCC_APB1RSTR_I2C3RST 0x00800000U\r
+#define RCC_APB1RSTR_I2C4RST 0x01000000U\r
+#define RCC_APB1RSTR_CAN1RST 0x02000000U\r
+#define RCC_APB1RSTR_CAN2RST 0x04000000U\r
+#define RCC_APB1RSTR_CECRST 0x08000000U\r
+#define RCC_APB1RSTR_PWRRST 0x10000000U\r
+#define RCC_APB1RSTR_DACRST 0x20000000U\r
+#define RCC_APB1RSTR_UART7RST 0x40000000U\r
+#define RCC_APB1RSTR_UART8RST 0x80000000U\r
+\r
+/******************** Bit definition for RCC_APB2RSTR register **************/\r
+#define RCC_APB2RSTR_TIM1RST 0x00000001U\r
+#define RCC_APB2RSTR_TIM8RST 0x00000002U\r
+#define RCC_APB2RSTR_USART1RST 0x00000010U\r
+#define RCC_APB2RSTR_USART6RST 0x00000020U\r
+#define RCC_APB2RSTR_SDMMC2RST 0x00000080U\r
+#define RCC_APB2RSTR_ADCRST 0x00000100U\r
+#define RCC_APB2RSTR_SDMMC1RST 0x00000800U\r
+#define RCC_APB2RSTR_SPI1RST 0x00001000U\r
+#define RCC_APB2RSTR_SPI4RST 0x00002000U\r
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U\r
+#define RCC_APB2RSTR_TIM9RST 0x00010000U\r
+#define RCC_APB2RSTR_TIM10RST 0x00020000U\r
+#define RCC_APB2RSTR_TIM11RST 0x00040000U\r
+#define RCC_APB2RSTR_SPI5RST 0x00100000U\r
+#define RCC_APB2RSTR_SPI6RST 0x00200000U\r
+#define RCC_APB2RSTR_SAI1RST 0x00400000U\r
+#define RCC_APB2RSTR_SAI2RST 0x00800000U\r
+#define RCC_APB2RSTR_LTDCRST 0x04000000U\r
+#define RCC_APB2RSTR_DFSDM1RST 0x20000000U\r
+#define RCC_APB2RSTR_MDIORST 0x40000000U\r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U\r
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U\r
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U\r
+#define RCC_AHB1ENR_GPIODEN 0x00000008U\r
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U\r
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U\r
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U\r
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U\r
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U\r
+#define RCC_AHB1ENR_GPIOJEN 0x00000200U\r
+#define RCC_AHB1ENR_GPIOKEN 0x00000400U\r
+#define RCC_AHB1ENR_CRCEN 0x00001000U\r
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U\r
+#define RCC_AHB1ENR_DTCMRAMEN 0x00100000U\r
+#define RCC_AHB1ENR_DMA1EN 0x00200000U\r
+#define RCC_AHB1ENR_DMA2EN 0x00400000U\r
+#define RCC_AHB1ENR_DMA2DEN 0x00800000U\r
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U\r
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U\r
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U\r
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U\r
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U\r
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U\r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_DCMIEN 0x00000001U\r
+#define RCC_AHB2ENR_JPEGEN 0x00000002U\r
+#define RCC_AHB2ENR_RNGEN 0x00000040U\r
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U\r
+\r
+/******************** Bit definition for RCC_AHB3ENR register ***************/\r
+#define RCC_AHB3ENR_FMCEN 0x00000001U\r
+#define RCC_AHB3ENR_QSPIEN 0x00000002U\r
+\r
+/******************** Bit definition for RCC_APB1ENR register ***************/\r
+#define RCC_APB1ENR_TIM2EN 0x00000001U\r
+#define RCC_APB1ENR_TIM3EN 0x00000002U\r
+#define RCC_APB1ENR_TIM4EN 0x00000004U\r
+#define RCC_APB1ENR_TIM5EN 0x00000008U\r
+#define RCC_APB1ENR_TIM6EN 0x00000010U\r
+#define RCC_APB1ENR_TIM7EN 0x00000020U\r
+#define RCC_APB1ENR_TIM12EN 0x00000040U\r
+#define RCC_APB1ENR_TIM13EN 0x00000080U\r
+#define RCC_APB1ENR_TIM14EN 0x00000100U\r
+#define RCC_APB1ENR_LPTIM1EN 0x00000200U\r
+#define RCC_APB1ENR_RTCEN 0x00000400U\r
+#define RCC_APB1ENR_WWDGEN 0x00000800U\r
+#define RCC_APB1ENR_CAN3EN 0x00002000U\r
+#define RCC_APB1ENR_SPI2EN 0x00004000U\r
+#define RCC_APB1ENR_SPI3EN 0x00008000U\r
+#define RCC_APB1ENR_SPDIFRXEN 0x00010000U\r
+#define RCC_APB1ENR_USART2EN 0x00020000U\r
+#define RCC_APB1ENR_USART3EN 0x00040000U\r
+#define RCC_APB1ENR_UART4EN 0x00080000U\r
+#define RCC_APB1ENR_UART5EN 0x00100000U\r
+#define RCC_APB1ENR_I2C1EN 0x00200000U\r
+#define RCC_APB1ENR_I2C2EN 0x00400000U\r
+#define RCC_APB1ENR_I2C3EN 0x00800000U\r
+#define RCC_APB1ENR_I2C4EN 0x01000000U\r
+#define RCC_APB1ENR_CAN1EN 0x02000000U\r
+#define RCC_APB1ENR_CAN2EN 0x04000000U\r
+#define RCC_APB1ENR_CECEN 0x08000000U\r
+#define RCC_APB1ENR_PWREN 0x10000000U\r
+#define RCC_APB1ENR_DACEN 0x20000000U\r
+#define RCC_APB1ENR_UART7EN 0x40000000U\r
+#define RCC_APB1ENR_UART8EN 0x80000000U\r
+\r
+/******************** Bit definition for RCC_APB2ENR register ***************/\r
+#define RCC_APB2ENR_TIM1EN 0x00000001U\r
+#define RCC_APB2ENR_TIM8EN 0x00000002U\r
+#define RCC_APB2ENR_USART1EN 0x00000010U\r
+#define RCC_APB2ENR_USART6EN 0x00000020U\r
+#define RCC_APB2ENR_SDMMC2EN 0x00000080U\r
+#define RCC_APB2ENR_ADC1EN 0x00000100U\r
+#define RCC_APB2ENR_ADC2EN 0x00000200U\r
+#define RCC_APB2ENR_ADC3EN 0x00000400U\r
+#define RCC_APB2ENR_SDMMC1EN 0x00000800U\r
+#define RCC_APB2ENR_SPI1EN 0x00001000U\r
+#define RCC_APB2ENR_SPI4EN 0x00002000U\r
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U\r
+#define RCC_APB2ENR_TIM9EN 0x00010000U\r
+#define RCC_APB2ENR_TIM10EN 0x00020000U\r
+#define RCC_APB2ENR_TIM11EN 0x00040000U\r
+#define RCC_APB2ENR_SPI5EN 0x00100000U\r
+#define RCC_APB2ENR_SPI6EN 0x00200000U\r
+#define RCC_APB2ENR_SAI1EN 0x00400000U\r
+#define RCC_APB2ENR_SAI2EN 0x00800000U\r
+#define RCC_APB2ENR_LTDCEN 0x04000000U\r
+#define RCC_APB2ENR_DFSDM1EN 0x20000000U\r
+#define RCC_APB2ENR_MDIOEN 0x40000000U\r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register *************/\r
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U\r
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U\r
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U\r
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U\r
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U\r
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U\r
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U\r
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U\r
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U\r
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U\r
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U\r
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U\r
+#define RCC_AHB1LPENR_AXILPEN 0x00002000U\r
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U\r
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U\r
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U\r
+#define RCC_AHB1LPENR_DTCMLPEN 0x00100000U\r
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U\r
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U\r
+#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U\r
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U\r
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U\r
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U\r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U\r
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U\r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register *************/\r
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U\r
+#define RCC_AHB2LPENR_JPEGLPEN 0x00000002U\r
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U\r
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U\r
+\r
+/******************** Bit definition for RCC_AHB3LPENR register *************/\r
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U\r
+#define RCC_AHB3LPENR_QSPILPEN 0x00000002U\r
+/******************** Bit definition for RCC_APB1LPENR register *************/\r
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U\r
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U\r
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U\r
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U\r
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U\r
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U\r
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U\r
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U\r
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U\r
+#define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U\r
+#define RCC_APB1LPENR_RTCLPEN 0x00000400U\r
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U\r
+#define RCC_APB1LPENR_CAN3LPEN 0x00002000U\r
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U\r
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U\r
+#define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U\r
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U\r
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U\r
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U\r
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U\r
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U\r
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U\r
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U\r
+#define RCC_APB1LPENR_I2C4LPEN 0x01000000U\r
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U\r
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U\r
+#define RCC_APB1LPENR_CECLPEN 0x08000000U\r
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U\r
+#define RCC_APB1LPENR_DACLPEN 0x20000000U\r
+#define RCC_APB1LPENR_UART7LPEN 0x40000000U\r
+#define RCC_APB1LPENR_UART8LPEN 0x80000000U\r
+\r
+/******************** Bit definition for RCC_APB2LPENR register *************/\r
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U\r
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U\r
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U\r
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U\r
+#define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U\r
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U\r
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U\r
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U\r
+#define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U\r
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U\r
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U\r
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U\r
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U\r
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U\r
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U\r
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U\r
+#define RCC_APB2LPENR_SPI6LPEN 0x00200000U\r
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U\r
+#define RCC_APB2LPENR_SAI2LPEN 0x00800000U\r
+#define RCC_APB2LPENR_LTDCLPEN 0x04000000U\r
+#define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U\r
+#define RCC_APB2LPENR_MDIOLPEN 0x40000000U\r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON 0x00000001U\r
+#define RCC_BDCR_LSERDY 0x00000002U\r
+#define RCC_BDCR_LSEBYP 0x00000004U\r
+#define RCC_BDCR_LSEDRV 0x00000018U\r
+#define RCC_BDCR_LSEDRV_0 0x00000008U\r
+#define RCC_BDCR_LSEDRV_1 0x00000010U\r
+#define RCC_BDCR_RTCSEL 0x00000300U\r
+#define RCC_BDCR_RTCSEL_0 0x00000100U\r
+#define RCC_BDCR_RTCSEL_1 0x00000200U\r
+#define RCC_BDCR_RTCEN 0x00008000U\r
+#define RCC_BDCR_BDRST 0x00010000U\r
+\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION 0x00000001U\r
+#define RCC_CSR_LSIRDY 0x00000002U\r
+#define RCC_CSR_RMVF 0x01000000U\r
+#define RCC_CSR_BORRSTF 0x02000000U\r
+#define RCC_CSR_PINRSTF 0x04000000U\r
+#define RCC_CSR_PORRSTF 0x08000000U\r
+#define RCC_CSR_SFTRSTF 0x10000000U\r
+#define RCC_CSR_IWDGRSTF 0x20000000U\r
+#define RCC_CSR_WWDGRSTF 0x40000000U\r
+#define RCC_CSR_LPWRRSTF 0x80000000U\r
+\r
+/******************** Bit definition for RCC_SSCGR register *****************/\r
+#define RCC_SSCGR_MODPER 0x00001FFFU\r
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U\r
+#define RCC_SSCGR_SPREADSEL 0x40000000U\r
+#define RCC_SSCGR_SSCGEN 0x80000000U\r
+\r
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U\r
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U\r
+#define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U\r
+#define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U\r
+#define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U\r
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U\r
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U\r
+\r
+/******************** Bit definition for RCC_PLLSAICFGR register ************/\r
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U\r
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U\r
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U\r
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U\r
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U\r
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U\r
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U\r
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U\r
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U\r
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U\r
+#define RCC_PLLSAICFGR_PLLSAIP 0x00030000U\r
+#define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U\r
+#define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U\r
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U\r
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U\r
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U\r
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U\r
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U\r
+#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U\r
+#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U\r
+#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U\r
+#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U\r
+\r
+/******************** Bit definition for RCC_DCKCFGR1 register ***************/\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U\r
+\r
+#define RCC_DCKCFGR1_SAI1SEL 0x00300000U\r
+#define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U\r
+#define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U\r
+\r
+#define RCC_DCKCFGR1_SAI2SEL 0x00C00000U\r
+#define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U\r
+#define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U\r
+\r
+#define RCC_DCKCFGR1_TIMPRE 0x01000000U\r
+#define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U\r
+#define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U\r
+\r
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/\r
+#define RCC_DCKCFGR2_USART1SEL 0x00000003U\r
+#define RCC_DCKCFGR2_USART1SEL_0 0x00000001U\r
+#define RCC_DCKCFGR2_USART1SEL_1 0x00000002U\r
+#define RCC_DCKCFGR2_USART2SEL 0x0000000CU\r
+#define RCC_DCKCFGR2_USART2SEL_0 0x00000004U\r
+#define RCC_DCKCFGR2_USART2SEL_1 0x00000008U\r
+#define RCC_DCKCFGR2_USART3SEL 0x00000030U\r
+#define RCC_DCKCFGR2_USART3SEL_0 0x00000010U\r
+#define RCC_DCKCFGR2_USART3SEL_1 0x00000020U\r
+#define RCC_DCKCFGR2_UART4SEL 0x000000C0U\r
+#define RCC_DCKCFGR2_UART4SEL_0 0x00000040U\r
+#define RCC_DCKCFGR2_UART4SEL_1 0x00000080U\r
+#define RCC_DCKCFGR2_UART5SEL 0x00000300U\r
+#define RCC_DCKCFGR2_UART5SEL_0 0x00000100U\r
+#define RCC_DCKCFGR2_UART5SEL_1 0x00000200U\r
+#define RCC_DCKCFGR2_USART6SEL 0x00000C00U\r
+#define RCC_DCKCFGR2_USART6SEL_0 0x00000400U\r
+#define RCC_DCKCFGR2_USART6SEL_1 0x00000800U\r
+#define RCC_DCKCFGR2_UART7SEL 0x00003000U\r
+#define RCC_DCKCFGR2_UART7SEL_0 0x00001000U\r
+#define RCC_DCKCFGR2_UART7SEL_1 0x00002000U\r
+#define RCC_DCKCFGR2_UART8SEL 0x0000C000U\r
+#define RCC_DCKCFGR2_UART8SEL_0 0x00004000U\r
+#define RCC_DCKCFGR2_UART8SEL_1 0x00008000U\r
+#define RCC_DCKCFGR2_I2C1SEL 0x00030000U\r
+#define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U\r
+#define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U\r
+#define RCC_DCKCFGR2_I2C2SEL 0x000C0000U\r
+#define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U\r
+#define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U\r
+#define RCC_DCKCFGR2_I2C3SEL 0x00300000U\r
+#define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U\r
+#define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U\r
+#define RCC_DCKCFGR2_I2C4SEL 0x00C00000U\r
+#define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U\r
+#define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U\r
+#define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U\r
+#define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U\r
+#define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U\r
+#define RCC_DCKCFGR2_CECSEL 0x04000000U\r
+#define RCC_DCKCFGR2_CK48MSEL 0x08000000U\r
+#define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U\r
+#define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN 0x00000004U\r
+#define RNG_CR_IE 0x00000008U\r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY 0x00000001U\r
+#define RNG_SR_CECS 0x00000002U\r
+#define RNG_SR_SECS 0x00000004U\r
+#define RNG_SR_CEIS 0x00000020U\r
+#define RNG_SR_SEIS 0x00000040U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM 0x00400000U\r
+#define RTC_TR_HT 0x00300000U\r
+#define RTC_TR_HT_0 0x00100000U\r
+#define RTC_TR_HT_1 0x00200000U\r
+#define RTC_TR_HU 0x000F0000U\r
+#define RTC_TR_HU_0 0x00010000U\r
+#define RTC_TR_HU_1 0x00020000U\r
+#define RTC_TR_HU_2 0x00040000U\r
+#define RTC_TR_HU_3 0x00080000U\r
+#define RTC_TR_MNT 0x00007000U\r
+#define RTC_TR_MNT_0 0x00001000U\r
+#define RTC_TR_MNT_1 0x00002000U\r
+#define RTC_TR_MNT_2 0x00004000U\r
+#define RTC_TR_MNU 0x00000F00U\r
+#define RTC_TR_MNU_0 0x00000100U\r
+#define RTC_TR_MNU_1 0x00000200U\r
+#define RTC_TR_MNU_2 0x00000400U\r
+#define RTC_TR_MNU_3 0x00000800U\r
+#define RTC_TR_ST 0x00000070U\r
+#define RTC_TR_ST_0 0x00000010U\r
+#define RTC_TR_ST_1 0x00000020U\r
+#define RTC_TR_ST_2 0x00000040U\r
+#define RTC_TR_SU 0x0000000FU\r
+#define RTC_TR_SU_0 0x00000001U\r
+#define RTC_TR_SU_1 0x00000002U\r
+#define RTC_TR_SU_2 0x00000004U\r
+#define RTC_TR_SU_3 0x00000008U\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT 0x00F00000U\r
+#define RTC_DR_YT_0 0x00100000U\r
+#define RTC_DR_YT_1 0x00200000U\r
+#define RTC_DR_YT_2 0x00400000U\r
+#define RTC_DR_YT_3 0x00800000U\r
+#define RTC_DR_YU 0x000F0000U\r
+#define RTC_DR_YU_0 0x00010000U\r
+#define RTC_DR_YU_1 0x00020000U\r
+#define RTC_DR_YU_2 0x00040000U\r
+#define RTC_DR_YU_3 0x00080000U\r
+#define RTC_DR_WDU 0x0000E000U\r
+#define RTC_DR_WDU_0 0x00002000U\r
+#define RTC_DR_WDU_1 0x00004000U\r
+#define RTC_DR_WDU_2 0x00008000U\r
+#define RTC_DR_MT 0x00001000U\r
+#define RTC_DR_MU 0x00000F00U\r
+#define RTC_DR_MU_0 0x00000100U\r
+#define RTC_DR_MU_1 0x00000200U\r
+#define RTC_DR_MU_2 0x00000400U\r
+#define RTC_DR_MU_3 0x00000800U\r
+#define RTC_DR_DT 0x00000030U\r
+#define RTC_DR_DT_0 0x00000010U\r
+#define RTC_DR_DT_1 0x00000020U\r
+#define RTC_DR_DU 0x0000000FU\r
+#define RTC_DR_DU_0 0x00000001U\r
+#define RTC_DR_DU_1 0x00000002U\r
+#define RTC_DR_DU_2 0x00000004U\r
+#define RTC_DR_DU_3 0x00000008U\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_ITSE 0x01000000U \r
+#define RTC_CR_COE 0x00800000U\r
+#define RTC_CR_OSEL 0x00600000U\r
+#define RTC_CR_OSEL_0 0x00200000U\r
+#define RTC_CR_OSEL_1 0x00400000U\r
+#define RTC_CR_POL 0x00100000U\r
+#define RTC_CR_COSEL 0x00080000U\r
+#define RTC_CR_BCK 0x00040000U\r
+#define RTC_CR_SUB1H 0x00020000U\r
+#define RTC_CR_ADD1H 0x00010000U\r
+#define RTC_CR_TSIE 0x00008000U\r
+#define RTC_CR_WUTIE 0x00004000U\r
+#define RTC_CR_ALRBIE 0x00002000U\r
+#define RTC_CR_ALRAIE 0x00001000U\r
+#define RTC_CR_TSE 0x00000800U\r
+#define RTC_CR_WUTE 0x00000400U\r
+#define RTC_CR_ALRBE 0x00000200U\r
+#define RTC_CR_ALRAE 0x00000100U\r
+#define RTC_CR_FMT 0x00000040U\r
+#define RTC_CR_BYPSHAD 0x00000020U\r
+#define RTC_CR_REFCKON 0x00000010U\r
+#define RTC_CR_TSEDGE 0x00000008U\r
+#define RTC_CR_WUCKSEL 0x00000007U\r
+#define RTC_CR_WUCKSEL_0 0x00000001U\r
+#define RTC_CR_WUCKSEL_1 0x00000002U\r
+#define RTC_CR_WUCKSEL_2 0x00000004U\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_ITSF 0x00020000U\r
+#define RTC_ISR_RECALPF 0x00010000U\r
+#define RTC_ISR_TAMP3F 0x00008000U\r
+#define RTC_ISR_TAMP2F 0x00004000U\r
+#define RTC_ISR_TAMP1F 0x00002000U\r
+#define RTC_ISR_TSOVF 0x00001000U\r
+#define RTC_ISR_TSF 0x00000800U\r
+#define RTC_ISR_WUTF 0x00000400U\r
+#define RTC_ISR_ALRBF 0x00000200U\r
+#define RTC_ISR_ALRAF 0x00000100U\r
+#define RTC_ISR_INIT 0x00000080U\r
+#define RTC_ISR_INITF 0x00000040U\r
+#define RTC_ISR_RSF 0x00000020U\r
+#define RTC_ISR_INITS 0x00000010U\r
+#define RTC_ISR_SHPF 0x00000008U\r
+#define RTC_ISR_WUTWF 0x00000004U\r
+#define RTC_ISR_ALRBWF 0x00000002U\r
+#define RTC_ISR_ALRAWF 0x00000001U\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A 0x007F0000U\r
+#define RTC_PRER_PREDIV_S 0x00007FFFU\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT 0x0000FFFFU\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 0x80000000U\r
+#define RTC_ALRMAR_WDSEL 0x40000000U\r
+#define RTC_ALRMAR_DT 0x30000000U\r
+#define RTC_ALRMAR_DT_0 0x10000000U\r
+#define RTC_ALRMAR_DT_1 0x20000000U\r
+#define RTC_ALRMAR_DU 0x0F000000U\r
+#define RTC_ALRMAR_DU_0 0x01000000U\r
+#define RTC_ALRMAR_DU_1 0x02000000U\r
+#define RTC_ALRMAR_DU_2 0x04000000U\r
+#define RTC_ALRMAR_DU_3 0x08000000U\r
+#define RTC_ALRMAR_MSK3 0x00800000U\r
+#define RTC_ALRMAR_PM 0x00400000U\r
+#define RTC_ALRMAR_HT 0x00300000U\r
+#define RTC_ALRMAR_HT_0 0x00100000U\r
+#define RTC_ALRMAR_HT_1 0x00200000U\r
+#define RTC_ALRMAR_HU 0x000F0000U\r
+#define RTC_ALRMAR_HU_0 0x00010000U\r
+#define RTC_ALRMAR_HU_1 0x00020000U\r
+#define RTC_ALRMAR_HU_2 0x00040000U\r
+#define RTC_ALRMAR_HU_3 0x00080000U\r
+#define RTC_ALRMAR_MSK2 0x00008000U\r
+#define RTC_ALRMAR_MNT 0x00007000U\r
+#define RTC_ALRMAR_MNT_0 0x00001000U\r
+#define RTC_ALRMAR_MNT_1 0x00002000U\r
+#define RTC_ALRMAR_MNT_2 0x00004000U\r
+#define RTC_ALRMAR_MNU 0x00000F00U\r
+#define RTC_ALRMAR_MNU_0 0x00000100U\r
+#define RTC_ALRMAR_MNU_1 0x00000200U\r
+#define RTC_ALRMAR_MNU_2 0x00000400U\r
+#define RTC_ALRMAR_MNU_3 0x00000800U\r
+#define RTC_ALRMAR_MSK1 0x00000080U\r
+#define RTC_ALRMAR_ST 0x00000070U\r
+#define RTC_ALRMAR_ST_0 0x00000010U\r
+#define RTC_ALRMAR_ST_1 0x00000020U\r
+#define RTC_ALRMAR_ST_2 0x00000040U\r
+#define RTC_ALRMAR_SU 0x0000000FU\r
+#define RTC_ALRMAR_SU_0 0x00000001U\r
+#define RTC_ALRMAR_SU_1 0x00000002U\r
+#define RTC_ALRMAR_SU_2 0x00000004U\r
+#define RTC_ALRMAR_SU_3 0x00000008U\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 0x80000000U\r
+#define RTC_ALRMBR_WDSEL 0x40000000U\r
+#define RTC_ALRMBR_DT 0x30000000U\r
+#define RTC_ALRMBR_DT_0 0x10000000U\r
+#define RTC_ALRMBR_DT_1 0x20000000U\r
+#define RTC_ALRMBR_DU 0x0F000000U\r
+#define RTC_ALRMBR_DU_0 0x01000000U\r
+#define RTC_ALRMBR_DU_1 0x02000000U\r
+#define RTC_ALRMBR_DU_2 0x04000000U\r
+#define RTC_ALRMBR_DU_3 0x08000000U\r
+#define RTC_ALRMBR_MSK3 0x00800000U\r
+#define RTC_ALRMBR_PM 0x00400000U\r
+#define RTC_ALRMBR_HT 0x00300000U\r
+#define RTC_ALRMBR_HT_0 0x00100000U\r
+#define RTC_ALRMBR_HT_1 0x00200000U\r
+#define RTC_ALRMBR_HU 0x000F0000U\r
+#define RTC_ALRMBR_HU_0 0x00010000U\r
+#define RTC_ALRMBR_HU_1 0x00020000U\r
+#define RTC_ALRMBR_HU_2 0x00040000U\r
+#define RTC_ALRMBR_HU_3 0x00080000U\r
+#define RTC_ALRMBR_MSK2 0x00008000U\r
+#define RTC_ALRMBR_MNT 0x00007000U\r
+#define RTC_ALRMBR_MNT_0 0x00001000U\r
+#define RTC_ALRMBR_MNT_1 0x00002000U\r
+#define RTC_ALRMBR_MNT_2 0x00004000U\r
+#define RTC_ALRMBR_MNU 0x00000F00U\r
+#define RTC_ALRMBR_MNU_0 0x00000100U\r
+#define RTC_ALRMBR_MNU_1 0x00000200U\r
+#define RTC_ALRMBR_MNU_2 0x00000400U\r
+#define RTC_ALRMBR_MNU_3 0x00000800U\r
+#define RTC_ALRMBR_MSK1 0x00000080U\r
+#define RTC_ALRMBR_ST 0x00000070U\r
+#define RTC_ALRMBR_ST_0 0x00000010U\r
+#define RTC_ALRMBR_ST_1 0x00000020U\r
+#define RTC_ALRMBR_ST_2 0x00000040U\r
+#define RTC_ALRMBR_SU 0x0000000FU\r
+#define RTC_ALRMBR_SU_0 0x00000001U\r
+#define RTC_ALRMBR_SU_1 0x00000002U\r
+#define RTC_ALRMBR_SU_2 0x00000004U\r
+#define RTC_ALRMBR_SU_3 0x00000008U\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY 0x000000FFU\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS 0x0000FFFFU\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS 0x00007FFFU\r
+#define RTC_SHIFTR_ADD1S 0x80000000U\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM 0x00400000U\r
+#define RTC_TSTR_HT 0x00300000U\r
+#define RTC_TSTR_HT_0 0x00100000U\r
+#define RTC_TSTR_HT_1 0x00200000U\r
+#define RTC_TSTR_HU 0x000F0000U\r
+#define RTC_TSTR_HU_0 0x00010000U\r
+#define RTC_TSTR_HU_1 0x00020000U\r
+#define RTC_TSTR_HU_2 0x00040000U\r
+#define RTC_TSTR_HU_3 0x00080000U\r
+#define RTC_TSTR_MNT 0x00007000U\r
+#define RTC_TSTR_MNT_0 0x00001000U\r
+#define RTC_TSTR_MNT_1 0x00002000U\r
+#define RTC_TSTR_MNT_2 0x00004000U\r
+#define RTC_TSTR_MNU 0x00000F00U\r
+#define RTC_TSTR_MNU_0 0x00000100U\r
+#define RTC_TSTR_MNU_1 0x00000200U\r
+#define RTC_TSTR_MNU_2 0x00000400U\r
+#define RTC_TSTR_MNU_3 0x00000800U\r
+#define RTC_TSTR_ST 0x00000070U\r
+#define RTC_TSTR_ST_0 0x00000010U\r
+#define RTC_TSTR_ST_1 0x00000020U\r
+#define RTC_TSTR_ST_2 0x00000040U\r
+#define RTC_TSTR_SU 0x0000000FU\r
+#define RTC_TSTR_SU_0 0x00000001U\r
+#define RTC_TSTR_SU_1 0x00000002U\r
+#define RTC_TSTR_SU_2 0x00000004U\r
+#define RTC_TSTR_SU_3 0x00000008U\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU 0x0000E000U\r
+#define RTC_TSDR_WDU_0 0x00002000U\r
+#define RTC_TSDR_WDU_1 0x00004000U\r
+#define RTC_TSDR_WDU_2 0x00008000U\r
+#define RTC_TSDR_MT 0x00001000U\r
+#define RTC_TSDR_MU 0x00000F00U\r
+#define RTC_TSDR_MU_0 0x00000100U\r
+#define RTC_TSDR_MU_1 0x00000200U\r
+#define RTC_TSDR_MU_2 0x00000400U\r
+#define RTC_TSDR_MU_3 0x00000800U\r
+#define RTC_TSDR_DT 0x00000030U\r
+#define RTC_TSDR_DT_0 0x00000010U\r
+#define RTC_TSDR_DT_1 0x00000020U\r
+#define RTC_TSDR_DU 0x0000000FU\r
+#define RTC_TSDR_DU_0 0x00000001U\r
+#define RTC_TSDR_DU_1 0x00000002U\r
+#define RTC_TSDR_DU_2 0x00000004U\r
+#define RTC_TSDR_DU_3 0x00000008U\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS 0x0000FFFFU\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP 0x00008000U\r
+#define RTC_CALR_CALW8 0x00004000U\r
+#define RTC_CALR_CALW16 0x00002000U\r
+#define RTC_CALR_CALM 0x000001FFU\r
+#define RTC_CALR_CALM_0 0x00000001U\r
+#define RTC_CALR_CALM_1 0x00000002U\r
+#define RTC_CALR_CALM_2 0x00000004U\r
+#define RTC_CALR_CALM_3 0x00000008U\r
+#define RTC_CALR_CALM_4 0x00000010U\r
+#define RTC_CALR_CALM_5 0x00000020U\r
+#define RTC_CALR_CALM_6 0x00000040U\r
+#define RTC_CALR_CALM_7 0x00000080U\r
+#define RTC_CALR_CALM_8 0x00000100U\r
+\r
+/******************** Bits definition for RTC_TAMPCR register ****************/\r
+#define RTC_TAMPCR_TAMP3MF 0x01000000U\r
+#define RTC_TAMPCR_TAMP3NOERASE 0x00800000U\r
+#define RTC_TAMPCR_TAMP3IE 0x00400000U\r
+#define RTC_TAMPCR_TAMP2MF 0x00200000U\r
+#define RTC_TAMPCR_TAMP2NOERASE 0x00100000U\r
+#define RTC_TAMPCR_TAMP2IE 0x00080000U\r
+#define RTC_TAMPCR_TAMP1MF 0x00040000U\r
+#define RTC_TAMPCR_TAMP1NOERASE 0x00020000U\r
+#define RTC_TAMPCR_TAMP1IE 0x00010000U\r
+#define RTC_TAMPCR_TAMPPUDIS 0x00008000U\r
+#define RTC_TAMPCR_TAMPPRCH 0x00006000U\r
+#define RTC_TAMPCR_TAMPPRCH_0 0x00002000U\r
+#define RTC_TAMPCR_TAMPPRCH_1 0x00004000U\r
+#define RTC_TAMPCR_TAMPFLT 0x00001800U\r
+#define RTC_TAMPCR_TAMPFLT_0 0x00000800U\r
+#define RTC_TAMPCR_TAMPFLT_1 0x00001000U\r
+#define RTC_TAMPCR_TAMPFREQ 0x00000700U\r
+#define RTC_TAMPCR_TAMPFREQ_0 0x00000100U\r
+#define RTC_TAMPCR_TAMPFREQ_1 0x00000200U\r
+#define RTC_TAMPCR_TAMPFREQ_2 0x00000400U\r
+#define RTC_TAMPCR_TAMPTS 0x00000080U\r
+#define RTC_TAMPCR_TAMP3TRG 0x00000040U\r
+#define RTC_TAMPCR_TAMP3E 0x00000020U\r
+#define RTC_TAMPCR_TAMP2TRG 0x00000010U\r
+#define RTC_TAMPCR_TAMP2E 0x00000008U\r
+#define RTC_TAMPCR_TAMPIE 0x00000004U\r
+#define RTC_TAMPCR_TAMP1TRG 0x00000002U\r
+#define RTC_TAMPCR_TAMP1E 0x00000001U\r
+\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS 0x0F000000U\r
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U\r
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U\r
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U\r
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U\r
+#define RTC_ALRMASSR_SS 0x00007FFFU\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U\r
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U\r
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U\r
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U\r
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U\r
+#define RTC_ALRMBSSR_SS 0x00007FFFU\r
+\r
+/******************** Bits definition for RTC_OR register ****************/\r
+#define RTC_OR_TSINSEL 0x00000006U\r
+#define RTC_OR_TSINSEL_0 0x00000002U\r
+#define RTC_OR_TSINSEL_1 0x00000004U\r
+#define RTC_OR_ALARMTYPE 0x00000008U\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R 0xFFFFFFFFU\r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R 0xFFFFFFFFU\r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER 0x00000020U\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Audio Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SAI_GCR register *******************/\r
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */\r
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */\r
+ \r
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */\r
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */\r
+\r
+/******************* Bit definition for SAI_xCR1 register *******************/\r
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */\r
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */\r
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */\r
+ \r
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */\r
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */\r
+ \r
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */\r
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */\r
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */\r
+ \r
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */\r
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */\r
+ \r
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */\r
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */\r
+ \r
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */\r
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */\r
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */\r
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */\r
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */\r
+ \r
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */\r
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */\r
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */\r
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */\r
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */\r
+\r
+/******************* Bit definition for SAI_xCR2 register *******************/\r
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */\r
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */\r
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */\r
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */\r
+ \r
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */\r
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */\r
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */\r
+ \r
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */\r
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */\r
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */\r
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */\r
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */\r
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */\r
+ \r
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */\r
+ \r
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */\r
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SAI_xFRCR register *******************/\r
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */\r
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */\r
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */\r
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */\r
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */\r
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */\r
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */\r
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */\r
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */\r
+ \r
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */\r
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */\r
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */\r
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */\r
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */\r
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */\r
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */\r
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */\r
+ \r
+#define SAI_xFRCR_FSDEF 0x00010000U /*!<Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */\r
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */\r
+ \r
+/* Legacy define */ \r
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL\r
+\r
+/****************** Bit definition for SAI_xSLOTR register *******************/\r
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */\r
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */\r
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */\r
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */\r
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */\r
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */\r
+ \r
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */\r
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */\r
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */\r
+ \r
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */\r
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */\r
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */\r
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */\r
+ \r
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */\r
+\r
+/******************* Bit definition for SAI_xIMR register *******************/\r
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */\r
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */\r
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */\r
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */\r
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */\r
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */\r
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */\r
+\r
+/******************** Bit definition for SAI_xSR register *******************/\r
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */\r
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */\r
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */\r
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */\r
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */\r
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */\r
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */\r
+ \r
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */\r
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */\r
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */\r
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */\r
+\r
+/****************** Bit definition for SAI_xCLRFR register ******************/\r
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */\r
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */\r
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */\r
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */\r
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */\r
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */\r
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */\r
+\r
+/****************** Bit definition for SAI_xDR register *********************/\r
+#define SAI_xDR_DATA 0xFFFFFFFFU \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SPDIF-RX Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SPDIF_CR register *******************/\r
+#define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */\r
+#define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */\r
+#define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */\r
+#define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */\r
+#define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */\r
+#define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */\r
+#define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */\r
+#define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */\r
+#define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */\r
+#define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */\r
+#define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */\r
+#define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */\r
+#define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIF input selection */\r
+\r
+/******************* Bit definition for SPDIFRX_IMR register *******************/\r
+#define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */\r
+#define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */\r
+#define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */\r
+#define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */\r
+#define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */\r
+#define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */\r
+#define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */\r
+\r
+/******************* Bit definition for SPDIFRX_SR register *******************/\r
+#define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */\r
+#define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */\r
+#define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */\r
+#define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */\r
+#define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */\r
+#define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */\r
+#define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */\r
+#define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */\r
+#define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */\r
+#define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with spdif_clk */\r
+\r
+/******************* Bit definition for SPDIFRX_IFCR register *******************/\r
+#define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */\r
+#define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */\r
+#define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */\r
+#define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/\r
+#define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */\r
+#define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */\r
+#define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */\r
+#define SPDIFRX_DR0_U 0x04000000U /*!<User bit */\r
+#define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */\r
+#define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/\r
+#define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */\r
+#define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */\r
+#define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */\r
+#define SPDIFRX_DR1_U 0x00000004U /*!<User bit */\r
+#define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */\r
+#define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/\r
+#define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */\r
+#define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */\r
+\r
+/******************* Bit definition for SPDIFRX_CSR register *******************/\r
+#define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */\r
+#define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */\r
+#define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */\r
+\r
+/******************* Bit definition for SPDIFRX_DIR register *******************/\r
+#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */\r
+#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDMMC_POWER register ******************/\r
+#define SDMMC_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDMMC_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */\r
+#define SDMMC_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SDMMC_CLKCR register ******************/\r
+#define SDMMC_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */\r
+#define SDMMC_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */\r
+#define SDMMC_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */\r
+#define SDMMC_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */\r
+ \r
+#define SDMMC_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDMMC_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */\r
+#define SDMMC_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */\r
+ \r
+#define SDMMC_CLKCR_NEGEDGE 0x2000U /*!<SDMMC_CK dephasing selection bit */\r
+#define SDMMC_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDMMC_ARG register *******************/\r
+#define SDMMC_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */\r
+\r
+/******************* Bit definition for SDMMC_CMD register *******************/\r
+#define SDMMC_CMD_CMDINDEX 0x003FU /*!<Command Index */\r
+ \r
+#define SDMMC_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDMMC_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */\r
+#define SDMMC_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */\r
+ \r
+#define SDMMC_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */\r
+#define SDMMC_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDMMC_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDMMC_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */\r
+\r
+/***************** Bit definition for SDMMC_RESPCMD register *****************/\r
+#define SDMMC_RESPCMD_RESPCMD 0x3FU /*!<Response command index */\r
+\r
+/****************** Bit definition for SDMMC_RESP0 register ******************/\r
+#define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP1 register ******************/\r
+#define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP2 register ******************/\r
+#define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP3 register ******************/\r
+#define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP4 register ******************/\r
+#define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_DTIMER register *****************/\r
+#define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDMMC_DLEN register *******************/\r
+#define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */\r
+\r
+/****************** Bit definition for SDMMC_DCTRL register ******************/\r
+#define SDMMC_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */\r
+#define SDMMC_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */\r
+#define SDMMC_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */\r
+#define SDMMC_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */\r
+\r
+#define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */\r
+\r
+#define SDMMC_DCTRL_RWSTART 0x0100U /*!<Read wait start */\r
+#define SDMMC_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */\r
+#define SDMMC_DCTRL_RWMOD 0x0400U /*!<Read wait mode */\r
+#define SDMMC_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDMMC_DCOUNT register *****************/\r
+#define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */\r
+\r
+/****************** Bit definition for SDMMC_STA registe ********************/\r
+#define SDMMC_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */\r
+#define SDMMC_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */\r
+#define SDMMC_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */\r
+#define SDMMC_STA_DTIMEOUT 0x00000008U /*!<Data timeout */\r
+#define SDMMC_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */\r
+#define SDMMC_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */\r
+#define SDMMC_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */\r
+#define SDMMC_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */\r
+#define SDMMC_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDMMC_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */\r
+#define SDMMC_STA_CMDACT 0x00000800U /*!<Command transfer in progress */\r
+#define SDMMC_STA_TXACT 0x00001000U /*!<Data transmit in progress */\r
+#define SDMMC_STA_RXACT 0x00002000U /*!<Data receive in progress */\r
+#define SDMMC_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDMMC_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDMMC_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */\r
+#define SDMMC_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */\r
+#define SDMMC_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */\r
+#define SDMMC_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */\r
+#define SDMMC_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */\r
+#define SDMMC_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */\r
+#define SDMMC_STA_SDIOIT 0x00400000U /*!<SDMMC interrupt received */\r
+\r
+/******************* Bit definition for SDMMC_ICR register *******************/\r
+#define SDMMC_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */\r
+#define SDMMC_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */\r
+#define SDMMC_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */\r
+#define SDMMC_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */\r
+#define SDMMC_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */\r
+#define SDMMC_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */\r
+#define SDMMC_ICR_SDIOITC 0x00400000U /*!<SDMMCIT flag clear bit */\r
+\r
+/****************** Bit definition for SDMMC_MASK register *******************/\r
+#define SDMMC_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDMMC_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDMMC_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */\r
+#define SDMMC_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */\r
+#define SDMMC_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */\r
+#define SDMMC_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */\r
+#define SDMMC_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */\r
+#define SDMMC_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDMMC_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */\r
+#define SDMMC_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDMMC_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDMMC_MASK_SDIOITIE 0x00400000U /*!<SDMMC Mode Interrupt Received interrupt Enable */\r
+\r
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/\r
+#define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDMMC_FIFO register *******************/\r
+#define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA 0x00000001U /*!< Clock Phase */\r
+#define SPI_CR1_CPOL 0x00000002U /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR 0x00000004U /*!< Master Selection */\r
+#define SPI_CR1_BR 0x00000038U /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 0x00000008U /*!< Bit 0 */\r
+#define SPI_CR1_BR_1 0x00000010U /*!< Bit 1 */\r
+#define SPI_CR1_BR_2 0x00000020U /*!< Bit 2 */\r
+#define SPI_CR1_SPE 0x00000040U /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST 0x00000080U /*!< Frame Format */\r
+#define SPI_CR1_SSI 0x00000100U /*!< Internal slave select */\r
+#define SPI_CR1_SSM 0x00000200U /*!< Software slave management */\r
+#define SPI_CR1_RXONLY 0x00000400U /*!< Receive only */\r
+#define SPI_CR1_CRCL 0x00000800U /*!< CRC Length */\r
+#define SPI_CR1_CRCNEXT 0x00001000U /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN 0x00002000U /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE 0x00004000U /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE 0x00008000U /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN 0x00000001U /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN 0x00000002U /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE 0x00000004U /*!< SS Output Enable */\r
+#define SPI_CR2_NSSP 0x00000008U /*!< NSS pulse management Enable */\r
+#define SPI_CR2_FRF 0x00000010U /*!< Frame Format Enable */\r
+#define SPI_CR2_ERRIE 0x00000020U /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE 0x00000040U /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE 0x00000080U /*!< Tx buffer Empty Interrupt Enable */\r
+#define SPI_CR2_DS 0x00000F00U /*!< DS[3:0] Data Size */\r
+#define SPI_CR2_DS_0 0x00000100U /*!< Bit 0 */\r
+#define SPI_CR2_DS_1 0x00000200U /*!< Bit 1 */\r
+#define SPI_CR2_DS_2 0x00000400U /*!< Bit 2 */\r
+#define SPI_CR2_DS_3 0x00000800U /*!< Bit 3 */\r
+#define SPI_CR2_FRXTH 0x00001000U /*!< FIFO reception Threshold */\r
+#define SPI_CR2_LDMARX 0x00002000U /*!< Last DMA transfer for reception */\r
+#define SPI_CR2_LDMATX 0x00004000U /*!< Last DMA transfer for transmission */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE 0x00000001U /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE 0x00000002U /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE 0x00000004U /*!< Channel side */\r
+#define SPI_SR_UDR 0x00000008U /*!< Underrun flag */\r
+#define SPI_SR_CRCERR 0x00000010U /*!< CRC Error flag */\r
+#define SPI_SR_MODF 0x00000020U /*!< Mode fault */\r
+#define SPI_SR_OVR 0x00000040U /*!< Overrun flag */\r
+#define SPI_SR_BSY 0x00000080U /*!< Busy flag */\r
+#define SPI_SR_FRE 0x00000100U /*!< TI frame format error */\r
+#define SPI_SR_FRLVL 0x00000600U /*!< FIFO Reception Level */\r
+#define SPI_SR_FRLVL_0 0x00000200U /*!< Bit 0 */\r
+#define SPI_SR_FRLVL_1 0x00000400U /*!< Bit 1 */\r
+#define SPI_SR_FTLVL 0x00001800U /*!< FIFO Transmission Level */\r
+#define SPI_SR_FTLVL_0 0x00000800U /*!< Bit 0 */\r
+#define SPI_SR_FTLVL_1 0x00001000U /*!< Bit 1 */ \r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR 0xFFFFU /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY 0xFFFFU /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC 0xFFFFU /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC 0xFFFFU /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */\r
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */\r
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */\r
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */\r
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */\r
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */\r
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */\r
+#define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV 0x00FFU /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD 0x0100U /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE 0x0200U /*!<Master Clock Output Enable */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/ \r
+#define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U /*!< Boot information after Reset */\r
+\r
+#define SYSCFG_MEMRMP_SWP_FB 0x00000100U /*!< User Flash Bank swap */\r
+\r
+#define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U /*!< FMC Memory Mapping swapping */\r
+#define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U \r
+#define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U \r
+\r
+/****************** Bit definition for SYSCFG_PMC register ******************/\r
+#define SYSCFG_PMC_I2C1_FMP 0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C2_FMP 0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C3_FMP 0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C4_FMP 0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U /*!< PB6_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U /*!< PB7_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U /*!< PB8_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U /*!< PB9_FMP Fast Mode + Enable */\r
+\r
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */\r
+\r
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */\r
+ \r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */\r
+\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */\r
+\r
+/****************** Bit definition for SYSCFG_CBR register ******************/ \r
+#define SYSCFG_CBR_CLL 0x00000001U /*!<Core Lockup Lock */\r
+#define SYSCFG_CBR_PVDL 0x00000004U /*!<PVD Lock */\r
+\r
+/****************** Bit definition for SYSCFG_CMPCR register ****************/ \r
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell power-down */\r
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell ready flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */\r
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */\r
+#define TIM_CR1_URS 0x0004U /*!<Update request source */\r
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */\r
+#define TIM_CR1_DIR 0x0010U /*!<Direction */\r
+\r
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */\r
+#define TIM_CR1_UIFREMAP 0x0800U /*!<UIF status bit */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC 0x00000001U /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS 0x00000004U /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS 0x00000008U /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_OIS5 0x00010000U /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS6 0x00040000U /*!<Output Idle state 4 (OC4 output) */\r
+\r
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */\r
+\r
+#define TIM_CR2_MMS2 0x00F00000U /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS2_0 0x00100000U /*!<Bit 0 */\r
+#define TIM_CR2_MMS2_1 0x00200000U /*!<Bit 1 */\r
+#define TIM_CR2_MMS2_2 0x00400000U /*!<Bit 2 */\r
+#define TIM_CR2_MMS2_3 0x00800000U /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS 0x00010007U /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 0x00000001U /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 0x00000002U /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 0x00000004U /*!<Bit 2 */\r
+#define TIM_SMCR_SMS_3 0x00010000U /*!<Bit 3 */\r
+#define TIM_SMCR_OCCS 0x00000008U /*!< OCREF clear selection */\r
+\r
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */\r
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */\r
+#define TIM_SR_B2IF 0x0100U /*!<Break2 interrupt Flag */\r
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG 0x00000001U /*!<Update Generation */\r
+#define TIM_EGR_CC1G 0x00000002U /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G 0x00000004U /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G 0x00000008U /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G 0x00000010U /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG 0x00000020U /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG 0x00000040U /*!<Trigger Generation */\r
+#define TIM_EGR_BG 0x00000080U /*!<Break Generation */\r
+#define TIM_EGR_B2G 0x00000100U /*!<Break2 Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S 0x00000003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 0x00000001U /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 0x00000002U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE 0x00000004U /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE 0x00000008U /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M 0x00010070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 0x00000010U /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 0x00000020U /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 0x00000040U /*!<Bit 2 */\r
+#define TIM_CCMR1_OC1M_3 0x00010000U /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_OC1CE 0x00000080U /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S 0x00000300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 0x00000100U /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 0x00000200U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE 0x00000400U /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE 0x00000800U /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M 0x01007000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 0x00001000U /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 0x00002000U /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 0x00004000U /*!<Bit 2 */\r
+#define TIM_CCMR1_OC2M_3 0x01000000U /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_OC2CE 0x00008000U /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S 0x00000003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 0x00000001U /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 0x00000002U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE 0x00000004U /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE 0x00000008U /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M 0x00010070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 0x00000010U /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 0x00000020U /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 0x00000040U /*!<Bit 2 */\r
+#define TIM_CCMR2_OC3M_3 0x00010000U /*!<Bit 3 */\r
+\r
+\r
+\r
+#define TIM_CCMR2_OC3CE 0x00000080U /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S 0x00000300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 0x00000100U /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 0x00000200U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE 0x00000400U /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE 0x00000800U /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 0x00001000U /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 0x00002000U /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 0x00004000U /*!<Bit 2 */\r
+#define TIM_CCMR2_OC4M_3 0x01000000U /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E 0x00000001U /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P 0x00000002U /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE 0x00000004U /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP 0x00000008U /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E 0x00000010U /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P 0x00000020U /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE 0x00000040U /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP 0x00000080U /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E 0x00000100U /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P 0x00000200U /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE 0x00000400U /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP 0x00000800U /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E 0x00001000U /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P 0x00002000U /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP 0x00008000U /*!<Capture/Compare 4 Complementary output Polarity */\r
+#define TIM_CCER_CC5E 0x00010000U /*!<Capture/Compare 5 output enable */\r
+#define TIM_CCER_CC5P 0x00020000U /*!<Capture/Compare 5 output Polarity */\r
+#define TIM_CCER_CC6E 0x00100000U /*!<Capture/Compare 6 output enable */\r
+#define TIM_CCER_CC6P 0x00200000U /*!<Capture/Compare 6 output Polarity */\r
+\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFFU) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG 0x000000FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 0x00000001U /*!<Bit 0 */\r
+#define TIM_BDTR_DTG_1 0x00000002U /*!<Bit 1 */\r
+#define TIM_BDTR_DTG_2 0x00000004U /*!<Bit 2 */\r
+#define TIM_BDTR_DTG_3 0x00000008U /*!<Bit 3 */\r
+#define TIM_BDTR_DTG_4 0x00000010U /*!<Bit 4 */\r
+#define TIM_BDTR_DTG_5 0x00000020U /*!<Bit 5 */\r
+#define TIM_BDTR_DTG_6 0x00000040U /*!<Bit 6 */\r
+#define TIM_BDTR_DTG_7 0x00000080U /*!<Bit 7 */\r
+\r
+#define TIM_BDTR_LOCK 0x00000300U /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 0x00000100U /*!<Bit 0 */\r
+#define TIM_BDTR_LOCK_1 0x00000200U /*!<Bit 1 */\r
+\r
+#define TIM_BDTR_OSSI 0x00000400U /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR 0x00000800U /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE 0x00001000U /*!<Break enable */\r
+#define TIM_BDTR_BKP 0x00002000U /*!<Break Polarity */\r
+#define TIM_BDTR_AOE 0x00004000U /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE 0x00008000U /*!<Main Output enable */\r
+#define TIM_BDTR_BKF 0x000F0000U /*!<Break Filter for Break1 */\r
+#define TIM_BDTR_BK2F 0x00F00000U /*!<Break Filter for Break2 */\r
+#define TIM_BDTR_BK2E 0x01000000U /*!<Break enable for Break2 */\r
+#define TIM_BDTR_BK2P 0x02000000U /*!<Break Polarity for Break2 */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR regiter *********************/\r
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */\r
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */\r
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */\r
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */\r
+\r
+/****************** Bit definition for TIM_CCMR3 register *******************/\r
+#define TIM_CCMR3_OC5FE 0x00000004U /*!<Output Compare 5 Fast enable */\r
+#define TIM_CCMR3_OC5PE 0x00000008U /*!<Output Compare 5 Preload enable */\r
+\r
+#define TIM_CCMR3_OC5M 0x00010070U /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r
+#define TIM_CCMR3_OC5M_0 0x00000010U /*!<Bit 0 */\r
+#define TIM_CCMR3_OC5M_1 0x00000020U /*!<Bit 1 */\r
+#define TIM_CCMR3_OC5M_2 0x00000040U /*!<Bit 2 */\r
+#define TIM_CCMR3_OC5M_3 0x00010000U /*!<Bit 3 */\r
+\r
+#define TIM_CCMR3_OC5CE 0x00000080U /*!<Output Compare 5 Clear Enable */\r
+\r
+#define TIM_CCMR3_OC6FE 0x00000400U /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR3_OC6PE 0x00000800U /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR3_OC6M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR3_OC6M_0 0x00001000U /*!<Bit 0 */\r
+#define TIM_CCMR3_OC6M_1 0x00002000U /*!<Bit 1 */\r
+#define TIM_CCMR3_OC6M_2 0x00004000U /*!<Bit 2 */\r
+#define TIM_CCMR3_OC6M_3 0x01000000U /*!<Bit 3 */\r
+\r
+#define TIM_CCMR3_OC6CE 0x00008000U /*!<Output Compare 4 Clear Enable */\r
+\r
+/******************* Bit definition for TIM_CCR5 register *******************/\r
+#define TIM_CCR5_CCR5 0xFFFFFFFFU /*!<Capture/Compare 5 Value */\r
+#define TIM_CCR5_GC5C1 0x20000000U /*!<Group Channel 5 and Channel 1 */\r
+#define TIM_CCR5_GC5C2 0x40000000U /*!<Group Channel 5 and Channel 2 */\r
+#define TIM_CCR5_GC5C3 0x80000000U /*!<Group Channel 5 and Channel 3 */\r
+\r
+/******************* Bit definition for TIM_CCR6 register *******************/\r
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */\r
+\r
+/******************* Bit definition for TIM1_AF1 register *******************/\r
+#define TIM1_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */\r
+#define TIM1_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */\r
+\r
+/******************* Bit definition for TIM1_AF2 register *******************/\r
+#define TIM1_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN input enable */\r
+#define TIM1_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */\r
+\r
+/******************* Bit definition for TIM8_AF1 register *******************/\r
+#define TIM8_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */\r
+#define TIM8_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */\r
+\r
+/******************* Bit definition for TIM8_AF2 register *******************/\r
+#define TIM8_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN2 input enable */\r
+#define TIM8_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Low Power Timer (LPTIM) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for LPTIM_ISR register *******************/\r
+#define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */\r
+#define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */\r
+#define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */\r
+#define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */\r
+#define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */\r
+#define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */\r
+#define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */\r
+\r
+/****************** Bit definition for LPTIM_ICR register *******************/\r
+#define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */\r
+#define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */\r
+#define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */\r
+#define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */\r
+#define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */\r
+#define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */\r
+#define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */\r
+\r
+/****************** Bit definition for LPTIM_IER register *******************/\r
+#define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */\r
+#define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */\r
+#define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */\r
+#define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */\r
+#define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */\r
+#define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */\r
+#define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */\r
+\r
+/****************** Bit definition for LPTIM_CFGR register*******************/\r
+#define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */\r
+\r
+#define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */\r
+#define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */\r
+#define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
+#define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */\r
+#define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
+#define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */\r
+#define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */\r
+#define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */\r
+#define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */\r
+\r
+#define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
+#define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */\r
+#define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */\r
+\r
+#define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
+#define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */\r
+#define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */\r
+#define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */\r
+#define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */\r
+#define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */ \r
+#define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */ \r
+\r
+/****************** Bit definition for LPTIM_CR register ********************/\r
+#define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */\r
+#define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */\r
+#define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */\r
+\r
+/****************** Bit definition for LPTIM_CMP register *******************/\r
+#define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */\r
+\r
+/****************** Bit definition for LPTIM_ARR register *******************/\r
+#define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */\r
+\r
+/****************** Bit definition for LPTIM_CNT register *******************/\r
+#define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_UE 0x00000001U /*!< USART Enable */\r
+#define USART_CR1_RE 0x00000004U /*!< Receiver Enable */\r
+#define USART_CR1_TE 0x00000008U /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE 0x00000010U /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE 0x00000020U /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE 0x00000040U /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE 0x00000080U /*!< TXE Interrupt Enable */\r
+#define USART_CR1_PEIE 0x00000100U /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS 0x00000200U /*!< Parity Selection */\r
+#define USART_CR1_PCE 0x00000400U /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE 0x00000800U /*!< Receiver Wakeup method */\r
+#define USART_CR1_M 0x10001000U /*!< Word length */\r
+#define USART_CR1_M_0 0x00001000U /*!< Word length - Bit 0 */\r
+#define USART_CR1_MME 0x00002000U /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE 0x00004000U /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8 0x00008000U /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT 0x001F0000U /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0 0x00010000U /*!< Bit 0 */\r
+#define USART_CR1_DEDT_1 0x00020000U /*!< Bit 1 */\r
+#define USART_CR1_DEDT_2 0x00040000U /*!< Bit 2 */\r
+#define USART_CR1_DEDT_3 0x00080000U /*!< Bit 3 */\r
+#define USART_CR1_DEDT_4 0x00100000U /*!< Bit 4 */\r
+#define USART_CR1_DEAT 0x03E00000U /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0 0x00200000U /*!< Bit 0 */\r
+#define USART_CR1_DEAT_1 0x00400000U /*!< Bit 1 */\r
+#define USART_CR1_DEAT_2 0x00800000U /*!< Bit 2 */\r
+#define USART_CR1_DEAT_3 0x01000000U /*!< Bit 3 */\r
+#define USART_CR1_DEAT_4 0x02000000U /*!< Bit 4 */\r
+#define USART_CR1_RTOIE 0x04000000U /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE 0x08000000U /*!< End of Block interrupt enable */\r
+#define USART_CR1_M_1 0x10000000U /*!< Word length - Bit 1 */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADDM7 0x00000010U /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL 0x00000020U /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE 0x00000040U /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL 0x00000100U /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA 0x00000200U /*!< Clock Phase */\r
+#define USART_CR2_CPOL 0x00000400U /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN 0x00000800U /*!< Clock Enable */\r
+#define USART_CR2_STOP 0x00003000U /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 0x00001000U /*!< Bit 0 */\r
+#define USART_CR2_STOP_1 0x00002000U /*!< Bit 1 */\r
+#define USART_CR2_LINEN 0x00004000U /*!< LIN mode enable */\r
+#define USART_CR2_SWAP 0x00008000U /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV 0x00010000U /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV 0x00020000U /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV 0x00040000U /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST 0x00080000U /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN 0x00100000U /*!< Auto Baud-Rate Enable */\r
+#define USART_CR2_ABRMODE 0x00600000U /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0 0x00200000U /*!< Bit 0 */\r
+#define USART_CR2_ABRMODE_1 0x00400000U /*!< Bit 1 */\r
+#define USART_CR2_RTOEN 0x00800000U /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD 0xFF000000U /*!< Address of the USART node */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE 0x00000001U /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN 0x00000002U /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP 0x00000004U /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL 0x00000008U /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK 0x00000010U /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN 0x00000020U /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR 0x00000040U /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT 0x00000080U /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE 0x00000100U /*!< RTS Enable */\r
+#define USART_CR3_CTSE 0x00000200U /*!< CTS Enable */\r
+#define USART_CR3_CTSIE 0x00000400U /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT 0x00000800U /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS 0x00001000U /*!< Overrun Disable */\r
+#define USART_CR3_DDRE 0x00002000U /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM 0x00004000U /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP 0x00008000U /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT 0x000E0000U /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0 0x00020000U /*!< Bit 0 */\r
+#define USART_CR3_SCARCNT_1 0x00040000U /*!< Bit 1 */\r
+#define USART_CR3_SCARCNT_2 0x00080000U /*!< Bit 2 */\r
+\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION 0x000FU /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA 0xFFF0U /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC 0x00FFU /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT 0xFF00U /*!< GT[7:0] bits (Guard time value) */\r
+\r
+\r
+/******************* Bit definition for USART_RTOR register *****************/\r
+#define USART_RTOR_RTO 0x00FFFFFFU /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN 0xFF000000U /*!< Block Length */\r
+\r
+/******************* Bit definition for USART_RQR register ******************/\r
+#define USART_RQR_ABRRQ 0x0001U /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ 0x0002U /*!< Send Break Request */\r
+#define USART_RQR_MMRQ 0x0004U /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ 0x0008U /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ 0x0010U /*!< Transmit data flush Request */\r
+\r
+/******************* Bit definition for USART_ISR register ******************/\r
+#define USART_ISR_PE 0x00000001U /*!< Parity Error */\r
+#define USART_ISR_FE 0x00000002U /*!< Framing Error */\r
+#define USART_ISR_NE 0x00000004U /*!< Noise detected Flag */\r
+#define USART_ISR_ORE 0x00000008U /*!< OverRun Error */\r
+#define USART_ISR_IDLE 0x00000010U /*!< IDLE line detected */\r
+#define USART_ISR_RXNE 0x00000020U /*!< Read Data Register Not Empty */\r
+#define USART_ISR_TC 0x00000040U /*!< Transmission Complete */\r
+#define USART_ISR_TXE 0x00000080U /*!< Transmit Data Register Empty */\r
+#define USART_ISR_LBDF 0x00000100U /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF 0x00000200U /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS 0x00000400U /*!< CTS flag */\r
+#define USART_ISR_RTOF 0x00000800U /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF 0x00001000U /*!< End Of Block Flag */\r
+#define USART_ISR_ABRE 0x00004000U /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF 0x00008000U /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY 0x00010000U /*!< Busy Flag */\r
+#define USART_ISR_CMF 0x00020000U /*!< Character Match Flag */\r
+#define USART_ISR_SBKF 0x00040000U /*!< Send Break Flag */\r
+#define USART_ISR_RWU 0x00080000U /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_WUF 0x00100000U /*!< Wake Up from stop mode Flag */\r
+#define USART_ISR_TEACK 0x00200000U /*!< Transmit Enable Acknowledge Flag */\r
+#define USART_ISR_REACK 0x00400000U /*!< Receive Enable Acknowledge Flag */\r
+\r
+\r
+/******************* Bit definition for USART_ICR register ******************/\r
+#define USART_ICR_PECF 0x00000001U /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF 0x00000002U /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NCF 0x00000004U /*!< Noise detected Clear Flag */\r
+#define USART_ICR_ORECF 0x00000008U /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF 0x00000010U /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TCCF 0x00000040U /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_LBDCF 0x00000100U /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF 0x00000200U /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF 0x00000800U /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF 0x00001000U /*!< End Of Block Clear Flag */\r
+#define USART_ICR_CMCF 0x00020000U /*!< Character Match Clear Flag */\r
+#define USART_ICR_WUCF 0x00100000U /*!< Wake Up from stop mode Clear Flag */\r
+\r
+/******************* Bit definition for USART_RDR register ******************/\r
+#define USART_RDR_RDR 0x01FFU /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/******************* Bit definition for USART_TDR register ******************/\r
+#define USART_TDR_TDR 0x01FFU /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */\r
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */\r
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */\r
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */\r
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */\r
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */\r
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */\r
+\r
+\r
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */\r
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */\r
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */\r
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */\r
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */\r
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */\r
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */\r
+\r
+\r
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */\r
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */\r
+\r
+\r
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU\r
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U\r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U\r
+#define DBGMCU_CR_DBG_STOP 0x00000002U\r
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U\r
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U\r
+\r
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U\r
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U /*!<Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U /*!<Bit 1 */\r
+\r
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U\r
+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U\r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U\r
+\r
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U\r
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Ethernet MAC Registers bits definitions */\r
+/* */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */\r
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */\r
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */\r
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ \r
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ \r
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */\r
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */\r
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */\r
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */\r
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */\r
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */\r
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */\r
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */\r
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ \r
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */\r
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */\r
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */ \r
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */ \r
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */ \r
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */ \r
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */\r
+#define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */\r
+#define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */ \r
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */ \r
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */ \r
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */ \r
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */ \r
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */\r
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */ \r
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */ \r
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */ \r
+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
+#define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
+#define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+#define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+#define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ \r
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */ \r
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */ \r
+ \r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */\r
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */\r
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */\r
+#define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */\r
+#define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */\r
+#define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */ \r
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */\r
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */\r
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */\r
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */\r
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ \r
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */\r
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */\r
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */\r
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */\r
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */\r
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */\r
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */\r
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */\r
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */\r
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */\r
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */\r
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */\r
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */\r
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */\r
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */\r
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */\r
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */\r
+\r
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */\r
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */\r
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */\r
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */\r
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ \r
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */\r
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */\r
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */\r
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */\r
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */\r
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */\r
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */\r
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */\r
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */\r
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */\r
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */\r
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */\r
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */\r
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */\r
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */\r
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */\r
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */\r
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */\r
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */\r
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */\r
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */\r
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS 0x00000040U /* Receive status */\r
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */\r
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */\r
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */\r
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */\r
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */\r
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */\r
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* USB_OTG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/\r
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */\r
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */\r
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */\r
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */\r
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */\r
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */\r
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */\r
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */\r
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */\r
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */\r
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */\r
+\r
+/******************** Bit definition for USB_OTG_HCFG register ********************/\r
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */\r
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */\r
+\r
+/******************** Bit definition for USB_OTG_DCFG register ********************/\r
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */\r
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */\r
+\r
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */\r
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */\r
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */\r
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */\r
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */\r
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */\r
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */\r
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */\r
+\r
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */\r
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */\r
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */\r
+\r
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */\r
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */\r
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */\r
+\r
+/******************** Bit definition for USB_OTG_PCGCR register ********************/\r
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */\r
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */\r
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */\r
+\r
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/\r
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */\r
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */\r
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */\r
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */\r
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */\r
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */\r
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */\r
+\r
+/******************** Bit definition for USB_OTG_DCTL register ********************/\r
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */\r
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */\r
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */\r
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */\r
+\r
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */\r
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */\r
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */\r
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */\r
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */\r
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */\r
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */\r
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */\r
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */\r
+\r
+/******************** Bit definition for USB_OTG_HFIR register ********************/\r
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */\r
+\r
+/******************** Bit definition for USB_OTG_HFNUM register ********************/\r
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */\r
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */\r
+\r
+/******************** Bit definition for USB_OTG_DSTS register ********************/\r
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */\r
+\r
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */\r
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */\r
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */\r
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */\r
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */\r
+\r
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/\r
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */\r
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */\r
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */\r
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */\r
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */\r
+\r
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/\r
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */\r
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */\r
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */\r
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */\r
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */\r
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */\r
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */\r
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */\r
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */\r
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */\r
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */\r
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */\r
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */\r
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */\r
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */\r
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */\r
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */\r
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */\r
+\r
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/\r
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */\r
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */\r
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */\r
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */\r
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */\r
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */\r
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/\r
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/\r
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */\r
+\r
+/******************** Bit definition for USB_OTG_HAINT register ********************/\r
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/\r
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */\r
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */\r
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */\r
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */\r
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/\r
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */\r
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */\r
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */\r
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */\r
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */\r
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */\r
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */\r
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */\r
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */\r
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */\r
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */\r
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */\r
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */\r
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */\r
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */\r
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */\r
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */\r
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */\r
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */\r
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */\r
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */\r
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */\r
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */\r
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */\r
+\r
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/\r
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */\r
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */\r
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */\r
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */\r
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */\r
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */\r
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */\r
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */\r
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */\r
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */\r
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */\r
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */\r
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */\r
+#define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */\r
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */\r
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */\r
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */\r
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */\r
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */\r
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */\r
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_DAINT register ********************/\r
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */\r
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */\r
+\r
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/\r
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/\r
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */\r
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */\r
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */\r
+\r
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */\r
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */\r
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */\r
+\r
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */\r
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */\r
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */\r
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */\r
+\r
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */\r
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */\r
+\r
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */\r
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */\r
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */\r
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */\r
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */\r
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */\r
+\r
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */\r
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */\r
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */\r
+\r
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */\r
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */\r
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */\r
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */\r
+\r
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */\r
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */\r
+\r
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */\r
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */\r
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */\r
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */\r
+\r
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/\r
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/\r
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */\r
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */\r
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */\r
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/\r
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */\r
+\r
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */\r
+\r
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/\r
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */\r
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */\r
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */\r
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */\r
+\r
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/\r
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */\r
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */\r
+\r
+/******************** Bit definition for USB_OTG_GCCFG register ********************/\r
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */\r
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */\r
+\r
+/******************** Bit definition for USB_OTG_GPWRDN) register ********************/\r
+#define USB_OTG_GPWRDN_ADPMEN 0x00000001U /*!< ADP module enable */\r
+#define USB_OTG_GPWRDN_ADPIF 0x00800000U /*!< ADP Interrupt flag */\r
+\r
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */\r
+ \r
+/******************** Bit definition for USB_OTG_CID register ********************/\r
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */\r
+\r
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */\r
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */\r
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */\r
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */\r
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */\r
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */\r
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */\r
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */\r
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */\r
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */\r
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPRT register ********************/\r
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */\r
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */\r
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */\r
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */\r
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */\r
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */\r
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */\r
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */\r
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */\r
+\r
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */\r
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */\r
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */\r
+\r
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */\r
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */\r
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */\r
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */\r
+\r
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */\r
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/\r
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */\r
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/\r
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */\r
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */\r
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */\r
+\r
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */\r
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */\r
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */\r
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */\r
+\r
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */\r
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */\r
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */\r
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */\r
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */\r
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */\r
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/\r
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */\r
+\r
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */\r
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */\r
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */\r
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */\r
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */\r
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */\r
+\r
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */\r
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */\r
+\r
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */\r
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */\r
+\r
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */\r
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */\r
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */\r
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */\r
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */\r
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */\r
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */\r
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */\r
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */\r
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/\r
+\r
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */\r
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */\r
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */\r
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */\r
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */\r
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */\r
+\r
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */\r
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */\r
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */\r
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */\r
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */\r
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */\r
+\r
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */\r
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */\r
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCINT register ********************/\r
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */\r
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */\r
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */\r
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */\r
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */\r
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */\r
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */\r
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */\r
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */\r
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */\r
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/\r
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */\r
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */\r
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */\r
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */\r
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */\r
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */\r
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */\r
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */\r
+\r
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/\r
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */\r
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */\r
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */\r
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */\r
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */\r
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */\r
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */\r
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */\r
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */\r
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/\r
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */\r
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */\r
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */\r
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */\r
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */\r
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/\r
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */\r
+\r
+/******************** Bit definition for USB_OTG_HCDMA register ********************/\r
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */\r
+\r
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/\r
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/\r
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */\r
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/\r
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */\r
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */\r
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */\r
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */\r
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */\r
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */\r
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */\r
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */\r
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */\r
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */\r
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/\r
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */\r
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */\r
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */\r
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */\r
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */\r
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */\r
+\r
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */\r
+\r
+/******************** Bit definition for PCGCCTL register ********************/\r
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */\r
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* JPEG Encoder/Decoder */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for CONFR0 register ********************/\r
+#define JPEG_CONFR0_START 0x00000001U /*!<Start/Stop bit */ \r
+\r
+/******************** Bit definition for CONFR1 register *******************/\r
+#define JPEG_CONFR1_NF 0x00000003U /*!<Number of color components */ \r
+#define JPEG_CONFR1_NF_0 0x00000001U /*!<Bit 0 */ \r
+#define JPEG_CONFR1_NF_1 0x00000002U /*!<Bit 1 */\r
+#define JPEG_CONFR1_RE 0x00000004U /*!<Restart maker Enable */ \r
+#define JPEG_CONFR1_DE 0x00000008U /*!<Decoding Enable */ \r
+#define JPEG_CONFR1_COLORSPACE 0x00000030U /*!<Color Space */ \r
+#define JPEG_CONFR1_COLORSPACE_0 0x00000010U /*!<Bit 0 */ \r
+#define JPEG_CONFR1_COLORSPACE_1 0x00000020U /*!<Bit 1 */ \r
+#define JPEG_CONFR1_NS 0x000000C0U /*!<Number of components for Scan */ \r
+#define JPEG_CONFR1_NS_0 0x00000040U /*!<Bit 0 */ \r
+#define JPEG_CONFR1_NS_1 0x00000080U /*!<Bit 1 */\r
+#define JPEG_CONFR1_HDR 0x00000100U /*!<Header Processing On/Off */\r
+#define JPEG_CONFR1_YSIZE 0xFFFF0000U /*!<Number of lines in source image */\r
+\r
+/******************** Bit definition for CONFR2 register *******************/\r
+#define JPEG_CONFR2_NMCU 0x03FFFFFFU /*!<Number of MCU units minus 1 to encode */\r
+\r
+/******************** Bit definition for CONFR3 register *******************/\r
+#define JPEG_CONFR3_NRST 0x0000FFFFU /*!<Number of MCU between two restart makers minus 1 */\r
+#define JPEG_CONFR3_XSIZE 0xFFFF0000U /*!<Number of pixels per line */\r
+\r
+/******************** Bit definition for CONFR4 register *******************/\r
+#define JPEG_CONFR4_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */ \r
+#define JPEG_CONFR4_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */ \r
+#define JPEG_CONFR4_QT 0x0000000CU /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR4_QT_0 0x00000004U /*!<Bit 0 */\r
+#define JPEG_CONFR4_QT_1 0x00000008U /*!<Bit 1 */\r
+#define JPEG_CONFR4_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR4_NB_0 0x00000010U /*!<Bit 0 */\r
+#define JPEG_CONFR4_NB_1 0x00000020U /*!<Bit 1 */\r
+#define JPEG_CONFR4_NB_2 0x00000040U /*!<Bit 2 */\r
+#define JPEG_CONFR4_NB_3 0x00000080U /*!<Bit 3 */\r
+#define JPEG_CONFR4_VSF 0x00000F00U /*!<Vertical sampling factor for component 1 */\r
+#define JPEG_CONFR4_VSF_0 0x00000100U /*!<Bit 0 */\r
+#define JPEG_CONFR4_VSF_1 0x00000200U /*!<Bit 1 */\r
+#define JPEG_CONFR4_VSF_2 0x00000400U /*!<Bit 2 */\r
+#define JPEG_CONFR4_VSF_3 0x00000800U /*!<Bit 3 */\r
+#define JPEG_CONFR4_HSF 0x0000F000U /*!<Horizontal sampling factor for component 1 */\r
+#define JPEG_CONFR4_HSF_0 0x00001000U /*!<Bit 0 */\r
+#define JPEG_CONFR4_HSF_1 0x00002000U /*!<Bit 1 */\r
+#define JPEG_CONFR4_HSF_2 0x00004000U /*!<Bit 2 */\r
+#define JPEG_CONFR4_HSF_3 0x00008000U /*!<Bit 3 */\r
+\r
+/******************** Bit definition for CONFR5 register *******************/\r
+#define JPEG_CONFR5_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */ \r
+#define JPEG_CONFR5_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */ \r
+#define JPEG_CONFR5_QT 0x0000000CU /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR5_QT_0 0x00000004U /*!<Bit 0 */\r
+#define JPEG_CONFR5_QT_1 0x00000008U /*!<Bit 1 */\r
+#define JPEG_CONFR5_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR5_NB_0 0x00000010U /*!<Bit 0 */\r
+#define JPEG_CONFR5_NB_1 0x00000020U /*!<Bit 1 */\r
+#define JPEG_CONFR5_NB_2 0x00000040U /*!<Bit 2 */\r
+#define JPEG_CONFR5_NB_3 0x00000080U /*!<Bit 3 */\r
+#define JPEG_CONFR5_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR5_VSF_0 0x00000100U /*!<Bit 0 */\r
+#define JPEG_CONFR5_VSF_1 0x00000200U /*!<Bit 1 */\r
+#define JPEG_CONFR5_VSF_2 0x00000400U /*!<Bit 2 */\r
+#define JPEG_CONFR5_VSF_3 0x00000800U /*!<Bit 3 */\r
+#define JPEG_CONFR5_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR5_HSF_0 0x00001000U /*!<Bit 0 */\r
+#define JPEG_CONFR5_HSF_1 0x00002000U /*!<Bit 1 */\r
+#define JPEG_CONFR5_HSF_2 0x00004000U /*!<Bit 2 */\r
+#define JPEG_CONFR5_HSF_3 0x00008000U /*!<Bit 3 */\r
+\r
+/******************** Bit definition for CONFR6 register *******************/\r
+#define JPEG_CONFR6_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */ \r
+#define JPEG_CONFR6_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */ \r
+#define JPEG_CONFR6_QT 0x0000000CU /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR6_QT_0 0x00000004U /*!<Bit 0 */\r
+#define JPEG_CONFR6_QT_1 0x00000008U /*!<Bit 1 */\r
+#define JPEG_CONFR6_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR6_NB_0 0x00000010U /*!<Bit 0 */\r
+#define JPEG_CONFR6_NB_1 0x00000020U /*!<Bit 1 */\r
+#define JPEG_CONFR6_NB_2 0x00000040U /*!<Bit 2 */\r
+#define JPEG_CONFR6_NB_3 0x00000080U /*!<Bit 3 */\r
+#define JPEG_CONFR6_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR6_VSF_0 0x00000100U /*!<Bit 0 */\r
+#define JPEG_CONFR6_VSF_1 0x00000200U /*!<Bit 1 */\r
+#define JPEG_CONFR6_VSF_2 0x00000400U /*!<Bit 2 */\r
+#define JPEG_CONFR6_VSF_3 0x00000800U /*!<Bit 3 */\r
+#define JPEG_CONFR6_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR6_HSF_0 0x00001000U /*!<Bit 0 */\r
+#define JPEG_CONFR6_HSF_1 0x00002000U /*!<Bit 1 */\r
+#define JPEG_CONFR6_HSF_2 0x00004000U /*!<Bit 2 */\r
+#define JPEG_CONFR6_HSF_3 0x00008000U /*!<Bit 3 */\r
+\r
+/******************** Bit definition for CONFR7 register *******************/\r
+#define JPEG_CONFR7_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */ \r
+#define JPEG_CONFR7_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */ \r
+#define JPEG_CONFR7_QT 0x0000000CU /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR7_QT_0 0x00000004U /*!<Bit 0 */\r
+#define JPEG_CONFR7_QT_1 0x00000008U /*!<Bit 1 */\r
+#define JPEG_CONFR7_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR7_NB_0 0x00000010U /*!<Bit 0 */\r
+#define JPEG_CONFR7_NB_1 0x00000020U /*!<Bit 1 */\r
+#define JPEG_CONFR7_NB_2 0x00000040U /*!<Bit 2 */\r
+#define JPEG_CONFR7_NB_3 0x00000080U /*!<Bit 3 */\r
+#define JPEG_CONFR7_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR7_VSF_0 0x00000100U /*!<Bit 0 */\r
+#define JPEG_CONFR7_VSF_1 0x00000200U /*!<Bit 1 */\r
+#define JPEG_CONFR7_VSF_2 0x00000400U /*!<Bit 2 */\r
+#define JPEG_CONFR7_VSF_3 0x00000800U /*!<Bit 3 */\r
+#define JPEG_CONFR7_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR7_HSF_0 0x00001000U /*!<Bit 0 */\r
+#define JPEG_CONFR7_HSF_1 0x00002000U /*!<Bit 1 */\r
+#define JPEG_CONFR7_HSF_2 0x00004000U /*!<Bit 2 */\r
+#define JPEG_CONFR7_HSF_3 0x00008000U /*!<Bit 3 */\r
+\r
+/******************** Bit definition for CR register *******************/\r
+#define JPEG_CR_JCEN 0x00000001U /*!<Enable the JPEG Codec Core */\r
+#define JPEG_CR_IFTIE 0x00000002U /*!<Input FIFO Threshold Interrupt Enable */\r
+#define JPEG_CR_IFNFIE 0x00000004U /*!<Input FIFO Not Full Interrupt Enable */\r
+#define JPEG_CR_OFTIE 0x00000008U /*!<Output FIFO Threshold Interrupt Enable */\r
+#define JPEG_CR_OFNEIE 0x00000010U /*!<Output FIFO Not Empty Interrupt Enable */\r
+#define JPEG_CR_EOCIE 0x00000020U /*!<End of Conversion Interrupt Enable */\r
+#define JPEG_CR_HPDIE 0x00000040U /*!<Header Parsing Done Interrupt Enable */\r
+#define JPEG_CR_IDMAEN 0x00000800U /*!<Enable the DMA request generation for the input FIFO */\r
+#define JPEG_CR_ODMAEN 0x00001000U /*!<Enable the DMA request generation for the output FIFO */\r
+#define JPEG_CR_IFF 0x00002000U /*!<Flush the input FIFO */\r
+#define JPEG_CR_OFF 0x00004000U /*!<Flush the output FIFO */\r
+\r
+/******************** Bit definition for SR register *******************/\r
+#define JPEG_SR_IFTF 0x00000002U /*!<Input FIFO is not full and is bellow its threshold flag */\r
+#define JPEG_SR_IFNFF 0x00000004U /*!<Input FIFO Not Full Flag, a data can be written */\r
+#define JPEG_SR_OFTF 0x00000008U /*!<Output FIFO is not empty and has reach its threshold */\r
+#define JPEG_SR_OFNEF 0x000000010U /*!<Output FIFO is not empty, a data is available */\r
+#define JPEG_SR_EOCF 0x000000020U /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */\r
+#define JPEG_SR_HPDF 0x000000040U /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */\r
+#define JPEG_SR_COF 0x000000080U /*!<JPEG Codec operation on going flag */\r
+\r
+/******************** Bit definition for CFR register *******************/\r
+#define JPEG_CFR_CEOCF 0x00000020U /*!<Clear End of Conversion Flag */\r
+#define JPEG_CFR_CHPDF 0x00000040U /*!<Clear Header Parsing Done Flag */\r
+\r
+/******************** Bit definition for DIR register ********************/\r
+#define JPEG_DIR_DATAIN 0xFFFFFFFFU /*!<Data Input FIFO */\r
+\r
+/******************** Bit definition for DOR register ********************/\r
+#define JPEG_DOR_DATAOUT 0xFFFFFFFFU /*!<Data Output FIFO */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* MDIOS */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for MDIOS_CR register *******************/\r
+#define MDIOS_CR_EN 0x00000001U /*!<Peripheral enable */\r
+#define MDIOS_CR_WRIE 0x00000002U /*!<Register write interrupt enable */ \r
+#define MDIOS_CR_RDIE 0x00000004U /*!<Register Read Interrupt Enable */\r
+#define MDIOS_CR_EIE 0x00000008U /*!<Error interrupt enable */\r
+#define MDIOS_CR_DPC 0x00000080U /*!<Disable Preamble Check */\r
+#define MDIOS_CR_PORT_ADDRESS 0x00001F00U /*!<PORT_ADDRESS[4:0] bits */\r
+#define MDIOS_CR_PORT_ADDRESS_0 0x00000100U /*!<Bit 0 */\r
+#define MDIOS_CR_PORT_ADDRESS_1 0x00000200U /*!<Bit 1 */\r
+#define MDIOS_CR_PORT_ADDRESS_2 0x00000400U /*!<Bit 2 */\r
+#define MDIOS_CR_PORT_ADDRESS_3 0x00000800U /*!<Bit 3 */\r
+#define MDIOS_CR_PORT_ADDRESS_4 0x00001000U /*!<Bit 4 */\r
+\r
+/******************** Bit definition for MDIOS_WRFR register *******************/\r
+#define MDIOS_WRFR_WRF 0xFFFFFFFFU /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_CWRFR register *******************/\r
+#define MDIOS_CWRFR_CWRF 0xFFFFFFFFU /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_RDFR register *******************/\r
+#define MDIOS_RDFR_RDF 0xFFFFFFFFU /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_CRDFR register *******************/\r
+#define MDIOS_CRDFR_CRDF 0xFFFFFFFFU /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_SR register *******************/\r
+#define MDIOS_SR_PERF 0x00000001U /*!< Preamble error flag */\r
+#define MDIOS_SR_SERF 0x00000002U /*!< Start error flag */\r
+#define MDIOS_SR_TERF 0x00000004U /*!< Turnaround error flag */\r
+\r
+/******************** Bit definition for MDIOS_CLRFR register *******************/\r
+#define MDIOS_CLRFR_CPERF 0x00000001U /*!< Clear the preamble error flag */\r
+#define MDIOS_CLRFR_CSERF 0x00000002U /*!< Clear the start error flag */\r
+#define MDIOS_CLRFR_CTERF 0x00000004U /*!< Clear the turnaround error flag */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+\r
+/******************************* ADC Instances ********************************/\r
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \\r
+ ((__INSTANCE__) == ADC2) || \\r
+ ((__INSTANCE__) == ADC3))\r
+\r
+/******************************* CAN Instances ********************************/\r
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \\r
+ ((__INSTANCE__) == CAN2) || \\r
+ ((__INSTANCE__) == CAN3))\r
+/******************************* CRC Instances ********************************/\r
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)\r
+\r
+/******************************* DAC Instances ********************************/\r
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)\r
+\r
+/******************************* DCMI Instances *******************************/\r
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r
+\r
+/****************************** DFSDM Instances *******************************/\r
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\r
+ ((INSTANCE) == DFSDM1_Filter1) || \\r
+ ((INSTANCE) == DFSDM1_Filter2) || \\r
+ ((INSTANCE) == DFSDM1_Filter3))\r
+\r
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\r
+ ((INSTANCE) == DFSDM1_Channel1) || \\r
+ ((INSTANCE) == DFSDM1_Channel2) || \\r
+ ((INSTANCE) == DFSDM1_Channel3) || \\r
+ ((INSTANCE) == DFSDM1_Channel4) || \\r
+ ((INSTANCE) == DFSDM1_Channel5) || \\r
+ ((INSTANCE) == DFSDM1_Channel6) || \\r
+ ((INSTANCE) == DFSDM1_Channel7))\r
+\r
+/******************************* DMA2D Instances *******************************/\r
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r
+\r
+/******************************** DMA Instances *******************************/\r
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \\r
+ ((__INSTANCE__) == DMA1_Stream1) || \\r
+ ((__INSTANCE__) == DMA1_Stream2) || \\r
+ ((__INSTANCE__) == DMA1_Stream3) || \\r
+ ((__INSTANCE__) == DMA1_Stream4) || \\r
+ ((__INSTANCE__) == DMA1_Stream5) || \\r
+ ((__INSTANCE__) == DMA1_Stream6) || \\r
+ ((__INSTANCE__) == DMA1_Stream7) || \\r
+ ((__INSTANCE__) == DMA2_Stream0) || \\r
+ ((__INSTANCE__) == DMA2_Stream1) || \\r
+ ((__INSTANCE__) == DMA2_Stream2) || \\r
+ ((__INSTANCE__) == DMA2_Stream3) || \\r
+ ((__INSTANCE__) == DMA2_Stream4) || \\r
+ ((__INSTANCE__) == DMA2_Stream5) || \\r
+ ((__INSTANCE__) == DMA2_Stream6) || \\r
+ ((__INSTANCE__) == DMA2_Stream7))\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+ \r
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+\r
+/****************************** CEC Instances *********************************/\r
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r
+\r
+/****************************** QSPI Instances *********************************/\r
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r
+\r
+ \r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\r
+ ((__INSTANCE__) == I2C2) || \\r
+ ((__INSTANCE__) == I2C3) || \\r
+ ((__INSTANCE__) == I2C4))\r
+\r
+/******************************** I2S Instances *******************************/\r
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3))\r
+\r
+/******************************* LPTIM Instances ********************************/\r
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\r
+\r
+/****************************** LTDC Instances ********************************/\r
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)\r
+\r
+/****************************** MDIOS Instances ********************************/\r
+#define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)\r
+\r
+/****************************** MDIOS Instances ********************************/\r
+#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)\r
+\r
+/******************************* RNG Instances ********************************/\r
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)\r
+\r
+/******************************* SAI Instances ********************************/\r
+#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \\r
+ ((__PERIPH__) == SAI1_Block_B) || \\r
+ ((__PERIPH__) == SAI2_Block_A) || \\r
+ ((__PERIPH__) == SAI2_Block_B))\r
+/* Legacy define */\r
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\r
+\r
+/******************************** SDMMC Instances *******************************/\r
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \\r
+ ((__INSTANCE__) == SDMMC2))\r
+\r
+/****************************** SPDIFRX Instances *********************************/\r
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)\r
+ \r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3) || \\r
+ ((__INSTANCE__) == SPI4) || \\r
+ ((__INSTANCE__) == SPI5) || \\r
+ ((__INSTANCE__) == SPI6))\r
+\r
+/****************** TIM Instances : All supported instances *******************/\r
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************* TIM Instances : at least 1 capture/compare channel *************/\r
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************ TIM Instances : at least 2 capture/compare channels *************/\r
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/************ TIM Instances : at least 3 capture/compare channels *************/\r
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : at least 4 capture/compare channels *************/\r
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting OCxREF clear *******************/\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+/****************** TIM Instances : at least 5 capture/compare channels *******/\r
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : at least 6 capture/compare channels *******/\r
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+ \r
+/******************** TIM Instances : Advanced-control timers *****************/\r
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting 2 break inputs *****************/\r
+#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/******************* TIM Instances : Timer input XOR function *****************/\r
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : DMA requests generation (UDE) *************/\r
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (COMDE) *****************/\r
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8)) \r
+\r
+/******************** TIM Instances : DMA burst feature ***********************/\r
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/********************** TIM Instances : 32 bit Counter ************************/\r
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5))\r
+\r
+/***************** TIM Instances : external trigger input available ************/\r
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : remapping capability **********************/\r
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM11))\r
+\r
+/******************* TIM Instances : output(s) available **********************/\r
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM2) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM3) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM4) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM5) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM9) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM10) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM11) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM12) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM13) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM14) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))))\r
+\r
+/************ TIM Instances : complementary output(s) available ***************/\r
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))))\r
+\r
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : supporting synchronization ****************/\r
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8)) \r
+ \r
+/******************** USART Instances : Synchronous mode **********************/\r
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Driver Enable *****************/\r
+#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Hardware Flow control ********************/\r
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/********************* UART Instances : Smart card mode ***********************/\r
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/*********************** UART Instances : IRDA mode ***************************/\r
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8)) \r
+\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)\r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)\r
+\r
+\r
+/******************************************************************************/\r
+/* For a painless codes migration between the STM32F7xx device product */\r
+/* lines, the aliases defined below are put in place to overcome the */\r
+/* differences in the interrupt handlers and IRQn definitions. */\r
+/* No need to update developed interrupt code when moving across */\r
+/* product lines within the same STM32F7 Family */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+#define HASH_RNG_IRQn RNG_IRQn\r
+\r
+/* Aliases for __IRQHandler */\r
+#define HASH_RNG_IRQHandler RNG_IRQHandler\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F767xx_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File. \r
+ * \r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The STM32F7xx device used in the target application\r
+ * - To use or not the peripheral\92s drivers in application code(i.e. \r
+ * code will be based on direct access to peripheral\92s registers \r
+ * rather than drivers API), this option is controlled by \r
+ * "#define USE_HAL_DRIVER"\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F7xx_H\r
+#define __STM32F7xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32 Family\r
+ */\r
+#if !defined (STM32F7)\r
+#define STM32F7\r
+#endif /* STM32F7 */\r
+\r
+/* Uncomment the line below according to the target STM32 device used in your\r
+ application \r
+ */\r
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \\r
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)\r
+ /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,\r
+ STM32F756NG Devices */\r
+ /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,\r
+ STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */\r
+ /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */\r
+ /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,\r
+ STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */\r
+ /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,\r
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */\r
+ /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,\r
+ STM32F769NG, STM32F769NI Devices */\r
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */\r
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */\r
+#endif\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+\r
+#if !defined (USE_HAL_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_HAL_DRIVER */\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+/**\r
+ * @brief CMSIS Device version number V1.1.0\r
+ */\r
+#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */\r
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\\r
+ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\\r
+ |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\\r
+ |(__STM32F7_CMSIS_VERSION))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Device_Included\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx)\r
+ #include "stm32f756xx.h"\r
+#elif defined(STM32F746xx)\r
+ #include "stm32f746xx.h"\r
+#elif defined(STM32F745xx)\r
+ #include "stm32f745xx.h"\r
+#elif defined(STM32F765xx)\r
+ #include "stm32f765xx.h"\r
+#elif defined(STM32F767xx)\r
+ #include "stm32f767xx.h"\r
+#elif defined(STM32F769xx)\r
+ #include "stm32f769xx.h"\r
+#elif defined(STM32F777xx)\r
+ #include "stm32f777xx.h"\r
+#elif defined(STM32F779xx)\r
+ #include "stm32f779xx.h" \r
+#else\r
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+typedef enum \r
+{\r
+ RESET = 0, \r
+ SET = !RESET\r
+} FlagStatus, ITStatus;\r
+\r
+typedef enum \r
+{\r
+ DISABLE = 0, \r
+ ENABLE = !DISABLE\r
+} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum \r
+{\r
+ ERROR = 0, \r
+ SUCCESS = !ERROR\r
+} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef USE_HAL_DRIVER\r
+ #include "stm32f7xx_hal_conf.h"\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F7xx_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f7xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. \r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F7XX_H\r
+#define __SYSTEM_STM32F7XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F7xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Variables\r
+ * @{\r
+ */\r
+ /* The SystemCoreClock variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */\r
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F7XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f767xx.s\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief STM32F767xx Devices vector table for GCC based toolchain. \r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M7 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+ \r
+ .syntax unified\r
+ .cpu cortex-m7\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section. \r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */ \r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+ ldr sp, =_estack /* set stack pointer */\r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+\r
+/* Call the clock system initialization function.*/\r
+ bl SystemInit \r
+/* Call static constructors */\r
+ bl __libc_init_array\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ * @param None \r
+ * @retval None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M7. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+* \r
+*******************************************************************************/\r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+ \r
+ \r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ \r
+ /* External Interrupts */\r
+ .word WWDG_IRQHandler /* Window WatchDog */\r
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */\r
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */\r
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */\r
+ .word FLASH_IRQHandler /* FLASH */\r
+ .word RCC_IRQHandler /* RCC */\r
+ .word EXTI0_IRQHandler /* EXTI Line0 */\r
+ .word EXTI1_IRQHandler /* EXTI Line1 */\r
+ .word EXTI2_IRQHandler /* EXTI Line2 */\r
+ .word EXTI3_IRQHandler /* EXTI Line3 */\r
+ .word EXTI4_IRQHandler /* EXTI Line4 */\r
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */\r
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */\r
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */\r
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */\r
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */\r
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */\r
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */\r
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */\r
+ .word CAN1_TX_IRQHandler /* CAN1 TX */\r
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */\r
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */\r
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */\r
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */\r
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */\r
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */\r
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */\r
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */\r
+ .word TIM2_IRQHandler /* TIM2 */\r
+ .word TIM3_IRQHandler /* TIM3 */\r
+ .word TIM4_IRQHandler /* TIM4 */\r
+ .word I2C1_EV_IRQHandler /* I2C1 Event */\r
+ .word I2C1_ER_IRQHandler /* I2C1 Error */\r
+ .word I2C2_EV_IRQHandler /* I2C2 Event */\r
+ .word I2C2_ER_IRQHandler /* I2C2 Error */\r
+ .word SPI1_IRQHandler /* SPI1 */\r
+ .word SPI2_IRQHandler /* SPI2 */\r
+ .word USART1_IRQHandler /* USART1 */\r
+ .word USART2_IRQHandler /* USART2 */\r
+ .word USART3_IRQHandler /* USART3 */\r
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */\r
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */\r
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */\r
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */\r
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */\r
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */\r
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */\r
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */\r
+ .word FMC_IRQHandler /* FMC */\r
+ .word SDMMC1_IRQHandler /* SDMMC1 */\r
+ .word TIM5_IRQHandler /* TIM5 */\r
+ .word SPI3_IRQHandler /* SPI3 */\r
+ .word UART4_IRQHandler /* UART4 */\r
+ .word UART5_IRQHandler /* UART5 */\r
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */\r
+ .word TIM7_IRQHandler /* TIM7 */\r
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */\r
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */\r
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */\r
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */\r
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */\r
+ .word ETH_IRQHandler /* Ethernet */\r
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */\r
+ .word CAN2_TX_IRQHandler /* CAN2 TX */\r
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */\r
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */\r
+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */\r
+ .word OTG_FS_IRQHandler /* USB OTG FS */\r
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */\r
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */\r
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */\r
+ .word USART6_IRQHandler /* USART6 */\r
+ .word I2C3_EV_IRQHandler /* I2C3 event */\r
+ .word I2C3_ER_IRQHandler /* I2C3 error */\r
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */\r
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */\r
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */\r
+ .word OTG_HS_IRQHandler /* USB OTG HS */\r
+ .word DCMI_IRQHandler /* DCMI */\r
+ .word 0 /* Reserved */\r
+ .word RNG_IRQHandler /* RNG */\r
+ .word FPU_IRQHandler /* FPU */\r
+ .word UART7_IRQHandler /* UART7 */\r
+ .word UART8_IRQHandler /* UART8 */\r
+ .word SPI4_IRQHandler /* SPI4 */\r
+ .word SPI5_IRQHandler /* SPI5 */\r
+ .word SPI6_IRQHandler /* SPI6 */\r
+ .word SAI1_IRQHandler /* SAI1 */\r
+ .word LTDC_IRQHandler /* LTDC */\r
+ .word LTDC_ER_IRQHandler /* LTDC error */\r
+ .word DMA2D_IRQHandler /* DMA2D */\r
+ .word SAI2_IRQHandler /* SAI2 */\r
+ .word QUADSPI_IRQHandler /* QUADSPI */\r
+ .word LPTIM1_IRQHandler /* LPTIM1 */\r
+ .word CEC_IRQHandler /* HDMI_CEC */\r
+ .word I2C4_EV_IRQHandler /* I2C4 Event */\r
+ .word I2C4_ER_IRQHandler /* I2C4 Error */\r
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */\r
+ .word 0 /* Reserved */\r
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */\r
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */\r
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */\r
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */\r
+ .word SDMMC2_IRQHandler /* SDMMC2 */\r
+ .word CAN3_TX_IRQHandler /* CAN3 TX */\r
+ .word CAN3_RX0_IRQHandler /* CAN3 RX0 */\r
+ .word CAN3_RX1_IRQHandler /* CAN3 RX1 */\r
+ .word CAN3_SCE_IRQHandler /* CAN3 SCE */\r
+ .word JPEG_IRQHandler /* JPEG */\r
+ .word MDIOS_IRQHandler /* MDIOS */\r
+ \r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler. \r
+* As they are weak aliases, any function with the same name will override \r
+* this definition.\r
+* \r
+*******************************************************************************/\r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+ \r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+ \r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+ \r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler \r
+ \r
+ .weak WWDG_IRQHandler \r
+ .thumb_set WWDG_IRQHandler,Default_Handler \r
+ \r
+ .weak PVD_IRQHandler \r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+ \r
+ .weak TAMP_STAMP_IRQHandler \r
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r
+ \r
+ .weak RTC_WKUP_IRQHandler \r
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
+ \r
+ .weak FLASH_IRQHandler \r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+ \r
+ .weak RCC_IRQHandler \r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI0_IRQHandler \r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI1_IRQHandler \r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI2_IRQHandler \r
+ .thumb_set EXTI2_IRQHandler,Default_Handler \r
+ \r
+ .weak EXTI3_IRQHandler \r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI4_IRQHandler \r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream0_IRQHandler \r
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream1_IRQHandler \r
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream2_IRQHandler \r
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream3_IRQHandler \r
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler \r
+ \r
+ .weak DMA1_Stream4_IRQHandler \r
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream5_IRQHandler \r
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream6_IRQHandler \r
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\r
+ \r
+ .weak ADC_IRQHandler \r
+ .thumb_set ADC_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_TX_IRQHandler \r
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_RX0_IRQHandler \r
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_RX1_IRQHandler \r
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_SCE_IRQHandler \r
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI9_5_IRQHandler \r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_BRK_TIM9_IRQHandler \r
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_UP_TIM10_IRQHandler \r
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_TRG_COM_TIM11_IRQHandler \r
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_CC_IRQHandler \r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM2_IRQHandler \r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM3_IRQHandler \r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM4_IRQHandler \r
+ .thumb_set TIM4_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C1_EV_IRQHandler \r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C1_ER_IRQHandler \r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C2_EV_IRQHandler \r
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C2_ER_IRQHandler \r
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI1_IRQHandler \r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI2_IRQHandler \r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+ \r
+ .weak USART1_IRQHandler \r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+ \r
+ .weak USART2_IRQHandler \r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+ \r
+ .weak USART3_IRQHandler \r
+ .thumb_set USART3_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI15_10_IRQHandler \r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+ \r
+ .weak RTC_Alarm_IRQHandler \r
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_FS_WKUP_IRQHandler \r
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_BRK_TIM12_IRQHandler \r
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_UP_TIM13_IRQHandler \r
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_TRG_COM_TIM14_IRQHandler \r
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_CC_IRQHandler \r
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream7_IRQHandler \r
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\r
+ \r
+ .weak FMC_IRQHandler \r
+ .thumb_set FMC_IRQHandler,Default_Handler\r
+ \r
+ .weak SDMMC1_IRQHandler \r
+ .thumb_set SDMMC1_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM5_IRQHandler \r
+ .thumb_set TIM5_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI3_IRQHandler \r
+ .thumb_set SPI3_IRQHandler,Default_Handler\r
+ \r
+ .weak UART4_IRQHandler \r
+ .thumb_set UART4_IRQHandler,Default_Handler\r
+ \r
+ .weak UART5_IRQHandler \r
+ .thumb_set UART5_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM6_DAC_IRQHandler \r
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM7_IRQHandler \r
+ .thumb_set TIM7_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream0_IRQHandler \r
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream1_IRQHandler \r
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream2_IRQHandler \r
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream3_IRQHandler \r
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream4_IRQHandler \r
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream4_IRQHandler \r
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler \r
+\r
+ .weak ETH_IRQHandler \r
+ .thumb_set ETH_IRQHandler,Default_Handler\r
+ \r
+ .weak ETH_WKUP_IRQHandler \r
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_TX_IRQHandler \r
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler \r
+ \r
+ .weak CAN2_RX0_IRQHandler \r
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN2_RX1_IRQHandler \r
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN2_SCE_IRQHandler \r
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_FS_IRQHandler \r
+ .thumb_set OTG_FS_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream5_IRQHandler \r
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream6_IRQHandler \r
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream7_IRQHandler \r
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\r
+ \r
+ .weak USART6_IRQHandler \r
+ .thumb_set USART6_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C3_EV_IRQHandler \r
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C3_ER_IRQHandler \r
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_EP1_OUT_IRQHandler \r
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_EP1_IN_IRQHandler \r
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_WKUP_IRQHandler \r
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_IRQHandler \r
+ .thumb_set OTG_HS_IRQHandler,Default_Handler\r
+ \r
+ .weak DCMI_IRQHandler \r
+ .thumb_set DCMI_IRQHandler,Default_Handler\r
+\r
+ .weak RNG_IRQHandler \r
+ .thumb_set RNG_IRQHandler,Default_Handler \r
+\r
+ .weak FPU_IRQHandler \r
+ .thumb_set FPU_IRQHandler,Default_Handler\r
+\r
+ .weak UART7_IRQHandler \r
+ .thumb_set UART7_IRQHandler,Default_Handler\r
+\r
+ .weak UART8_IRQHandler \r
+ .thumb_set UART8_IRQHandler,Default_Handler \r
+\r
+ .weak SPI4_IRQHandler \r
+ .thumb_set SPI4_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI5_IRQHandler \r
+ .thumb_set SPI5_IRQHandler,Default_Handler\r
+\r
+ .weak SPI6_IRQHandler \r
+ .thumb_set SPI6_IRQHandler,Default_Handler \r
+\r
+ .weak SAI1_IRQHandler \r
+ .thumb_set SAI1_IRQHandler,Default_Handler\r
+ \r
+ .weak LTDC_IRQHandler \r
+ .thumb_set LTDC_IRQHandler,Default_Handler\r
+\r
+ .weak LTDC_ER_IRQHandler \r
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2D_IRQHandler \r
+ .thumb_set DMA2D_IRQHandler,Default_Handler \r
+\r
+ .weak SAI2_IRQHandler \r
+ .thumb_set SAI2_IRQHandler,Default_Handler\r
+ \r
+ .weak QUADSPI_IRQHandler \r
+ .thumb_set QUADSPI_IRQHandler,Default_Handler\r
+ \r
+ .weak LPTIM1_IRQHandler \r
+ .thumb_set LPTIM1_IRQHandler,Default_Handler\r
+\r
+ .weak CEC_IRQHandler \r
+ .thumb_set CEC_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C4_EV_IRQHandler \r
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler \r
+ \r
+ .weak I2C4_ER_IRQHandler \r
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak SPDIF_RX_IRQHandler \r
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT0_IRQHandler \r
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT1_IRQHandler \r
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT2_IRQHandler \r
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT3_IRQHandler \r
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler\r
+\r
+ .weak SDMMC2_IRQHandler \r
+ .thumb_set SDMMC2_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_TX_IRQHandler \r
+ .thumb_set CAN3_TX_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_RX0_IRQHandler \r
+ .thumb_set CAN3_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_RX1_IRQHandler \r
+ .thumb_set CAN3_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_SCE_IRQHandler \r
+ .thumb_set CAN3_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak JPEG_IRQHandler \r
+ .thumb_set JPEG_IRQHandler,Default_Handler\r
+\r
+ .weak MDIOS_IRQHandler \r
+ .thumb_set MDIOS_IRQHandler,Default_Handler \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+ \r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f7xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r
+ *\r
+ * This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f7xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F7xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f7xx.h"\r
+\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+ uint32_t SystemCoreClock = 16000000;\r
+ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U)\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ int32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __builtin_clz\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x04) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+#endif\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x07U) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "core_cmInstr.h" /* Core Instruction Access */\r
+#include "core_cmFunc.h" /* Core Function Access */\r
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000U\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0U\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0U\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DTCM_PRESENT\r
+ #define __DTCM_PRESENT 0U\r
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable External Interrupt\r
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable External Interrupt\r
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of an external interrupt.\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of an external interrupt.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of an interrupt.\r
+ \note The priority cannot be set for every core interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of an interrupt.\r
+ The interrupt number can be positive to specify an external (device specific) interrupt,\r
+ or negative to specify an internal (core) interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = SCB->MVFR0;\r
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL)\r
+ {\r
+ return 2UL; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)\r
+ {\r
+ return 1UL; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0UL; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+\r
+\r
+/**\r
+ \brief Enable I-Cache\r
+ \details Turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable I-Cache\r
+ \details Turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate I-Cache\r
+ \details Invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable D-Cache\r
+ \details Turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+ __DSB();\r
+\r
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable D-Cache\r
+ \details Turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate D-Cache\r
+ \details Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean D-Cache\r
+ \details Cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean & Invalidate D-Cache\r
+ \details Cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Invalidate by address\r
+ \details Invalidates D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t)addr;\r
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCIMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean by address\r
+ \details Cleans D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean and Invalidate by address\r
+ \details Cleans and invalidates D_Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCIMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmSimd.h\r
+ * @brief CMSIS Cortex-M SIMD Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CMSIMD_H */\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_hal_legacy.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief This file contains aliases definition for the STM32Cube HAL constants \r
+ * macros and functions maintained for legacy purpose.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32_HAL_LEGACY\r
+#define __STM32_HAL_LEGACY\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR\r
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR\r
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF\r
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR\r
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B\r
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B\r
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B\r
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B\r
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN\r
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED\r
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV\r
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV\r
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV\r
+#define REGULAR_GROUP ADC_REGULAR_GROUP\r
+#define INJECTED_GROUP ADC_INJECTED_GROUP\r
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP\r
+#define AWD_EVENT ADC_AWD_EVENT\r
+#define AWD1_EVENT ADC_AWD1_EVENT\r
+#define AWD2_EVENT ADC_AWD2_EVENT\r
+#define AWD3_EVENT ADC_AWD3_EVENT\r
+#define OVR_EVENT ADC_OVR_EVENT\r
+#define JQOVF_EVENT ADC_JQOVF_EVENT\r
+#define ALL_CHANNELS ADC_ALL_CHANNELS\r
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS\r
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS\r
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR\r
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8\r
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO \r
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 \r
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO \r
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 \r
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO\r
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11\r
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1\r
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE\r
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING\r
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING\r
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5\r
+\r
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY\r
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY\r
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC\r
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC\r
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL\r
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL\r
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */ \r
+ \r
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE\r
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE\r
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1\r
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2\r
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3\r
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4\r
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5\r
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6\r
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7\r
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR\r
+#if defined(STM32F373xC) || defined(STM32F378xx)\r
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1\r
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR\r
+#endif /* STM32F373xC || STM32F378xx */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r
+\r
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1\r
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2\r
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3\r
+ \r
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT\r
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT\r
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT\r
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT\r
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1\r
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2\r
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3\r
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4\r
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5\r
+\r
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW\r
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH\r
+\r
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */\r
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */\r
+#if defined(COMP_CSR_LOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_LOCK\r
+#elif defined(COMP_CSR_COMP1LOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK\r
+#elif defined(COMP_CSR_COMPxLOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1\r
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2\r
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2\r
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2\r
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE\r
+#endif\r
+\r
+#if defined(STM32L0)\r
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER\r
+#else\r
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED\r
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER\r
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER\r
+#endif\r
+\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE\r
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2\r
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC_WAVE_NONE ((uint32_t)0x00000000U)\r
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)\r
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) \r
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE\r
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE\r
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 \r
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 \r
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 \r
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 \r
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 \r
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32\r
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6\r
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 \r
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 \r
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 \r
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 \r
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 \r
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 \r
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 \r
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 \r
+ \r
+#define IS_HAL_REMAPDMA IS_DMA_REMAP \r
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE\r
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE\r
+ \r
+ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD\r
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD\r
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS\r
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE\r
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE\r
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE\r
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE\r
+#define OBEX_PCROP OPTIONBYTE_PCROP\r
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG\r
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE\r
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE\r
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE\r
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD\r
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD\r
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE\r
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD\r
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD\r
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE\r
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD\r
+#define PAGESIZE FLASH_PAGE_SIZE\r
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD\r
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1\r
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2\r
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3\r
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4\r
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST\r
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST\r
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA\r
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB\r
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA\r
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB\r
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE\r
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN\r
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE\r
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN\r
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE\r
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD\r
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP\r
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV\r
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR\r
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA\r
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS\r
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST\r
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR\r
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO\r
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS\r
+#define OB_WDG_SW OB_IWDG_SW\r
+#define OB_WDG_HW OB_IWDG_HW\r
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET\r
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET\r
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET\r
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET\r
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR\r
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0\r
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1\r
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
+ * @{\r
+ */\r
+#if defined(STM32L4) || defined(STM32F7)\r
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16\r
+#else\r
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef\r
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define GET_GPIO_SOURCE GPIO_GET_INDEX\r
+#define GET_GPIO_INDEX GPIO_GET_INDEX\r
+\r
+#if defined(STM32F4)\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO\r
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1\r
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1\r
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1\r
+\r
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)\r
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW \r
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM \r
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH \r
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH \r
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */\r
+\r
+#if defined(STM32L1) \r
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW \r
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM \r
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH \r
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH \r
+#endif /* STM32L1 */\r
+\r
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW\r
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH\r
+#endif /* STM32F0 || STM32F3 || STM32F1 */\r
+\r
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r
+ \r
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER\r
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER\r
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD\r
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD\r
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE\r
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE\r
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE\r
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE\r
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE\r
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE\r
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE\r
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE\r
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE\r
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE\r
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD\r
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE\r
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE\r
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
+\r
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING\r
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING\r
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING\r
+\r
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS \r
+\r
+/* The following 3 definition have also been present in a temporary version of lptim.h */\r
+/* They need to be renamed also to the right name, just in case */\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b\r
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b\r
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b\r
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b\r
+\r
+#define NAND_AddressTypedef NAND_AddressTypeDef\r
+\r
+#define __ARRAY_ADDRESS ARRAY_ADDRESS\r
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE\r
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE\r
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE\r
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef\r
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS\r
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING\r
+#define NOR_ERROR HAL_NOR_STATUS_ERROR\r
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT\r
+\r
+#define __NOR_WRITE NOR_WRITE\r
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0\r
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1\r
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2\r
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3\r
+ \r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 \r
+\r
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0\r
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 \r
+\r
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1\r
+ \r
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO \r
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 \r
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS\r
+#if defined(STM32F7) \r
+ #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/* Compact Flash-ATA registers description */\r
+#define CF_DATA ATA_DATA \r
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT \r
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER \r
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW \r
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH \r
+#define CF_CARD_HEAD ATA_CARD_HEAD \r
+#define CF_STATUS_CMD ATA_STATUS_CMD \r
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE\r
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA \r
+\r
+/* Compact Flash-ATA commands */\r
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD \r
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD\r
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD\r
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD\r
+\r
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef\r
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS\r
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING\r
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR\r
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define FORMAT_BIN RTC_FORMAT_BIN\r
+#define FORMAT_BCD RTC_FORMAT_BCD\r
+\r
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE\r
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+\r
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE \r
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE \r
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
+\r
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT\r
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 \r
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2\r
+\r
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE\r
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1\r
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1\r
+\r
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT \r
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 \r
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE\r
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE\r
+\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE\r
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE\r
+\r
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE\r
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE\r
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE\r
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE\r
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE\r
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE\r
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE\r
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE\r
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE\r
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE\r
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE\r
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE\r
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE\r
+\r
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE\r
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE\r
+\r
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE\r
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK\r
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK\r
+ \r
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1\r
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2\r
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR\r
+#define TIM_DMABase_DIER TIM_DMABASE_DIER\r
+#define TIM_DMABase_SR TIM_DMABASE_SR\r
+#define TIM_DMABase_EGR TIM_DMABASE_EGR\r
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1\r
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2\r
+#define TIM_DMABase_CCER TIM_DMABASE_CCER\r
+#define TIM_DMABase_CNT TIM_DMABASE_CNT\r
+#define TIM_DMABase_PSC TIM_DMABASE_PSC\r
+#define TIM_DMABase_ARR TIM_DMABASE_ARR\r
+#define TIM_DMABase_RCR TIM_DMABASE_RCR\r
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1\r
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2\r
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3\r
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4\r
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR\r
+#define TIM_DMABase_DCR TIM_DMABASE_DCR\r
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR\r
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1\r
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3\r
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5\r
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6\r
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2\r
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3\r
+#define TIM_DMABase_OR TIM_DMABASE_OR\r
+\r
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE\r
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1\r
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2\r
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3\r
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4\r
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM\r
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER\r
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK\r
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2\r
+\r
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER\r
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS\r
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS\r
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS\r
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS\r
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS\r
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS\r
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS\r
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS\r
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS\r
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS\r
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS\r
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS\r
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS\r
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS\r
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS\r
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS\r
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING\r
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
+\r
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16\r
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16\r
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16\r
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16\r
+\r
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8\r
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8\r
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8\r
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8\r
+\r
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE\r
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE\r
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE\r
+\r
+#define USARTNACK_ENABLED USART_NACK_ENABLE\r
+#define USARTNACK_DISABLED USART_NACK_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CFR_BASE WWDG_CFR_BASE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0\r
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)\r
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)\r
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define VLAN_TAG ETH_VLAN_TAG\r
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD\r
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD\r
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD\r
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK\r
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK\r
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK\r
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK\r
+\r
+#define ETH_MMCCR ((uint32_t)0x00000100U) \r
+#define ETH_MMCRIR ((uint32_t)0x00000104U) \r
+#define ETH_MMCTIR ((uint32_t)0x00000108U) \r
+#define ETH_MMCRIMR ((uint32_t)0x0000010CU) \r
+#define ETH_MMCTIMR ((uint32_t)0x00000110U) \r
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) \r
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) \r
+#define ETH_MMCTGFCR ((uint32_t)0x00000168U) \r
+#define ETH_MMCRFCECR ((uint32_t)0x00000194U) \r
+#define ETH_MMCRFAECR ((uint32_t)0x00000198U) \r
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)\r
+ \r
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */\r
+#if defined(STM32F1)\r
+#else\r
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#endif\r
+#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR\r
+#define DCMI_IT_OVF DCMI_IT_OVR\r
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI\r
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI\r
+\r
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop\r
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop\r
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\\r
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\r
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888\r
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 \r
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 \r
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555\r
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444\r
+\r
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888\r
+#define CM_RGB888 DMA2D_INPUT_RGB888 \r
+#define CM_RGB565 DMA2D_INPUT_RGB565 \r
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555\r
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444\r
+#define CM_L8 DMA2D_INPUT_L8 \r
+#define CM_AL44 DMA2D_INPUT_AL44 \r
+#define CM_AL88 DMA2D_INPUT_AL88 \r
+#define CM_L4 DMA2D_INPUT_L4 \r
+#define CM_A8 DMA2D_INPUT_A8 \r
+#define CM_A4 DMA2D_INPUT_A4 \r
+/**\r
+ * @}\r
+ */ \r
+#endif /* STM32L4xx || STM32F7*/\r
+\r
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */ \r
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef\r
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef\r
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish\r
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish\r
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish\r
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish\r
+\r
+/*HASH Algorithm Selection*/\r
+\r
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 \r
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224\r
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256\r
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5\r
+\r
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH \r
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC\r
+\r
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY\r
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect\r
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
+#if defined(STM32L0)\r
+#else\r
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
+#endif\r
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram\r
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown\r
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown\r
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock\r
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock\r
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase\r
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter\r
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter\r
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter\r
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter\r
+\r
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg\r
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown\r
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor\r
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg\r
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown\r
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor\r
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler\r
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler\r
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback\r
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive\r
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive\r
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC\r
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC\r
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM\r
+\r
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL\r
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING\r
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING\r
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING\r
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING\r
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING\r
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING\r
+\r
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB\r
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB\r
+\r
+#define DBP_BitNumber DBP_BIT_NUMBER\r
+#define PVDE_BitNumber PVDE_BIT_NUMBER\r
+#define PMODE_BitNumber PMODE_BIT_NUMBER\r
+#define EWUP_BitNumber EWUP_BIT_NUMBER\r
+#define FPDS_BitNumber FPDS_BIT_NUMBER\r
+#define ODEN_BitNumber ODEN_BIT_NUMBER\r
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER\r
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER\r
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER\r
+#define BRE_BitNumber BRE_BIT_NUMBER\r
+\r
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT\r
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback \r
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt\r
+#define HAL_TIM_DMAError TIM_DMAError\r
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt\r
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */ \r
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */ \r
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ \r
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_IT_CC CRYP_IT_CC\r
+#define AES_IT_ERR CRYP_IT_ERR\r
+#define AES_FLAG_CCF CRYP_FLAG_CCF\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE\r
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH\r
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM\r
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC\r
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM \r
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC\r
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK\r
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG\r
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG\r
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
+\r
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY\r
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48\r
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS\r
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER\r
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __ADC_ENABLE __HAL_ADC_ENABLE\r
+#define __ADC_DISABLE __HAL_ADC_DISABLE\r
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS\r
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS\r
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR\r
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING\r
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE\r
+\r
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK\r
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT\r
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR\r
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION\r
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE\r
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT\r
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS\r
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN\r
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ\r
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET\r
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET\r
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL\r
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL\r
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET\r
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET\r
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD\r
+\r
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER\r
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI\r
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER\r
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE\r
+\r
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT\r
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT\r
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL\r
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET\r
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE\r
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE\r
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER\r
+\r
+#define __HAL_ADC_SQR1 ADC_SQR1\r
+#define __HAL_ADC_SMPR1 ADC_SMPR1\r
+#define __HAL_ADC_SMPR2 ADC_SMPR2\r
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK\r
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK\r
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK\r
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS\r
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS\r
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV\r
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection\r
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq\r
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
+#define __HAL_ADC_JSQR ADC_JSQR\r
+\r
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL\r
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF\r
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT\r
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS\r
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN\r
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR\r
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT\r
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT\r
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT\r
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
+\r
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
+\r
+\r
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined(STM32F3)\r
+#define COMP_START __HAL_COMP_ENABLE\r
+#define COMP_STOP __HAL_COMP_DISABLE\r
+#define COMP_LOCK __HAL_COMP_LOCK\r
+ \r
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F302xE) || defined(STM32F302xC)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F373xC) ||defined(STM32F378xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+# endif\r
+#else\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+#endif\r
+\r
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/* Note: On these STM32 families, the only argument of this macro */\r
+/* is COMP_FLAG_LOCK. */\r
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */\r
+/* argument. */\r
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
+ ((WAVE) == DAC_WAVE_NOISE)|| \\r
+ ((WAVE) == DAC_WAVE_TRIANGLE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_WRPAREA IS_OB_WRPAREA\r
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEERASE IS_FLASH_TYPEERASE\r
+#define IS_NBSECTORS IS_FLASH_NBSECTORS\r
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2\r
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START\r
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE\r
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME\r
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD\r
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST\r
+#define __HAL_I2C_SPEED I2C_SPEED\r
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE\r
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ\r
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS\r
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE\r
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ\r
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB\r
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB\r
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE\r
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE\r
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE\r
+\r
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+\r
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS\r
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT\r
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT\r
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD\r
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX\r
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX\r
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX\r
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX\r
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L\r
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H\r
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM\r
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES\r
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX\r
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT\r
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION\r
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE\r
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine\r
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention\r
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2\r
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2\r
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB\r
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB\r
+\r
+#if defined (STM32F4)\r
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() \r
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT\r
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG \r
+#endif /* STM32F4 */\r
+/** \r
+ * @}\r
+ */ \r
+ \r
+ \r
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI\r
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI\r
+\r
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
+\r
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE\r
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE\r
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET\r
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET\r
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE\r
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE\r
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET\r
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET\r
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE \r
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE \r
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE\r
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE\r
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE\r
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE\r
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET\r
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET\r
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE\r
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE\r
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET\r
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET\r
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE\r
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE\r
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET\r
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET\r
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE\r
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE\r
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET\r
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET\r
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE\r
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE\r
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE\r
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE \r
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET\r
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET\r
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE\r
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE\r
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE\r
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE \r
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET\r
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET\r
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE\r
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE\r
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET\r
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET\r
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE\r
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE\r
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET\r
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET\r
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE\r
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE\r
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET\r
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE\r
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE\r
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET\r
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET\r
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE\r
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE\r
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET\r
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET\r
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
+\r
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE \r
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE \r
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE \r
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE \r
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE \r
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE\r
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET\r
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET\r
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE \r
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE\r
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE\r
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET\r
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET\r
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE \r
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE\r
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE\r
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET\r
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET\r
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE \r
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE\r
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE\r
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET\r
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET\r
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE \r
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE \r
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE \r
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE \r
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE \r
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE \r
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE \r
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE\r
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE\r
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE \r
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE \r
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE\r
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE\r
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET\r
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET\r
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE \r
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE\r
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE\r
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET\r
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET\r
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE \r
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE\r
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE\r
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET\r
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET\r
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE \r
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE\r
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE\r
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET\r
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET\r
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE \r
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE\r
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE\r
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET\r
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE \r
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE\r
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE \r
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE\r
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE\r
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET\r
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET\r
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE \r
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE \r
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE \r
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE \r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED \r
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET \r
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE \r
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE \r
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE \r
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE \r
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE \r
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET\r
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET\r
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE \r
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE \r
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE\r
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE\r
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET\r
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET\r
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
+\r
+/* alias define maintained for legacy */\r
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+\r
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE\r
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE\r
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE\r
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE\r
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE\r
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE\r
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE\r
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE\r
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE\r
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE\r
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE\r
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE\r
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE\r
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE\r
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE\r
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE\r
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE\r
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE\r
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE\r
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE\r
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE\r
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE\r
+\r
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET\r
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET\r
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET\r
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET\r
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET\r
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET\r
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET\r
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET\r
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET\r
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET\r
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET\r
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET\r
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET\r
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET\r
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET\r
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET\r
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET\r
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET\r
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET\r
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET\r
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET\r
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET\r
+\r
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED\r
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED\r
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED\r
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED\r
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED\r
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED\r
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED\r
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED\r
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED\r
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED\r
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED\r
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED\r
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED\r
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED\r
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED\r
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED\r
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED\r
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED\r
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED\r
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED\r
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED\r
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED\r
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED\r
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED\r
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED\r
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED\r
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED\r
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED\r
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED\r
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED\r
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED\r
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED\r
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED\r
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED\r
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED\r
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED\r
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED\r
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED\r
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED\r
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED\r
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED\r
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED\r
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED\r
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED\r
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED\r
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED\r
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED\r
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED\r
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED\r
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED\r
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED\r
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED\r
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED\r
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED\r
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED\r
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED\r
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED\r
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED\r
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED\r
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED\r
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED\r
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED\r
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED\r
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED\r
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED\r
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED\r
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED\r
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED\r
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED\r
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED\r
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED\r
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED\r
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED\r
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED\r
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED\r
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED\r
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED\r
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED\r
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED\r
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED\r
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED\r
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED\r
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED\r
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED\r
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED\r
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED\r
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED\r
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED\r
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED\r
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED\r
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED\r
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED\r
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED\r
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED\r
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED\r
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED\r
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED\r
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED\r
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED\r
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED\r
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED\r
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED\r
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED\r
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED\r
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED\r
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED\r
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED\r
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED\r
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED\r
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED\r
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED\r
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED\r
+\r
+#if defined(STM32F4)\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED\r
+#define Sdmmc1ClockSelection SdioClockSelection\r
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO\r
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48\r
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK\r
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET\r
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE\r
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r
+#define SdioClockSelection Sdmmc1ClockSelection\r
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1\r
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG\r
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE \r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48\r
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK\r
+#endif\r
+\r
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG\r
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG\r
+\r
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE\r
+\r
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE\r
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE\r
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK\r
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK\r
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK\r
+\r
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY\r
+\r
+#if defined(STM32L0)\r
+#define RCC_IT_LSECSS RCC_IT_CSSLSE \r
+#define RCC_IT_CSS RCC_IT_CSSHSE\r
+#endif\r
+\r
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE\r
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG\r
+#define RCC_MCO_NODIV RCC_MCODIV_1\r
+#define RCC_MCO_DIV1 RCC_MCODIV_1\r
+#define RCC_MCO_DIV2 RCC_MCODIV_2\r
+#define RCC_MCO_DIV4 RCC_MCODIV_4\r
+#define RCC_MCO_DIV8 RCC_MCODIV_8\r
+#define RCC_MCO_DIV16 RCC_MCODIV_16\r
+#define RCC_MCO_DIV32 RCC_MCODIV_32\r
+#define RCC_MCO_DIV64 RCC_MCODIV_64\r
+#define RCC_MCO_DIV128 RCC_MCODIV_128\r
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK\r
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI\r
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE\r
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK\r
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI\r
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14\r
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48\r
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE\r
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2\r
+\r
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK\r
+\r
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1\r
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI\r
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5\r
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2\r
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3\r
+\r
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER\r
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER\r
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER\r
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER\r
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER\r
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER\r
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER\r
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER\r
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER\r
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER\r
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER\r
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER\r
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER\r
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER\r
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER\r
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER\r
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER\r
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER\r
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER\r
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER\r
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER\r
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER\r
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER\r
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER\r
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER\r
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS\r
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS\r
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS\r
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS\r
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE\r
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE\r
+\r
+#define CR_HSION_BB RCC_CR_HSION_BB\r
+#define CR_CSSON_BB RCC_CR_CSSON_BB\r
+#define CR_PLLON_BB RCC_CR_PLLON_BB\r
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB\r
+#define CR_MSION_BB RCC_CR_MSION_BB\r
+#define CSR_LSION_BB RCC_CSR_LSION_BB\r
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB\r
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB\r
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB\r
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB\r
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB\r
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB\r
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB\r
+#define CR_HSEON_BB RCC_CR_HSEON_BB\r
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB\r
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB\r
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB\r
+\r
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r
+\r
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT\r
+\r
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN\r
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF\r
+\r
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48\r
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ\r
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP\r
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ\r
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE\r
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48\r
+\r
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET\r
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r
+#define DfsdmClockSelection Dfsdm1ClockSelection\r
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1\r
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK\r
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK\r
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG\r
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG\r
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT\r
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT\r
+\r
+#if defined (STM32F1)\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
+#endif /* STM32F1 */\r
+\r
+#define IS_ALARM IS_RTC_ALARM\r
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK\r
+#define IS_TAMPER IS_RTC_TAMPER\r
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE\r
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER \r
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT\r
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE\r
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION\r
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE\r
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ\r
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER\r
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK\r
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER\r
+\r
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE\r
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE\r
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS\r
+\r
+#if defined(STM32F4)\r
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED\r
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY \r
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED \r
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION \r
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND \r
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT \r
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED \r
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE \r
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE \r
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE \r
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL \r
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT \r
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT \r
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG \r
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG \r
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT \r
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT \r
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS \r
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT \r
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND\r
+/* alias CMSIS */\r
+#define SDMMC1_IRQn SDIO_IRQn\r
+#define SDMMC1_IRQHandler SDIO_IRQHandler\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED\r
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY \r
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED \r
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION\r
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND\r
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT\r
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED\r
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE\r
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE\r
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE\r
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE\r
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT\r
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT\r
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG\r
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG\r
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT\r
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT\r
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS\r
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT\r
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND\r
+/* alias CMSIS for compatibilities */\r
+#define SDIO_IRQn SDMMC1_IRQn\r
+#define SDIO_IRQHandler SDMMC1_IRQHandler\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT\r
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT\r
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE\r
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE\r
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
+\r
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+\r
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1\r
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2\r
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START\r
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH\r
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR\r
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE\r
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE\r
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX\r
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX\r
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+\r
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD\r
+\r
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE \r
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT\r
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT\r
+#define __USART_ENABLE __HAL_USART_ENABLE\r
+#define __USART_DISABLE __HAL_USART_DISABLE\r
+\r
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE\r
+\r
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE\r
+\r
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE\r
+\r
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+\r
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup\r
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup\r
+\r
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo\r
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE\r
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
+\r
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT\r
+\r
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+\r
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN\r
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER\r
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER\r
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER\r
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD\r
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD\r
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION\r
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION\r
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER\r
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER\r
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE\r
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE\r
+\r
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
+\r
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE \r
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE\r
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_LTDC_LAYER LTDC_LAYER\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE\r
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE\r
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE\r
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE\r
+#define SAI_STREOMODE SAI_STEREOMODE\r
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY\r
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL\r
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL\r
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL\r
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL\r
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL\r
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE\r
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1\r
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ___STM32_HAL_LEGACY */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief This file contains all the functions prototypes for the HAL \r
+ * module driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_H\r
+#define __STM32F7xx_HAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_conf.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_BootMode Boot Mode\r
+ * @{\r
+ */\r
+#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U)\r
+#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup HAL_Exported_Macros HAL Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Freeze/Unfreeze Peripherals in Debug mode \r
+ */\r
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))\r
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r
+\r
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r
+\r
+\r
+/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))\r
+ \r
+\r
+/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\\r
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\\r
+ }while(0);\r
+/**\r
+ * @brief Return the memory boot mapping as configured by user.\r
+ * @retval The boot mode as configured by user. The returned value can be one\r
+ * of the following values:\r
+ * @arg @ref SYSCFG_MEM_BOOT_ADD0\r
+ * @arg @ref SYSCFG_MEM_BOOT_ADD1\r
+ */\r
+#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @brief SYSCFG Break Cortex-M7 Lockup lock.\r
+ * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)\r
+\r
+/** @brief SYSCFG Break PVD lock.\r
+ * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HAL_Exported_Functions\r
+ * @{\r
+ */\r
+/** @addtogroup HAL_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_Init(void);\r
+HAL_StatusTypeDef HAL_DeInit(void);\r
+void HAL_MspInit(void);\r
+void HAL_MspDeInit(void);\r
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup HAL_Exported_Functions_Group2\r
+ * @{\r
+ */ \r
+/* Peripheral Control functions ************************************************/\r
+void HAL_IncTick(void);\r
+void HAL_Delay(__IO uint32_t Delay);\r
+uint32_t HAL_GetTick(void);\r
+void HAL_SuspendTick(void);\r
+void HAL_ResumeTick(void);\r
+uint32_t HAL_GetHalVersion(void);\r
+uint32_t HAL_GetREVID(void);\r
+uint32_t HAL_GetDEVID(void);\r
+void HAL_DBGMCU_EnableDBGSleepMode(void);\r
+void HAL_DBGMCU_DisableDBGSleepMode(void);\r
+void HAL_DBGMCU_EnableDBGStopMode(void);\r
+void HAL_DBGMCU_DisableDBGStopMode(void);\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void);\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void);\r
+void HAL_EnableCompensationCell(void);\r
+void HAL_DisableCompensationCell(void);\r
+void HAL_EnableFMCMemorySwapping(void);\r
+void HAL_DisableFMCMemorySwapping(void);\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+void HAL_EnableMemorySwappingBank(void);\r
+void HAL_DisableMemorySwappingBank(void);\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup HAL_Private_Variables HAL Private Variables\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup HAL_Private_Constants HAL Private Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cortex.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of CORTEX HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CORTEX_H\r
+#define __STM32F7xx_HAL_CORTEX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CORTEX\r
+ * @{\r
+ */ \r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
+ * @brief MPU Region initialization structure \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t Enable; /*!< Specifies the status of the region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */\r
+ uint8_t Number; /*!< Specifies the number of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */\r
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */\r
+ uint8_t Size; /*!< Specifies the size of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */\r
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. \r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ \r
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.\r
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ \r
+ uint8_t AccessPermission; /*!< Specifies the region access permission type. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */\r
+ uint8_t DisableExec; /*!< Specifies the instruction access status. \r
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */\r
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */\r
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */\r
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */\r
+}MPU_Region_InitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r
+ * @{\r
+ */\r
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source \r
+ * @{\r
+ */\r
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)\r
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r
+ * @{\r
+ */\r
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) \r
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)\r
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)\r
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
+ * @{\r
+ */\r
+#define MPU_REGION_ENABLE ((uint8_t)0x01U)\r
+#define MPU_REGION_DISABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
+ * @{\r
+ */\r
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)\r
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)\r
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)\r
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)\r
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r
+ * @{\r
+ */\r
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)\r
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)\r
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
+ * @{\r
+ */\r
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)\r
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)\r
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) \r
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) \r
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) \r
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) \r
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)\r
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) \r
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) \r
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) \r
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) \r
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) \r
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)\r
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)\r
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)\r
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) \r
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) \r
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) \r
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) \r
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)\r
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)\r
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)\r
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)\r
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)\r
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)\r
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) \r
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) \r
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \r
+ * @{\r
+ */\r
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) \r
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) \r
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) \r
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) \r
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) \r
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
+ * @{\r
+ */\r
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) \r
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) \r
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) \r
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) \r
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) \r
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)\r
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)\r
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported Macros -----------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CORTEX_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup CORTEX_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SystemReset(void);\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+#if (__MPU_PRESENT == 1)\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
+#endif /* __MPU_PRESENT */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
+void HAL_SYSTICK_IRQHandler(void);\r
+void HAL_SYSTICK_Callback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
+ * @{\r
+ */\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)\r
+\r
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)\r
+\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
+\r
+#if (__MPU_PRESENT == 1)\r
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
+ ((STATE) == MPU_REGION_DISABLE))\r
+\r
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
+\r
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
+\r
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
+\r
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
+\r
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \\r
+ ((TYPE) == MPU_TEX_LEVEL1) || \\r
+ ((TYPE) == MPU_TEX_LEVEL2))\r
+\r
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
+\r
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER1) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER2) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER3) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER4) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER5) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER6) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER7))\r
+\r
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4GB))\r
+\r
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)\r
+#endif /* __MPU_PRESENT */\r
+\r
+/** \r
+ * @} \r
+ */ \r
+ \r
+/* Private functions ---------------------------------------------------------*/ \r
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions\r
+ * @brief CORTEX private functions \r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+ * @brief Disables the MPU\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void HAL_MPU_Disable(void)\r
+{\r
+ /* Disable fault exceptions */\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+ \r
+ /* Disable the MPU */\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MPU\r
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault, \r
+ * NMI, FAULTMASK and privileged access to the default memory \r
+ * This parameter can be one of the following values:\r
+ * @arg MPU_HFNMI_PRIVDEF_NONE\r
+ * @arg MPU_HARDFAULT_NMI\r
+ * @arg MPU_PRIVILEGED_DEFAULT\r
+ * @arg MPU_HFNMI_PRIVDEF\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ /* Enable the MPU */\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+ \r
+ /* Enable fault exceptions */\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CORTEX_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_def.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief This file contains HAL common defines, enumeration, macros and \r
+ * structures definitions. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DEF\r
+#define __STM32F7xx_HAL_DEF\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx.h"\r
+#include "Legacy/stm32_hal_legacy.h"\r
+#include <stdio.h>\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief HAL Status structures definition \r
+ */ \r
+typedef enum \r
+{\r
+ HAL_OK = 0x00U,\r
+ HAL_ERROR = 0x01U,\r
+ HAL_BUSY = 0x02U,\r
+ HAL_TIMEOUT = 0x03U\r
+} HAL_StatusTypeDef;\r
+\r
+/** \r
+ * @brief HAL Lock structures definition \r
+ */\r
+typedef enum \r
+{\r
+ HAL_UNLOCKED = 0x00,\r
+ HAL_LOCKED = 0x01 \r
+} HAL_LockTypeDef;\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#define HAL_MAX_DELAY 0xFFFFFFFFU\r
+\r
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)\r
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)\r
+\r
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\r
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \\r
+ } while(0)\r
+\r
+#define UNUSED(x) ((void)(x))\r
+\r
+/** @brief Reset the Handle's State field.\r
+ * @param __HANDLE__: specifies the Peripheral Handle.\r
+ * @note This macro can be used for the following purpose: \r
+ * - When the Handle is declared as local variable; before passing it as parameter\r
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro \r
+ * to set to 0 the Handle's "State" field.\r
+ * Otherwise, "State" field may have any random value and the first time the function \r
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
+ * (i.e. HAL_PPP_MspInit() will not be executed).\r
+ * - When there is a need to reconfigure the low level hardware: instead of calling\r
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
+ * @retval None\r
+ */\r
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\r
+\r
+#if (USE_RTOS == 1)\r
+ /* Reserved for future use */\r
+ #error "USE_RTOS should be 0 in the current HAL release"\r
+#else\r
+ #define __HAL_LOCK(__HANDLE__) \\r
+ do{ \\r
+ if((__HANDLE__)->Lock == HAL_LOCKED) \\r
+ { \\r
+ return HAL_BUSY; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Lock = HAL_LOCKED; \\r
+ } \\r
+ }while (0)\r
+\r
+ #define __HAL_UNLOCK(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \\r
+ }while (0)\r
+#endif /* USE_RTOS */\r
+\r
+#if defined ( __GNUC__ )\r
+ #ifndef __weak\r
+ #define __weak __attribute__((weak))\r
+ #endif /* __weak */\r
+ #ifndef __packed\r
+ #define __packed __attribute__((__packed__))\r
+ #endif /* __packed */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
+#if defined (__GNUC__) /* GNU Compiler */\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END __attribute__ ((aligned (4)))\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN \r
+ #define __ALIGN_BEGIN\r
+ #endif /* __ALIGN_BEGIN */\r
+#else\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN \r
+ #if defined (__CC_ARM) /* ARM Compiler */\r
+ #define __ALIGN_BEGIN __align(4) \r
+ #elif defined (__ICCARM__) /* IAR Compiler */\r
+ #define __ALIGN_BEGIN \r
+ #endif /* __CC_ARM */\r
+ #endif /* __ALIGN_BEGIN */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/** \r
+ * @brief __RAM_FUNC definition\r
+ */ \r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options. \r
+ Functions that are executed in RAM should reside in a separate source module.\r
+ Using the 'Options for File' dialog you can simply change the 'Code / Const' \r
+ area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
+ dialog. \r
+*/\r
+#define __RAM_FUNC HAL_StatusTypeDef \r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+*/\r
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute \r
+ "__attribute__((section(".RamFunc")))".\r
+*/\r
+#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))\r
+\r
+#endif\r
+\r
+/** \r
+ * @brief __NOINLINE definition\r
+ */ \r
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )\r
+/* ARM & GNUCompiler \r
+ ---------------- \r
+*/\r
+#define __NOINLINE __attribute__ ( (noinline) )\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+*/\r
+#define __NOINLINE _Pragma("optimize = no_inline")\r
+\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ___STM32F7xx_HAL_DEF */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of DMA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA_H\r
+#define __STM32F7xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+ * @brief DMA Exported Types \r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief DMA Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Channel; /*!< Specifies the channel used for the specified stream. \r
+ This parameter can be a value of @ref DMAEx_Channel_selection */\r
+\r
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, \r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Stream */\r
+\r
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_Priority_level */\r
+\r
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\r
+ This parameter can be a value of @ref DMA_FIFO_direct_mode\r
+ @note The Direct mode (FIFO mode disabled) cannot be used if the \r
+ memory-to-memory data transfer is configured on the selected stream */\r
+\r
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.\r
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */\r
+\r
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction.\r
+ This parameter can be a value of @ref DMA_Memory_burst \r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+\r
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction. \r
+ This parameter can be a value of @ref DMA_Peripheral_burst\r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+}DMA_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */\r
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */\r
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */\r
+ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */\r
+ HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */\r
+ HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */\r
+ HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */\r
+ HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */\r
+ HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */\r
+ HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */\r
+ HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */\r
+}HAL_DMA_CallbackIDTypeDef;\r
+\r
+/** \r
+ * @brief DMA handle Structure definition\r
+ */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */\r
+\r
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */ \r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA locking object */ \r
+\r
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
+\r
+ void *Parent; /*!< Parent object state */ \r
+\r
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
+\r
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
+\r
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */\r
+ \r
+ void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */\r
+ \r
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
+ \r
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ \r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA Error code */\r
+ \r
+ uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */\r
+\r
+ uint32_t StreamIndex; /*!< DMA Stream Index */\r
+ \r
+}DMA_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @brief DMA Exported constants \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+ * @brief DMA Error Code \r
+ * @{\r
+ */ \r
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */\r
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */\r
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */\r
+#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */\r
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */\r
+#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */\r
+#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */ \r
+#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+ * @brief DMA data transfer direction \r
+ * @{\r
+ */ \r
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+ * @brief DMA peripheral incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */\r
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+ * @brief DMA memory incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */\r
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+ * @brief DMA peripheral data size \r
+ * @{\r
+ */ \r
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */\r
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */\r
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+ * @brief DMA memory data size \r
+ * @{ \r
+ */\r
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */\r
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */\r
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+ * @brief DMA mode \r
+ * @{\r
+ */ \r
+#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */\r
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */\r
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+ * @brief DMA priority levels \r
+ * @{\r
+ */\r
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */\r
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */\r
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */\r
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\r
+ * @brief DMA FIFO direct mode\r
+ * @{\r
+ */\r
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */\r
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\r
+ * @brief DMA FIFO level \r
+ * @{\r
+ */\r
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */\r
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */\r
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */\r
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_burst DMA Memory burst\r
+ * @brief DMA memory burst \r
+ * @{\r
+ */ \r
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) \r
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) \r
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) \r
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\r
+ * @brief DMA peripheral burst \r
+ * @{\r
+ */ \r
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)\r
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)\r
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)\r
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+ * @brief DMA interrupts definition \r
+ * @{\r
+ */\r
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)\r
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)\r
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)\r
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)\r
+#define DMA_IT_FE ((uint32_t)0x00000080U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+ * @brief DMA flag definitions \r
+ * @{\r
+ */ \r
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)\r
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)\r
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)\r
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)\r
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)\r
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)\r
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)\r
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)\r
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)\r
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)\r
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)\r
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)\r
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)\r
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)\r
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)\r
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)\r
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)\r
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)\r
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)\r
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @brief Reset DMA handle state\r
+ * @param __HANDLE__: specifies the DMA handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO filled level.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The FIFO filling state.\r
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \r
+ * and not empty.\r
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r
+ * - DMA_FIFOStatus_Empty: when FIFO is empty\r
+ * - DMA_FIFOStatus_Full: when FIFO is full\r
+ */\r
+#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)\r
+\r
+/* Interrupt & Flag management */\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ DMA_FLAG_TCIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream half transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */ \r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ DMA_FLAG_HTIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ DMA_FLAG_TEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified FIFO error flag index.\r
+ */\r
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ DMA_FLAG_FEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream direct mode error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified direct mode error flag index.\r
+ */\r
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ DMA_FLAG_DMEIF3_7)\r
+\r
+/**\r
+ * @brief Get the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Check whether the specified DMA Stream interrupt is enabled or not.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval The state of DMA_IT.\r
+ */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+ ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \\r
+ ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Writes the number of data units to be transferred on the DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) \r
+ * Number of data items depends only on the Peripheral data format.\r
+ * \r
+ * @note If Peripheral data format is Bytes: number of data units is equal \r
+ * to total number of bytes to be transferred.\r
+ * \r
+ * @note If Peripheral data format is Half-Word: number of data units is \r
+ * equal to total number of bytes to be transferred / 2.\r
+ * \r
+ * @note If Peripheral data format is Word: number of data units is equal \r
+ * to total number of bytes to be transferred / 4.\r
+ * \r
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.\r
+ */\r
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.\r
+ * @param __HANDLE__: DMA handle\r
+ * \r
+ * @retval The number of remaining data units in the current DMA Stream transfer.\r
+ */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)\r
+\r
+\r
+/* Include DMA HAL Extension module */\r
+#include "stm32f7xx_hal_dma_ex.h" \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
+ * @brief DMA Exported functions \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); \r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\r
+ * @brief I/O operation functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\r
+ * @brief Peripheral State functions \r
+ * @{\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+/* Private Constants -------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Constants DMA Private Constants\r
+ * @brief DMA private defines and constants \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+ * @brief DMA private macros \r
+ * @{\r
+ */\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) \r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+ ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
+ ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
+ ((MODE) == DMA_CIRCULAR) || \\r
+ ((MODE) == DMA_PFCTRL)) \r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) \r
+\r
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\r
+ ((STATE) == DMA_FIFOMODE_ENABLE))\r
+\r
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\r
+\r
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\r
+ ((BURST) == DMA_MBURST_INC4) || \\r
+ ((BURST) == DMA_MBURST_INC8) || \\r
+ ((BURST) == DMA_MBURST_INC16))\r
+\r
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\r
+ ((BURST) == DMA_PBURST_INC4) || \\r
+ ((BURST) == DMA_PBURST_INC8) || \\r
+ ((BURST) == DMA_PBURST_INC16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Functions DMA Private Functions\r
+ * @brief DMA private functions \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma_ex.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of DMA HAL extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA_EX_H\r
+#define __STM32F7xx_HAL_DMA_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMAEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r
+ * @brief DMAEx Exported types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief HAL DMA Memory definition \r
+ */ \r
+typedef enum\r
+{\r
+ MEMORY0 = 0x00U, /*!< Memory 0 */\r
+ MEMORY1 = 0x01U, /*!< Memory 1 */\r
+\r
+}HAL_DMA_MemoryTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @brief DMA Exported constants \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx_Channel_selection DMA Channel selection\r
+ * @brief DMAEx channel selection \r
+ * @{\r
+ */ \r
+#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */\r
+#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */\r
+#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */\r
+#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */\r
+#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */\r
+#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */\r
+#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */\r
+#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */\r
+#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */\r
+#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/\r
+#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/\r
+#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/\r
+#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/\r
+#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/\r
+#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r
+ * @brief DMAEx Exported functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Macros DMA Private Macros\r
+ * @brief DMAEx private macros \r
+ * @{\r
+ */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\r
+ ((CHANNEL) == DMA_CHANNEL_1) || \\r
+ ((CHANNEL) == DMA_CHANNEL_2) || \\r
+ ((CHANNEL) == DMA_CHANNEL_3) || \\r
+ ((CHANNEL) == DMA_CHANNEL_4) || \\r
+ ((CHANNEL) == DMA_CHANNEL_5) || \\r
+ ((CHANNEL) == DMA_CHANNEL_6) || \\r
+ ((CHANNEL) == DMA_CHANNEL_7) || \\r
+ ((CHANNEL) == DMA_CHANNEL_8) || \\r
+ ((CHANNEL) == DMA_CHANNEL_9) || \\r
+ ((CHANNEL) == DMA_CHANNEL_10) || \\r
+ ((CHANNEL) == DMA_CHANNEL_11) || \\r
+ ((CHANNEL) == DMA_CHANNEL_12) || \\r
+ ((CHANNEL) == DMA_CHANNEL_13) || \\r
+ ((CHANNEL) == DMA_CHANNEL_14) || \\r
+ ((CHANNEL) == DMA_CHANNEL_15)) \r
+#else\r
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\r
+ ((CHANNEL) == DMA_CHANNEL_1) || \\r
+ ((CHANNEL) == DMA_CHANNEL_2) || \\r
+ ((CHANNEL) == DMA_CHANNEL_3) || \\r
+ ((CHANNEL) == DMA_CHANNEL_4) || \\r
+ ((CHANNEL) == DMA_CHANNEL_5) || \\r
+ ((CHANNEL) == DMA_CHANNEL_6) || \\r
+ ((CHANNEL) == DMA_CHANNEL_7))\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions\r
+ * @brief DMAEx Private functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of FLASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_FLASH_H\r
+#define __STM32F7xx_HAL_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief FLASH Procedure structure definition\r
+ */\r
+typedef enum \r
+{\r
+ FLASH_PROC_NONE = 0U, \r
+ FLASH_PROC_SECTERASE,\r
+ FLASH_PROC_MASSERASE,\r
+ FLASH_PROC_PROGRAM\r
+} FLASH_ProcedureTypeDef;\r
+\r
+\r
+/** \r
+ * @brief FLASH handle Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */\r
+ \r
+ __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */\r
+ \r
+ __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */\r
+ \r
+ __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */\r
+\r
+ __IO uint32_t Address; /* Internal variable to save address selected for program */\r
+ \r
+ HAL_LockTypeDef Lock; /* FLASH locking object */\r
+\r
+ __IO uint32_t ErrorCode; /* FLASH error code */\r
+\r
+}FLASH_ProcessTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Error_Code FLASH Error Code\r
+ * @brief FLASH Error Code \r
+ * @{\r
+ */ \r
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */\r
+#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */\r
+#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */\r
+#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */\r
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */\r
+#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Type_Program FLASH Type Program\r
+ * @{\r
+ */ \r
+#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Flag_definition FLASH Flag definition\r
+ * @brief Flag definition\r
+ * @{\r
+ */ \r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */\r
+#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition\r
+ * @brief FLASH Interrupt definition\r
+ * @{\r
+ */\r
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */\r
+#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism\r
+ * @{\r
+ */\r
+#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)\r
+#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)\r
+#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)\r
+#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)\r
+#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys FLASH Keys\r
+ * @{\r
+ */ \r
+#define FLASH_KEY1 ((uint32_t)0x45670123U)\r
+#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)\r
+#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)\r
+#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Sectors FLASH Sectors\r
+ * @{\r
+ */\r
+#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */\r
+#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */\r
+#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */\r
+#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */\r
+#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */\r
+#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */\r
+#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */\r
+#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Set the FLASH Latency.\r
+ * @param __LATENCY__: FLASH Latency \r
+ * The value of this parameter depend on device used within the same series\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \\r
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))\r
+\r
+/**\r
+ * @brief Get the FLASH Latency.\r
+ * @retval FLASH Latency \r
+ * The value of this parameter depend on device used within the same series\r
+ */ \r
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\r
+\r
+/**\r
+ * @brief Enable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)\r
+\r
+/**\r
+ * @brief Disable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))\r
+\r
+/**\r
+ * @brief Enable the FLASH Adaptive Real-Time memory accelerator.\r
+ * @note The ART accelerator is available only for flash access on ITCM interface.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r
+\r
+/**\r
+ * @brief Disable the FLASH Adaptive Real-Time memory accelerator.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r
+\r
+/**\r
+ * @brief Resets the FLASH Adaptive Real-Time memory accelerator.\r
+ * @note This function must be used only when the Adaptive Real-Time memory accelerator\r
+ * is disabled. \r
+ * @retval None\r
+ */\r
+#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST)\r
+\r
+/**\r
+ * @brief Enable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ : FLASH interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+ * @arg FLASH_IT_ERR: Error Interrupt \r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ : FLASH interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+ * @arg FLASH_IT_ERR: Error Interrupt \r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Get the specified FLASH flag status. \r
+ * @param __FLAG__: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag \r
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag \r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r
+ * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag \r
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag\r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the specified FLASH flag.\r
+ * @param __FLAG__: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag \r
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag \r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r
+ * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag \r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include FLASH HAL Extension module */\r
+#include "stm32f7xx_hal_flash_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+/** @addtogroup FLASH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Program operation functions ***********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+/* FLASH IRQ handler method */\r
+void HAL_FLASH_IRQHandler(void);\r
+/* Callbacks in non blocking modes */ \r
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r
+/* Option bytes control */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+uint32_t HAL_FLASH_GetError(void);\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief OPTCR register byte 1 (Bits[15:8]) base address \r
+ */ \r
+#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_FLASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash_ex.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of FLASH HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_FLASH_EX_H\r
+#define __STM32F7xx_HAL_FLASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief FLASH Erase structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.\r
+ This parameter can be a value of @ref FLASHEx_Type_Erase */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK) \r
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.\r
+ This parameter must be a value of @ref FLASHEx_Banks */\r
+#endif /* FLASH_OPTCR_nDBANK */ \r
+ \r
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled\r
+ This parameter must be a value of @ref FLASHEx_Sectors */\r
+\r
+ uint32_t NbSectors; /*!< Number of sectors to be erased.\r
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\r
+\r
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism\r
+ This parameter must be a value of @ref FLASHEx_Voltage_Range */\r
+\r
+} FLASH_EraseInitTypeDef;\r
+\r
+/**\r
+ * @brief FLASH Option Bytes Program structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OptionType; /*!< Option byte to be configured.\r
+ This parameter can be a value of @ref FLASHEx_Option_Type */\r
+\r
+ uint32_t WRPState; /*!< Write protection activation or deactivation.\r
+ This parameter can be a value of @ref FLASHEx_WRP_State */\r
+\r
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.\r
+ The value of this parameter depend on device used within the same series */\r
+\r
+ uint32_t RDPLevel; /*!< Set the read protection level.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\r
+\r
+ uint32_t BORLevel; /*!< Set the BOR Level.\r
+ This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */\r
+\r
+ uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / \r
+ IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.\r
+ nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */\r
+ \r
+ uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.\r
+ This parameter can be a value of @ref FLASHEx_Boot_Address */\r
+\r
+ uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.\r
+ This parameter can be a value of @ref FLASHEx_Boot_Address */\r
+\r
+} FLASH_OBProgramInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase\r
+ * @{\r
+ */ \r
+#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */\r
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range\r
+ * @{\r
+ */ \r
+#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */\r
+#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */\r
+#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */\r
+#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_WRP_State FLASH WRP State\r
+ * @{\r
+ */ \r
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */\r
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Option_Type FLASH Option Type\r
+ * @{\r
+ */ \r
+#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */\r
+#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */\r
+#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */\r
+#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */\r
+#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */\r
+#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection\r
+ * @{\r
+ */\r
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)\r
+#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)\r
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 \r
+ it s no more possible to go back to level 1 or 0 */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog\r
+ * @{\r
+ */ \r
+#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */\r
+#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog\r
+ * @{\r
+ */ \r
+#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */\r
+#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP\r
+ * @{\r
+ */ \r
+#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY\r
+ * @{\r
+ */ \r
+#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP\r
+ * @{\r
+ */\r
+#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */\r
+#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY\r
+ * @{\r
+ */\r
+#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */\r
+#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level\r
+ * @{\r
+ */\r
+#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */\r
+#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */\r
+#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */\r
+#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (FLASH_OPTCR_nDBOOT)\r
+/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT\r
+ * @{\r
+ */ \r
+#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */\r
+#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash \r
+ (Dual bank Boot mode), or RAM if Boot address option in RAM */\r
+/**\r
+ * @}\r
+ */ \r
+#endif /* FLASH_OPTCR_nDBOOT */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank\r
+ * @{\r
+ */\r
+#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */\r
+#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address\r
+ * @{\r
+ */\r
+#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */\r
+#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */\r
+#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */\r
+#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */\r
+#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */\r
+#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */\r
+#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Latency FLASH Latency\r
+ * @{\r
+ */\r
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */\r
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */\r
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */\r
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */\r
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */\r
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */\r
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */\r
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */\r
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */\r
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */\r
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */\r
+#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */\r
+#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */\r
+#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */\r
+#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */\r
+#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+/** @defgroup FLASHEx_Banks FLASH Banks\r
+ * @{\r
+ */\r
+#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */\r
+#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */\r
+#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit\r
+ * @{\r
+ */\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */\r
+#else\r
+#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Sectors FLASH Sectors\r
+ * @{\r
+ */\r
+#if (FLASH_SECTOR_TOTAL == 24)\r
+#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */\r
+#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */\r
+#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */\r
+#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */\r
+#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */\r
+#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */\r
+#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */\r
+#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */\r
+#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */\r
+#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */\r
+#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */\r
+#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */\r
+#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */\r
+#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */\r
+#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */\r
+#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */\r
+#endif /* FLASH_SECTOR_TOTAL == 24 */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#if (FLASH_SECTOR_TOTAL == 24)\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r
+ * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.\r
+ * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r
+ * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and \r
+ * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).\r
+ * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.\r
+ * @{\r
+ */\r
+/* Single Bank Sectors */\r
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */\r
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */\r
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */\r
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */\r
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */\r
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */\r
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */\r
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */\r
+#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */\r
+#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */\r
+#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */\r
+#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ \r
+#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */\r
+\r
+/* Dual Bank Sectors */\r
+#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */\r
+#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */\r
+#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */\r
+#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */\r
+#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */\r
+#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */\r
+#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */\r
+#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */\r
+#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */\r
+#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */\r
+#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */\r
+#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ \r
+#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */\r
+#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */\r
+#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */\r
+#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */\r
+#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */\r
+#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */\r
+#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */\r
+#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */\r
+#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */\r
+#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */\r
+#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */\r
+#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */\r
+#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 24 */\r
+ \r
+#if (FLASH_SECTOR_TOTAL == 8)\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @{\r
+ */\r
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */\r
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */\r
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */\r
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */\r
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */\r
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */\r
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */\r
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */\r
+#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 8 */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)\r
+ * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].\r
+ * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)\r
+ * @retval The FLASH Boot Base Adress\r
+ */\r
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)\r
+ /**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Extension Program operation functions *************************************/\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \\r
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE)) \r
+\r
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_4)) \r
+\r
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \\r
+ ((VALUE) == OB_WRPSTATE_ENABLE)) \r
+\r
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\r
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))\r
+\r
+#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)\r
+\r
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\\r
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\\r
+ ((LEVEL) == OB_RDP_LEVEL_2))\r
+\r
+#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))\r
+\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))\r
+\r
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))\r
+\r
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\r
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \\r
+ ((LATENCY) == FLASH_LATENCY_1) || \\r
+ ((LATENCY) == FLASH_LATENCY_2) || \\r
+ ((LATENCY) == FLASH_LATENCY_3) || \\r
+ ((LATENCY) == FLASH_LATENCY_4) || \\r
+ ((LATENCY) == FLASH_LATENCY_5) || \\r
+ ((LATENCY) == FLASH_LATENCY_6) || \\r
+ ((LATENCY) == FLASH_LATENCY_7) || \\r
+ ((LATENCY) == FLASH_LATENCY_8) || \\r
+ ((LATENCY) == FLASH_LATENCY_9) || \\r
+ ((LATENCY) == FLASH_LATENCY_10) || \\r
+ ((LATENCY) == FLASH_LATENCY_11) || \\r
+ ((LATENCY) == FLASH_LATENCY_12) || \\r
+ ((LATENCY) == FLASH_LATENCY_13) || \\r
+ ((LATENCY) == FLASH_LATENCY_14) || \\r
+ ((LATENCY) == FLASH_LATENCY_15))\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))\r
+\r
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))\r
+\r
+#if (FLASH_SECTOR_TOTAL == 8)\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\\r
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\\r
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\\r
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r
+#endif /* FLASH_SECTOR_TOTAL == 8 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 24)\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\\r
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\\r
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\\r
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\\r
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\\r
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\\r
+ ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\\r
+ ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\\r
+ ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\\r
+ ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\\r
+ ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\\r
+ ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r
+#endif /* FLASH_SECTOR_TOTAL == 24 */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \\r
+ ((VALUE) == OB_NDBANK_DUAL_BANK))\r
+\r
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \\r
+ ((BANK) == FLASH_BANK_2) || \\r
+ ((BANK) == FLASH_BANK_BOTH))\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+#if defined (FLASH_OPTCR_nDBOOT)\r
+#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \\r
+ ((VALUE) == OB_DUAL_BOOT_ENABLE))\r
+#endif /* FLASH_OPTCR_nDBOOT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_FLASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of GPIO HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_GPIO_H\r
+#define __STM32F7xx_HAL_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief GPIO Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIO_mode_define */\r
+\r
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
+ This parameter can be a value of @ref GPIO_pull_define */\r
+\r
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIO_speed_define */\r
+\r
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. \r
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */\r
+}GPIO_InitTypeDef;\r
+\r
+/** \r
+ * @brief GPIO Bit SET and Bit RESET enumeration \r
+ */\r
+typedef enum\r
+{\r
+ GPIO_PIN_RESET = 0,\r
+ GPIO_PIN_SET\r
+}GPIO_PinState;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_pins_define GPIO pins define\r
+ * @{\r
+ */\r
+#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */\r
+#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */\r
+#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */\r
+#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */\r
+#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */\r
+#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */\r
+#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */\r
+#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */\r
+#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */\r
+#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */\r
+#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */\r
+#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */\r
+#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */\r
+#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */\r
+#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */\r
+#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */\r
+#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */\r
+\r
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_mode_define GPIO mode define\r
+ * @brief GPIO Configuration Mode \r
+ * Elements values convention: 0xX0yz00YZ\r
+ * - X : GPIO mode or EXTI Mode\r
+ * - y : External IT or Event trigger detection \r
+ * - z : IO configuration on External IT or Event\r
+ * - Y : Output type (Push Pull or Open Drain)\r
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)\r
+ * @{\r
+ */ \r
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */\r
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */\r
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */\r
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */\r
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */\r
+\r
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */\r
+ \r
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+ \r
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_speed_define GPIO speed define\r
+ * @brief GPIO Output Maximum frequency\r
+ * @{\r
+ */ \r
+#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */\r
+#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */\r
+#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */\r
+#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup GPIO_pull_define GPIO pull define\r
+ * @brief GPIO Pull-Up or Pull-Down Activation\r
+ * @{\r
+ */ \r
+#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */\r
+#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */\r
+#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param __EXTI_LINE__: specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include GPIO HAL Extension module */\r
+#include "stm32f7xx_hal_gpio_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
+#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\\r
+ ((MODE) == GPIO_MODE_AF_PP) ||\\r
+ ((MODE) == GPIO_MODE_AF_OD) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_ANALOG))\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \\r
+ ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))\r
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\r
+ ((PULL) == GPIO_PULLDOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Functions GPIO Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_GPIO_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio_ex.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of GPIO HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_GPIO_EX_H\r
+#define __STM32F7xx_HAL_GPIO_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIOEx GPIOEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */\r
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */\r
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */\r
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */\r
+#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */\r
+#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */\r
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */\r
+#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */\r
+#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */\r
+#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */\r
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */\r
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */\r
+#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */\r
+#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 6 selection \r
+ */ \r
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ \r
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */\r
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */\r
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */\r
+#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */\r
+#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */\r
+#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 8 selection \r
+ */ \r
+#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */\r
+#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */\r
+#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */\r
+#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */\r
+#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */\r
+#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+\r
+/** \r
+ * @brief AF 9 selection \r
+ */ \r
+#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */\r
+#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */\r
+#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */\r
+#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */\r
+#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */\r
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */\r
+#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */\r
+#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */\r
+#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */\r
+#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */\r
+#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */\r
+#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+/** \r
+ * @brief AF 12 selection \r
+ */ \r
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */\r
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */\r
+#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */\r
+#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */\r
+#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+/** \r
+ * @brief AF 13 selection \r
+ */ \r
+#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */\r
+#if defined (STM32F769xx) || defined (STM32F779xx) \r
+#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ \r
+ \r
+/** \r
+ * @brief AF 14 selection \r
+ */\r
+#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/ \r
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO pin available on the platform\r
+ */\r
+/* Defines the available pins per GPIOs */\r
+#define GPIOA_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOB_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOC_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOD_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOE_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOF_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOG_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOI_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOH_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \\r
+ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\r
+ * @{\r
+ */\r
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\r
+ ((__GPIOx__) == (GPIOB))? 1U :\\r
+ ((__GPIOx__) == (GPIOC))? 2U :\\r
+ ((__GPIOx__) == (GPIOD))? 3U :\\r
+ ((__GPIOx__) == (GPIOE))? 4U :\\r
+ ((__GPIOx__) == (GPIOF))? 5U :\\r
+ ((__GPIOx__) == (GPIOG))? 6U :\\r
+ ((__GPIOx__) == (GPIOH))? 7U :\\r
+ ((__GPIOx__) == (GPIOI))? 8U :\\r
+ ((__GPIOx__) == (GPIOJ))? 9U : 10U) \r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \\r
+ ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))\r
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \\r
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \\r
+ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))\r
+#elif defined(STM32F745xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \\r
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))\r
+#elif defined(STM32F767xx) || defined(STM32F777xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \\r
+ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \\r
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \\r
+ ((AF) == GPIO_AF14_LTDC))\r
+#elif defined(STM32F769xx) || defined(STM32F779xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \\r
+ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \\r
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \\r
+ ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI))\r
+#elif defined(STM32F765xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \\r
+ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \\r
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \\r
+ ((AF) == GPIO_AF10_OTG_FS))\r
+#endif /* STM32F756xx || STM32F746xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_GPIO_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of I2C HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_I2C_H\r
+#define __STM32F7xx_HAL_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup I2C_Exported_Types I2C Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r
+ * @brief I2C Configuration Structure definition \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.\r
+ This parameter calculated by referring to I2C initialization \r
+ section in Reference manual */\r
+\r
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_ADDRESSING_MODE */\r
+\r
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */\r
+\r
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected\r
+ This parameter can be a 7-bit address. */\r
+\r
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected\r
+ This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */\r
+\r
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.\r
+ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */\r
+\r
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.\r
+ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */\r
+\r
+}I2C_InitTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_state_structure_definition HAL state structure definition\r
+ * @brief HAL State structure definition\r
+ * @note HAL I2C State value coding follow below described bitmap :\r
+ * b7-b6 Error information \r
+ * 00 : No Error\r
+ * 01 : Abort (Abort user request on going)\r
+ * 10 : Timeout\r
+ * 11 : Error\r
+ * b5 IP initilisation status\r
+ * 0 : Reset (IP not initialized)\r
+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\r
+ * b4 (not used)\r
+ * x : Should be set to 0\r
+ * b3\r
+ * 0 : Ready or Busy (No Listen mode ongoing)\r
+ * 1 : Listen (IP in Address Listen Mode)\r
+ * b2 Intrinsic process state\r
+ * 0 : Ready\r
+ * 1 : Busy (IP busy with some configuration or internal operations)\r
+ * b1 Rx state\r
+ * 0 : Ready (no Rx operation ongoing)\r
+ * 1 : Busy (Rx operation ongoing)\r
+ * b0 Tx state\r
+ * 0 : Ready (no Tx operation ongoing)\r
+ * 1 : Busy (Tx operation ongoing)\r
+ * @{\r
+ */ \r
+\r
+typedef enum\r
+{\r
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */\r
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */\r
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ \r
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */\r
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */\r
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission\r
+ process is ongoing */\r
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception\r
+ process is ongoing */\r
+ HAL_I2C_STATE_ABORT = 0x60, /*!< Abort user request ongoing */\r
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */\r
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ \r
+\r
+}HAL_I2C_StateTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition\r
+ * @brief HAL Mode structure definition\r
+ * @note HAL I2C Mode value coding follow below described bitmap :\r
+ * b7 (not used)\r
+ * x : Should be set to 0\r
+ * b6\r
+ * 0 : None\r
+ * 1 : Memory (HAL I2C communication is in Memory Mode)\r
+ * b5\r
+ * 0 : None\r
+ * 1 : Slave (HAL I2C communication is in Slave Mode)\r
+ * b4\r
+ * 0 : None\r
+ * 1 : Master (HAL I2C communication is in Master Mode)\r
+ * b3-b2-b1-b0 (not used)\r
+ * xxxx : Should be set to 0000\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */\r
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */\r
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */\r
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */\r
+\r
+}HAL_I2C_ModeTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r
+ * @brief I2C Error Code definition \r
+ * @{\r
+ */\r
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */\r
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */\r
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */\r
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< ACKF error */\r
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */\r
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */\r
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */\r
+#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) /*!< Size Management error */\r
+#define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) /*!< Abort user request */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\r
+ * @brief I2C handle Structure definition \r
+ * @{\r
+ */\r
+typedef struct __I2C_HandleTypeDef\r
+{\r
+ I2C_TypeDef *Instance; /*!< I2C registers base address */\r
+\r
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */\r
+\r
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */\r
+\r
+ uint16_t XferSize; /*!< I2C transfer size */\r
+\r
+ __IO uint16_t XferCount; /*!< I2C transfer counter */\r
+\r
+ __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can\r
+ be a value of @ref I2C_XFEROPTIONS */\r
+\r
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state */\r
+\r
+ HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< I2C locking object */\r
+\r
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */\r
+\r
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */\r
+\r
+ __IO uint32_t ErrorCode; /*!< I2C Error code */\r
+\r
+ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */\r
+}I2C_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Constants I2C Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options\r
+ * @{\r
+ */\r
+#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)\r
+#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)\r
+#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
+#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)\r
+#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U)\r
+#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)\r
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks\r
+ * @{\r
+ */\r
+#define I2C_OA2_NOMASK ((uint8_t)0x00U)\r
+#define I2C_OA2_MASK01 ((uint8_t)0x01U)\r
+#define I2C_OA2_MASK02 ((uint8_t)0x02U)\r
+#define I2C_OA2_MASK03 ((uint8_t)0x03U)\r
+#define I2C_OA2_MASK04 ((uint8_t)0x04U)\r
+#define I2C_OA2_MASK05 ((uint8_t)0x05U)\r
+#define I2C_OA2_MASK06 ((uint8_t)0x06U)\r
+#define I2C_OA2_MASK07 ((uint8_t)0x07U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)\r
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode\r
+ * @{\r
+ */\r
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)\r
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size\r
+ * @{\r
+ */\r
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)\r
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup I2C_XferDirection I2C Transfer Direction\r
+ * @{\r
+ */\r
+#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U)\r
+#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode\r
+ * @{\r
+ */\r
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD\r
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND\r
+#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode\r
+ * @{\r
+ */\r
+#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U)\r
+#define I2C_GENERATE_STOP I2C_CR2_STOP\r
+#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)\r
+#define I2C_GENERATE_START_WRITE I2C_CR2_START\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r
+ * @brief I2C Interrupt definition\r
+ * Elements values convention: 0xXXXXXXXX\r
+ * - XXXXXXXX : Interrupt control mask\r
+ * @{\r
+ */\r
+#define I2C_IT_ERRI I2C_CR1_ERRIE\r
+#define I2C_IT_TCI I2C_CR1_TCIE\r
+#define I2C_IT_STOPI I2C_CR1_STOPIE\r
+#define I2C_IT_NACKI I2C_CR1_NACKIE\r
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE\r
+#define I2C_IT_RXI I2C_CR1_RXIE\r
+#define I2C_IT_TXI I2C_CR1_TXIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Flag_definition I2C Flag definition\r
+ * @{\r
+ */ \r
+#define I2C_FLAG_TXE I2C_ISR_TXE\r
+#define I2C_FLAG_TXIS I2C_ISR_TXIS\r
+#define I2C_FLAG_RXNE I2C_ISR_RXNE\r
+#define I2C_FLAG_ADDR I2C_ISR_ADDR\r
+#define I2C_FLAG_AF I2C_ISR_NACKF\r
+#define I2C_FLAG_STOPF I2C_ISR_STOPF\r
+#define I2C_FLAG_TC I2C_ISR_TC\r
+#define I2C_FLAG_TCR I2C_ISR_TCR\r
+#define I2C_FLAG_BERR I2C_ISR_BERR\r
+#define I2C_FLAG_ARLO I2C_ISR_ARLO\r
+#define I2C_FLAG_OVR I2C_ISR_OVR\r
+#define I2C_FLAG_PECERR I2C_ISR_PECERR\r
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT\r
+#define I2C_FLAG_ALERT I2C_ISR_ALERT\r
+#define I2C_FLAG_BUSY I2C_ISR_BUSY\r
+#define I2C_FLAG_DIR I2C_ISR_DIR\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+ \r
+/** @defgroup I2C_Exported_Macros I2C Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset I2C handle state.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r
+\r
+/** @brief Enable the specified I2C interrupt.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified I2C interrupt.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ * \r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r
+ \r
+/** @brief Check whether the specified I2C interrupt source is enabled or not.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the I2C interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Check whether the specified I2C flag is set or not.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty\r
+ * @arg @ref I2C_FLAG_TXIS Transmit interrupt status\r
+ * @arg @ref I2C_FLAG_RXNE Receive data register not empty\r
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)\r
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag\r
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag\r
+ * @arg @ref I2C_FLAG_TC Transfer complete (master mode)\r
+ * @arg @ref I2C_FLAG_TCR Transfer complete reload\r
+ * @arg @ref I2C_FLAG_BERR Bus error\r
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost\r
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun\r
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception\r
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
+ * @arg @ref I2C_FLAG_ALERT SMBus alert\r
+ * @arg @ref I2C_FLAG_BUSY Bus busy\r
+ * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)\r
+ *\r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)\r
+\r
+/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty\r
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)\r
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag\r
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag\r
+ * @arg @ref I2C_FLAG_BERR Bus error\r
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost\r
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun \r
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception\r
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag \r
+ * @arg @ref I2C_FLAG_ALERT SMBus alert\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \\r
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))\r
+ \r
+/** @brief Enable the specified I2C peripheral.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief Disable the specified I2C peripheral.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.\r
+ * @param __HANDLE__: specifies the I2C Handle. \r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include I2C HAL Extended module */\r
+#include "stm32f7xx_hal_i2c_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup I2C_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions******************************/\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ * @{\r
+ */\r
+/* IO operation functions ****************************************************/\r
+ /******* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r
+\r
+ /******* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\r
+\r
+ /******* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */\r
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\r
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
+ * @{\r
+ */\r
+/* Peripheral State, Mode and Error functions *********************************/\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Constants I2C Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Macro I2C Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\r
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r
+\r
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\r
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r
+\r
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \\r
+ ((MASK) == I2C_OA2_MASK01) || \\r
+ ((MASK) == I2C_OA2_MASK02) || \\r
+ ((MASK) == I2C_OA2_MASK03) || \\r
+ ((MASK) == I2C_OA2_MASK04) || \\r
+ ((MASK) == I2C_OA2_MASK05) || \\r
+ ((MASK) == I2C_OA2_MASK06) || \\r
+ ((MASK) == I2C_OA2_MASK07))\r
+\r
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \\r
+ ((CALL) == I2C_GENERALCALL_ENABLE))\r
+\r
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\r
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r
+\r
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\r
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r
+\r
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \\r
+ ((MODE) == I2C_AUTOEND_MODE) || \\r
+ ((MODE) == I2C_SOFTEND_MODE))\r
+\r
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \\r
+ ((REQUEST) == I2C_GENERATE_START_READ) || \\r
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \\r
+ ((REQUEST) == I2C_NO_STARTSTOP))\r
+\r
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \\r
+ ((REQUEST) == I2C_NEXT_FRAME) || \\r
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \\r
+ ((REQUEST) == I2C_LAST_FRAME))\r
+\r
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r
+\r
+#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)\r
+#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)\r
+#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)\r
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)\r
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)\r
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)\r
+\r
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))\r
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))\r
+\r
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\r
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32f7xx_hal_i2c.c file */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_I2C_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c_ex.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of I2C HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_I2C_EX_H\r
+#define __STM32F7xx_HAL_I2C_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2CEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter\r
+ * @{\r
+ */\r
+#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)\r
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus\r
+ * @{\r
+ */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+\r
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP\r
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP\r
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP\r
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP\r
+\r
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP\r
+#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP\r
+#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP\r
+#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP\r
+\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Peripheral Control methods ************************************************/\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);\r
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Constants I2C Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Macro I2C Private Macros\r
+ * @{\r
+ */\r
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\r
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r
+\r
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)\r
+\r
+#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP) \r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))\r
+#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))\r
+#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))\r
+#elif defined(SYSCFG_PMC_I2C1_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))\r
+#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_I2C_EX_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of PWR HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PWR_H\r
+#define __STM32F7xx_HAL_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Types PWR Exported Types\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief PWR PVD configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.\r
+ This parameter can be a value of @ref PWR_PVD_detection_level */\r
+\r
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref PWR_PVD_Mode */\r
+}PWR_PVDTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r
+ * @{\r
+ */ \r
+#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0\r
+#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1\r
+#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2\r
+#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3\r
+#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4\r
+#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5\r
+#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6\r
+#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage \r
+ (Compare internally to VREFINT) */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PWR_PVD_Mode PWR PVD Mode\r
+ * @{\r
+ */\r
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */\r
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)\r
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r
+ * @{\r
+ */\r
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)\r
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r
+ * @{\r
+ */\r
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)\r
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale\r
+ * @{\r
+ */\r
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS\r
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1\r
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag PWR Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_WU PWR_CSR1_WUIF\r
+#define PWR_FLAG_SB PWR_CSR1_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR1_PVDO\r
+#define PWR_FLAG_BRR PWR_CSR1_BRR\r
+#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Macro PWR Exported Macro\r
+ * @{\r
+ */\r
+\r
+/** @brief macros configure the main internal regulator output voltage.\r
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption when the device does\r
+ * not operate at the maximum frequency (refer to the datasheets for more details).\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \\r
+ __IO uint32_t tmpreg; \\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Check PWR flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
+ * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),\r
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
+ * resumed from StandBy mode. \r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode \r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the PVDE bit is set.\r
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset \r
+ * when the device wakes up from Standby mode or by a system reset \r
+ * or power reset. \r
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage \r
+ * scaling output selection is ready.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the PWR's pending flags.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ */\r
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2)\r
+\r
+/**\r
+ * @brief Enable the PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Disable the PVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Enable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Disable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief checks whether the specified PVD Exti interrupt flag is set or not.\r
+ * @retval EXTI PVD Line Status.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Clear the PVD Exti flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on PVD EXTI line.\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include PWR HAL Extension module */\r
+#include "stm32f7xx_hal_pwr_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_PWR_DeInit(void);\r
+void HAL_PWR_EnableBkUpAccess(void);\r
+void HAL_PWR_DisableBkUpAccess(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+/* PVD configuration */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
+void HAL_PWR_EnablePVD(void);\r
+void HAL_PWR_DisablePVD(void);\r
+\r
+/* WakeUp pins configuration */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
+\r
+/* Low Power modes entry */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
+void HAL_PWR_EnterSTANDBYMode(void);\r
+\r
+/* Power PVD IRQ Handler */\r
+void HAL_PWR_PVD_IRQHandler(void);\r
+void HAL_PWR_PVDCallback(void);\r
+\r
+/* Cortex System Control functions *******************************************/\r
+void HAL_PWR_EnableSleepOnExit(void);\r
+void HAL_PWR_DisableSleepOnExit(void);\r
+void HAL_PWR_EnableSEVOnPend(void);\r
+void HAL_PWR_DisableSEVOnPend(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Constants PWR Private Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\r
+ * @{\r
+ */\r
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Macros PWR Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\r
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_NORMAL))\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\r
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PWR_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr_ex.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of PWR HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PWR_EX_H\r
+#define __STM32F7xx_HAL_PWR_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWREx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1\r
+#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2\r
+#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3\r
+#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4\r
+#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5\r
+#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6\r
+#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1\r
+#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2\r
+#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3\r
+#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4\r
+#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5\r
+#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6\r
+#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)\r
+#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)\r
+#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)\r
+#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)\r
+#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)\r
+#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS\r
+#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY\r
+#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY\r
+#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1\r
+#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2\r
+#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3\r
+#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4\r
+#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5\r
+#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro\r
+ * @{\r
+ */\r
+/** @brief Macros to enable or disable the Over drive mode.\r
+ */\r
+#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)\r
+#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))\r
+\r
+/** @brief Macros to enable or disable the Over drive switching.\r
+ */\r
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)\r
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))\r
+\r
+/** @brief Macros to enable or disable the Under drive mode.\r
+ * @note This mode is enabled only with STOP low power mode.\r
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r
+ * mode is only available when the main regulator or the low power regulator \r
+ * is in low voltage mode. \r
+ * @note If the Under-drive mode was enabled, it is automatically disabled after \r
+ * exiting Stop mode. \r
+ * When the voltage regulator operates in Under-drive mode, an additional \r
+ * startup delay is induced when waking up from Stop mode.\r
+ */\r
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)\r
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))\r
+\r
+/** @brief Check PWR flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode\r
+ * is ready \r
+ * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode\r
+ * switching is ready \r
+ * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode\r
+ * is enabled in Stop mode\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the Under-Drive Ready flag.\r
+ */\r
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)\r
+\r
+/** @brief Check Wake Up flag is set or not.\r
+ * @param __WUFLAG__: specifies the Wake Up flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 \r
+ */\r
+#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))\r
+\r
+/** @brief Clear the WakeUp pins flags.\r
+ * @param __WUFLAG__: specifies the Wake Up pin flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 \r
+ */\r
+#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup PWREx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+uint32_t HAL_PWREx_GetVoltageRange(void);\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r
+\r
+void HAL_PWREx_EnableFlashPowerDown(void);\r
+void HAL_PWREx_DisableFlashPowerDown(void); \r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); \r
+\r
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void);\r
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void);\r
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void);\r
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void);\r
+\r
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);\r
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Private_Macros PWREx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))\r
+#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6_LOW))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PWR_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of RCC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RCC_H\r
+#define __STM32F7xx_HAL_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+ \r
+/* Include RCC HAL Extended module */\r
+/* (include on top of file since RCC structures are defined in extended file) */\r
+#include "stm32f7xx_hal_rcc_ex.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** @defgroup RCC_Exported_Types RCC Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OscillatorType; /*!< The oscillators to be configured.\r
+ This parameter can be a value of @ref RCC_Oscillator_Type */\r
+\r
+ uint32_t HSEState; /*!< The new state of the HSE.\r
+ This parameter can be a value of @ref RCC_HSE_Config */\r
+\r
+ uint32_t LSEState; /*!< The new state of the LSE.\r
+ This parameter can be a value of @ref RCC_LSE_Config */\r
+ \r
+ uint32_t HSIState; /*!< The new state of the HSI.\r
+ This parameter can be a value of @ref RCC_HSI_Config */\r
+\r
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
+ \r
+ uint32_t LSIState; /*!< The new state of the LSI.\r
+ This parameter can be a value of @ref RCC_LSI_Config */\r
+\r
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ \r
+\r
+}RCC_OscInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC System, AHB and APB busses clock configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockType; /*!< The clock to be configured.\r
+ This parameter can be a value of @ref RCC_System_Clock_Type */\r
+ \r
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.\r
+ This parameter can be a value of @ref RCC_System_Clock_Source */\r
+\r
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */\r
+\r
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+}RCC_ClkInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Oscillator_Type Oscillator Type\r
+ * @{\r
+ */\r
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)\r
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)\r
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)\r
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)\r
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Config RCC HSE Config\r
+ * @{\r
+ */\r
+#define RCC_HSE_OFF ((uint32_t)0x00000000U)\r
+#define RCC_HSE_ON RCC_CR_HSEON\r
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Config RCC LSE Config\r
+ * @{\r
+ */\r
+#define RCC_LSE_OFF ((uint32_t)0x00000000U)\r
+#define RCC_LSE_ON RCC_BDCR_LSEON\r
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSI_Config RCC HSI Config\r
+ * @{\r
+ */\r
+#define RCC_HSI_OFF ((uint32_t)0x00000000U)\r
+#define RCC_HSI_ON RCC_CR_HSION\r
+\r
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Config RCC LSI Config\r
+ * @{\r
+ */\r
+#define RCC_LSI_OFF ((uint32_t)0x00000000U)\r
+#define RCC_LSI_ON RCC_CSR_LSION\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Config RCC PLL Config\r
+ * @{\r
+ */\r
+#define RCC_PLL_NONE ((uint32_t)0x00000000U)\r
+#define RCC_PLL_OFF ((uint32_t)0x00000001U)\r
+#define RCC_PLL_ON ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)\r
+#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)\r
+#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)\r
+#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
+ * @{\r
+ */\r
+#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI\r
+#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Type RCC System Clock Type\r
+ * @{\r
+ */\r
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)\r
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)\r
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)\r
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_System_Clock_Source RCC System Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)\r
+#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup RCC_MCO_Index RCC MCO Index\r
+ * @{\r
+ */\r
+#define RCC_MCO1 ((uint32_t)0x00000000U)\r
+#define RCC_MCO2 ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)\r
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0\r
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1\r
+#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)\r
+#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0\r
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1\r
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler\r
+ * @{\r
+ */\r
+#define RCC_MCODIV_1 ((uint32_t)0x00000000U)\r
+#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2\r
+#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Interrupt RCC Interrupt \r
+ * @{\r
+ */\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01U)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02U)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04U)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08U)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10U)\r
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)\r
+#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)\r
+#define RCC_IT_CSS ((uint8_t)0x80U)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_Flag RCC Flags\r
+ * Elements values convention: 0XXYYYYYb\r
+ * - YYYYY : Flag position in the register\r
+ * - 0XX : Register index\r
+ * - 01: CR register\r
+ * - 10: BDCR register\r
+ * - 11: CSR register\r
+ * @{\r
+ */\r
+/* Flags in the CR register */\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31U)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)\r
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)\r
+#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)\r
+\r
+/* Flags in the BDCR register */\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x41U)\r
+\r
+/* Flags in the CSR register */\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)\r
+#define RCC_FLAG_BORRST ((uint8_t)0x79U)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x7AU)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x7BU)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations\r
+ * @{\r
+ */\r
+#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)\r
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1\r
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0\r
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r
+ * @brief Enable or disable the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\r
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\r
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable \r
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) \r
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r
+ * @brief EGet the enable or disable status of the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release\r
+ * @brief Force or release AHB peripheral reset.\r
+ * @{\r
+ */ \r
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\r
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))\r
+\r
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)\r
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\r
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset \r
+ * @brief Force or release APB1 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) \r
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\r
+\r
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) \r
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset \r
+ * @brief Force or release APB2 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) \r
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))\r
+\r
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)\r
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r
+\r
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))\r
+\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_HSI_Configuration HSI Configuration\r
+ * @{ \r
+ */ \r
+ \r
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after startup\r
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
+ * of the HSE used directly or indirectly as system clock (if the Clock\r
+ * Security System CSS is enabled). \r
+ * @note HSI can not be stopped if it is used as system clock source. In this case,\r
+ * you have to select another source of the system clock then stop the HSI. \r
+ * @note After enabling the HSI, the application software should wait on HSIRDY\r
+ * flag to be set indicating that HSI clock is stable and can be used as\r
+ * system clock source. \r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles. \r
+ */\r
+#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))\r
+#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))\r
+\r
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.\r
+ * (default is RCC_HSICALIBRATION_DEFAULT).\r
+ */\r
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\\r
+ RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Configuration LSI Configuration\r
+ * @{ \r
+ */ \r
+\r
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles. \r
+ */\r
+#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))\r
+#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Configuration HSE Configuration\r
+ * @{ \r
+ */ \r
+/**\r
+ * @brief Macro to configure the External High Speed oscillator (HSE).\r
+ * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this macro. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param __STATE__: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator.\r
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \\r
+ do { \\r
+ if ((__STATE__) == RCC_HSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Configuration LSE Configuration\r
+ * @{ \r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the External Low Speed oscillator (LSE).\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. \r
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass. \r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using \r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset). \r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param __STATE__: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.\r
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \\r
+ do { \\r
+ if((__STATE__) == RCC_LSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else if((__STATE__) == RCC_LSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ } \\r
+ else if((__STATE__) == RCC_LSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macros to enable or disable the RTC clock.\r
+ * @note These macros must be used only after the RTC clock source was selected.\r
+ */\r
+#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))\r
+#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))\r
+\r
+/** @brief Macros to configure the RTC clock (RTCCLK).\r
+ * @note As the RTC clock configuration bits are in the Backup domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using the Power Backup Access macro before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * @note Once the RTC clock is configured it can't be changed unless the \r
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by\r
+ * a Power On Reset (POR).\r
+ * @param __RTCCLKSource__: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.\r
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.\r
+ * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected\r
+ * as RTC clock, where x:[2,31]\r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes. \r
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ */\r
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)\r
+ \r
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \\r
+ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \\r
+ } while (0)\r
+\r
+/** @brief Macros to force or release the Backup domain reset.\r
+ * @note This function resets the RTC peripheral (including the backup registers)\r
+ * and the RTC clock source selection in RCC_CSR register.\r
+ * @note The BKPSRAM is not affected by this reset. \r
+ */\r
+#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))\r
+#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Configuration PLL Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macros to enable or disable the main PLL.\r
+ * @note After enabling the main PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * @note The main PLL can not be disabled if it is used as system clock source\r
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)\r
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r
+ \r
+/** @brief Macro to configure the PLL clock source.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __PLLSOURCE__: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * \r
+ */\r
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r
+\r
+/** @brief Macro to configure the PLL multiplication factor.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * \r
+ */\r
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macro to configure the I2S clock source (I2SCLK).\r
+ * @note This function must be called before enabling the I2S APB clock.\r
+ * @param __SOURCE__: specifies the I2S clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.\r
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin\r
+ * used as I2S clock source.\r
+ */\r
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \\r
+ RCC->CFGR |= (__SOURCE__); \\r
+ }while(0)\r
+\r
+/** @brief Macros to enable or disable the PLLI2S. \r
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))\r
+#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Get_Clock_source Get Clock source\r
+ * @{ \r
+ */\r
+/**\r
+ * @brief Macro to configure the system clock source.\r
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.\r
+ * This parameter can be one of the following values:\r
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r
+ */\r
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))\r
+\r
+/** @brief Macro to get the clock source used as system clock.\r
+ * @retval The clock source used as system clock. The returned value can be one\r
+ * of the following:\r
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r
+ */ \r
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))\r
+\r
+/**\r
+ * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.\r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using\r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset).\r
+ * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.\r
+ * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \\r
+ (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))\r
+\r
+/** @brief Macro to get the oscillator used as PLL clock source.\r
+ * @retval The oscillator used as PLL clock source. The returned value can be one\r
+ * of the following:\r
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r
+ */\r
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\r
+ * @{ \r
+ */ \r
+ \r
+/** @brief Macro to configure the MCO1 clock.\r
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r
+ * @param __MCODIV__ specifies the MCO clock prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock\r
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r
+ */\r
+\r
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r
+ \r
+/** @brief Macro to configure the MCO2 clock.\r
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source \r
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r
+ * @param __MCODIV__ specifies the MCO clock prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock\r
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r
+ */\r
+\r
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
+ * @brief macros to manage the specified RCC Flags and interrupts.\r
+ * @{\r
+ */\r
+\r
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable\r
+ * the selected interrupts).\r
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ */\r
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\r
+\r
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable \r
+ * the selected interrupts).\r
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ */\r
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))\r
+\r
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]\r
+ * bits to clear the selected interrupt pending bits.\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ */\r
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\r
+\r
+/** @brief Check the RCC's interrupt has occurred or not.\r
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r
+ */\r
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)\r
+\r
+/** @brief Check RCC flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.\r
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.\r
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.\r
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.\r
+ * @arg RCC_FLAG_PINRST: Pin reset.\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.\r
+ * @arg RCC_FLAG_SFTRST: Software reset.\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define RCC_FLAG_MASK ((uint8_t)0x1F)\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include RCC HAL Extension module */\r
+#include "stm32f7xx_hal_rcc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+ /** @addtogroup RCC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group1\r
+ * @{\r
+ */ \r
+/* Initialization and de-initialization functions ******************************/\r
+void HAL_RCC_DeInit(void);\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
+void HAL_RCC_EnableCSS(void);\r
+void HAL_RCC_DisableCSS(void);\r
+uint32_t HAL_RCC_GetSysClockFreq(void);\r
+uint32_t HAL_RCC_GetHCLKFreq(void);\r
+uint32_t HAL_RCC_GetPCLK1Freq(void);\r
+uint32_t HAL_RCC_GetPCLK2Freq(void);\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
+\r
+/* CSS NMI IRQ handler */\r
+void HAL_RCC_NMI_IRQHandler(void);\r
+\r
+/* User Callbacks in non blocking mode (IT mode) */ \r
+void HAL_RCC_CSSCallback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Constants RCC Private Constants\r
+ * @{\r
+ */\r
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT\r
+#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */\r
+#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */\r
+#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */\r
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ \r
+\r
+/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias\r
+ * @brief RCC registers bit address alias\r
+ * @{\r
+ */\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))\r
+\r
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)\r
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */ \r
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)\r
+\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_BYPASS))\r
+\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_BYPASS))\r
+\r
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))\r
+\r
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))\r
+\r
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))\r
+\r
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_PLLSOURCE_HSE))\r
+\r
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))\r
+#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))\r
+\r
+#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r
+\r
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \\r
+ ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))\r
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV512))\r
+\r
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))\r
+\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \\r
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \\r
+ ((PCLK) == RCC_HCLK_DIV16))\r
+\r
+#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))\r
+\r
+\r
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \\r
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))\r
+\r
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \\r
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))\r
+\r
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \\r
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \\r
+ ((DIV) == RCC_MCODIV_5)) \r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+\r
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))\r
+\r
+\r
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_HIGH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RCC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc_ex.h\r
+ * @author MCD Application Team \r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of RCC HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RCC_EX_H\r
+#define __STM32F7xx_HAL_RCC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCCEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief RCC PLL configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLState; /*!< The new state of the PLL.\r
+ This parameter can be a value of @ref RCC_PLL_Config */\r
+\r
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.\r
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */ \r
+\r
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ \r
+\r
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.\r
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432 */\r
+\r
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).\r
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
+\r
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15 */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7 */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+}RCC_PLLInitTypeDef; \r
+\r
+/** \r
+ * @brief PLLI2S Clock structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.\r
+ This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */\r
+}RCC_PLLI2SInitTypeDef;\r
+\r
+/** \r
+ * @brief PLLSAI Clock structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ \r
+ \r
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\r
+ \r
+ uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source LTDC */\r
+\r
+ uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.\r
+ This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider\r
+ This parameter will be used only when PLLSAI is disabled */\r
+}RCC_PLLSAIInitTypeDef;\r
+\r
+/** \r
+ * @brief RCC extended clocks structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
+\r
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */\r
+\r
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32\r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.\r
+ This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */\r
+\r
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. \r
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */\r
+ \r
+ uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. \r
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */\r
+\r
+ uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. \r
+ This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */\r
+ \r
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection\r
+ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r
+\r
+ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection\r
+ This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\r
+ \r
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source \r
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */\r
+ \r
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source \r
+ This parameter can be a value of @ref RCCEx_USART2_Clock_Source */\r
+\r
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source \r
+ This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ \r
+ \r
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source \r
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */\r
+ \r
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source \r
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */\r
+ \r
+ uint32_t Usart6ClockSelection; /*!< USART6 clock source \r
+ This parameter can be a value of @ref RCCEx_USART6_Clock_Source */\r
+ \r
+ uint32_t Uart7ClockSelection; /*!< UART7 clock source \r
+ This parameter can be a value of @ref RCCEx_UART7_Clock_Source */\r
+ \r
+ uint32_t Uart8ClockSelection; /*!< UART8 clock source \r
+ This parameter can be a value of @ref RCCEx_UART8_Clock_Source */\r
+ \r
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */\r
+\r
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */\r
+\r
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */\r
+ \r
+ uint32_t I2c4ClockSelection; /*!< I2C4 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r
+ \r
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source\r
+ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r
+ \r
+ uint32_t CecClockSelection; /*!< CEC clock source \r
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */\r
+ \r
+ uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC\r
+ This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\r
+ \r
+ uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source \r
+ This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */\r
+ \r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+ uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source \r
+ This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */\r
+ \r
+ uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source \r
+ This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */\r
+ \r
+ uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source \r
+ This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+}RCC_PeriphCLKInitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection\r
+ * @{\r
+ */\r
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)\r
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)\r
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)\r
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)\r
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)\r
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)\r
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)\r
+#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)\r
+#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)\r
+#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)\r
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)\r
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)\r
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)\r
+#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)\r
+#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)\r
+#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)\r
+#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)\r
+#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)\r
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)\r
+#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)\r
+#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)\r
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)\r
+#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)\r
+#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)\r
+#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)\r
+#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)\r
+#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)\r
+#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)\r
+#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)\r
+#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR\r
+ * @{\r
+ */\r
+#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)\r
+#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0\r
+#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1\r
+#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)\r
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ \r
+/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)\r
+#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0\r
+#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)\r
+#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0\r
+#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)\r
+#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)\r
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0\r
+#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1\r
+#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0\r
+#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1\r
+#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0\r
+#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1\r
+#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0\r
+#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1\r
+#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0\r
+#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1\r
+#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)\r
+#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0\r
+#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1\r
+#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0\r
+#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1\r
+#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0\r
+#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1\r
+#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0\r
+#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0\r
+#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0\r
+#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0\r
+#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)\r
+#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0\r
+#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1\r
+#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)\r
+#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection\r
+ * @{\r
+ */\r
+#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)\r
+#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)\r
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)\r
+#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)\r
+#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)\r
+#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) \r
+/**\r
+ * @}\r
+ */ \r
+#endif /* STM32F769xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
+ * @{\r
+ */\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable\r
+ * @brief Enables or disables the AHB/APB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @{\r
+ */\r
+ \r
+/** @brief Enables or disables the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ */\r
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\r
+#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))\r
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))\r
+#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\r
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))\r
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))\r
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))\r
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\r
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\r
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\r
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\r
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))\r
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))\r
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))\r
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))\r
+/**\r
+ * @brief Enable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \\r
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \\r
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \\r
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \\r
+ } while(0)\r
+/**\r
+ * @brief Disable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))\r
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \\r
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \\r
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \\r
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \\r
+ } while(0)\r
+ \r
+/** @brief Enable or disable the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ */\r
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_JPEG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\r
+ UNUSED(tmpreg); \\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\\r
+ } while(0) \r
+ \r
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) \r
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) \r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))\r
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) \r
+#endif /* STM32F756x || STM32F777xx || STM32F779xx */\r
+ \r
+/** @brief Enables or disables the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ */\r
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))\r
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\r
+\r
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ */\r
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_CAN3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\r
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\r
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\r
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\r
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\r
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\r
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) \r
+#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\r
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))\r
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\r
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\r
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\r
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\r
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\r
+#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))\r
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\r
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\r
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))\r
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))\r
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))\r
+\r
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+#if defined (STM32F769xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+#endif /* STM32F769xx || STM32F779xx */\r
+ \r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_MDIO_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\r
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\r
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\r
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\r
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\r
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))\r
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\r
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\r
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\r
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\r
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\r
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\r
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))\r
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\r
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))\r
+#endif /* STM32F769xx || STM32F779xx */ \r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))\r
+#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB/APB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+ \r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it. \r
+ */\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)\r
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) \r
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)\r
+\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)\r
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)\r
+/**\r
+ * @brief Enable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)\r
+#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \\r
+ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \\r
+ __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())\r
+\r
+/**\r
+ * @brief Disable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)\r
+#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \\r
+ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \\r
+ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it. \r
+ */\r
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)\r
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\r
+ \r
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)\r
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) \r
+#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)\r
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) \r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)\r
+#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */ \r
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)\r
+\r
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)\r
+#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)\r
+#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) \r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset\r
+ * @brief Forces or releases AHB/APB peripheral reset.\r
+ * @{\r
+ */\r
+ \r
+/** @brief Force or release AHB1 peripheral reset.\r
+ */ \r
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))\r
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))\r
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\r
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\r
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\r
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))\r
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))\r
+#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))\r
+#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))\r
+\r
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))\r
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))\r
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\r
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\r
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\r
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))\r
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))\r
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))\r
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))\r
+ \r
+/** @brief Force or release AHB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) \r
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\r
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\r
+\r
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)\r
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\r
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))\r
+#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\r
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+\r
+/** @brief Force or release AHB3 peripheral reset\r
+ */ \r
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) \r
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\r
+\r
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)\r
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))\r
+ \r
+/** @brief Force or release APB1 peripheral reset.\r
+ */ \r
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\r
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\r
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\r
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))\r
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\r
+#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))\r
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\r
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\r
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))\r
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))\r
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))\r
+\r
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\r
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\r
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\r
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))\r
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\r
+#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))\r
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\r
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\r
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))\r
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))\r
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))\r
+\r
+/** @brief Force or release APB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))\r
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\r
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\r
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))\r
+#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))\r
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\r
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\r
+#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))\r
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\r
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\r
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\r
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\r
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))\r
+#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))\r
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\r
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\r
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))\r
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\r
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))\r
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))\r
+#endif /* STM32F769xx || STM32F779xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))\r
+#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))\r
+#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))\r
+\r
+#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))\r
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))\r
+#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable\r
+ * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */ \r
+ \r
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ */ \r
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\r
+#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\r
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\r
+#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))\r
+\r
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\r
+#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\r
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\r
+#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))\r
+\r
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r
+ \r
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+\r
+/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))\r
+\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))\r
+#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\r
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))\r
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))\r
+#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\r
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))\r
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))\r
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))\r
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))\r
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))\r
+#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))\r
+\r
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))\r
+#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+ \r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode. \r
+ */\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)\r
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)\r
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)\r
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)\r
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)\r
+\r
+#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)\r
+#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)\r
+\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)\r
+ \r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)\r
+\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)\r
+#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)\r
+#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*------------------------------- PLL Configuration --------------------------*/\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. \r
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
+ * output frequency is between 100 and 432 MHz.\r
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)\r
+ * This parameter must be a number in the range {2, 4, 6, or 8}.\r
+ * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on\r
+ * the System clock frequency.\r
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @note If the USB OTG FS is used in your application, you have to set the\r
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
+ * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r
+ * correctly.\r
+ * @param __PLLR__: specifies the division factor for DSI clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ */\r
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \\r
+ (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \\r
+ ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \\r
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \\r
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \\r
+ ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))\r
+#else\r
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. \r
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
+ * output frequency is between 100 and 432 MHz.\r
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)\r
+ * This parameter must be a number in the range {2, 4, 6, or 8}.\r
+ * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on\r
+ * the System clock frequency.\r
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @note If the USB OTG FS is used in your application, you have to set the\r
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
+ * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r
+ * correctly.\r
+ */\r
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \\r
+ (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \\r
+ ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \\r
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \\r
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+/*---------------------------------------------------------------------------------------------*/\r
+\r
+/** @brief Macro to configure the Timers clocks prescalers \r
+ * @param __PRESC__ : specifies the Timers clocks prescalers selection\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is \r
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2, \r
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to \r
+ * division by 4 or more. \r
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is \r
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, \r
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding \r
+ * to division by 8 or more.\r
+ */ \r
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\\r
+ RCC->DCKCFGR1 |= (__PRESC__); \\r
+ }while(0)\r
+\r
+/** @brief Macros to Enable or Disable the PLLISAI. \r
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. \r
+ */\r
+#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))\r
+#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))\r
+\r
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.\r
+ * @note This function must be used only when the PLLSAI is disabled.\r
+ * @note PLLSAI clock source is common with the main PLL (configured in \r
+ * RCC_PLLConfig function )\r
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO \r
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r
+ * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks\r
+ * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. \r
+ * @param __PLLSAIQ__: specifies the division factor for SAI clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ */ \r
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \\r
+ (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\\r
+ ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\\r
+ ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\\r
+ ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))\r
+\r
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors.\r
+ * @note This macro must be used only when the PLLI2S is disabled.\r
+ * @note PLLI2S clock source is common with the main PLL (configured in \r
+ * HAL_RCC_ClockConfig() API) \r
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO \r
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r
+ * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.\r
+ * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. \r
+ * @param __PLLI2SQ__: specifies the division factor for SAI clock.\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15. \r
+ * @param __PLLI2SR__: specifies the division factor for I2S clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r
+ * on the I2S clock frequency. \r
+ */\r
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \\r
+ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\\r
+ ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\\r
+ ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\\r
+ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))\r
+ \r
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.\r
+ * @note This function must be called before enabling the PLLI2S. \r
+ * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .\r
+ * This parameter must be a number between 1 and 32.\r
+ * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ \r
+ */\r
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))\r
+\r
+/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.\r
+ * @note This function must be called before enabling the PLLSAI.\r
+ * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .\r
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 32.\r
+ * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ \r
+ */\r
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))\r
+\r
+/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.\r
+ * \r
+ * @note This function must be called before enabling the PLLSAI. \r
+ * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .\r
+ * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.\r
+ * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ \r
+ */ \r
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))\r
+\r
+/** @brief Macro to configure SAI1 clock source selection.\r
+ * @note This function must be called before enabling PLLSAI, PLLI2S and \r
+ * the SAI clock.\r
+ * @param __SOURCE__: specifies the SAI1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI1 clock. \r
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r
+ * used as SAI1 clock.\r
+ * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices \r
+ */\r
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))\r
+\r
+/** @brief Macro to get the SAI1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI1 clock. \r
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r
+ * used as SAI1 clock.\r
+ * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices \r
+ */\r
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))\r
+\r
+\r
+/** @brief Macro to configure SAI2 clock source selection.\r
+ * @note This function must be called before enabling PLLSAI, PLLI2S and \r
+ * the SAI clock.\r
+ * @param __SOURCE__: specifies the SAI2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI2 clock. \r
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI2 clock. \r
+ * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r
+ * used as SAI2 clock.\r
+ * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices \r
+ */\r
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))\r
+\r
+\r
+/** @brief Macro to get the SAI2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI2 clock. \r
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r
+ * used as SAI2 clock.\r
+ * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices \r
+ */\r
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))\r
+\r
+\r
+/** @brief Enable PLLSAI_RDY interrupt.\r
+ */\r
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Disable PLLSAI_RDY interrupt.\r
+ */\r
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Clear the PLLSAI RDY interrupt pending bits.\r
+ */\r
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))\r
+\r
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.\r
+ * @retval The new state (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Check PLLSAI RDY flag is set or not.\r
+ * @retval The new state (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))\r
+\r
+/** @brief Macro to Get I2S clock source selection.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. \r
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source\r
+ */\r
+#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))\r
+\r
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).\r
+ *\r
+ * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the I2C1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))\r
+\r
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).\r
+ *\r
+ * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the I2C2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))\r
+\r
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).\r
+ *\r
+ * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))\r
+\r
+/** @brief macro to get the I2C3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))\r
+\r
+/** @brief Macro to configure the I2C4 clock (I2C4CLK).\r
+ *\r
+ * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))\r
+\r
+/** @brief macro to get the I2C4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))\r
+\r
+/** @brief Macro to configure the USART1 clock (USART1CLK).\r
+ *\r
+ * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))\r
+\r
+/** @brief Macro to configure the USART2 clock (USART2CLK).\r
+ *\r
+ * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))\r
+\r
+/** @brief Macro to configure the USART3 clock (USART3CLK).\r
+ *\r
+ * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))\r
+\r
+ /** @brief Macro to configure the UART4 clock (UART4CLK).\r
+ *\r
+ * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))\r
+\r
+ /** @brief Macro to configure the UART5 clock (UART5CLK).\r
+ *\r
+ * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))\r
+\r
+ /** @brief Macro to configure the USART6 clock (USART6CLK).\r
+ *\r
+ * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART6 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))\r
+\r
+ /** @brief Macro to configure the UART7 clock (UART7CLK).\r
+ *\r
+ * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART7 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))\r
+\r
+/** @brief Macro to configure the UART8 clock (UART8CLK).\r
+ *\r
+ * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART8 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))\r
+\r
+/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).\r
+ *\r
+ * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the LPTIM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))\r
+\r
+/** @brief Macro to configure the CEC clock (CECCLK).\r
+ *\r
+ * @param __CEC_CLKSOURCE__: specifies the CEC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock\r
+ */\r
+#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))\r
+\r
+/** @brief macro to get the CEC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock\r
+ */\r
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))\r
+\r
+/** @brief Macro to configure the CLK48 source (CLK48CLK).\r
+ *\r
+ * @param __CLK48_SOURCE__: specifies the CLK48 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source\r
+ * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source\r
+ */\r
+#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))\r
+\r
+/** @brief macro to get the CLK48 source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source\r
+ * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source\r
+ */\r
+#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))\r
+\r
+/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).\r
+ *\r
+ * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock\r
+ * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock\r
+ */\r
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the SDMMC1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock\r
+ * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock\r
+ */\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).\r
+ * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r
+ * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r
+ */\r
+#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))\r
+\r
+/** @brief macro to get the SDMMC2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r
+ * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r
+ */\r
+#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))\r
+ \r
+/** @brief Macro to configure the DFSDM1 clock\r
+ * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock\r
+ * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock\r
+ */\r
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the DFSDM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock\r
+ * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock\r
+ */\r
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))\r
+\r
+/** @brief Macro to configure the DFSDM1 Audio clock\r
+ * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock\r
+ */\r
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the DFSDM1 Audio clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock\r
+ */\r
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+/** @brief Macro to configure the DSI clock.\r
+ * @param __DSI_CLKSOURCE__: specifies the DSI clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. \r
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. \r
+ */\r
+#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))\r
+\r
+/** @brief Macro to Get the DSI clock.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. \r
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. \r
+ */\r
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) \r
+#endif /* STM32F769xx || STM32F779xx */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#elif defined(STM32F745xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) \r
+#elif defined (STM32F765xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) \r
+#endif /* STM32F746xx || STM32F756xx */\r
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\\r
+ ((VALUE) == RCC_PLLI2SP_DIV4) ||\\r
+ ((VALUE) == RCC_PLLI2SP_DIV6) ||\\r
+ ((VALUE) == RCC_PLLI2SP_DIV8)) \r
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r
+\r
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\\r
+ ((VALUE) == RCC_PLLSAIP_DIV4) ||\\r
+ ((VALUE) == RCC_PLLSAIP_DIV6) ||\\r
+ ((VALUE) == RCC_PLLSAIP_DIV8))\r
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) \r
+\r
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r
+\r
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r
+\r
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_4) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_8) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_16))\r
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))\r
+\r
+#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))\r
+\r
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))\r
+#define IS_RCC_USART1CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART2CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_HSI))\r
+#define IS_RCC_USART3CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART4CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART5CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART6CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART7CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART8CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_HSI))\r
+#define IS_RCC_I2C1CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))\r
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))\r
+#define IS_RCC_I2C4CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))\r
+#define IS_RCC_LPTIM1CLK(SOURCE) \\r
+ (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))\r
+#define IS_RCC_CLK48SOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \\r
+ ((SOURCE) == RCC_CLK48SOURCE_PLL))\r
+#define IS_RCC_TIMPRES(VALUE) \\r
+ (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \\r
+ ((VALUE) == RCC_TIMPRES_ACTIVATED))\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)\r
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))\r
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx */\r
+ \r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r
+ \r
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))\r
+\r
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))\r
+\r
+#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))\r
+\r
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \\r
+ ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))\r
+\r
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \\r
+ ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\\r
+ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RCC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_uart.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of UART HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_UART_H\r
+#define __STM32F7xx_HAL_UART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Types UART Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART Init Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.\r
+ The baud rate register is computed using the following formula:\r
+ - If oversampling is 16 or in LIN mode,\r
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))\r
+ - If oversampling is 8,\r
+ Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]\r
+ Baud Rate Register[3] = 0\r
+ Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */\r
+\r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref UARTEx_Word_Length */\r
+\r
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref UART_Stop_Bits */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref UART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+\r
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref UART_Mode */\r
+\r
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */\r
+\r
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r
+ This parameter can be a value of @ref UART_Over_Sampling */\r
+\r
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.\r
+ Selecting the single sample method increases the receiver tolerance to clock\r
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling */\r
+}UART_InitTypeDef;\r
+\r
+/**\r
+ * @brief UART Advanced Features initialization structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several\r
+ Advanced Features may be initialized at the same time .\r
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */\r
+\r
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.\r
+ This parameter can be a value of @ref UART_Tx_Inv */\r
+\r
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.\r
+ This parameter can be a value of @ref UART_Rx_Inv */\r
+\r
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic\r
+ vs negative/inverted logic).\r
+ This parameter can be a value of @ref UART_Data_Inv */\r
+\r
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.\r
+ This parameter can be a value of @ref UART_Rx_Tx_Swap */\r
+\r
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.\r
+ This parameter can be a value of @ref UART_Overrun_Disable */\r
+\r
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.\r
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */\r
+\r
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.\r
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable */\r
+\r
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate\r
+ detection is carried out.\r
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */\r
+\r
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.\r
+ This parameter can be a value of @ref UART_MSB_First */\r
+} UART_AdvFeatureInitTypeDef;\r
+\r
+\r
+\r
+/**\r
+ * @brief HAL UART State structures definition\r
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState.\r
+ * - gState contains UART state information related to global Handle management \r
+ * and also information related to Tx operations.\r
+ * gState value coding follow below described bitmap :\r
+ * b7-b6 Error information \r
+ * 00 : No Error\r
+ * 01 : (Not Used)\r
+ * 10 : Timeout\r
+ * 11 : Error\r
+ * b5 IP initilisation status\r
+ * 0 : Reset (IP not initialized)\r
+ * 1 : Init done (IP not initialized. HAL UART Init function already called)\r
+ * b4-b3 (not used)\r
+ * xx : Should be set to 00\r
+ * b2 Intrinsic process state\r
+ * 0 : Ready\r
+ * 1 : Busy (IP busy with some configuration or internal operations)\r
+ * b1 (not used)\r
+ * x : Should be set to 0\r
+ * b0 Tx state\r
+ * 0 : Ready (no Tx operation ongoing)\r
+ * 1 : Busy (Tx operation ongoing)\r
+ * - RxState contains information related to Rx operations.\r
+ * RxState value coding follow below described bitmap :\r
+ * b7-b6 (not used)\r
+ * xx : Should be set to 00\r
+ * b5 IP initilisation status\r
+ * 0 : Reset (IP not initialized)\r
+ * 1 : Init done (IP not initialized)\r
+ * b4-b2 (not used)\r
+ * xxx : Should be set to 000\r
+ * b1 Rx state\r
+ * 0 : Ready (no Rx operation ongoing)\r
+ * 1 : Busy (Rx operation ongoing)\r
+ * b0 (not used)\r
+ * x : Should be set to 0.\r
+ */\r
+typedef enum\r
+{\r
+ HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized\r
+ Value is allowed for gState and RxState */\r
+ HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use\r
+ Value is allowed for gState and RxState */\r
+ HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing \r
+ Value is allowed for gState only */\r
+ HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing\r
+ Value is allowed for gState only */\r
+ HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing\r
+ Value is allowed for RxState only */\r
+ HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing\r
+ Not to be used for neither gState nor RxState.\r
+ Value is result of combination (Or) between gState and RxState values */\r
+ HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state\r
+ Value is allowed for gState only */\r
+ HAL_UART_STATE_ERROR = 0xE0U /*!< Error\r
+ Value is allowed for gState only */\r
+}HAL_UART_StateTypeDef;\r
+\r
+/**\r
+ * @brief UART clock sources definition\r
+ */\r
+typedef enum\r
+{\r
+ UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */\r
+ UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */\r
+ UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */\r
+ UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */\r
+ UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */\r
+ UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */\r
+}UART_ClockSourceTypeDef;\r
+\r
+/**\r
+ * @brief UART handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ USART_TypeDef *Instance; /*!< UART registers base address */\r
+\r
+ UART_InitTypeDef Init; /*!< UART communication parameters */\r
+\r
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */\r
+\r
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */\r
+\r
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */\r
+\r
+ uint16_t Mask; /*!< UART Rx RDR register mask */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+\r
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management \r
+ and also related to Tx operations.\r
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.\r
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+ __IO uint32_t ErrorCode; /*!< UART Error code */\r
+\r
+}UART_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Constants UART Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup UART_Error_Definition UART Error Definition\r
+ * @{\r
+ */\r
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */\r
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */\r
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */\r
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */\r
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */\r
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits\r
+ * @{\r
+ */\r
+#define UART_STOPBITS_1 ((uint32_t)0x00000000U)\r
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Parity UART Parity\r
+ * @{\r
+ */\r
+#define UART_PARITY_NONE ((uint32_t)0x00000000U)\r
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)\r
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r
+ * @{\r
+ */\r
+#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U)\r
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)\r
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)\r
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Mode UART Transfer Mode\r
+ * @{\r
+ */\r
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)\r
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)\r
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup UART_State UART State\r
+ * @{\r
+ */\r
+#define UART_STATE_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Over_Sampling UART Over Sampling\r
+ * @{\r
+ */\r
+#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)\r
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method\r
+ * @{\r
+ */\r
+#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut\r
+ * @{\r
+ */\r
+#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_LIN UART Local Interconnection Network mode\r
+ * @{\r
+ */\r
+#define UART_LIN_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection\r
+ * @{\r
+ */\r
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)\r
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Tx UART DMA Tx\r
+ * @{\r
+ */\r
+#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Rx UART DMA Rx\r
+ * @{\r
+ */\r
+#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U)\r
+#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection\r
+ * @{\r
+ */\r
+#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U)\r
+#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods\r
+ * @{\r
+ */\r
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)\r
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Request_Parameters UART Request Parameters\r
+ * @{\r
+ */\r
+#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */\r
+#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */\r
+#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */\r
+#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */\r
+#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)\r
+#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)\r
+#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)\r
+#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)\r
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)\r
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U)\r
+#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U)\r
+#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register\r
+ * @{\r
+ */\r
+#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity\r
+ * @{\r
+ */\r
+#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U)\r
+#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register\r
+ * @{\r
+ */\r
+#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register\r
+ * @{\r
+ */\r
+#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask\r
+ * @{\r
+ */\r
+#define UART_IT_MASK ((uint32_t)0x001FU)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value\r
+ * @{\r
+ */\r
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Flags UART Status Flags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the ISR register\r
+ * @{\r
+ */\r
+#define UART_FLAG_TEACK ((uint32_t)0x00200000U)\r
+#define UART_FLAG_SBKF ((uint32_t)0x00040000U)\r
+#define UART_FLAG_CMF ((uint32_t)0x00020000U)\r
+#define UART_FLAG_BUSY ((uint32_t)0x00010000U)\r
+#define UART_FLAG_ABRF ((uint32_t)0x00008000U)\r
+#define UART_FLAG_ABRE ((uint32_t)0x00004000U)\r
+#define UART_FLAG_EOBF ((uint32_t)0x00001000U)\r
+#define UART_FLAG_RTOF ((uint32_t)0x00000800U)\r
+#define UART_FLAG_CTS ((uint32_t)0x00000400U)\r
+#define UART_FLAG_CTSIF ((uint32_t)0x00000200U)\r
+#define UART_FLAG_LBDF ((uint32_t)0x00000100U)\r
+#define UART_FLAG_TXE ((uint32_t)0x00000080U)\r
+#define UART_FLAG_TC ((uint32_t)0x00000040U)\r
+#define UART_FLAG_RXNE ((uint32_t)0x00000020U)\r
+#define UART_FLAG_IDLE ((uint32_t)0x00000010U)\r
+#define UART_FLAG_ORE ((uint32_t)0x00000008U)\r
+#define UART_FLAG_NE ((uint32_t)0x00000004U)\r
+#define UART_FLAG_FE ((uint32_t)0x00000002U)\r
+#define UART_FLAG_PE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition\r
+ * Elements values convention: 0000ZZZZ0XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ * @{\r
+ */\r
+#define UART_IT_PE ((uint32_t)0x0028U)\r
+#define UART_IT_TXE ((uint32_t)0x0727U)\r
+#define UART_IT_TC ((uint32_t)0x0626U)\r
+#define UART_IT_RXNE ((uint32_t)0x0525U)\r
+#define UART_IT_IDLE ((uint32_t)0x0424U)\r
+#define UART_IT_LBD ((uint32_t)0x0846U)\r
+#define UART_IT_CTS ((uint32_t)0x096AU)\r
+#define UART_IT_CM ((uint32_t)0x112EU)\r
+\r
+/** Elements values convention: 000000000XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ */\r
+#define UART_IT_ERR ((uint32_t)0x0060U)\r
+\r
+/** Elements values convention: 0000ZZZZ00000000b\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ */\r
+#define UART_IT_ORE ((uint32_t)0x0300U)\r
+#define UART_IT_NE ((uint32_t)0x0200U)\r
+#define UART_IT_FE ((uint32_t)0x0100U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags\r
+ * @{\r
+ */\r
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */\r
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */\r
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */\r
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */\r
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */\r
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */\r
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */\r
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */\r
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */\r
+#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */\r
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Macros UART Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset UART handle state\r
+ * @param __HANDLE__: UART handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \\r
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \\r
+ } while(0)\r
+\r
+/** @brief Flush the UART Data registers\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ */\r
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \\r
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \\r
+ } while(0)\r
+\r
+/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __FLAG__: specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_CLEAR_PEF: Parity Error Clear Flag\r
+ * @arg UART_CLEAR_FEF: Framing Error Clear Flag\r
+ * @arg UART_CLEAR_NEF: Noise detected Clear Flag\r
+ * @arg UART_CLEAR_OREF: OverRun Error Clear Flag\r
+ * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag\r
+ * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag\r
+ * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag\r
+ * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag\r
+ * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag\r
+ * @arg UART_CLEAR_EOBF: End Of Block Clear Flag\r
+ * @arg UART_CLEAR_CMF: Character Match Clear Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))\r
+\r
+/** @brief Clear the UART PE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)\r
+\r
+/** @brief Clear the UART FE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)\r
+\r
+/** @brief Clear the UART NE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)\r
+\r
+/** @brief Clear the UART ORE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)\r
+\r
+/** @brief Clear the UART IDLE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)\r
+\r
+/** @brief Checks whether the specified UART flag is set or not.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_FLAG_REACK: Receive enable acknowledge flag\r
+ * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag\r
+ * @arg UART_FLAG_WUF: Wake up from stop mode flag\r
+ * @arg UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode)\r
+ * @arg UART_FLAG_SBKF: Send Break flag\r
+ * @arg UART_FLAG_CMF: Character match flag\r
+ * @arg UART_FLAG_BUSY: Busy flag\r
+ * @arg UART_FLAG_ABRF: Auto Baud rate detection flag\r
+ * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag\r
+ * @arg UART_FLAG_EOBF: End of block flag\r
+ * @arg UART_FLAG_RTOF: Receiver timeout flag\r
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r
+ * @arg UART_FLAG_LBD: LIN Break detection flag\r
+ * @arg UART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg UART_FLAG_TC: Transmission Complete flag\r
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg UART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg UART_FLAG_ORE: OverRun Error flag\r
+ * @arg UART_FLAG_NE: Noise Error flag\r
+ * @arg UART_FLAG_FE: Framing Error flag\r
+ * @arg UART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Enables the specified UART interrupt.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __INTERRUPT__: specifies the UART interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt\r
+ * @arg UART_IT_CM: Character match interrupt\r
+ * @arg UART_IT_CTS: CTS change interrupt\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+\r
+/** @brief Disables the specified UART interrupt.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __INTERRUPT__: specifies the UART interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CM: Character match interrupt\r
+ * @arg UART_IT_CTS: CTS change interrupt\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+/** @brief Checks whether the specified UART interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __IT__: specifies the UART interrupt to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CM: Character match interrupt\r
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_ORE: OverRun Error interrupt\r
+ * @arg UART_IT_NE: Noise Error interrupt\r
+ * @arg UART_IT_FE: Framing Error interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))\r
+\r
+/** @brief Checks whether the specified UART interrupt source is enabled.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __IT__: specifies the UART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_ORE: OverRun Error interrupt\r
+ * @arg UART_IT_NE: Noise Error interrupt\r
+ * @arg UART_IT_FE: Framing Error interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \\r
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))\r
+\r
+/** @brief Set a specific UART request flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __REQ__: specifies the request flag to set\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request\r
+ * @arg UART_SENDBREAK_REQUEST: Send Break Request\r
+ * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request\r
+ * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request\r
+ * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))\r
+\r
+/** @brief Enables the UART one bit sample method\r
+ * @param __HANDLE__: specifies the UART Handle. \r
+ * @retval None\r
+ */ \r
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r
+\r
+/** @brief Disables the UART one bit sample method\r
+ * @param __HANDLE__: specifies the UART Handle. \r
+ * @retval None\r
+ */ \r
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))\r
+\r
+/** @brief Enable UART\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable UART\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/** @brief Enable CTS flow control \r
+ * This macro allows to enable CTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \\r
+ } while(0)\r
+\r
+/** @brief Disable CTS flow control \r
+ * This macro allows to disable CTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \\r
+ } while(0)\r
+\r
+/** @brief Enable RTS flow control \r
+ * This macro allows to enable RTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \\r
+ } while(0)\r
+\r
+/** @brief Disable RTS flow control \r
+ * This macro allows to disable RTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \\r
+ } while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup UART_Private_Macros UART Private Macros\r
+ * @{\r
+ */\r
+/** @brief BRR division operation to set BRR register with LPUART\r
+ * @param _PCLK_: LPUART clock\r
+ * @param _BAUD_: Baud rate set by the user\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))\r
+\r
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode\r
+ * @param _PCLK_: UART clock\r
+ * @param _BAUD_: Baud rate set by the user\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))\r
+\r
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode\r
+ * @param _PCLK_: UART clock\r
+ * @param _BAUD_: Baud rate set by the user\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))\r
+\r
+/** @brief Check UART Baud rate\r
+ * @param BAUDRATE: Baudrate specified by the user\r
+ * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)\r
+ * divided by the smallest oversampling used on the USART (i.e. 8)\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)\r
+\r
+/** @brief Check UART assertion time\r
+ * @param TIME: 5-bit value assertion time\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)\r
+\r
+/** @brief Check UART deassertion time\r
+ * @param TIME: 5-bit value deassertion time\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)\r
+\r
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \\r
+ ((STOPBITS) == UART_STOPBITS_2))\r
+\r
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \\r
+ ((PARITY) == UART_PARITY_EVEN) || \\r
+ ((PARITY) == UART_PARITY_ODD))\r
+\r
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == UART_HWCONTROL_NONE) || \\r
+ ((CONTROL) == UART_HWCONTROL_RTS) || \\r
+ ((CONTROL) == UART_HWCONTROL_CTS) || \\r
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))\r
+\r
+#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))\r
+\r
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \\r
+ ((STATE) == UART_STATE_ENABLE))\r
+\r
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \\r
+ ((SAMPLING) == UART_OVERSAMPLING_8))\r
+\r
+#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \\r
+ ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \\r
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \\r
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \\r
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))\r
+\r
+#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \\r
+ ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))\r
+\r
+#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \\r
+ ((LIN) == UART_LIN_ENABLE))\r
+\r
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \\r
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))\r
+\r
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \\r
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))\r
+\r
+#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \\r
+ ((DMATX) == UART_DMA_TX_ENABLE))\r
+\r
+#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \\r
+ ((DMARX) == UART_DMA_RX_ENABLE))\r
+\r
+#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \\r
+ ((HDSEL) == UART_HALF_DUPLEX_ENABLE))\r
+\r
+#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \\r
+ ((PARAM) == UART_SENDBREAK_REQUEST) || \\r
+ ((PARAM) == UART_MUTE_MODE_REQUEST) || \\r
+ ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \\r
+ ((PARAM) == UART_TXDATA_FLUSH_REQUEST))\r
+\r
+#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \\r
+ UART_ADVFEATURE_TXINVERT_INIT | \\r
+ UART_ADVFEATURE_RXINVERT_INIT | \\r
+ UART_ADVFEATURE_DATAINVERT_INIT | \\r
+ UART_ADVFEATURE_SWAP_INIT | \\r
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\r
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \\r
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \\r
+ UART_ADVFEATURE_MSBFIRST_INIT))\r
+\r
+#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \\r
+ ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \\r
+ ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \\r
+ ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \\r
+ ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))\r
+\r
+#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \\r
+ ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))\r
+\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \\r
+ ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \\r
+ ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))\r
+\r
+#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \\r
+ ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))\r
+\r
+#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \\r
+ ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))\r
+\r
+#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \\r
+ ((POLARITY) == UART_DE_POLARITY_LOW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Include UART HAL Extension module */\r
+#include "stm32f7xx_hal_uart_ex.h"\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup UART_Exported_Functions UART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);\r
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);\r
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r
+\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral State and Errors functions **************************************************/\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions -----------------------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions UART Private Functions\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_UART_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_uart_ex.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Header file of UART HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_UART_EX_H\r
+#define __STM32F7xx_HAL_UART_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UARTEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup UARTEx_Word_Length UARTEx Word Length\r
+ * @{\r
+ */\r
+#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)\r
+#define UART_WORDLENGTH_8B ((uint32_t)0x0000U)\r
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)\r
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \\r
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \\r
+ ((__LENGTH__) == UART_WORDLENGTH_9B))\r
+#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length\r
+ * @{\r
+ */\r
+#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U)\r
+#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)\r
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \\r
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reports the UART clock source.\r
+ * @param __HANDLE__: specifies the UART Handle\r
+ * @param __CLOCKSOURCE__: output variable \r
+ * @retval UART clocking source, written in __CLOCKSOURCE__.\r
+ */\r
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\r
+ do { \\r
+ if((__HANDLE__)->Instance == USART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \\r
+ { \\r
+ case RCC_USART1CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART2) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \\r
+ { \\r
+ case RCC_USART2CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART3) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \\r
+ { \\r
+ case RCC_USART3CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == UART4) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \\r
+ { \\r
+ case RCC_UART4CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Instance == UART5) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \\r
+ { \\r
+ case RCC_UART5CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART6) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \\r
+ { \\r
+ case RCC_USART6CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Instance == UART7) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART7_SOURCE()) \\r
+ { \\r
+ case RCC_UART7CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Instance == UART8) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART8_SOURCE()) \\r
+ { \\r
+ case RCC_UART8CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/** @brief Reports the UART mask to apply to retrieve the received data\r
+ * according to the word length and to the parity bits activation.\r
+ * If PCE = 1, the parity bit is not included in the data extracted\r
+ * by the reception API().\r
+ * This masking operation is not carried out in the case of\r
+ * DMA transfers. \r
+ * @param __HANDLE__: specifies the UART Handle\r
+ * @retval mask to apply to UART RDR register value.\r
+ */\r
+#define UART_MASK_COMPUTATION(__HANDLE__) \\r
+ do { \\r
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x01FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x003F ; \\r
+ } \\r
+ } \\r
+} while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup UARTEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_UART_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief HAL module driver.\r
+ * This is the common part of the HAL initialization\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The common HAL driver contains a set of generic and common APIs that can be\r
+ used by the PPP peripheral drivers and the user to start using the HAL. \r
+ [..]\r
+ The HAL contains two APIs' categories: \r
+ (+) Common HAL APIs\r
+ (+) Services HAL APIs\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL HAL\r
+ * @brief HAL module driver.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup HAL_Private_Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @brief STM32F7xx HAL Driver version number V1.1.0\r
+ */\r
+#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */\r
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\\r
+ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\\r
+ |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\\r
+ |(__STM32F7xx_HAL_VERSION_RC))\r
+ \r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup HAL_Private_Variables\r
+ * @{\r
+ */\r
+__IO uint32_t uwTick;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Functions HAL Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions \r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initializes the Flash interface the NVIC allocation and initial clock \r
+ configuration. It initializes the systick also when timeout is needed \r
+ and the backup domain when enabled.\r
+ (+) de-Initializes common part of the HAL\r
+ (+) Configure The time base source to have 1ms time base with a dedicated \r
+ Tick interrupt priority. \r
+ (++) Systick timer is used by default as source of time base, but user \r
+ can eventually implement his proper time base source (a general purpose \r
+ timer for example or other time source), keeping in mind that Time base \r
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and \r
+ handled in milliseconds basis.\r
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically \r
+ at the beginning of the program after reset by HAL_Init() or at any time \r
+ when clock is configured, by HAL_RCC_ClockConfig(). \r
+ (++) Source of time base is configured to generate interrupts at regular \r
+ time intervals. Care must be taken if HAL_Delay() is called from a \r
+ peripheral ISR process, the Tick interrupt line must have higher priority \r
+ (numerically lower) than the peripheral interrupt. Otherwise the caller \r
+ ISR process will be blocked. \r
+ (++) functions affecting time base configurations are declared as __weak \r
+ to make override possible in case of other implementations in user file.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is used to initialize the HAL Library; it must be the first \r
+ * instruction to be executed in the main program (before to call any other\r
+ * HAL function), it performs the following:\r
+ * Configure the Flash prefetch, and instruction cache through ART accelerator.\r
+ * Configures the SysTick to generate an interrupt each 1 millisecond,\r
+ * which is clocked by the HSI (at this stage, the clock is not yet\r
+ * configured and thus the system is running from the internal HSI at 16 MHz).\r
+ * Set NVIC Group Priority to 4.\r
+ * Calls the HAL_MspInit() callback function defined in user file \r
+ * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization \r
+ * \r
+ * @note SysTick is used as time base for the HAL_Delay() function, the application\r
+ * need to ensure that the SysTick time base is always set to 1 millisecond\r
+ * to have correct HAL operation.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_Init(void)\r
+{\r
+ /* Configure Flash prefetch and Instruction cache through ART accelerator */ \r
+#if (ART_ACCLERATOR_ENABLE != 0)\r
+ __HAL_FLASH_ART_ENABLE();\r
+#endif /* ART_ACCLERATOR_ENABLE */\r
+\r
+ /* Set Interrupt Group Priority */\r
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
+\r
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\r
+ HAL_InitTick(TICK_INT_PRIORITY);\r
+ \r
+ /* Init the low level hardware */\r
+ HAL_MspInit();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function de-Initializes common part of the HAL and stops the systick.\r
+ * This function is optional. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DeInit(void)\r
+{\r
+ /* Reset of all peripherals */\r
+ __HAL_RCC_APB1_FORCE_RESET();\r
+ __HAL_RCC_APB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB2_FORCE_RESET();\r
+ __HAL_RCC_APB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB1_FORCE_RESET();\r
+ __HAL_RCC_AHB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB2_FORCE_RESET();\r
+ __HAL_RCC_AHB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB3_FORCE_RESET();\r
+ __HAL_RCC_AHB3_RELEASE_RESET();\r
+\r
+ /* De-Init the low level hardware */\r
+ HAL_MspDeInit();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief This function configures the source of the time base.\r
+ * The time source is configured to have 1ms time base with a dedicated \r
+ * Tick interrupt priority.\r
+ * @note This function is called automatically at the beginning of program after\r
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().\r
+ * @note In the default implementation, SysTick timer is the source of time base. \r
+ * It is used to generate interrupts at regular time intervals. \r
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process, \r
+ * The the SysTick interrupt must have higher priority (numerically lower) \r
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
+ * The function is declared as __weak to be overwritten in case of other\r
+ * implementation in user file.\r
+ * @param TickPriority: Tick interrupt priority.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+ /*Configure the SysTick to have interrupt in 1ms time basis*/\r
+ HAL_SYSTICK_Config(SystemCoreClock/1000);\r
+\r
+ /*Configure the SysTick IRQ priority */\r
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions \r
+ * @brief HAL Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### HAL Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Provide a tick value in millisecond\r
+ (+) Provide a blocking delay in millisecond\r
+ (+) Suspend the time base source interrupt\r
+ (+) Resume the time base source interrupt\r
+ (+) Get the HAL API driver version\r
+ (+) Get the device identifier\r
+ (+) Get the device revision identifier\r
+ (+) Enable/Disable Debug module during SLEEP mode\r
+ (+) Enable/Disable Debug module during STOP mode\r
+ (+) Enable/Disable Debug module during STANDBY mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is called to increment a global variable "uwTick"\r
+ * used as application time base.\r
+ * @note In the default implementation, this variable is incremented each 1ms\r
+ * in Systick ISR.\r
+ * @note This function is declared as __weak to be overwritten in case of other \r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IncTick(void)\r
+{\r
+ uwTick++;\r
+}\r
+\r
+/**\r
+ * @brief Provides a tick value in millisecond.\r
+ * @note This function is declared as __weak to be overwritten in case of other \r
+ * implementations in user file.\r
+ * @retval tick value\r
+ */\r
+__weak uint32_t HAL_GetTick(void)\r
+{\r
+ return uwTick;\r
+}\r
+\r
+/**\r
+ * @brief This function provides accurate delay (in milliseconds) based \r
+ * on variable incremented.\r
+ * @note In the default implementation , SysTick timer is the source of time base.\r
+ * It is used to generate interrupts at regular time intervals where uwTick\r
+ * is incremented.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @param Delay: specifies the delay time length, in milliseconds.\r
+ * @retval None\r
+ */\r
+__weak void HAL_Delay(__IO uint32_t Delay)\r
+{\r
+ uint32_t tickstart = 0;\r
+ tickstart = HAL_GetTick();\r
+ while((HAL_GetTick() - tickstart) < Delay)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Suspend Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
+ * is called, the SysTick interrupt will be disabled and so Tick increment \r
+ * is suspended.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SuspendTick(void)\r
+{\r
+ /* Disable SysTick Interrupt */\r
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Resume Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
+ * is called, the SysTick interrupt will be enabled and so Tick increment \r
+ * is resumed.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ResumeTick(void)\r
+{\r
+ /* Enable SysTick Interrupt */\r
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HAL revision\r
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r
+ */\r
+uint32_t HAL_GetHalVersion(void)\r
+{\r
+ return __STM32F7xx_HAL_VERSION;\r
+}\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t HAL_GetREVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) >> 16U);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetDEVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGSleepMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGSleepMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGStopMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGStopMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @brief Enables the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V. \r
+ * @retval None\r
+ */\r
+void HAL_EnableCompensationCell(void)\r
+{\r
+ SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;\r
+}\r
+\r
+/**\r
+ * @brief Power-down the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V. \r
+ * @retval None\r
+ */\r
+void HAL_DisableCompensationCell(void)\r
+{\r
+ SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);\r
+}\r
+\r
+/**\r
+ * @brief Enables the FMC Memory Mapping Swapping.\r
+ * \r
+ * @note SDRAM is accessible at 0x60000000 \r
+ * and NOR/RAM is accessible at 0xC0000000 \r
+ *\r
+ * @retval None\r
+ */\r
+void HAL_EnableFMCMemorySwapping(void)\r
+{\r
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;\r
+}\r
+\r
+/**\r
+ * @brief Disables the FMC Memory Mapping Swapping\r
+ * \r
+ * @note SDRAM is accessible at 0xC0000000 (default mapping) \r
+ * and NOR/RAM is accessible at 0x60000000 (default mapping) \r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_DisableFMCMemorySwapping(void)\r
+{\r
+\r
+ SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);\r
+}\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/**\r
+* @brief Enable the Internal FLASH Bank Swapping.\r
+* \r
+* @note This function can be used only for STM32F77xx/STM32F76xx devices. \r
+*\r
+* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r
+* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) \r
+*\r
+* @retval None\r
+*/\r
+void HAL_EnableMemorySwappingBank(void)\r
+{\r
+ SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r
+}\r
+\r
+/**\r
+* @brief Disable the Internal FLASH Bank Swapping.\r
+* \r
+* @note This function can be used only for STM32F77xx/STM32F76xx devices. \r
+*\r
+* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r
+* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) \r
+* \r
+* @retval None\r
+*/\r
+void HAL_DisableMemorySwappingBank(void)\r
+{\r
+ CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r
+}\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_adc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + State and errors functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### ADC Peripheral features #####\r
+ ==============================================================================\r
+ [..] \r
+ (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.\r
+ (#) Interrupt generation at the end of conversion, end of injected conversion, \r
+ and in case of analog watchdog or overrun events\r
+ (#) Single and continuous conversion modes.\r
+ (#) Scan mode for automatic conversion of channel 0 to channel x.\r
+ (#) Data alignment with in-built data coherency.\r
+ (#) Channel-wise programmable sampling time.\r
+ (#) External trigger option with configurable polarity for both regular and \r
+ injected conversion.\r
+ (#) Dual/Triple mode (on devices with 2 ADCs or more).\r
+ (#) Configurable DMA data storage in Dual/Triple ADC mode. \r
+ (#) Configurable delay between conversions in Dual/Triple interleaved mode.\r
+ (#) ADC conversion type (refer to the datasheets).\r
+ (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at \r
+ slower speed.\r
+ (#) ADC input range: VREF(minus) = VIN = VREF(plus).\r
+ (#) DMA request generation during regular channel conversion.\r
+\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r
+ (##) ADC pins configuration\r
+ (+++) Enable the clock for the ADC GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE() \r
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r
+ (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r
+ (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream.\r
+ \r
+ *** Configuration of ADC, groups regular/injected, channels parameters ***\r
+ ==============================================================================\r
+ [..]\r
+ (#) Configure the ADC parameters (resolution, data alignment, ...)\r
+ and regular group parameters (conversion trigger, sequencer, ...)\r
+ using function HAL_ADC_Init().\r
+\r
+ (#) Configure the channels for regular group parameters (channel number, \r
+ channel rank into sequencer, ..., into regular group)\r
+ using function HAL_ADC_ConfigChannel().\r
+\r
+ (#) Optionally, configure the injected group parameters (conversion trigger, \r
+ sequencer, ..., of injected group)\r
+ and the channels for injected group parameters (channel number, \r
+ channel rank into sequencer, ..., into injected group)\r
+ using function HAL_ADCEx_InjectedConfigChannel().\r
+\r
+ (#) Optionally, configure the analog watchdog parameters (channels\r
+ monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().\r
+\r
+ (#) Optionally, for devices with several ADC instances: configure the \r
+ multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().\r
+\r
+ *** Execution of ADC conversions ***\r
+ ==============================================================================\r
+ [..] \r
+ (#) ADC driver can be used among three modes: polling, interruption,\r
+ transfer by DMA. \r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADC_Start() \r
+ (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\r
+ user can specify the value of timeout according to his end application \r
+ (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.\r
+ (+) Stop the ADC peripheral using HAL_ADC_Stop()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADC_Start_IT() \r
+ (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r
+ (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r
+ (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() \r
+\r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r
+ (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()\r
+ \r
+ *** ADC HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in ADC HAL driver.\r
+ \r
+ (+) __HAL_ADC_ENABLE : Enable the ADC peripheral\r
+ (+) __HAL_ADC_DISABLE : Disable the ADC peripheral\r
+ (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt\r
+ (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt\r
+ (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled\r
+ (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags\r
+ (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status\r
+ (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register \r
+ \r
+ [..] \r
+ (@) You can refer to the ADC HAL driver header file for more useful macros \r
+\r
+ *** Deinitialization of ADC ***\r
+ ==============================================================================\r
+ [..]\r
+ (#) Disable the ADC interface\r
+ (++) ADC clock can be hard reset and disabled at RCC top level.\r
+ (++) Hard reset of ADC peripherals\r
+ using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().\r
+ (++) ADC clock disable using the equivalent macro/functions as configuration step.\r
+ (+++) Example:\r
+ Into HAL_ADC_MspDeInit() (recommended code location) or with\r
+ other device clock parameters configuration:\r
+ (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);\r
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;\r
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)\r
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);\r
+\r
+ (#) ADC pins configuration\r
+ (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()\r
+\r
+ (#) Optionally, in case of usage of ADC with interruptions:\r
+ (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)\r
+\r
+ (#) Optionally, in case of usage of DMA:\r
+ (++) Deinitialize the DMA using function HAL_DMA_DeInit().\r
+ (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) \r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC ADC\r
+ * @brief ADC driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void ADC_Init(ADC_HandleTypeDef* hadc);\r
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);\r
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);\r
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup ADC_Exported_Functions ADC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the ADC. \r
+ (+) De-initialize the ADC. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters \r
+ * in the ADC_InitStruct and initializes the ADC MSP.\r
+ * \r
+ * @note This function is used to configure the global features of the ADC ( \r
+ * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,\r
+ * the rest of the configuration parameters are specific to the regular\r
+ * channels group (scan mode activation, continuous mode activation,\r
+ * External trigger source and edge, DMA continuous request after the \r
+ * last transfer and End of conversion selection).\r
+ * \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)\r
+{\r
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r
+ \r
+ /* Check ADC handle */\r
+ if(hadc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));\r
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));\r
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));\r
+ assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r
+ assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));\r
+\r
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r
+ {\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r
+ }\r
+\r
+ if(hadc->State == HAL_ADC_STATE_RESET)\r
+ {\r
+ /* Initialize ADC error code */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ \r
+ /* Allocate lock resource and initialize it */\r
+ hadc->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_ADC_MspInit(hadc);\r
+ }\r
+ \r
+ /* Configuration of ADC parameters if previous preliminary actions are */ \r
+ /* correctly completed. */\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r
+ {\r
+ /* Set ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r
+ HAL_ADC_STATE_BUSY_INTERNAL);\r
+ \r
+ /* Set ADC parameters */\r
+ ADC_Init(hadc);\r
+ \r
+ /* Set ADC error code to none */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ \r
+ /* Set the ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_BUSY_INTERNAL,\r
+ HAL_ADC_STATE_READY);\r
+ }\r
+ else\r
+ {\r
+ tmp_hal_status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hadc);\r
+\r
+ /* Return function status */\r
+ return tmp_hal_status;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values. \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)\r
+{\r
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r
+ \r
+ /* Check ADC handle */\r
+ if(hadc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ \r
+ /* Set ADC state */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);\r
+ \r
+ /* Stop potential conversion on going, on regular and injected groups */\r
+ /* Disable ADC peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Configuration of ADC parameters if previous preliminary actions are */ \r
+ /* correctly completed. */\r
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* DeInit the low level hardware */\r
+ HAL_ADC_MspDeInit(hadc);\r
+ \r
+ /* Set ADC error code to none */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ \r
+ /* Set ADC state */\r
+ hadc->State = HAL_ADC_STATE_RESET;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return tmp_hal_status;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADC MSP.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hadc);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the ADC MSP.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hadc);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion of regular channel.\r
+ (+) Stop conversion of regular channel.\r
+ (+) Start conversion of regular channel and enable interrupt.\r
+ (+) Stop conversion of regular channel and disable interrupt.\r
+ (+) Start conversion of regular channel and enable DMA transfer.\r
+ (+) Stop conversion of regular channel and disable DMA transfer.\r
+ (+) Handle ADC interrupt request. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables ADC and starts conversion of the regular channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable the ADC peripheral */\r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Start conversion if ADC is effectively enabled */\r
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ /* - Clear state bitfield related to regular group conversion results */\r
+ /* - Set state bitfield related to regular group operation */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r
+ HAL_ADC_STATE_REG_BUSY);\r
+ \r
+ /* If conversions on group regular are also triggering group injected, */\r
+ /* update ADC state. */\r
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r
+ {\r
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); \r
+ }\r
+ \r
+ /* State machine update: Check if an injected conversion is ongoing */\r
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ {\r
+ /* Reset ADC error code fields related to conversions on group regular */\r
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); \r
+ }\r
+ else\r
+ {\r
+ /* Reset ADC all error code fields */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ /* Unlock before starting ADC conversions: in case of potential */\r
+ /* interruption, to let the process to ADC IRQ Handler. */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Clear regular group conversion flag and overrun flag */\r
+ /* (To ensure of no unknown state from potential previous ADC operations) */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables ADC and stop conversion of regular channels.\r
+ * \r
+ * @note Caution: This function will stop also injected channels. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ *\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Stop potential conversion on going, on regular and injected groups */\r
+ /* Disable ADC peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Check if ADC is effectively disabled */\r
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r
+ HAL_ADC_STATE_READY);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Poll for regular conversion complete\r
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of\r
+ * conversion) are cleared by this function.\r
+ * @note This function cannot be used in a particular setup: ADC configured \r
+ * in DMA mode and polling for end of each conversion (ADC init\r
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).\r
+ * In this case, DMA resets the flag EOC and polling cannot be\r
+ * performed on each conversion. Nevertheless, polling can still \r
+ * be performed on the complete sequence.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param Timeout: Timeout value in millisecond. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Verification that ADC configuration is compliant with polling for */\r
+ /* each conversion: */\r
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */\r
+ /* several ranks and polling for end of each conversion. */\r
+ /* For code simplicity sake, this particular case is generalized to */\r
+ /* ADC configured in DMA mode and polling for end of each conversion. */\r
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&\r
+ HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )\r
+ {\r
+ /* Update ADC state machine to error */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check End of conversion flag */\r
+ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))\r
+ {\r
+ /* Check if timeout is disabled (set to infinite wait) */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update ADC state machine to timeout */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear regular group conversion flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\r
+ \r
+ /* Update ADC state machine */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r
+ \r
+ /* Determine whether any further conversion upcoming on group regular */\r
+ /* by external trigger, continuous mode or scan sequence on going. */\r
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */\r
+ /* The test of scan sequence on going is done either with scan */\r
+ /* sequence disabled or with end of conversion flag set to */\r
+ /* of end of sequence. */\r
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r
+ (hadc->Init.ContinuousConvMode == DISABLE) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||\r
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )\r
+ {\r
+ /* Set ADC state */\r
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); \r
+ \r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ { \r
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+ \r
+ /* Return ADC state */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Poll for conversion event\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param EventType: the ADC event type.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.\r
+ * @arg ADC_OVR_EVENT: ADC Overrun event.\r
+ * @param Timeout: Timeout value in millisecond. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ assert_param(IS_ADC_EVENT_TYPE(EventType));\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check selected event flag */\r
+ while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update ADC state machine to timeout */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Analog watchdog (level out of window) event */\r
+ if(EventType == ADC_AWD_EVENT)\r
+ {\r
+ /* Set ADC state */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\r
+ \r
+ /* Clear ADC analog watchdog flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\r
+ }\r
+ /* Overrun event */\r
+ else\r
+ {\r
+ /* Set ADC state */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);\r
+ /* Set ADC error code to overrun */\r
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\r
+ \r
+ /* Clear ADC overrun flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r
+ }\r
+ \r
+ /* Return ADC state */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables the interrupt and starts ADC conversion of regular channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable the ADC peripheral */\r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Start conversion if ADC is effectively enabled */\r
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ /* - Clear state bitfield related to regular group conversion results */\r
+ /* - Set state bitfield related to regular group operation */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r
+ HAL_ADC_STATE_REG_BUSY);\r
+ \r
+ /* If conversions on group regular are also triggering group injected, */\r
+ /* update ADC state. */\r
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r
+ {\r
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); \r
+ }\r
+ \r
+ /* State machine update: Check if an injected conversion is ongoing */\r
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ {\r
+ /* Reset ADC error code fields related to conversions on group regular */\r
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); \r
+ }\r
+ else\r
+ {\r
+ /* Reset ADC all error code fields */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ /* Unlock before starting ADC conversions: in case of potential */\r
+ /* interruption, to let the process to ADC IRQ Handler. */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Clear regular group conversion flag and overrun flag */\r
+ /* (To ensure of no unknown state from potential previous ADC operations) */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r
+ \r
+ /* Enable end of conversion interrupt for regular group */\r
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables the interrupt and stop ADC conversion of regular channels.\r
+ * \r
+ * @note Caution: This function will stop also injected channels. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Stop potential conversion on going, on regular and injected groups */\r
+ /* Disable ADC peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Check if ADC is effectively disabled */\r
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Disable ADC end of conversion interrupt for regular group */\r
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\r
+\r
+ /* Set ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r
+ HAL_ADC_STATE_READY);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles ADC interrupt request \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)\r
+{\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r
+ assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);\r
+ /* Check End of conversion flag for regular channels */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Update state machine on conversion status if not in error state */\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r
+ {\r
+ /* Set ADC state */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); \r
+ }\r
+ \r
+ /* Determine whether any further conversion upcoming on group regular */\r
+ /* by external trigger, continuous mode or scan sequence on going. */\r
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */\r
+ /* The test of scan sequence on going is done either with scan */\r
+ /* sequence disabled or with end of conversion flag set to */\r
+ /* of end of sequence. */\r
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r
+ (hadc->Init.ContinuousConvMode == DISABLE) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )\r
+ {\r
+ /* Disable ADC end of single conversion interrupt on group regular */\r
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */\r
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */\r
+ /* by overrun IRQ process below. */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* Set ADC state */\r
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);\r
+ \r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ {\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+ \r
+ /* Conversion complete callback */ \r
+ HAL_ADC_ConvCpltCallback(hadc);\r
+ \r
+ /* Clear regular group conversion flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\r
+ }\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); \r
+ /* Check End of conversion flag for injected channels */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Update state machine on conversion status if not in error state */\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r
+ {\r
+ /* Set ADC state */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\r
+ }\r
+\r
+ /* Determine whether any further conversion upcoming on group injected */\r
+ /* by external trigger, scan sequence on going or by automatic injected */\r
+ /* conversion from group regular (same conditions as group regular */\r
+ /* interruption disabling above). */\r
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||\r
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\r
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r
+ (hadc->Init.ContinuousConvMode == DISABLE))))\r
+ {\r
+ /* Disable ADC end of single conversion interrupt on group injected */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\r
+ \r
+ /* Set ADC state */\r
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); \r
+\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r
+ { \r
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+\r
+ /* Conversion complete callback */ \r
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);\r
+ \r
+ /* Clear injected group conversion flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));\r
+ }\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); \r
+ /* Check Analog watchdog flag */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))\r
+ {\r
+ /* Set ADC state */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\r
+ \r
+ /* Level out of window callback */ \r
+ HAL_ADC_LevelOutOfWindowCallback(hadc);\r
+ \r
+ /* Clear the ADC analog watchdog flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\r
+ }\r
+ }\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);\r
+ /* Check Overrun flag */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Note: On STM32F7, ADC overrun can be set through other parameters */\r
+ /* refer to description of parameter "EOCSelection" for more */\r
+ /* details. */\r
+ \r
+ /* Set ADC error code to overrun */\r
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\r
+ \r
+ /* Clear ADC overrun flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r
+ \r
+ /* Error callback */ \r
+ HAL_ADC_ErrorCallback(hadc);\r
+ \r
+ /* Clear the Overrun flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param pData: The destination Buffer address.\r
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable the ADC peripheral */\r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Start conversion if ADC is effectively enabled */\r
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ /* - Clear state bitfield related to regular group conversion results */\r
+ /* - Set state bitfield related to regular group operation */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r
+ HAL_ADC_STATE_REG_BUSY);\r
+ \r
+ /* If conversions on group regular are also triggering group injected, */\r
+ /* update ADC state. */\r
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r
+ {\r
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); \r
+ }\r
+ \r
+ /* State machine update: Check if an injected conversion is ongoing */\r
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ {\r
+ /* Reset ADC error code fields related to conversions on group regular */\r
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); \r
+ }\r
+ else\r
+ {\r
+ /* Reset ADC all error code fields */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ /* Unlock before starting ADC conversions: in case of potential */\r
+ /* interruption, to let the process to ADC IRQ Handler. */\r
+ __HAL_UNLOCK(hadc); \r
+\r
+ /* Set the DMA transfer complete callback */\r
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;\r
+\r
+ /* Set the DMA half transfer complete callback */\r
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;\r
+\r
+ \r
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */\r
+ /* start (in case of SW start): */\r
+ \r
+ /* Clear regular group conversion flag and overrun flag */\r
+ /* (To ensure of no unknown state from potential previous ADC operations) */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r
+\r
+ /* Enable ADC overrun interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Enable ADC DMA mode */\r
+ hadc->Instance->CR2 |= ADC_CR2_DMA;\r
+ \r
+ /* Start the DMA channel */\r
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)\r
+{\r
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Stop potential conversion on going, on regular and injected groups */\r
+ /* Disable ADC peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Check if ADC is effectively disabled */\r
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Disable the selected ADC DMA mode */\r
+ hadc->Instance->CR2 &= ~ADC_CR2_DMA;\r
+ \r
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */\r
+ /* DMA transfer is on going) */\r
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\r
+ \r
+ /* Disable ADC overrun interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Set ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r
+ HAL_ADC_STATE_READY);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return tmp_hal_status;\r
+}\r
+\r
+/**\r
+ * @brief Gets the converted value from data register of regular channel.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval Converted value\r
+ */\r
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)\r
+{ \r
+ /* Return the selected ADC converted value */ \r
+ return hadc->Instance->DR;\r
+}\r
+\r
+/**\r
+ * @brief Regular conversion complete callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hadc);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_ConvCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Regular conversion half DMA transfer callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hadc);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Analog watchdog callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hadc);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error ADC callback.\r
+ * @note In case of error due to overrun when using ADC with DMA transfer \r
+ * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):\r
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".\r
+ * - If needed, restart a new ADC conversion using function\r
+ * "HAL_ADC_Start_DMA()"\r
+ * (this function is also clearing overrun flag)\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hadc);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure regular channels. \r
+ (+) Configure injected channels.\r
+ (+) Configure multimode.\r
+ (+) Configure the analog watch dog.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param sConfig: ADC configuration structure. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)\r
+{\r
+ __IO uint32_t counter = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r
+ if (sConfig->Channel > ADC_CHANNEL_9)\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);\r
+\r
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)\r
+ {\r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);\r
+ }\r
+ else\r
+ { \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);\r
+ }\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);\r
+ \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);\r
+ }\r
+ \r
+ /* For Rank 1 to 6 */\r
+ if (sConfig->Rank < 7)\r
+ {\r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (sConfig->Rank < 13)\r
+ {\r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);\r
+ }\r
+ /* For Rank 13 to 16 */\r
+ else\r
+ {\r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);\r
+ }\r
+ \r
+ /* if ADC1 Channel_18 is selected enable VBAT Channel */\r
+ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))\r
+ {\r
+ /* Enable the VBAT channel*/\r
+ ADC->CCR |= ADC_CCR_VBATE;\r
+ }\r
+ \r
+ /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r
+ if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))\r
+ {\r
+ /* Enable the TSVREFE channel*/\r
+ ADC->CCR |= ADC_CCR_TSVREFE;\r
+\r
+ if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)\r
+ {\r
+ /* Delay for temperature sensor stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog.\r
+ * @note Analog watchdog thresholds can be modified while ADC conversion\r
+ * is on going.\r
+ * In this case, some constraints must be taken into account:\r
+ * the programmed threshold values are effective from the next\r
+ * ADC EOC (end of unitary conversion).\r
+ * Considering that registers write delay may happen due to\r
+ * bus activity, this might cause an uncertainty on the\r
+ * effective timing of the new programmed threshold values.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure \r
+ * that contains the configuration information of ADC analog watchdog.\r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)\r
+{\r
+#ifdef USE_FULL_ASSERT \r
+ uint32_t tmp = 0;\r
+#endif /* USE_FULL_ASSERT */ \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));\r
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));\r
+\r
+#ifdef USE_FULL_ASSERT \r
+ tmp = ADC_GET_RESOLUTION(hadc);\r
+ assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));\r
+ assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));\r
+#endif /* USE_FULL_ASSERT */\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ if(AnalogWDGConfig->ITMode == ENABLE)\r
+ {\r
+ /* Enable the ADC Analog watchdog interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the ADC Analog watchdog interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);\r
+ }\r
+ \r
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);\r
+ \r
+ /* Set the analog watchdog enable mode */\r
+ hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;\r
+ \r
+ /* Set the high threshold */\r
+ hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;\r
+ \r
+ /* Set the low threshold */\r
+ hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;\r
+ \r
+ /* Clear the Analog watchdog channel select bits */\r
+ hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;\r
+ \r
+ /* Set the Analog watchdog channel */\r
+ hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions\r
+ * @brief ADC Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the ADC state\r
+ (+) Check the ADC Error\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief return the ADC state\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL state\r
+ */\r
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Return ADC state */\r
+ return hadc->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the ADC error code\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval ADC Error Code\r
+ */\r
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)\r
+{\r
+ return hadc->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Functions ADC Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters \r
+ * in the ADC_InitStruct without initializing the ADC MSP. \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval None\r
+ */\r
+static void ADC_Init(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Set ADC parameters */\r
+ /* Set the ADC clock prescaler */\r
+ ADC->CCR &= ~(ADC_CCR_ADCPRE);\r
+ ADC->CCR |= hadc->Init.ClockPrescaler;\r
+ \r
+ /* Set ADC scan mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);\r
+ hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);\r
+ \r
+ /* Set ADC resolution */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_RES);\r
+ hadc->Instance->CR1 |= hadc->Init.Resolution;\r
+ \r
+ /* Set ADC data alignment */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);\r
+ hadc->Instance->CR2 |= hadc->Init.DataAlign;\r
+ \r
+ /* Enable external trigger if trigger selection is different of software */\r
+ /* start. */\r
+ /* Note: This configuration keeps the hardware feature of parameter */\r
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */\r
+ /* software start. */\r
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r
+ {\r
+ /* Select external trigger to start conversion */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;\r
+ \r
+ /* Select external trigger polarity */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the external trigger */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r
+ }\r
+ \r
+ /* Enable or disable ADC continuous conversion mode */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_CONT);\r
+ hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);\r
+ \r
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)\r
+ {\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));\r
+ \r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
+ \r
+ /* Set the number of channels to be converted in discontinuous mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);\r
+ hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);\r
+ }\r
+ \r
+ /* Set ADC number of conversion */\r
+ hadc->Instance->SQR1 &= ~(ADC_SQR1_L);\r
+ hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);\r
+ \r
+ /* Enable or disable ADC DMA continuous request */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_DDS);\r
+ hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);\r
+ \r
+ /* Enable or disable ADC end of conversion selection */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);\r
+ hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);\r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ /* Retrieve ADC handle corresponding to current DMA handle */\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Update state machine on conversion status if not in error state */\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\r
+ {\r
+ /* Update ADC state machine */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r
+ \r
+ /* Determine whether any further conversion upcoming on group regular */\r
+ /* by external trigger, continuous mode or scan sequence on going. */\r
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */\r
+ /* The test of scan sequence on going is done either with scan */\r
+ /* sequence disabled or with end of conversion flag set to */\r
+ /* of end of sequence. */\r
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r
+ (hadc->Init.ContinuousConvMode == DISABLE) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )\r
+ {\r
+ /* Disable ADC end of single conversion interrupt on group regular */\r
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */\r
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */\r
+ /* by overrun IRQ process below. */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* Set ADC state */\r
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); \r
+ \r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ {\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+ \r
+ /* Conversion complete callback */\r
+ HAL_ADC_ConvCpltCallback(hadc);\r
+ }\r
+ else\r
+ {\r
+ /* Call DMA error callback */\r
+ hadc->DMA_Handle->XferErrorCallback(hdma);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_ADC_ConvHalfCpltCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;\r
+ /* Set ADC error code to DMA error */\r
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r
+ HAL_ADC_ErrorCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_adc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the ADC extension peripheral:\r
+ * + Extended features functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r
+ (##) ADC pins configuration\r
+ (+++) Enable the clock for the ADC GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE() \r
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r
+ (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r
+ (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the ADC DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream. \r
+ (#) Configure the ADC Prescaler, conversion resolution and data alignment \r
+ using the HAL_ADC_Init() function. \r
+ \r
+ (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()\r
+ and HAL_ADC_ConfigChannel() functions.\r
+ \r
+ (#) Three operation modes are available within this driver : \r
+ \r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() \r
+ (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\r
+ user can specify the value of timeout according to his end application \r
+ (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.\r
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() \r
+ (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r
+ (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r
+ (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()\r
+ \r
+ \r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r
+ (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()\r
+ \r
+ *** Multi mode ADCs Regular channels configuration ***\r
+ ======================================================\r
+ [..] \r
+ (+) Select the Multi mode ADC regular channels features (dual or triple mode) \r
+ and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. \r
+ (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.\r
+ \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADCEx ADCEx\r
+ * @brief ADC Extended driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup ADCEx_Private_Functions\r
+ * @{\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);\r
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);\r
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup ADCEx_Exported_Functions ADC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions \r
+ * @brief Extended features functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion of injected channel.\r
+ (+) Stop conversion of injected channel.\r
+ (+) Start multimode and enable DMA transfer.\r
+ (+) Stop multimode and disable DMA transfer.\r
+ (+) Get result of injected channel conversion.\r
+ (+) Get result of multimode conversion.\r
+ (+) Configure injected channels.\r
+ (+) Configure multimode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the injected channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable the ADC peripheral */\r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Start conversion if ADC is effectively enabled */\r
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ /* - Clear state bitfield related to injected group conversion results */\r
+ /* - Set state bitfield related to injected operation */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\r
+ HAL_ADC_STATE_INJ_BUSY);\r
+ \r
+ /* Check if a regular conversion is ongoing */\r
+ /* Note: On this device, there is no ADC error code fields related to */\r
+ /* conversions on group injected only. In case of conversion on */\r
+ /* going on group regular, no error code is reset. */\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r
+ {\r
+ /* Reset ADC all error code fields */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ /* Unlock before starting ADC conversions: in case of potential */\r
+ /* interruption, to let the process to ADC IRQ Handler. */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Clear injected group conversion flag */\r
+ /* (To ensure of no unknown state from potential previous ADC operations) */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if((hadc->Instance == ADC1) && tmp1 && tmp2) \r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the interrupt and starts ADC conversion of injected channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ *\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable the ADC peripheral */\r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Start conversion if ADC is effectively enabled */\r
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ /* - Clear state bitfield related to injected group conversion results */\r
+ /* - Set state bitfield related to injected operation */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\r
+ HAL_ADC_STATE_INJ_BUSY);\r
+ \r
+ /* Check if a regular conversion is ongoing */\r
+ /* Note: On this device, there is no ADC error code fields related to */\r
+ /* conversions on group injected only. In case of conversion on */\r
+ /* going on group regular, no error code is reset. */\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r
+ {\r
+ /* Reset ADC all error code fields */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ /* Unlock before starting ADC conversions: in case of potential */\r
+ /* interruption, to let the process to ADC IRQ Handler. */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Clear injected group conversion flag */\r
+ /* (To ensure of no unknown state from potential previous ADC operations) */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r
+ \r
+ /* Enable end of conversion interrupt for injected channels */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if((hadc->Instance == ADC1) && tmp1 && tmp2) \r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if\r
+ * no regular conversion is on going.\r
+ * @note If ADC must be disabled and if conversion is on going on \r
+ * regular group, function HAL_ADC_Stop must be used to stop both\r
+ * injected and regular groups, and disable the ADC.\r
+ * @note If injected group mode auto-injection is enabled,\r
+ * function HAL_ADC_Stop must be used.\r
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.\r
+ * @param hadc: ADC handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)\r
+{\r
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Stop potential conversion and disable ADC peripheral */\r
+ /* Conditioned to: */\r
+ /* - No conversion on the other group (regular group) is intended to */\r
+ /* continue (injected and regular groups stop conversion and ADC disable */\r
+ /* are common) */\r
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */\r
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&\r
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )\r
+ {\r
+ /* Stop potential conversion on going, on regular and injected groups */\r
+ /* Disable ADC peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Check if ADC is effectively disabled */\r
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r
+ HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update ADC state machine to error */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r
+ \r
+ tmp_hal_status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return tmp_hal_status;\r
+}\r
+\r
+/**\r
+ * @brief Poll for injected conversion complete\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param Timeout: Timeout value in millisecond. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check End of conversion flag */\r
+ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hadc->State= HAL_ADC_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear injected group conversion flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);\r
+ \r
+ /* Update ADC state machine */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\r
+ \r
+ /* Determine whether any further conversion upcoming on group injected */\r
+ /* by external trigger, continuous mode or scan sequence on going. */\r
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */\r
+ /* The test of scan sequence on going is done either with scan */\r
+ /* sequence disabled or with end of conversion flag set to */\r
+ /* of end of sequence. */\r
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||\r
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\r
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )\r
+ {\r
+ /* Set ADC state */\r
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);\r
+ \r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r
+ { \r
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+ \r
+ /* Return ADC state */\r
+ return HAL_OK;\r
+} \r
+ \r
+/**\r
+ * @brief Stop conversion of injected channels, disable interruption of \r
+ * end-of-conversion. Disable ADC peripheral if no regular conversion\r
+ * is on going.\r
+ * @note If ADC must be disabled and if conversion is on going on \r
+ * regular group, function HAL_ADC_Stop must be used to stop both\r
+ * injected and regular groups, and disable the ADC.\r
+ * @note If injected group mode auto-injection is enabled,\r
+ * function HAL_ADC_Stop must be used.\r
+ * @param hadc: ADC handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Stop potential conversion and disable ADC peripheral */\r
+ /* Conditioned to: */\r
+ /* - No conversion on the other group (regular group) is intended to */\r
+ /* continue (injected and regular groups stop conversion and ADC disable */\r
+ /* are common) */\r
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ \r
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&\r
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )\r
+ {\r
+ /* Stop potential conversion on going, on regular and injected groups */\r
+ /* Disable ADC peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Check if ADC is effectively disabled */\r
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Disable ADC end of conversion interrupt for injected channels */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\r
+ \r
+ /* Set ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r
+ HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update ADC state machine to error */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r
+ \r
+ tmp_hal_status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return tmp_hal_status;\r
+}\r
+\r
+/**\r
+ * @brief Gets the converted value from data register of injected channel.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param InjectedRank: the ADC injected rank.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected\r
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected\r
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected\r
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected\r
+ * @retval None\r
+ */\r
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));\r
+ \r
+ /* Clear injected group conversion flag to have similar behaviour as */\r
+ /* regular group: reading data register also clears end of conversion flag. */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r
+ \r
+ /* Return the selected ADC converted value */ \r
+ switch(InjectedRank)\r
+ { \r
+ case ADC_INJECTED_RANK_4:\r
+ {\r
+ tmp = hadc->Instance->JDR4;\r
+ } \r
+ break;\r
+ case ADC_INJECTED_RANK_3: \r
+ { \r
+ tmp = hadc->Instance->JDR3;\r
+ } \r
+ break;\r
+ case ADC_INJECTED_RANK_2: \r
+ { \r
+ tmp = hadc->Instance->JDR2;\r
+ }\r
+ break;\r
+ case ADC_INJECTED_RANK_1:\r
+ {\r
+ tmp = hadc->Instance->JDR1;\r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ return tmp;\r
+}\r
+\r
+/**\r
+ * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral\r
+ * \r
+ * @note Caution: This function must be used only with the ADC master. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. \r
+ * @param Length: The length of data to be transferred from ADC peripheral to memory. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for temperature sensor stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Start conversion if ADC is effectively enabled */\r
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Set ADC state */\r
+ /* - Clear state bitfield related to regular group conversion results */\r
+ /* - Set state bitfield related to regular group operation */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r
+ HAL_ADC_STATE_REG_BUSY);\r
+ \r
+ /* If conversions on group regular are also triggering group injected, */\r
+ /* update ADC state. */\r
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r
+ {\r
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); \r
+ }\r
+ \r
+ /* State machine update: Check if an injected conversion is ongoing */\r
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ {\r
+ /* Reset ADC error code fields related to conversions on group regular */\r
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); \r
+ }\r
+ else\r
+ {\r
+ /* Reset ADC all error code fields */\r
+ ADC_CLEAR_ERRORCODE(hadc);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ /* Unlock before starting ADC conversions: in case of potential */\r
+ /* interruption, to let the process to ADC IRQ Handler. */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Set the DMA transfer complete callback */\r
+ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;\r
+ \r
+ /* Set the DMA half transfer complete callback */\r
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;\r
+ \r
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */\r
+ /* start (in case of SW start): */\r
+ \r
+ /* Clear regular group conversion flag and overrun flag */\r
+ /* (To ensure of no unknown state from potential previous ADC operations) */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);\r
+\r
+ /* Enable ADC overrun interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ if (hadc->Init.DMAContinuousRequests != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request after last transfer */\r
+ ADC->CCR |= ADC_CCR_DDS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC EOC rising on each regular channel conversion */\r
+ ADC->CCR &= ~ADC_CCR_DDS;\r
+ }\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);\r
+ \r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)\r
+{\r
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Stop potential conversion on going, on regular and injected groups */\r
+ /* Disable ADC peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Check if ADC is effectively disabled */\r
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r
+ {\r
+ /* Disable the selected ADC DMA mode for multimode */\r
+ ADC->CCR &= ~ADC_CCR_DDS;\r
+ \r
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */\r
+ /* DMA transfer is on going) */\r
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\r
+ \r
+ /* Disable ADC overrun interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Set ADC state */\r
+ ADC_STATE_CLR_SET(hadc->State,\r
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r
+ HAL_ADC_STATE_READY);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return tmp_hal_status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results \r
+ * data in the selected multi mode.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval The converted data value.\r
+ */\r
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Return the multi mode conversion value */\r
+ return ADC->CDR;\r
+}\r
+\r
+/**\r
+ * @brief Injected conversion complete callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hadc);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param sConfigInjected: ADC configuration structure for injected channel. \r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)\r
+{\r
+ \r
+#ifdef USE_FULL_ASSERT \r
+ uint32_t tmp = 0;\r
+#endif /* USE_FULL_ASSERT */\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));\r
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));\r
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));\r
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));\r
+\r
+#ifdef USE_FULL_ASSERT\r
+ tmp = ADC_GET_RESOLUTION(hadc);\r
+ assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+ if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)\r
+ {\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r
+ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);\r
+ \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);\r
+ \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r
+ }\r
+ \r
+ /*---------------------------- ADCx JSQR Configuration -----------------*/\r
+ hadc->Instance->JSQR &= ~(ADC_JSQR_JL);\r
+ hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);\r
+ \r
+ /* Rank configuration */\r
+ \r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r
+\r
+ /* Enable external trigger if trigger selection is different of software */\r
+ /* start. */\r
+ /* Note: This configuration keeps the hardware feature of parameter */\r
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */\r
+ /* software start. */ \r
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)\r
+ { \r
+ /* Select external trigger to start conversion */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\r
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;\r
+ \r
+ /* Select external trigger polarity */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);\r
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the external trigger */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); \r
+ }\r
+ \r
+ if (sConfigInjected->AutoInjectedConv != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ hadc->Instance->CR1 |= ADC_CR1_JAUTO;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);\r
+ }\r
+ \r
+ if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ hadc->Instance->CR1 |= ADC_CR1_JDISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);\r
+ }\r
+ \r
+ switch(sConfigInjected->InjectedRank)\r
+ {\r
+ case 1:\r
+ /* Set injected channel 1 offset */\r
+ hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);\r
+ hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ case 2:\r
+ /* Set injected channel 2 offset */\r
+ hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);\r
+ hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ case 3:\r
+ /* Set injected channel 3 offset */\r
+ hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);\r
+ hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ default:\r
+ /* Set injected channel 4 offset */\r
+ hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);\r
+ hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ }\r
+ \r
+ /* if ADC1 Channel_18 is selected enable VBAT Channel */\r
+ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))\r
+ {\r
+ /* Enable the VBAT channel*/\r
+ ADC->CCR |= ADC_CCR_VBATE;\r
+ }\r
+ \r
+ /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r
+ if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))\r
+ {\r
+ /* Enable the TSVREFE channel*/\r
+ ADC->CCR |= ADC_CCR_TSVREFE;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADC multi-mode \r
+ * @param hadc : pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains \r
+ * the configuration information for multimode.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_MODE(multimode->Mode));\r
+ assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));\r
+ assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Set ADC mode */\r
+ ADC->CCR &= ~(ADC_CCR_MULTI);\r
+ ADC->CCR |= multimode->Mode;\r
+ \r
+ /* Set the ADC DMA access mode */\r
+ ADC->CCR &= ~(ADC_CCR_DMA);\r
+ ADC->CCR |= multimode->DMAAccessMode;\r
+ \r
+ /* Set delay between two sampling phases */\r
+ ADC->CCR &= ~(ADC_CCR_DELAY);\r
+ ADC->CCR |= multimode->TwoSamplingDelay;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @brief DMA transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ /* Retrieve ADC handle corresponding to current DMA handle */\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Update state machine on conversion status if not in error state */\r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\r
+ {\r
+ /* Update ADC state machine */\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r
+ \r
+ /* Determine whether any further conversion upcoming on group regular */\r
+ /* by external trigger, continuous mode or scan sequence on going. */\r
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */\r
+ /* The test of scan sequence on going is done either with scan */\r
+ /* sequence disabled or with end of conversion flag set to */\r
+ /* of end of sequence. */\r
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r
+ (hadc->Init.ContinuousConvMode == DISABLE) &&\r
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )\r
+ {\r
+ /* Disable ADC end of single conversion interrupt on group regular */\r
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */\r
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */\r
+ /* by overrun IRQ process below. */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* Set ADC state */\r
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); \r
+ \r
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r
+ {\r
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r
+ }\r
+ }\r
+ \r
+ /* Conversion complete callback */\r
+ HAL_ADC_ConvCpltCallback(hadc);\r
+ }\r
+ else\r
+ {\r
+ /* Call DMA error callback */\r
+ hadc->DMA_Handle->XferErrorCallback(hdma);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_ADC_ConvHalfCpltCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;\r
+ /* Set ADC error code to DMA error */\r
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r
+ HAL_ADC_ErrorCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_can.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CAN HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Controller Area Network (CAN) peripheral:\r
+ * + Initialization and de-initialization functions \r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Error functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (#) Enable the CAN controller interface clock using \r
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2\r
+ and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3\r
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.\r
+ \r
+ (#) CAN pins configuration\r
+ (++) Enable the clock for the CAN GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE() \r
+ (++) Connect and configure the involved CAN pins to AF9 using the \r
+ following function HAL_GPIO_Init() \r
+ \r
+ (#) Initialize and configure the CAN using HAL_CAN_Init() function. \r
+ \r
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.\r
+\r
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.\r
+ \r
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.\r
+\r
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the CAN peripheral transmission and wait the end of this operation \r
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout\r
+ according to his end application\r
+ (+) Start the CAN peripheral reception and wait the end of this operation \r
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout\r
+ according to his end application \r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()\r
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() \r
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine\r
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback \r
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback\r
+ \r
+ *** CAN HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in CAN HAL driver.\r
+ \r
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts\r
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts\r
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled\r
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags\r
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status\r
+ \r
+ [..] \r
+ (@) You can refer to the CAN HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN CAN\r
+ * @brief CAN driver modules\r
+ * @{\r
+ */ \r
+ \r
+#ifdef HAL_CAN_MODULE_ENABLED \r
+\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup CAN_Private_Constants\r
+ * @{\r
+ */\r
+#define CAN_TIMEOUT_VALUE 10\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup CAN_Private_Functions\r
+ * @{\r
+ */\r
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);\r
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup CAN_Exported_Functions CAN Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the CAN. \r
+ (+) De-initialize the CAN. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_InitStruct.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t InitStatus = CAN_INITSTATUS_FAILED;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check CAN handle */\r
+ if(hcan == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));\r
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));\r
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));\r
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));\r
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));\r
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));\r
+ \r
+\r
+ if(hcan->State == HAL_CAN_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hcan->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_CAN_MspInit(hcan);\r
+ }\r
+ \r
+ /* Initialize the CAN state*/\r
+ hcan->State = HAL_CAN_STATE_BUSY;\r
+ \r
+ /* Exit from sleep mode */\r
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r
+\r
+ /* Request initialisation */\r
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check acknowledge */\r
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (hcan->Init.TTCM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (hcan->Init.ABOM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (hcan->Init.AWUM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (hcan->Init.NART == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (hcan->Init.RFLM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (hcan->Init.TXFP == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \\r
+ ((uint32_t)hcan->Init.SJW) | \\r
+ ((uint32_t)hcan->Init.BS1) | \\r
+ ((uint32_t)hcan->Init.BS2) | \\r
+ ((uint32_t)hcan->Init.Prescaler - 1);\r
+\r
+ /* Request leave initialisation */\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check acknowledged */\r
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CAN_INITSTATUS_SUCCESS;\r
+ }\r
+ }\r
+ \r
+ if(InitStatus == CAN_INITSTATUS_SUCCESS)\r
+ {\r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Initialize the CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Initialize the CAN state */\r
+ hcan->State = HAL_CAN_STATE_ERROR;\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the CAN reception filter according to the specified\r
+ * parameters in the CAN_FilterInitStruct.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that\r
+ * contains the filter configuration information.\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)\r
+{\r
+ uint32_t filternbrbitpos = 0;\r
+ CAN_TypeDef *can_ip;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));\r
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));\r
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));\r
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));\r
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));\r
+ \r
+ filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;\r
+#if defined (CAN3)\r
+ /* Check the CAN instance */\r
+ if(hcan->Instance == CAN3)\r
+ { \r
+ can_ip = CAN3;\r
+ }\r
+ else\r
+ {\r
+ can_ip = CAN1; \r
+ }\r
+#else\r
+ can_ip = CAN1;\r
+#endif\r
+\r
+ /* Initialisation mode for the filter */\r
+ can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;\r
+ \r
+ /* Select the start slave bank */\r
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);\r
+ can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);\r
+ \r
+ /* Filter Deactivation */\r
+ can_ip->FA1R &= ~(uint32_t)filternbrbitpos;\r
+\r
+ /* Filter Scale */\r
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ can_ip->FS1R &= ~(uint32_t)filternbrbitpos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);\r
+ }\r
+\r
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ can_ip->FS1R |= filternbrbitpos;\r
+ \r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r
+ \r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ can_ip->FM1R &= ~(uint32_t)filternbrbitpos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ can_ip->FM1R |= (uint32_t)filternbrbitpos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;\r
+ }\r
+\r
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ can_ip->FFA1R |= (uint32_t)filternbrbitpos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (sFilterConfig->FilterActivation == ENABLE)\r
+ {\r
+ can_ip->FA1R |= filternbrbitpos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the CANx peripheral registers to their default reset values. \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Check CAN handle */\r
+ if(hcan == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_CAN_MspDeInit(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN MSP.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcan);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CAN MSP.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcan);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a CAN frame message.\r
+ (+) Receive a CAN frame message.\r
+ (+) Enter CAN peripheral in sleep mode. \r
+ (+) Wake up the CAN peripheral from sleep mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)\r
+{\r
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r
+\r
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \\r
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \\r
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))\r
+ { \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Select one empty transmit mailbox */\r
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmitmailbox = CAN_TXMAILBOX_0;\r
+ }\r
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmitmailbox = CAN_TXMAILBOX_1;\r
+ }\r
+ else\r
+ {\r
+ transmitmailbox = CAN_TXMAILBOX_2;\r
+ }\r
+ \r
+ /* Set up the Id */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); \r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\r
+ hcan->pTxMsg->IDE | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ \r
+ /* Set up the DLC */\r
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r
+\r
+ /* Set up the data field */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r
+ ((uint32_t)hcan->pTxMsg->Data[0]));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r
+ ((uint32_t)hcan->pTxMsg->Data[4]));\r
+ /* Request transmission */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check End of transmission flag */\r
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_ERROR; \r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r
+ \r
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \\r
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \\r
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Select one empty transmit mailbox */\r
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmitmailbox = CAN_TXMAILBOX_0;\r
+ }\r
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmitmailbox = CAN_TXMAILBOX_1;\r
+ }\r
+ else\r
+ {\r
+ transmitmailbox = CAN_TXMAILBOX_2;\r
+ }\r
+ \r
+ /* Set up the Id */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); \r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\r
+ hcan->pTxMsg->IDE | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ \r
+ /* Set up the DLC */\r
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r
+\r
+ /* Set up the data field */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r
+ ((uint32_t)hcan->pTxMsg->Data[0]));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r
+ ((uint32_t)hcan->pTxMsg->Data[4]));\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Enable Error warning, Error passive, Bus-off,\r
+ Last error and Error Interrupts */ \r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |\r
+ CAN_IT_EPV |\r
+ CAN_IT_BOF |\r
+ CAN_IT_LEC |\r
+ CAN_IT_ERR |\r
+ CAN_IT_TME);\r
+ \r
+ /* Request transmission */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_ERROR; \r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: FIFO Number value\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check pending message */\r
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Get the Id */\r
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ \r
+ /* Release the FIFO */\r
+ if(FIFONumber == CAN_FIFO0)\r
+ {\r
+ /* Release FIFO0 */\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r
+ }\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ /* Release FIFO1 */\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: Specify the FIFO number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ \r
+ tmp = hcan->State;\r
+ if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))\r
+ {\r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+\r
+ /* Enable Error warning, Error passive, Bus-off,\r
+ Last error and Error Interrupts */ \r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |\r
+ CAN_IT_EPV |\r
+ CAN_IT_BOF |\r
+ CAN_IT_LEC |\r
+ CAN_IT_ERR);\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ if(FIFONumber == CAN_FIFO0)\r
+ {\r
+ /* Enable FIFO 0 message pending Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);\r
+ }\r
+ else\r
+ {\r
+ /* Enable FIFO 1 message pending Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);\r
+ }\r
+ \r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enters the Sleep (low power) mode.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY; \r
+ \r
+ /* Request Sleep mode */\r
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
+ \r
+ /* Sleep mode status */\r
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral\r
+ * is in the normal mode.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY; \r
+ \r
+ /* Wake up request */\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Sleep mode status */\r
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles CAN interrupt request \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;\r
+ \r
+ /* Check End of transmission flag */\r
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))\r
+ {\r
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);\r
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);\r
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);\r
+ if(tmp1 || tmp2 || tmp3) \r
+ {\r
+ /* Call transmit function */\r
+ CAN_Transmit_IT(hcan);\r
+ }\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);\r
+ /* Check End of reception flag for FIFO0 */\r
+ if((tmp1 != 0) && tmp2)\r
+ {\r
+ /* Call receive function */\r
+ CAN_Receive_IT(hcan, CAN_FIFO0);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);\r
+ /* Check End of reception flag for FIFO1 */\r
+ if((tmp1 != 0) && tmp2)\r
+ {\r
+ /* Call receive function */\r
+ CAN_Receive_IT(hcan, CAN_FIFO1);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r
+ /* Check Error Warning Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to EWG error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); \r
+ /* Check Error Passive Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to EPV error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); \r
+ /* Check Bus-Off Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to BOF error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;\r
+ }\r
+ \r
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r
+ /* Check Last error code Flag */\r
+ if((!tmp1) && tmp2 && tmp3)\r
+ {\r
+ tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;\r
+ switch(tmp1)\r
+ {\r
+ case(CAN_ESR_LEC_0):\r
+ /* Set CAN error code to STF error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;\r
+ break;\r
+ case(CAN_ESR_LEC_1):\r
+ /* Set CAN error code to FOR error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;\r
+ break;\r
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):\r
+ /* Set CAN error code to ACK error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;\r
+ break;\r
+ case(CAN_ESR_LEC_2):\r
+ /* Set CAN error code to BR error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;\r
+ break;\r
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):\r
+ /* Set CAN error code to BD error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;\r
+ break;\r
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):\r
+ /* Set CAN error code to CRC error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Clear Last error code Flag */ \r
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);\r
+ }\r
+\r
+ /* Call the Error call Back in case of Errors */\r
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)\r
+ {\r
+ /* Clear ERRI Flag */ \r
+ hcan->Instance->MSR = CAN_MSR_ERRI; \r
+ /* Set the CAN state ready to be able to start again the process */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ /* Call Error callback function */\r
+ HAL_CAN_ErrorCallback(hcan);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Transmission complete callback in non blocking mode \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcan);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Transmission complete callback in non blocking mode \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcan);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error CAN callback.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcan);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions\r
+ * @brief CAN Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Error functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to :\r
+ (+) Check the CAN state.\r
+ (+) Check CAN Errors detected during interrupt process\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the CAN state\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL state\r
+ */\r
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Return CAN state */\r
+ return hcan->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the CAN error code\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval CAN Error Code\r
+ */\r
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)\r
+{\r
+ return hcan->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Disable Transmit mailbox empty Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)\r
+ { \r
+ /* Disable Error warning, Error passive, Bus-off, Last error code\r
+ and Error Interrupts */ \r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |\r
+ CAN_IT_EPV |\r
+ CAN_IT_BOF |\r
+ CAN_IT_LEC |\r
+ CAN_IT_ERR );\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+ \r
+ /* Transmission complete callback */ \r
+ HAL_CAN_TxCpltCallback(hcan);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: Specify the FIFO number \r
+ * @retval HAL status\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r
+{\r
+ /* Get the Id */\r
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ /* Release the FIFO */\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r
+ \r
+ /* Disable FIFO 0 message pending Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r
+ \r
+ /* Disable FIFO 1 message pending Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)\r
+ { \r
+ /* Disable Error warning, Error passive, Bus-off, Last error code\r
+ and Error Interrupts */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |\r
+ CAN_IT_EPV |\r
+ CAN_IT_BOF |\r
+ CAN_IT_LEC |\r
+ CAN_IT_ERR);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Disable CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+\r
+ /* Receive complete callback */ \r
+ HAL_CAN_RxCpltCallback(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CAN_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cec.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CEC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the High Definition Multimedia Interface \r
+ * Consumer Electronics Control Peripheral (CEC).\r
+ * + Initialization and de-initialization function\r
+ * + IO operation function\r
+ * + Peripheral Control function\r
+ *\r
+ * \r
+ @verbatim \r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The CEC HAL driver can be used as follow:\r
+ \r
+ (#) Declare a CEC_HandleTypeDef handle structure.\r
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:\r
+ (##) Enable the CEC interface clock.\r
+ (##) CEC pins configuration:\r
+ (+++) Enable the clock for the CEC GPIOs.\r
+ (+++) Configure these CEC pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()\r
+ and HAL_CEC_Receive_IT() APIs):\r
+ (+++) Configure the CEC interrupt priority.\r
+ (+++) Enable the NVIC CEC IRQ handle.\r
+ (+++) The specific CEC interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit \r
+ and receive process.\r
+\r
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in\r
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical\r
+ address and Listen mode in the hcec Init structure.\r
+\r
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.\r
+\r
+ [..] \r
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customed HAL_CEC_MspInit() API.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC CEC \r
+ * @brief HAL CEC module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_CEC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup CEC_Private_Constants CEC Private Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup CEC_Private_Functions CEC Private Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CEC_Exported_Functions CEC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the CEC\r
+ (+) The following parameters need to be configured: \r
+ (++) SignalFreeTime\r
+ (++) Tolerance \r
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)\r
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)\r
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)\r
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)\r
+ (++) SignalFreeTimeOption (SFT Timer start definition)\r
+ (++) OwnAddress (CEC device address)\r
+ (++) ListenMode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CEC mode according to the specified\r
+ * parameters in the CEC_InitTypeDef and creates the associated handle .\r
+ * @param hcec: CEC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)\r
+{ \r
+ /* Check the CEC handle allocation */\r
+ if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */ \r
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));\r
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); \r
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));\r
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));\r
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));\r
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));\r
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); \r
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));\r
+ assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress)); \r
+\r
+ if(hcec->gState == HAL_CEC_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hcec->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_CEC_MspInit(hcec);\r
+ }\r
+ hcec->gState = HAL_CEC_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ /* Write to CEC Control Register */\r
+ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\\r
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\\r
+ hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\\r
+ hcec->Init.ListenMode;\r
+ \r
+ /* Enable the following CEC Transmission/Reception interrupts as\r
+ * well as the following CEC Transmission/Reception Errors interrupts \r
+ * Rx Byte Received IT \r
+ * End of Reception IT \r
+ * Rx overrun\r
+ * Rx bit rising error\r
+ * Rx short bit period error\r
+ * Rx long bit period error\r
+ * Rx missing acknowledge\r
+ * Tx Byte Request IT \r
+ * End of Transmission IT\r
+ * Tx Missing Acknowledge IT\r
+ * Tx-Error IT\r
+ * Tx-Buffer Underrun IT \r
+ * Tx arbitration lost */\r
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);\r
+ \r
+ /* Enable the CEC Peripheral */\r
+ __HAL_CEC_ENABLE(hcec);\r
+ \r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ hcec->gState = HAL_CEC_STATE_READY;\r
+ hcec->RxState = HAL_CEC_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CEC peripheral \r
+ * @param hcec: CEC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* Check the CEC handle allocation */\r
+ if(hcec == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r
+\r
+ hcec->gState = HAL_CEC_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_CEC_MspDeInit(hcec);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ /* Clear Flags */\r
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);\r
+ \r
+ /* Disable the following CEC Transmission/Reception interrupts as\r
+ * well as the following CEC Transmission/Reception Errors interrupts \r
+ * Rx Byte Received IT \r
+ * End of Reception IT \r
+ * Rx overrun\r
+ * Rx bit rising error\r
+ * Rx short bit period error\r
+ * Rx long bit period error\r
+ * Rx missing acknowledge\r
+ * Tx Byte Request IT \r
+ * End of Transmission IT\r
+ * Tx Missing Acknowledge IT\r
+ * Tx-Error IT\r
+ * Tx-Buffer Underrun IT \r
+ * Tx arbitration lost */\r
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);\r
+ \r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ hcec->gState = HAL_CEC_STATE_RESET;\r
+ hcec->RxState = HAL_CEC_STATE_RESET;\r
+ \r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the Own Address of the CEC device\r
+ * @param hcec: CEC handle\r
+ * @param CEC_OwnAddress: The CEC own address. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));\r
+\r
+ if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcec); \r
+ \r
+ hcec->gState = HAL_CEC_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)\r
+ {\r
+ hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);\r
+ }\r
+ else\r
+ {\r
+ hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);\r
+ }\r
+ \r
+ hcec->gState = HAL_CEC_STATE_READY;\r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec); \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_CEC_ENABLE(hcec);\r
+ \r
+ return HAL_OK; \r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief CEC MSP Init\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcec);\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_MspInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief CEC MSP DeInit\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcec);\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_MspDeInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions \r
+ * @brief CEC Transmit/Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions ##### \r
+ =============================================================================== \r
+ This subsection provides a set of functions allowing to manage the CEC data transfers.\r
+ \r
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)\r
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)\r
+ \r
+ (#) The communication is performed using Interrupts. \r
+ These API's return the HAL status.\r
+ The end of the data processing will be indicated through the \r
+ dedicated CEC IRQ when using Interrupt mode.\r
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks \r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_CEC_ErrorCallback() user callback will be executed when a communication \r
+ error is detected\r
+ \r
+ (#) API's with Interrupt are :\r
+ (+) HAL_CEC_Transmit_IT()\r
+ (+) HAL_CEC_IRQHandler()\r
+\r
+ (#) A set of User Callbacks are provided:\r
+ (+) HAL_CEC_TxCpltCallback()\r
+ (+) HAL_CEC_RxCpltCallback()\r
+ (+) HAL_CEC_ErrorCallback()\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Send data in interrupt mode \r
+ * @param hcec: CEC handle \r
+ * @param InitiatorAddress: Initiator address\r
+ * @param DestinationAddress: destination logical address \r
+ * @param pData: pointer to input byte data buffer\r
+ * @param Size: amount of data to be sent in bytes (without counting the header).\r
+ * 0 means only the header is sent (ping operation).\r
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)\r
+{\r
+ /* if the IP isn't already busy and if there is no previous transmission\r
+ already pending due to arbitration lost */\r
+ if (hcec->gState == HAL_CEC_STATE_READY) \r
+ { \r
+ if((pData == NULL ) && (Size > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+\r
+ assert_param(IS_CEC_ADDRESS(DestinationAddress)); \r
+ assert_param(IS_CEC_ADDRESS(InitiatorAddress)); \r
+ assert_param(IS_CEC_MSGSIZE(Size));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcec);\r
+ hcec->pTxBuffPtr = pData;\r
+ hcec->gState = HAL_CEC_STATE_BUSY_TX;\r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ \r
+ /* initialize the number of bytes to send,\r
+ * 0 means only one header is sent (ping operation) */\r
+ hcec->TxXferCount = Size;\r
+ \r
+ /* in case of no payload (Size = 0), sender is only pinging the system;\r
+ Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */\r
+ if (Size == 0)\r
+ {\r
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r
+ }\r
+ /* send header block */\r
+ hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);\r
+ /* Set TX Start of Message (TXSOM) bit */\r
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec); \r
+ \r
+ return HAL_OK;\r
+\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get size of the received frame.\r
+ * @param hcec: CEC handle\r
+ * @retval Frame size\r
+ */\r
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)\r
+{\r
+ return hcec->RxXferSize;\r
+}\r
+\r
+/**\r
+ * @brief Change Rx Buffer.\r
+ * @param hcec: CEC handle\r
+ * @param Rxbuffer: Rx Buffer\r
+ * @note This function can be called only inside the HAL_CEC_RxCpltCallback() \r
+ * @retval Frame size\r
+ */\r
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)\r
+{\r
+ hcec->Init.RxBuffer = Rxbuffer; \r
+}\r
+ \r
+/**\r
+ * @brief This function handles CEC interrupt requests.\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)\r
+{\r
+ \r
+ /* save interrupts register for further error or interrupts handling purposes */\r
+ uint32_t reg = 0;\r
+ reg = hcec->Instance->ISR;\r
+\r
+ \r
+ /* ----------------------------Arbitration Lost Management----------------------------------*/ \r
+ /* CEC TX arbitration error interrupt occurred --------------------------------------*/\r
+ if((reg & CEC_FLAG_ARBLST) != RESET) \r
+ { \r
+ hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;\r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);\r
+ }\r
+ \r
+ /* ----------------------------Rx Management----------------------------------*/ \r
+ /* CEC RX byte received interrupt ---------------------------------------------------*/\r
+ if((reg & CEC_FLAG_RXBR) != RESET) \r
+ { \r
+ /* reception is starting */ \r
+ hcec->RxState = HAL_CEC_STATE_BUSY_RX;\r
+ hcec->RxXferSize++;\r
+ /* read received byte */\r
+ *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;\r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); \r
+ }\r
+ \r
+ /* CEC RX end received interrupt ---------------------------------------------------*/\r
+ if((reg & CEC_FLAG_RXEND) != RESET) \r
+ { \r
+ /* clear IT */\r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);\r
+ \r
+ /* Rx process is completed, restore hcec->RxState to Ready */\r
+ hcec->RxState = HAL_CEC_STATE_READY; \r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ hcec->Init.RxBuffer-=hcec->RxXferSize;\r
+ HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); \r
+ hcec->RxXferSize = 0; \r
+ }\r
+ \r
+ /* ----------------------------Tx Management----------------------------------*/ \r
+ /* CEC TX byte request interrupt ------------------------------------------------*/\r
+ if((reg & CEC_FLAG_TXBR) != RESET) \r
+ {\r
+ if (hcec->TxXferCount == 0)\r
+ {\r
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */\r
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r
+ }\r
+ else\r
+ { \r
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r
+ hcec->TxXferCount--;\r
+ } \r
+ /* clear Tx-Byte request flag */\r
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); \r
+ } \r
+ \r
+ /* CEC TX end interrupt ------------------------------------------------*/\r
+ if((reg & CEC_FLAG_TXEND) != RESET) \r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);\r
+ \r
+ /* Tx process is ended, restore hcec->gState to Ready */ \r
+ hcec->gState = HAL_CEC_STATE_READY;\r
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to\r
+ start again the Transmission under the Tx call back API */\r
+ __HAL_UNLOCK(hcec);\r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ HAL_CEC_TxCpltCallback(hcec);\r
+ } \r
+ \r
+ /* ----------------------------Rx/Tx Error Management----------------------------------*/ \r
+ if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)\r
+ {\r
+ hcec->ErrorCode = reg;\r
+ __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);\r
+\r
+ \r
+ if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)\r
+ {\r
+ hcec->Init.RxBuffer-=hcec->RxXferSize; \r
+ hcec->RxXferSize = 0; \r
+ hcec->RxState = HAL_CEC_STATE_READY;\r
+ }\r
+ else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))\r
+ { \r
+ /* Set the CEC state ready to be able to start again the process */\r
+ hcec->gState = HAL_CEC_STATE_READY;\r
+ } \r
+ \r
+ /* Error Call Back */ \r
+ HAL_CEC_ErrorCallback(hcec);\r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callback\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcec); \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_TxCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callback\r
+ * @param hcec: CEC handle\r
+ * @param RxFrameSize: Size of frame\r
+ * @retval None\r
+ */\r
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcec);\r
+ UNUSED(RxFrameSize);\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_RxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief CEC error callbacks\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcec);\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_ErrorCallback can be implemented in the user file\r
+ */ \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function \r
+ * @brief CEC control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control function #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the CEC.\r
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. \r
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief return the CEC state\r
+ * @param hcec: pointer to a CEC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CEC module.\r
+ * @retval HAL state\r
+ */\r
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)\r
+{\r
+ uint32_t temp1= 0x00U, temp2 = 0x00U;\r
+ temp1 = hcec->gState;\r
+ temp2 = hcec->RxState;\r
+ \r
+ return (HAL_CEC_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+* @brief Return the CEC error code\r
+* @param hcec : pointer to a CEC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CEC.\r
+* @retval CEC Error Code\r
+*/\r
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)\r
+{\r
+ return hcec->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+#endif /* HAL_CEC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cortex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CORTEX HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the CORTEX:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+\r
+ [..] \r
+ *** How to configure Interrupts using CORTEX HAL driver ***\r
+ ===========================================================\r
+ [..] \r
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).\r
+ The Cortex-M4 exceptions are managed by CMSIS functions.\r
+ \r
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\r
+ function according to the following table.\r
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). \r
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r
+ (#) please refer to programming manual for details in how to configure priority. \r
+ \r
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. \r
+ The pending IRQ priority will be managed only by the sub priority.\r
+ \r
+ -@- IRQ priority order (sorted by highest to lowest priority):\r
+ (+@) Lowest preemption priority\r
+ (+@) Lowest sub priority\r
+ (+@) Lowest hardware priority (IRQ number)\r
+ \r
+ [..] \r
+ *** How to configure Systick using CORTEX HAL driver ***\r
+ ========================================================\r
+ [..]\r
+ Setup SysTick Timer for time base.\r
+ \r
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r
+ is a CMSIS function that:\r
+ (++) Configures the SysTick Reload register with value passed as function parameter.\r
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r
+ (++) Resets the SysTick Counter register.\r
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
+ (++) Enables the SysTick Interrupt.\r
+ (++) Starts the SysTick Counter.\r
+ \r
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r
+ inside the stm32f7xx_hal_cortex.h file.\r
+\r
+ (+) You can change the SysTick IRQ priority by calling the\r
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \r
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
+\r
+ (+) To adjust the SysTick time base, use the following formula:\r
+ \r
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)\r
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
+ (++) Reload Value should not exceed 0xFFFFFF\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX CORTEX\r
+ * @brief CORTEX HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r
+ Systick functionalities \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Sets the priority grouping field (preemption priority and subpriority)\r
+ * using the required unlock sequence.\r
+ * @param PriorityGroup: The priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. \r
+ * The pending IRQ priority will be managed only by the subpriority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
+ NVIC_SetPriorityGrouping(PriorityGroup);\r
+}\r
+\r
+/**\r
+ * @brief Sets the priority of an interrupt.\r
+ * @param IRQn: External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @param PreemptPriority: The preemption priority for the IRQn channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority \r
+ * @param SubPriority: the subpriority level for the IRQ channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{ \r
+ uint32_t prioritygroup = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
+ \r
+ prioritygroup = NVIC_GetPriorityGrouping();\r
+ \r
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
+}\r
+\r
+/**\r
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Enable interrupt */\r
+ NVIC_EnableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Disable interrupt */\r
+ NVIC_DisableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Initiates a system reset request to reset the MCU.\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SystemReset(void)\r
+{\r
+ /* System Reset */\r
+ NVIC_SystemReset();\r
+}\r
+\r
+/**\r
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ * Counter is in free running mode to generate periodic interrupts.\r
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.\r
+ * @retval status: - 0 Function succeeded.\r
+ * - 1 Function failed.\r
+ */\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
+{\r
+ return SysTick_Config(TicksNumb);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Cortex control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the CORTEX\r
+ (NVIC, SYSTICK, MPU) functionalities. \r
+ \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+ * @brief Initializes and configures the Region and the memory to be protected.\r
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains\r
+ * the initialization and configuration information.\r
+ * @retval None\r
+ */\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
+\r
+ /* Set the Region number */\r
+ MPU->RNR = MPU_Init->Number;\r
+\r
+ if ((MPU_Init->Enable) != RESET)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
+ \r
+ MPU->RBAR = MPU_Init->BaseAddress;\r
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |\r
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |\r
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |\r
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |\r
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |\r
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |\r
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |\r
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |\r
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);\r
+ }\r
+ else\r
+ {\r
+ MPU->RBAR = 0x00;\r
+ MPU->RASR = 0x00;\r
+ }\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.\r
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
+ */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
+{\r
+ /* Get the PRIGROUP[10:8] field value */\r
+ return NVIC_GetPriorityGrouping();\r
+}\r
+\r
+/**\r
+ * @brief Gets the priority of an interrupt.\r
+ * @param IRQn: External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @param PriorityGroup: the priority grouping bits length.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).\r
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ /* Get priority for Cortex-M system or device specific interrupts */\r
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
+}\r
+\r
+/**\r
+ * @brief Sets Pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Set interrupt pending */\r
+ NVIC_SetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC \r
+ * and returns the pending bit for the specified interrupt).\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Return 1 if pending else 0 */\r
+ return NVIC_GetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Clears the pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Clear pending interrupt */\r
+ NVIC_ClearPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Return 1 if active else 0 */\r
+ return NVIC_GetActive(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
+ {\r
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SYSTICK interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_IRQHandler(void)\r
+{\r
+ HAL_SYSTICK_Callback();\r
+}\r
+\r
+/**\r
+ * @brief SYSTICK callback.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SYSTICK_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SYSTICK_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_crc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CRC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### CRC How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+\r
+ (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();\r
+\r
+ (#) Initialize CRC calculator\r
+ (++) specify generating polynomial (IP default or non-default one)\r
+ (++) specify initialization value (IP default or non-default one)\r
+ (++) specify input data format\r
+ (++) specify input or output data inversion mode if any\r
+\r
+ (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the \r
+ input data buffer starting with the previously computed CRC as \r
+ initialization value\r
+\r
+ (#) Use HAL_CRC_Calculate() function to compute the CRC value of the \r
+ input data buffer starting with the defined initialization value \r
+ (default or non-default) to initiate CRC calculation\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC CRC\r
+ * @brief CRC HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);\r
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Functions CRC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the CRC according to the specified parameters \r
+ in the CRC_InitTypeDef and create the associated handle\r
+ (+) DeInitialize the CRC peripheral\r
+ (+) Initialize the CRC MSP\r
+ (+) DeInitialize CRC MSP \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the CRC according to the specified\r
+ * parameters in the CRC_InitTypeDef and create the associated handle.\r
+ * @param hcrc: CRC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* Check the CRC handle allocation */\r
+ if(hcrc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r
+\r
+ if(hcrc->State == HAL_CRC_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hcrc->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_CRC_MspInit(hcrc);\r
+ }\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ /* check whether or not non-default generating polynomial has been \r
+ * picked up by user */\r
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); \r
+ if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)\r
+ {\r
+ /* initialize IP with default generating polynomial */\r
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); \r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);\r
+ }\r
+ else\r
+ {\r
+ /* initialize CRC IP with generating polynomial defined by user */\r
+ if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* check whether or not non-default CRC initial value has been \r
+ * picked up by user */\r
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));\r
+ if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)\r
+ {\r
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); \r
+ }\r
+ else\r
+ {\r
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);\r
+ }\r
+ \r
+\r
+ /* set input data inversion mode */\r
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); \r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); \r
+ \r
+ /* set output data inversion mode */\r
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); \r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); \r
+ \r
+ /* makes sure the input data format (bytes, halfwords or words stream)\r
+ * is properly specified by user */\r
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));\r
+\r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the CRC peripheral.\r
+ * @param hcrc: CRC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* Check the CRC handle allocation */\r
+ if(hcrc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r
+ \r
+ /* Check the CRC peripheral state */\r
+ if(hcrc->State == HAL_CRC_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ /* Reset CRC calculation unit */\r
+ __HAL_CRC_DR_RESET(hcrc);\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_CRC_MspDeInit(hcrc);\r
+\r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_RESET;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcrc);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the CRC MSP.\r
+ * @param hcrc: CRC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcrc);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CRC_MspInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the CRC MSP.\r
+ * @param hcrc: CRC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcrc);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CRC_MspDeInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Group2 Peripheral Control functions \r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ using combination of the previous CRC value and the new one.\r
+ \r
+ or\r
+ \r
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ independently of the previous CRC value.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ * starting with the previously computed CRC as initialization value.\r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer, exact input data format is\r
+ * provided by hcrc->InputDataFormat. \r
+ * @param BufferLength: input data buffer length (number of bytes if pBuffer\r
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,\r
+ * number of words if pBuffer type is * uint32_t).\r
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.\r
+ * Input buffer pointers with other types simply need to be cast in uint32_t\r
+ * and the API will internally adjust its input data processing based on the \r
+ * handle field hcrc->InputDataFormat. \r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */\r
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0; /* CRC input data buffer index */\r
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcrc); \r
+ \r
+ /* Change CRC peripheral state */ \r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ switch (hcrc->InputDataFormat)\r
+ {\r
+ case CRC_INPUTDATA_FORMAT_WORDS: \r
+ /* Enter Data to the CRC calculator */\r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ hcrc->Instance->DR = pBuffer[index];\r
+ }\r
+ temp = hcrc->Instance->DR;\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_BYTES: \r
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_HALFWORDS: \r
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Change CRC peripheral state */ \r
+ hcrc->State = HAL_CRC_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcrc);\r
+ \r
+ /* Return the CRC computed value */ \r
+ return temp;\r
+}\r
+\r
+/** \r
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ * starting with hcrc->Instance->INIT as initialization value.\r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer, exact input data format is\r
+ * provided by hcrc->InputDataFormat. \r
+ * @param BufferLength: input data buffer length (number of bytes if pBuffer\r
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,\r
+ * number of words if pBuffer type is * uint32_t).\r
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.\r
+ * Input buffer pointers with other types simply need to be cast in uint32_t\r
+ * and the API will internally adjust its input data processing based on the \r
+ * handle field hcrc->InputDataFormat. \r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */ \r
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0; /* CRC input data buffer index */\r
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcrc); \r
+ \r
+ /* Change CRC peripheral state */ \r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is \r
+ * written in hcrc->Instance->DR) */\r
+ __HAL_CRC_DR_RESET(hcrc);\r
+ \r
+ switch (hcrc->InputDataFormat)\r
+ {\r
+ case CRC_INPUTDATA_FORMAT_WORDS: \r
+ /* Enter 32-bit input data to the CRC calculator */\r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ hcrc->Instance->DR = pBuffer[index];\r
+ }\r
+ temp = hcrc->Instance->DR;\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_BYTES: \r
+ /* Specific 8-bit input data handling */\r
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_HALFWORDS: \r
+ /* Specific 16-bit input data handling */\r
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcrc);\r
+ \r
+ /* Return the CRC computed value */ \r
+ return temp;\r
+}\r
+\r
+/** \r
+ * @brief Enter 8-bit input data to the CRC calculator.\r
+ * Specific data handling to optimize processing time. \r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer\r
+ * @param BufferLength: input data buffer length\r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */\r
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t i = 0; /* input data buffer index */\r
+ \r
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,\r
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type\r
+ * handling by the IP */\r
+ for(i = 0; i < (BufferLength/4); i++)\r
+ {\r
+ hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));\r
+ }\r
+ /* last bytes specific handling */\r
+ if((BufferLength%4) != 0)\r
+ {\r
+ if(BufferLength%4 == 1)\r
+ {\r
+ *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];\r
+ }\r
+ if(BufferLength%4 == 2)\r
+ {\r
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));\r
+ }\r
+ if(BufferLength%4 == 3)\r
+ {\r
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));\r
+ *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; \r
+ }\r
+ }\r
+ \r
+ /* Return the CRC computed value */ \r
+ return hcrc->Instance->DR;\r
+}\r
+\r
+/** \r
+ * @brief Enter 16-bit input data to the CRC calculator.\r
+ * Specific data handling to optimize processing time. \r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer\r
+ * @param BufferLength: input data buffer length\r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */ \r
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t i = 0; /* input data buffer index */\r
+ \r
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,\r
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure \r
+ * a correct type handling by the IP */\r
+ for(i = 0; i < (BufferLength/2); i++)\r
+ {\r
+ hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));\r
+ }\r
+ if((BufferLength%2) != 0)\r
+ {\r
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; \r
+ }\r
+ \r
+ /* Return the CRC computed value */ \r
+ return hcrc->Instance->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Group3 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the CRC state.\r
+ * @param hcrc: CRC handle\r
+ * @retval HAL state\r
+ */\r
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)\r
+{\r
+ return hcrc->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_crc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Extended CRC HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the CRC peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### CRC specific features #####\r
+ ==============================================================================\r
+ [..] \r
+ (#) Polynomial configuration.\r
+ (#) Input data reverse mode.\r
+ (#) Output data reverse mode.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRCEx\r
+ * @brief CRC Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup CRCEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRCEx_Exported_Functions_Group1\r
+ * @brief Extended CRC features functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### CRC Extended features functions #####\r
+ =============================================================================== \r
+ [..]\r
+This subsection provides function allowing to:\r
+ (+) Set CRC polynomial if different from default one.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRC polynomial if different from default one.\r
+ * @param hcrc: CRC handle\r
+ * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)\r
+ * This parameter is written in normal representation, e.g.\r
+ * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 \r
+ * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 \r
+ * @param PolyLength: CRC polynomial length \r
+ * This parameter can be one of the following values:\r
+ * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)\r
+ * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)\r
+ * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)\r
+ * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32) \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)\r
+{\r
+ uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));\r
+ \r
+ /* check polynomial definition vs polynomial size:\r
+ * polynomial length must be aligned with polynomial\r
+ * definition. HAL_ERROR is reported if Pol degree is \r
+ * larger than that indicated by PolyLength.\r
+ * Look for MSB position: msb will contain the degree of\r
+ * the second to the largest polynomial member. E.g., for\r
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */\r
+ while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))\r
+ {\r
+ }\r
+\r
+ switch (PolyLength)\r
+ {\r
+ case CRC_POLYLENGTH_7B:\r
+ if (msb >= HAL_CRC_LENGTH_7B)\r
+ { \r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ case CRC_POLYLENGTH_8B:\r
+ if (msb >= HAL_CRC_LENGTH_8B)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ case CRC_POLYLENGTH_16B:\r
+ if (msb >= HAL_CRC_LENGTH_16B)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ case CRC_POLYLENGTH_32B:\r
+ /* no polynomial definition vs. polynomial length issue possible */\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* set generating polynomial */\r
+ WRITE_REG(hcrc->Instance->POL, Pol);\r
+ \r
+ /* set generating polynomial size */\r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the Reverse Input data mode.\r
+ * @param hcrc: CRC handle\r
+ * @param InputReverseMode: Input Data inversion mode\r
+ * This parameter can be one of the following values:\r
+ * @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)\r
+ * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal\r
+ * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal\r
+ * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+\r
+ /* set input data inversion mode */\r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the Reverse Output data mode.\r
+ * @param hcrc: CRC handle\r
+ * @param OutputReverseMode: Output Data inversion mode\r
+ * This parameter can be one of the following values:\r
+ * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)\r
+ * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+\r
+ /* set output data inversion mode */\r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); \r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cryp.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief CRYP HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Cryptography (CRYP) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + AES processing functions\r
+ * + DES processing functions\r
+ * + TDES processing functions\r
+ * + DMA callback functions\r
+ * + CRYP IRQ handler management\r
+ * + Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The CRYP HAL driver can be used as follows:\r
+\r
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()\r
+ (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())\r
+ (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams one for managing data transfer from\r
+ memory to peripheral (input stream) and another stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ \r
+ (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r
+ (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r
+ (##) The encryption/decryption key. It's size depends on the algorithm\r
+ used for encryption/decryption\r
+ (##) The initialization vector (counter). It is not used ECB mode.\r
+ \r
+ (#)Three processing (encryption/decryption) functions are available:\r
+ (##) Polling mode: encryption and decryption APIs are blocking functions\r
+ i.e. they process the data and wait till the processing is finished,\r
+ e.g. HAL_CRYP_AESCBC_Encrypt()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt,\r
+ e.g. HAL_CRYP_AESCBC_Encrypt_IT()\r
+ (##) DMA mode: encryption and decryption APIs are not blocking functions\r
+ i.e. the data transfer is ensured by DMA,\r
+ e.g. HAL_CRYP_AESCBC_Encrypt_DMA()\r
+ \r
+ (#)When the processing function is called at first time after HAL_CRYP_Init()\r
+ the CRYP peripheral is initialized and processes the buffer in input.\r
+ At second call, the processing function performs an append of the already\r
+ processed buffer.\r
+ When a new data block is to be processed, call HAL_CRYP_Init() then the\r
+ processing function.\r
+ \r
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @defgroup CRYP CRYP\r
+ * @brief CRYP HAL module driver.\r
+ * @{\r
+ */\r
+\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup CRYP_Private_define\r
+ * @{\r
+ */\r
+#define CRYP_TIMEOUT_VALUE 1\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup CRYP_Private_Functions_prototypes\r
+ * @{\r
+ */ \r
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);\r
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);\r
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+/**\r
+ * @}\r
+ */ \r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup CRYP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA CRYP Input Data process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit\r
+ in the DMACR register */\r
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r
+ \r
+ /* Call input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP Output Data process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit\r
+ in the DMACR register */\r
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r
+ \r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Change the CRYP state to ready */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Call output data transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ hcryp->State= HAL_CRYP_STATE_READY;\r
+ HAL_CRYP_ErrorCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief Writes the Key in Key registers. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Key: Pointer to Key buffer\r
+ * @param KeySize: Size of Key\r
+ * @retval None\r
+ */\r
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r
+{\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ \r
+ switch(KeySize)\r
+ {\r
+ case CRYP_KEYSIZE_256B:\r
+ /* Key Initialisation */\r
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_192B:\r
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_128B: \r
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes the InitVector/InitCounter in IV registers. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param InitVector: Pointer to InitVector/InitCounter buffer\r
+ * @param IVSize: Size of the InitVector/InitCounter\r
+ * @retval None\r
+ */\r
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)\r
+{\r
+ uint32_t ivaddr = (uint32_t)InitVector;\r
+ \r
+ switch(IVSize)\r
+ {\r
+ case CRYP_KEYSIZE_128B:\r
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));\r
+ break;\r
+ /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */\r
+ case CRYP_KEYSIZE_192B:\r
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_256B:\r
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Process Data: Writes Input data in polling mode and read the output data\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16.\r
+ * @param Output: Pointer to the returned buffer\r
+ * @param Timeout: Timeout value\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ uint32_t i = 0;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ \r
+ for(i=0; (i < Ilength); i+=16)\r
+ {\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r
+ { \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Process Data: Write Input data in polling mode. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 8\r
+ * @param Output: Pointer to the returned buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ uint32_t i = 0;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ \r
+ for(i=0; (i < Ilength); i+=8)\r
+ {\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the DMA configuration and start the DMA transfer\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param inputaddr: address of the Input buffer\r
+ * @param Size: Size of the Input buffer, must be a multiple of 16.\r
+ * @param outputaddr: address of the Output buffer\r
+ * @retval None\r
+ */\r
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r
+{\r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;\r
+ \r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);\r
+\r
+ /* Enable In DMA request */\r
+ hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);\r
+ \r
+ /* Enable the DMA Out DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);\r
+ \r
+ /* Enable Out DMA request */\r
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in DES ECB mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);\r
+ \r
+ /* Set the key */\r
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in DES CBC mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);\r
+ \r
+ /* Set the key */\r
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in TDES ECB mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);\r
+ \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in TDES CBC mode\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES CBC mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);\r
+ \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ /* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CRYP_Exported_Functions\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the CRYP according to the specified parameters \r
+ in the CRYP_InitTypeDef and creates the associated handle\r
+ (+) DeInitialize the CRYP peripheral\r
+ (+) Initialize the CRYP MSP\r
+ (+) DeInitialize CRYP MSP \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP according to the specified\r
+ * parameters in the CRYP_InitTypeDef and creates the associated handle.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)\r
+{ \r
+ /* Check the CRYP handle allocation */\r
+ if(hcryp == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));\r
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hcryp->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_CRYP_MspInit(hcryp);\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set the key size and data type*/\r
+ CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);\r
+ \r
+ /* Reset CrypInCount and CrypOutCount */\r
+ hcryp->CrypInCount = 0;\r
+ hcryp->CrypOutCount = 0;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Set the default CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CRYP peripheral. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* Check the CRYP handle allocation */\r
+ if(hcryp == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set the default CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_READY;\r
+ \r
+ /* Reset CrypInCount and CrypOutCount */\r
+ hcryp->CrypInCount = 0;\r
+ hcryp->CrypOutCount = 0;\r
+ \r
+ /* Disable the CRYP Peripheral Clock */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* DeInit the low level hardware: CLOCK, NVIC.*/\r
+ HAL_CRYP_MspDeInit(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hcryp);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP MSP.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcryp);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes CRYP MSP.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcryp);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions \r
+ * @brief processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### AES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using AES-128/192/256 using chaining modes\r
+ (+) Decrypt cyphertext using AES-128/192/256 using chaining modes\r
+ [..] Three processing functions are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ { \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{ \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions \r
+ * @brief processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### DES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using DES using ECB or CBC chaining modes\r
+ (+) Decrypt cyphertext using ECB or CBC chaining modes\r
+ [..] Three processing functions are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB encryption mode */\r
+ CRYP_SetDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB decryption mode */\r
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC encryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC decryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB encryption mode */\r
+ CRYP_SetDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ \r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ \r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC encryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ \r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB decryption mode */\r
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ \r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC decryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB encryption mode */\r
+ CRYP_SetDESECBMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC encryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB decryption mode */\r
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC decryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions \r
+ * @brief processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### TDES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes\r
+ (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes\r
+ [..] Three processing functions are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB encryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB decryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Cypher Data and Get Plain Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC encryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC decryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write Cypher Data and Get Plain Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB encryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call the Output data transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC encryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ \r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB decryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC decryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB encryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC encryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB decryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC decryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions \r
+ * @brief DMA callback functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### DMA callback functions #####\r
+ ============================================================================== \r
+ [..] This section provides DMA callback functions:\r
+ (+) DMA Input data transfer complete\r
+ (+) DMA Output data transfer complete\r
+ (+) DMA error\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Input FIFO transfer completed callbacks.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcryp);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_InCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Output FIFO transfer completed callbacks.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcryp);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_OutCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief CRYP error callbacks.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hcryp);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management \r
+ * @brief CRYP IRQ handler.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### CRYP IRQ handler management #####\r
+ ============================================================================== \r
+[..] This section provides CRYP IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles CRYP interrupt request.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r
+ {\r
+ case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:\r
+ HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:\r
+ HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:\r
+ HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:\r
+ HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:\r
+ HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:\r
+ HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:\r
+ HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:\r
+ HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:\r
+ HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:\r
+ HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:\r
+ HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:\r
+ HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:\r
+ HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL); \r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:\r
+ HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL); \r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the CRYP state.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval HAL state\r
+ */\r
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ return hcryp->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cryp_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Extended CRYP HAL module driver\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of CRYP extension peripheral:\r
+ * + Extended AES processing functions \r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The CRYP Extension HAL driver can be used as follows:\r
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()\r
+ (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())\r
+ (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams one for managing data transfer from\r
+ memory to peripheral (input stream) and another stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r
+ (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r
+ (##) The encryption/decryption key. Its size depends on the algorithm\r
+ used for encryption/decryption\r
+ (##) The initialization vector (counter). It is not used ECB mode.\r
+ (#)Three processing (encryption/decryption) functions are available:\r
+ (##) Polling mode: encryption and decryption APIs are blocking functions\r
+ i.e. they process the data and wait till the processing is finished\r
+ e.g. HAL_CRYPEx_AESGCM_Encrypt()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt\r
+ e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()\r
+ (##) DMA mode: encryption and decryption APIs are not blocking functions\r
+ i.e. the data transfer is ensured by DMA\r
+ e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()\r
+ (#)When the processing function is called at first time after HAL_CRYP_Init()\r
+ the CRYP peripheral is initialized and processes the buffer in input.\r
+ At second call, the processing function performs an append of the already\r
+ processed buffer.\r
+ When a new data block is to be processed, call HAL_CRYP_Init() then the\r
+ processing function.\r
+ (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms\r
+ which provide authentication messages.\r
+ HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those\r
+ authentication messages.\r
+ Call those functions after the processing ones (polling, interrupt or DMA).\r
+ e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data\r
+ then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message \r
+ -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version. \r
+ -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length \r
+ (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).\r
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @defgroup CRYPEx CRYPEx\r
+ * @brief CRYP Extension HAL module driver.\r
+ * @{\r
+ */\r
+\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup CRYPEx_Private_define\r
+ * @{\r
+ */\r
+#define CRYPEx_TIMEOUT_VALUE 1\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup CRYPEx_Private_Functions_prototypes CRYP Private Functions Prototypes\r
+ * @{\r
+ */\r
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);\r
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);\r
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);\r
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup CRYPEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA CRYP Input Data process complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit\r
+ in the DMACR register */\r
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r
+ \r
+ /* Call input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP Output Data process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit\r
+ in the DMACR register */\r
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Call output data transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hcryp->State= HAL_CRYP_STATE_READY;\r
+ HAL_CRYP_ErrorCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief Writes the Key in Key registers. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Key: Pointer to Key buffer\r
+ * @param KeySize: Size of Key\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r
+{\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ \r
+ switch(KeySize)\r
+ {\r
+ case CRYP_KEYSIZE_256B:\r
+ /* Key Initialisation */\r
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_192B:\r
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_128B: \r
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes the InitVector/InitCounter in IV registers.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param InitVector: Pointer to InitVector/InitCounter buffer\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)\r
+{\r
+ uint32_t ivaddr = (uint32_t)InitVector;\r
+ \r
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));\r
+}\r
+\r
+/**\r
+ * @brief Process Data: Writes Input data in polling mode and read the Output data.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer.\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16\r
+ * @param Output: Pointer to the returned buffer\r
+ * @param Timeout: Timeout value \r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t i = 0;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ \r
+ for(i=0; (i < Ilength); i+=16)\r
+ {\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the Output block from the OUT FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the header phase\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer.\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16\r
+ * @param Timeout: Timeout value \r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t loopcounter = 0;\r
+ uint32_t headeraddr = (uint32_t)Input;\r
+ \r
+ /***************************** Header phase *********************************/\r
+ if(hcryp->Init.HeaderSize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Wait until the complete message has been processed */\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the DMA configuration and start the DMA transfer.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param inputaddr: Address of the Input buffer\r
+ * @param Size: Size of the Input buffer, must be a multiple of 16\r
+ * @param outputaddr: Address of the Output buffer\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r
+{\r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r
+ \r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);\r
+ \r
+ /* Enable In DMA request */\r
+ hcryp->Instance->DMACR = CRYP_DMACR_DIEN;\r
+ \r
+ /* Enable the DMA Out DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);\r
+ \r
+ /* Enable Out DMA request */\r
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions---------------------------------------------------------*/\r
+/** @addtogroup CRYPEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions \r
+ * @brief Extended processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extended AES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes\r
+ (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes\r
+ (+) Finish the processing. This function is available only for GCM and CCM\r
+ [..] Three processing methods are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode then \r
+ * encrypt pPlainData. The cypher data are available in pCypherData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *********************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFF;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFE;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 **************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter *****************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks\r
+ are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /***************************** Header phase *******************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode then \r
+ * encrypt pPlainData. The cypher data are available in pCypherData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode then\r
+ * decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the cyphertext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer \r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Computes the authentication TAG.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Size: Total length of the plain/cyphertext buffer\r
+ * @param AuthTag: Pointer to the authentication buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */\r
+ uint64_t inputlength = Size * 8; /* input length in bits */\r
+ uint32_t tagaddr = (uint32_t)AuthTag;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r
+ {\r
+ /* Change the CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r
+ \r
+ /* Disable CRYP to start the final phase */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select final phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write the number of bits in header (64 bits) followed by the number of bits\r
+ in the payload */\r
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)\r
+ {\r
+ hcryp->Instance->DR = __RBIT(headerlength >> 32);\r
+ hcryp->Instance->DR = __RBIT(headerlength);\r
+ hcryp->Instance->DR = __RBIT(inputlength >> 32);\r
+ hcryp->Instance->DR = __RBIT(inputlength);\r
+ }\r
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)\r
+ {\r
+ hcryp->Instance->DR = __REV(headerlength >> 32);\r
+ hcryp->Instance->DR = __REV(headerlength);\r
+ hcryp->Instance->DR = __REV(inputlength >> 32);\r
+ hcryp->Instance->DR = __REV(inputlength);\r
+ }\r
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)\r
+ {\r
+ hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);\r
+ hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);\r
+ hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);\r
+ hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);\r
+ }\r
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)\r
+ {\r
+ hcryp->Instance->DR = (uint32_t)(headerlength >> 32);\r
+ hcryp->Instance->DR = (uint32_t)(headerlength);\r
+ hcryp->Instance->DR = (uint32_t)(inputlength >> 32);\r
+ hcryp->Instance->DR = (uint32_t)(inputlength);\r
+ }\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the Auth TAG in the IN FIFO */\r
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r
+ tagaddr+=4;\r
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r
+ tagaddr+=4;\r
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r
+ tagaddr+=4;\r
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Computes the authentication TAG for AES CCM mode.\r
+ * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param AuthTag: Pointer to the authentication buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t tagaddr = (uint32_t)AuthTag;\r
+ uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;\r
+ uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */\r
+ uint32_t loopcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r
+ {\r
+ /* Change the CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r
+ \r
+ /* Disable CRYP to start the final phase */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select final phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Write the counter block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;\r
+ ctraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;\r
+ ctraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;\r
+ ctraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the Auth TAG in the IN FIFO */\r
+ temptag[0] = hcryp->Instance->DOUT;\r
+ temptag[1] = hcryp->Instance->DOUT;\r
+ temptag[2] = hcryp->Instance->DOUT;\r
+ temptag[3] = hcryp->Instance->DOUT;\r
+ }\r
+ \r
+ /* Copy temporary authentication TAG in user TAG buffer */\r
+ for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)\r
+ {\r
+ /* Set the authentication TAG buffer */\r
+ *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode then\r
+ * decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *********************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 **************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter *****************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /***************************** Header phase *******************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ \r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ \r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ if(Size != 0)\r
+ {\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state and phase */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ { \r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ if(Size != 0)\r
+ {\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ }\r
+ else\r
+ {\r
+ /* Change the CRYP state and phase */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the cyphertext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ if(Size != 0)\r
+ {\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state and phase */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer \r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t tickstart = 0;\r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t headersize;\r
+ uint32_t headeraddr;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ headersize = hcryp->Init.HeaderSize;\r
+ headeraddr = (uint32_t)hcryp->Init.Header;\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer.\r
+ * @param Size: Length of the cyphertext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM decryption mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE(hcryp);\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer \r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t headersize;\r
+ uint32_t headeraddr;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ headersize = hcryp->Init.HeaderSize;\r
+ headeraddr = (uint32_t)hcryp->Init.Header;\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ \r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ \r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE(hcryp);\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH(hcryp);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management \r
+ * @brief CRYPEx IRQ handler.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### CRYPEx IRQ handler management #####\r
+ ============================================================================== \r
+[..] This section provides CRYPEx IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles CRYPEx interrupt request.\r
+ * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r
+ { \r
+ case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:\r
+ HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:\r
+ HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:\r
+ HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:\r
+ HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dac.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief DAC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Errors functions \r
+ * \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### DAC Peripheral features #####\r
+ ==============================================================================\r
+ [..] \r
+ *** DAC Channels ***\r
+ ==================== \r
+ [..] \r
+ The device integrates two 12-bit Digital Analog Converters that can \r
+ be used independently or simultaneously (dual mode):\r
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output\r
+ (#) DAC channel2 with DAC_OUT2 (PA5) as output\r
+ \r
+ *** DAC Triggers ***\r
+ ====================\r
+ [..]\r
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE\r
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. \r
+ [..] \r
+ Digital to Analog conversion can be triggered by:\r
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.\r
+ The used pin (GPIOx_Pin9) must be configured in input mode.\r
+ \r
+ (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 \r
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)\r
+ \r
+ (#) Software using DAC_TRIGGER_SOFTWARE\r
+ \r
+ *** DAC Buffer mode feature ***\r
+ =============================== \r
+ [..] \r
+ Each DAC channel integrates an output buffer that can be used to \r
+ reduce the output impedance, and to drive external loads directly\r
+ without having to add an external operational amplifier.\r
+ To enable, the output buffer use \r
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;\r
+ [..] \r
+ (@) Refer to the device datasheet for more details about output \r
+ impedance value with and without output buffer.\r
+ \r
+ *** DAC wave generation feature ***\r
+ =================================== \r
+ [..] \r
+ Both DAC channels can be used to generate\r
+ (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() \r
+ (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()\r
+ \r
+ *** DAC data format ***\r
+ =======================\r
+ [..] \r
+ The DAC data format can be:\r
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R\r
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L\r
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R\r
+ \r
+ *** DAC data value to voltage correspondence *** \r
+ ================================================ \r
+ [..] \r
+ The analog output voltage on each DAC channel pin is determined\r
+ by the following equation: \r
+ DAC_OUTx = VREF+ * DOR / 4095\r
+ with DOR is the Data Output Register\r
+ VEF+ is the input voltage reference (refer to the device datasheet)\r
+ e.g. To set DAC_OUT1 to 0.7V, use\r
+ Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V\r
+ \r
+ *** DMA requests ***\r
+ =====================\r
+ [..] \r
+ A DMA1 request can be generated when an external trigger (but not\r
+ a software trigger) occurs if DMA1 requests are enabled using\r
+ HAL_DAC_Start_DMA()\r
+ [..]\r
+ DMA1 requests are mapped as following:\r
+ (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be \r
+ already configured\r
+ (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be \r
+ already configured\r
+ \r
+ -@- For Dual mode and specific signal (Triangle and noise) generation please \r
+ refer to Extension Features Driver description \r
+ \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (+) DAC APB clock must be enabled to get write access to DAC\r
+ registers using HAL_DAC_Init()\r
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.\r
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the DAC peripheral using HAL_DAC_Start() \r
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.\r
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()\r
+\r
+ \r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() \r
+ function is executed and user can add his own code by customization of function pointer \r
+ HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2\r
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can \r
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1\r
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()\r
+\r
+ \r
+ *** DAC HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DAC HAL driver.\r
+ \r
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral\r
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral\r
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags\r
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status\r
+ \r
+ [..]\r
+ (@) You can refer to the DAC HAL driver header file for more useful macros \r
+ \r
+ @endverbatim \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC DAC\r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup DAC_Private_Functions\r
+ * @{\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);\r
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);\r
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DAC_Exported_Functions DAC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DAC. \r
+ (+) De-initialize the DAC. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified parameters\r
+ * in the DAC_InitStruct.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)\r
+{ \r
+ /* Check DAC handle */\r
+ if(hdac == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));\r
+ \r
+ if(hdac->State == HAL_DAC_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hdac->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware */\r
+ HAL_DAC_MspInit(hdac);\r
+ }\r
+ \r
+ /* Initialize the DAC state*/\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Set DAC error code to none */\r
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;\r
+ \r
+ /* Initialize the DAC state*/\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Check DAC handle */\r
+ if(hdac == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));\r
+\r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_DAC_MspDeInit(hdac);\r
+\r
+ /* Set DAC error code to none */\r
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;\r
+\r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdac);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC MSP.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DAC MSP.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion.\r
+ (+) Stop conversion.\r
+ (+) Start conversion and enable DMA transfer.\r
+ (+) Stop conversion and disable DMA transfer.\r
+ (+) Get result of conversion.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables DAC and starts conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_DAC_ENABLE(hdac, Channel);\r
+ \r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN1;\r
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;\r
+ /* Check if software trigger enabled */\r
+ if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))\r
+ {\r
+ /* Enable the selected DAC software conversion */\r
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN2;\r
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; \r
+ /* Check if software trigger enabled */\r
+ if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))\r
+ {\r
+ /* Enable the selected DAC software conversion*/\r
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;\r
+ }\r
+ }\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables DAC and stop conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_DAC_DISABLE(hdac, Channel);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables DAC and starts conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @param pData: The destination peripheral Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to DAC peripheral\r
+ * @param Alignment: Specifies the data alignment for DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected\r
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected\r
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_ALIGN(Alignment));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+\r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ /* Set the DMA transfer complete callback for channel1 */\r
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;\r
+\r
+ /* Set the DMA half transfer complete callback for channel1 */\r
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;\r
+\r
+ /* Set the DMA error callback for channel1 */\r
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;\r
+\r
+ /* Enable the selected DAC channel1 DMA request */\r
+ hdac->Instance->CR |= DAC_CR_DMAEN1;\r
+ \r
+ /* Case of use of channel 1 */\r
+ switch(Alignment)\r
+ {\r
+ case DAC_ALIGN_12B_R:\r
+ /* Get DHR12R1 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;\r
+ break;\r
+ case DAC_ALIGN_12B_L:\r
+ /* Get DHR12L1 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;\r
+ break;\r
+ case DAC_ALIGN_8B_R:\r
+ /* Get DHR8R1 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the DMA transfer complete callback for channel2 */\r
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;\r
+\r
+ /* Set the DMA half transfer complete callback for channel2 */\r
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;\r
+\r
+ /* Set the DMA error callback for channel2 */\r
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;\r
+\r
+ /* Enable the selected DAC channel2 DMA request */\r
+ hdac->Instance->CR |= DAC_CR_DMAEN2;\r
+\r
+ /* Case of use of channel 2 */\r
+ switch(Alignment)\r
+ {\r
+ case DAC_ALIGN_12B_R:\r
+ /* Get DHR12R2 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;\r
+ break;\r
+ case DAC_ALIGN_12B_L:\r
+ /* Get DHR12L2 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;\r
+ break;\r
+ case DAC_ALIGN_8B_R:\r
+ /* Get DHR8R2 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Enable the DMA Stream */\r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ /* Enable the DAC DMA underrun interrupt */\r
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);\r
+ } \r
+ else\r
+ {\r
+ /* Enable the DAC DMA underrun interrupt */\r
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_DAC_ENABLE(hdac, Channel);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables DAC and stop conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Disable the selected DAC channel DMA request */\r
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_DAC_DISABLE(hdac, Channel);\r
+ \r
+ /* Disable the DMA Channel */\r
+ /* Channel1 is used */\r
+ if(Channel == DAC_CHANNEL_1)\r
+ { \r
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);\r
+ }\r
+ else /* Channel2 is used for */\r
+ { \r
+ status = HAL_DMA_Abort(hdac->DMA_Handle2); \r
+ }\r
+\r
+ /* Check if DMA Channel effectively disabled */\r
+ if(status != HAL_OK)\r
+ {\r
+ /* Update DAC state machine to error */\r
+ hdac->State = HAL_DAC_STATE_ERROR; \r
+ }\r
+ else\r
+ {\r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ return hdac->Instance->DOR1;\r
+ }\r
+ else\r
+ {\r
+ return hdac->Instance->DOR2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handles DAC interrupt request \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Check underrun channel 1 flag */\r
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))\r
+ {\r
+ /* Change DAC state to error state */\r
+ hdac->State = HAL_DAC_STATE_ERROR;\r
+ \r
+ /* Set DAC error code to channel1 DMA underrun error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;\r
+ \r
+ /* Clear the underrun flag */\r
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);\r
+ \r
+ /* Disable the selected DAC channel1 DMA request */\r
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;\r
+ \r
+ /* Error callback */ \r
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);\r
+ }\r
+ /* Check underrun channel 2 flag */\r
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))\r
+ {\r
+ /* Change DAC state to error state */\r
+ hdac->State = HAL_DAC_STATE_ERROR;\r
+ \r
+ /* Set DAC error code to channel2 DMA underrun error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;\r
+ \r
+ /* Clear the underrun flag */\r
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);\r
+ \r
+ /* Disable the selected DAC channel1 DMA request */\r
+ hdac->Instance->CR &= ~DAC_CR_DMAEN2;\r
+ \r
+ /* Error callback */ \r
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Conversion complete callback in non blocking mode for Channel1 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ConvCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error DAC callback for Channel1.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DMA underrun DAC callback for channel1.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure channels. \r
+ (+) Set the specified data holding register value for DAC channel.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the selected DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param sConfig: DAC configuration structure.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Get the DAC CR value */\r
+ tmpreg1 = hdac->Instance->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << Channel;\r
+ /* Write to DAC CR */\r
+ hdac->Instance->CR = tmpreg1;\r
+ /* Disable wave generation */\r
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected \r
+ * @param Alignment: Specifies the data alignment.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected\r
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected\r
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected\r
+ * @param Data: Data to be loaded in the selected data holding register.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_ALIGN(Alignment));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)hdac->Instance; \r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);\r
+ }\r
+ else\r
+ {\r
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);\r
+ }\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions\r
+ * @brief Peripheral State and Errors functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DAC state.\r
+ (+) Check the DAC Errors.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the DAC state\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval HAL state\r
+ */\r
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Return DAC state */\r
+ return hdac->State;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the DAC error code\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval DAC Error Code\r
+ */\r
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)\r
+{\r
+ return hdac->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief DMA conversion complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ HAL_DAC_ConvCpltCallbackCh1(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Set DAC error code to DMA error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;\r
+ \r
+ HAL_DAC_ErrorCallbackCh1(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dac_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Extended DAC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of DAC extension peripheral:\r
+ * + Extended features functions\r
+ * \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :\r
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use\r
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. \r
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.\r
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.\r
+ \r
+ @endverbatim \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DACEx DACEx\r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DACEx_Exported_Functions DAC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extended features functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion.\r
+ (+) Stop conversion.\r
+ (+) Start conversion and enable DMA transfer.\r
+ (+) Stop conversion and disable DMA transfer.\r
+ (+) Get result of conversion.\r
+ (+) Get result of dual mode conversion.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ tmp |= hdac->Instance->DOR1;\r
+ \r
+ tmp |= hdac->Instance->DOR2 << 16;\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return tmp;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected \r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @param Amplitude: Select max triangle amplitude. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1\r
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3\r
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7\r
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15\r
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31\r
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63\r
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127\r
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255\r
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511\r
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023\r
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047\r
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);\r
+\r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC. \r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected \r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. \r
+ * This parameter can be one of the following values: \r
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation\r
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation\r
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Alignment: Specifies the data alignment for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected\r
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected\r
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected\r
+ * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.\r
+ * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.\r
+ * @note In dual mode, a unique register access is required to write in both\r
+ * DAC channels at the same time.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)\r
+{ \r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(Alignment));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (Alignment == DAC_ALIGN_8B_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)hdac->Instance;\r
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Conversion complete callback in non blocking mode for Channel2 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error DAC callback for Channel2.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DMA underrun DAC callback for channel2.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdac);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DMA conversion complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ HAL_DACEx_ConvCpltCallbackCh2(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Set DAC error code to DMA error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;\r
+ \r
+ HAL_DACEx_ErrorCallbackCh2(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dcmi.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief DCMI HAL module driver\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Digital Camera Interface (DCMI) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Error functions \r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The sequence below describes how to use this driver to capture image\r
+ from a camera module connected to the DCMI Interface.\r
+ This sequence does not take into account the configuration of the\r
+ camera module, which should be made before to configure and enable\r
+ the DCMI to capture images.\r
+\r
+ (#) Program the required configuration through following parameters:\r
+ horizontal and vertical polarity, pixel clock polarity, Capture Rate,\r
+ Synchronization Mode, code of the frame delimiter and data width \r
+ using HAL_DCMI_Init() function.\r
+\r
+ (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR\r
+ register to the destination memory buffer.\r
+\r
+ (#) Program the required configuration through following parameters:\r
+ DCMI mode, destination memory Buffer address and the data length \r
+ and enable capture using HAL_DCMI_Start_DMA() function.\r
+\r
+ (#) Optionally, configure and Enable the CROP feature to select a rectangular\r
+ window from the received image using HAL_DCMI_ConfigCrop() \r
+ and HAL_DCMI_EnableCROP() functions\r
+\r
+ (#) The capture can be stopped using HAL_DCMI_Stop() function.\r
+\r
+ (#) To control DCMI state you can use the function HAL_DCMI_GetState().\r
+\r
+ *** DCMI HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DCMI HAL driver.\r
+ \r
+ (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.\r
+ (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.\r
+ (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.\r
+ (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.\r
+ (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.\r
+ (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.\r
+ (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.\r
+ \r
+ [..] \r
+ (@) You can refer to the DCMI HAL driver header file for more useful macros\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @defgroup DCMI DCMI\r
+ * @brief DCMI HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */\r
+\r
+#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */\r
+#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */\r
+\r
+#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */\r
+#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */\r
+#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);\r
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DCMI\r
+ (+) De-initialize the DCMI \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the DCMI according to the specified\r
+ * parameters in the DCMI_InitTypeDef and create the associated handle.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)\r
+{ \r
+ /* Check the DCMI peripheral state */\r
+ if(hdcmi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));\r
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));\r
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));\r
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));\r
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));\r
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));\r
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));\r
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));\r
+\r
+ assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));\r
+ assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));\r
+ assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));\r
+ assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));\r
+ \r
+ if(hdcmi->State == HAL_DCMI_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_DCMI_MspInit(hdcmi);\r
+ } \r
+ \r
+ /* Change the DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY; \r
+ /* Configures the HS, VS, DE and PC polarity */\r
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\\r
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\\r
+ DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\\r
+ DCMI_CR_LSM | DCMI_CR_OELS);\r
+\r
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\\r
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\\r
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\\r
+ hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\\r
+ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\\r
+ hdcmi->Init.LineSelectStart);\r
+ \r
+ if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)\r
+ {\r
+ hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\\r
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\\r
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\\r
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));\r
+\r
+ }\r
+\r
+ /* Enable the Line, Vsync, Error and Overrun interrupts */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;\r
+ \r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the DCMI peripheral registers to their default reset\r
+ * values.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* DeInit the low level hardware */\r
+ HAL_DCMI_MspDeInit(hdcmi);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;\r
+\r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DCMI MSP.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdcmi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DCMI MSP.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdcmi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure destination address and data length and \r
+ Enables DCMI DMA request and enables DCMI capture\r
+ (+) Stop the DCMI capture.\r
+ (+) Handles DCMI interrupt request.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables DCMI DMA request and enables DCMI capture \r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.\r
+ * @param pData: The destination memory Buffer address (LCD Frame buffer).\r
+ * @param Length: The length of capture to be transferred.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)\r
+{ \r
+ /* Initialize the second memory address */\r
+ uint32_t SecondMemAddress = 0;\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+ \r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Enable DCMI by setting DCMIEN bit */\r
+ __HAL_DCMI_ENABLE(hdcmi);\r
+ \r
+ /* Configure the DCMI Mode */\r
+ hdcmi->Instance->CR &= ~(DCMI_CR_CM);\r
+ hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);\r
+\r
+ /* Set the DMA memory0 conversion complete callback */\r
+ hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;\r
+\r
+ /* Set the dma abort callback */\r
+ hdcmi->DMA_Handle->XferAbortCallback = NULL;\r
+\r
+ /* Reset transfer counters value */ \r
+ hdcmi->XferCount = 0;\r
+ hdcmi->XferTransferNumber = 0;\r
+ \r
+ if(Length <= 0xFFFF)\r
+ {\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);\r
+ }\r
+ else /* DCMI_DOUBLE_BUFFER Mode */\r
+ {\r
+ /* Set the DMA memory1 conversion complete callback */\r
+ hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt; \r
+\r
+ /* Initialize transfer parameters */\r
+ hdcmi->XferCount = 1;\r
+ hdcmi->XferSize = Length;\r
+ hdcmi->pBuffPtr = pData;\r
+ \r
+ /* Get the number of buffer */\r
+ while(hdcmi->XferSize > 0xFFFF)\r
+ {\r
+ hdcmi->XferSize = (hdcmi->XferSize/2);\r
+ hdcmi->XferCount = hdcmi->XferCount*2;\r
+ }\r
+\r
+ /* Update DCMI counter and transfer number*/\r
+ hdcmi->XferCount = (hdcmi->XferCount - 2);\r
+ hdcmi->XferTransferNumber = hdcmi->XferCount;\r
+\r
+ /* Update second memory address */\r
+ SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));\r
+\r
+ /* Start DMA multi buffer transfer */\r
+ HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);\r
+ }\r
+ \r
+ /* Enable Capture */\r
+ hdcmi->Instance->CR |= DCMI_CR_CAPTURE;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable DCMI DMA request and Disable DCMI capture \r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI. \r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdcmi);\r
+ \r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Disable Capture */\r
+ hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);\r
+\r
+ /* Check if the DCMI capture effectively disabled */\r
+ do\r
+ {\r
+ if (count-- == 0)\r
+ {\r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;\r
+ \r
+ status = HAL_TIMEOUT;\r
+ break;\r
+ } \r
+ }\r
+ while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);\r
+\r
+ /* Disable the DCMI */\r
+ __HAL_DCMI_DISABLE(hdcmi);\r
+\r
+ /* Disable the DMA */\r
+ HAL_DMA_Abort(hdcmi->DMA_Handle);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;\r
+\r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Suspend DCMI capture \r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI. \r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ if(hdcmi->State == HAL_DCMI_STATE_BUSY)\r
+ {\r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_SUSPENDED;\r
+\r
+ /* Disable Capture */\r
+ hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);\r
+\r
+ /* Check if the DCMI capture effectively disabled */\r
+ do\r
+ {\r
+ if (count-- == 0)\r
+ { \r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;\r
+ \r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+ \r
+ status = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+ while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);\r
+ } \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+ \r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Resume DCMI capture \r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI. \r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdcmi);\r
+ \r
+ if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)\r
+ {\r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+ \r
+ /* Disable Capture */\r
+ hdcmi->Instance->CR |= DCMI_CR_CAPTURE;\r
+ } \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles DCMI interrupt request.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for the DCMI.\r
+ * @retval None\r
+ */\r
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)\r
+{ \r
+ uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);\r
+ \r
+ /* Synchronization error interrupt management *******************************/\r
+ if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)\r
+ {\r
+ /* Clear the Synchronization error flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);\r
+ \r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;\r
+ \r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_ERROR;\r
+ \r
+ /* Set the synchronization error callback */\r
+ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;\r
+ \r
+ /* Abort the DMA Transfer */\r
+ HAL_DMA_Abort_IT(hdcmi->DMA_Handle); \r
+ }\r
+ /* Overflow interrupt management ********************************************/\r
+ if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)\r
+ {\r
+ /* Clear the Overflow flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);\r
+ \r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;\r
+ \r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_ERROR;\r
+ \r
+ /* Set the overflow callback */\r
+ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;\r
+ \r
+ /* Abort the DMA Transfer */\r
+ HAL_DMA_Abort_IT(hdcmi->DMA_Handle);\r
+ }\r
+ /* Line Interrupt management ************************************************/\r
+ if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)\r
+ {\r
+ /* Clear the Line interrupt flag */ \r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);\r
+ \r
+ /* Line interrupt Callback */\r
+ HAL_DCMI_LineEventCallback(hdcmi);\r
+ }\r
+ /* VSYNC interrupt management ***********************************************/\r
+ if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)\r
+ {\r
+ /* Clear the VSYNC flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);\r
+ \r
+ /* VSYNC Callback */\r
+ HAL_DCMI_VsyncEventCallback(hdcmi);\r
+ }\r
+ /* FRAME interrupt management ***********************************************/\r
+ if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI) \r
+ {\r
+ /* When snapshot mode, disable Vsync, Error and Overrun interrupts */\r
+ if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)\r
+ { \r
+ /* Disable the Line, Vsync, Error and Overrun interrupts */\r
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);\r
+ }\r
+ \r
+ /* Disable the Frame interrupt */\r
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);\r
+ \r
+ /* Clear the End of Frame flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);\r
+ \r
+ /* Frame Callback */\r
+ HAL_DCMI_FrameEventCallback(hdcmi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Error DCMI callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdcmi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Line Event callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_LineEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief VSYNC Event callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdcmi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_VsyncEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Frame Event callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdcmi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_FrameEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+[..] This section provides functions allowing to:\r
+ (+) Configure the CROP feature.\r
+ (+) Enable/Disable the CROP feature.\r
+ (+) Set embedded synchronization delimiters unmasks.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the DCMI CROP coordinate.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @param YSize: DCMI Line number\r
+ * @param XSize: DCMI Pixel per line\r
+ * @param X0: DCMI window X offset\r
+ * @param Y0: DCMI window Y offset\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DCMI_WINDOW_COORDINATE(X0));\r
+ assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));\r
+ assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));\r
+ assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));\r
+ \r
+ /* Configure CROP */\r
+ hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));\r
+ hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));\r
+\r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the Crop feature.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Disable DCMI Crop feature */\r
+ hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP; \r
+\r
+ /* Change the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Enable the Crop feature.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Enable DCMI Crop feature */\r
+ hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;\r
+\r
+ /* Change the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DCMI state.\r
+ (+) Get the specific DCMI error flag. \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Return the DCMI state\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL state\r
+ */\r
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) \r
+{\r
+ return hdcmi->State;\r
+}\r
+\r
+/**\r
+* @brief Return the DCMI error code\r
+* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+* @retval DCMI Error Code\r
+*/\r
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ return hdcmi->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DCMI_Private_Functions DCMI Private Functions\r
+ * @{\r
+ */\r
+ /**\r
+ * @brief DMA conversion complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ if(hdcmi->XferCount != 0)\r
+ {\r
+ /* Update memory 0 address location */\r
+ tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);\r
+ if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))\r
+ {\r
+ tmp = hdcmi->DMA_Handle->Instance->M0AR;\r
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);\r
+ hdcmi->XferCount--;\r
+ }\r
+ /* Update memory 1 address location */\r
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ tmp = hdcmi->DMA_Handle->Instance->M1AR;\r
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);\r
+ hdcmi->XferCount--;\r
+ }\r
+ }\r
+ /* Update memory 0 address location */\r
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)\r
+ {\r
+ hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;\r
+ }\r
+ /* Update memory 1 address location */\r
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ tmp = hdcmi->pBuffPtr;\r
+ hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));\r
+ hdcmi->XferCount = hdcmi->XferTransferNumber;\r
+ }\r
+\r
+ /* Check if the frame is transferred */\r
+ if(hdcmi->XferCount == hdcmi->XferTransferNumber)\r
+ {\r
+ /* Enable the Frame interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);\r
+ \r
+ /* When snapshot mode, set dcmi state to ready */\r
+ if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)\r
+ { \r
+ hdcmi->State= HAL_DCMI_STATE_READY;\r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)\r
+ {\r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+ \r
+ /* Set DCMI Error Code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;\r
+ }\r
+\r
+ /* DCMI error Callback */ \r
+ HAL_DCMI_ErrorCallback(hdcmi);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dcmi_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Empty file; This file is no longer used to handle the Black&White\r
+ * feature. Its content is now moved to common files\r
+ * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7\r
+ * family. It's just kept for compatibility reasons.\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dfsdm.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Digital Filter for Sigma-Delta Modulators\r
+ * (DFSDM) peripherals:\r
+ * + Initialization and configuration of channels and filters\r
+ * + Regular channels configuration\r
+ * + Injected channels configuration\r
+ * + Regular/Injected Channels DMA Configuration\r
+ * + Interrupts and flags management\r
+ * + Analog watchdog feature\r
+ * + Short-circuit detector feature\r
+ * + Extremes detector feature\r
+ * + Clock absence detector feature\r
+ * + Break generation on analog watchdog or short-circuit event\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ *** Channel initialization ***\r
+ ==============================\r
+ [..]\r
+ (#) User has first to initialize channels (before filters initialization).\r
+ (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :\r
+ (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().\r
+ (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
+ (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().\r
+ (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global\r
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+ (#) Configure the output clock, input, serial interface, analog watchdog,\r
+ offset and data right bit shift parameters for this channel using the \r
+ HAL_DFSDM_ChannelInit() function.\r
+\r
+ *** Channel clock absence detector ***\r
+ ======================================\r
+ [..]\r
+ (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or\r
+ HAL_DFSDM_ChannelCkabStart_IT().\r
+ (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock\r
+ absence.\r
+ (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if\r
+ clock absence is detected.\r
+ (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or\r
+ HAL_DFSDM_ChannelCkabStop_IT().\r
+ (#) Please note that the same mode (polling or interrupt) has to be used \r
+ for all channels because the channels are sharing the same interrupt.\r
+ (#) Please note also that in interrupt mode, if clock absence detector is\r
+ stopped for one channel, interrupt will be disabled for all channels.\r
+\r
+ *** Channel short circuit detector ***\r
+ ======================================\r
+ [..] \r
+ (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or\r
+ or HAL_DFSDM_ChannelScdStart_IT().\r
+ (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short\r
+ circuit.\r
+ (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if \r
+ short circuit is detected.\r
+ (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or\r
+ or HAL_DFSDM_ChannelScdStop_IT().\r
+ (#) Please note that the same mode (polling or interrupt) has to be used \r
+ for all channels because the channels are sharing the same interrupt.\r
+ (#) Please note also that in interrupt mode, if short circuit detector is\r
+ stopped for one channel, interrupt will be disabled for all channels.\r
+\r
+ *** Channel analog watchdog value ***\r
+ =====================================\r
+ [..] \r
+ (#) Get analog watchdog filter value of a channel using\r
+ HAL_DFSDM_ChannelGetAwdValue().\r
+\r
+ *** Channel offset value ***\r
+ =====================================\r
+ [..] \r
+ (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().\r
+\r
+ *** Filter initialization ***\r
+ =============================\r
+ [..]\r
+ (#) After channel initialization, user has to init filters.\r
+ (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :\r
+ (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global\r
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+ Please note that DFSDMz_FLT0 global interrupt could be already\r
+ enabled if interrupt is used for channel.\r
+ (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it\r
+ with DFSDMz filter handle using __HAL_LINKDMA().\r
+ (#) Configure the regular conversion, injected conversion and filter\r
+ parameters for this filter using the HAL_DFSDM_FilterInit() function.\r
+\r
+ *** Filter regular channel conversion ***\r
+ =========================================\r
+ [..] \r
+ (#) Select regular channel and enable/disable continuous mode using\r
+ HAL_DFSDM_FilterConfigRegChannel().\r
+ (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),\r
+ HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or\r
+ HAL_DFSDM_FilterRegularMsbStart_DMA().\r
+ (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect \r
+ the end of regular conversion.\r
+ (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called\r
+ at the end of regular conversion.\r
+ (#) Get value of regular conversion and corresponding channel using \r
+ HAL_DFSDM_FilterGetRegularValue().\r
+ (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and \r
+ HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the\r
+ half transfer and at the transfer complete. Please note that \r
+ HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA\r
+ circular mode.\r
+ (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),\r
+ HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().\r
+\r
+ *** Filter injected channels conversion ***\r
+ ===========================================\r
+ [..]\r
+ (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().\r
+ (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),\r
+ HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or\r
+ HAL_DFSDM_FilterInjectedMsbStart_DMA().\r
+ (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect \r
+ the end of injected conversion.\r
+ (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called\r
+ at the end of injected conversion.\r
+ (#) Get value of injected conversion and corresponding channel using \r
+ HAL_DFSDM_FilterGetInjectedValue().\r
+ (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and \r
+ HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the\r
+ half transfer and at the transfer complete. Please note that \r
+ HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA\r
+ circular mode.\r
+ (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),\r
+ HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().\r
+\r
+ *** Filter analog watchdog ***\r
+ ==============================\r
+ [..]\r
+ (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().\r
+ (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.\r
+ (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().\r
+\r
+ *** Filter extreme detector ***\r
+ ===============================\r
+ [..]\r
+ (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().\r
+ (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().\r
+ (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().\r
+ (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().\r
+\r
+ *** Filter conversion time ***\r
+ ==============================\r
+ [..]\r
+ (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+#ifdef HAL_DFSDM_MODULE_ENABLED\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+/** @defgroup DFSDM DFSDM\r
+ * @brief DFSDM HAL driver module\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Define DFSDM Private Define\r
+ * @{\r
+ */\r
+#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)\r
+#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)\r
+#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)\r
+#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)\r
+#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)\r
+#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)\r
+#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8\r
+#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)\r
+#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)\r
+#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)\r
+#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)\r
+#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)\r
+#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)\r
+#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)\r
+#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)\r
+#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)\r
+#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)\r
+#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)\r
+#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)\r
+#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)\r
+#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)\r
+#define DFSDM_MSB_MASK 0xFFFF0000U\r
+#define DFSDM_LSB_MASK 0x0000FFFFU\r
+#define DFSDM_CKAB_TIMEOUT 5000U\r
+#define DFSDM1_CHANNEL_NUMBER 8U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Variables DFSDM Private Variables\r
+ * @{\r
+ */\r
+__IO uint32_t v_dfsdm1ChannelCounter = 0;\r
+DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Functions DFSDM Private Functions\r
+ * @{\r
+ */\r
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);\r
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);\r
+static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);\r
+static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);\r
+static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);\r
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);\r
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);\r
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r
+ * @brief Channel initialization and de-initialization functions \r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Channel initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the DFSDM channel.\r
+ (+) De-initialize the DFSDM channel.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the DFSDM channel according to the specified parameters\r
+ * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ /* Check DFSDM Channel handle */\r
+ if(hdfsdm_channel == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));\r
+ assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));\r
+ assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));\r
+ assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));\r
+ assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));\r
+ assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));\r
+ assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));\r
+ assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));\r
+ assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));\r
+ assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));\r
+ \r
+ /* Check that channel has not been already initialized */\r
+ if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Call MSP init function */\r
+ HAL_DFSDM_ChannelMspInit(hdfsdm_channel);\r
+ \r
+ /* Update the channel counter */\r
+ v_dfsdm1ChannelCounter++;\r
+ \r
+ /* Configure output serial clock and enable global DFSDM interface only for first channel */\r
+ if(v_dfsdm1ChannelCounter == 1)\r
+ {\r
+ assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));\r
+ /* Set the output serial clock source */\r
+ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);\r
+ DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;\r
+ \r
+ /* Reset clock divider */\r
+ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);\r
+ if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)\r
+ {\r
+ assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));\r
+ /* Set the output clock divider */\r
+ DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << \r
+ DFSDM_CHCFGR1_CLK_DIV_OFFSET);\r
+ }\r
+ \r
+ /* enable the DFSDM global interface */\r
+ DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;\r
+ }\r
+ \r
+ /* Set channel input parameters */\r
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | \r
+ DFSDM_CHCFGR1_CHINSEL);\r
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | \r
+ hdfsdm_channel->Init.Input.DataPacking | \r
+ hdfsdm_channel->Init.Input.Pins);\r
+ \r
+ /* Set serial interface parameters */\r
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);\r
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | \r
+ hdfsdm_channel->Init.SerialInterface.SpiClock);\r
+ \r
+ /* Set analog watchdog parameters */\r
+ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);\r
+ hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | \r
+ ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));\r
+\r
+ /* Set channel offset and right bit shift */\r
+ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);\r
+ hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | \r
+ (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));\r
+\r
+ /* Enable DFSDM channel */\r
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;\r
+ \r
+ /* Set DFSDM Channel to ready state */\r
+ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;\r
+\r
+ /* Store channel handle in DFSDM channel handle table */\r
+ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-initialize the DFSDM channel.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ /* Check DFSDM Channel handle */\r
+ if(hdfsdm_channel == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ \r
+ /* Check that channel has not been already deinitialized */\r
+ if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable the DFSDM channel */\r
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);\r
+ \r
+ /* Update the channel counter */\r
+ v_dfsdm1ChannelCounter--;\r
+ \r
+ /* Disable global DFSDM at deinit of last channel */\r
+ if(v_dfsdm1ChannelCounter == 0)\r
+ {\r
+ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);\r
+ }\r
+\r
+ /* Call MSP deinit function */\r
+ HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);\r
+\r
+ /* Set DFSDM Channel in reset state */\r
+ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;\r
+\r
+ /* Reset channel handle in DFSDM channel handle table */\r
+ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the DFSDM channel MSP.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_channel);\r
+ \r
+ /* NOTE : This function should not be modified, when the function is needed,\r
+ the HAL_DFSDM_ChannelMspInit could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief De-initialize the DFSDM channel MSP.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_channel);\r
+ \r
+ /* NOTE : This function should not be modified, when the function is needed,\r
+ the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r
+ * @brief Channel operation functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Channel operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Manage clock absence detector feature.\r
+ (+) Manage short circuit detector feature.\r
+ (+) Get analog watchdog value.\r
+ (+) Modify offset value.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function allows to start clock absence detection in polling mode.\r
+ * @note Same mode has to be used for all channels.\r
+ * @note If clock is not available on this channel during 5 seconds,\r
+ * clock absence detection will not be activated and function\r
+ * will return HAL_TIMEOUT error.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t channel;\r
+ uint32_t tickstart;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Get channel number from channel instance */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+\r
+ /* Get timeout */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Clear clock absence flag */\r
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)\r
+ {\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r
+\r
+ /* Check the Timeout */\r
+ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)\r
+ {\r
+ /* Set timeout status */\r
+ status = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /* Start clock absence detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to poll for the clock absence detection.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @param Timeout : Timeout value in milliseconds.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, \r
+ uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+ uint32_t channel;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Get channel number from channel instance */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+ \r
+ /* Get timeout */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait clock absence detection */\r
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)\r
+ {\r
+ /* Check the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r
+ {\r
+ /* Return timeout status */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear clock absence detection flag */\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop clock absence detection in polling mode.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t channel;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop clock absence detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r
+ \r
+ /* Clear clock absence flag */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start clock absence detection in interrupt mode.\r
+ * @note Same mode has to be used for all channels.\r
+ * @note If clock is not available on this channel during 5 seconds,\r
+ * clock absence detection will not be activated and function\r
+ * will return HAL_TIMEOUT error.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t channel;\r
+ uint32_t tickstart;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Get channel number from channel instance */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+\r
+ /* Get timeout */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Clear clock absence flag */\r
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)\r
+ {\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r
+\r
+ /* Check the Timeout */\r
+ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)\r
+ {\r
+ /* Set timeout status */\r
+ status = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /* Activate clock absence detection interrupt */\r
+ DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;\r
+\r
+ /* Start clock absence detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Clock absence detection callback. \r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_channel);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop clock absence detection in interrupt mode.\r
+ * @note Interrupt will be disabled for all channels\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t channel;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop clock absence detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r
+ \r
+ /* Clear clock absence flag */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r
+\r
+ /* Disable clock absence detection interrupt */\r
+ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start short circuit detection in polling mode.\r
+ * @note Same mode has to be used for all channels\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @param Threshold : Short circuit detector threshold.\r
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r
+ * @param BreakSignal : Break signals assigned to short circuit event.\r
+ * This parameter can be a values combination of @ref DFSDM_BreakSignals.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+ uint32_t Threshold,\r
+ uint32_t BreakSignal)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r
+ assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Configure threshold and break signals */\r
+ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \\r
+ Threshold);\r
+ \r
+ /* Start short circuit detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to poll for the short circuit detection.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @param Timeout : Timeout value in milliseconds.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, \r
+ uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+ uint32_t channel;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Get channel number from channel instance */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+ \r
+ /* Get timeout */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait short circuit detection */\r
+ while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)\r
+ {\r
+ /* Check the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r
+ {\r
+ /* Return timeout status */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear short circuit detection flag */\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop short circuit detection in polling mode.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t channel;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop short circuit detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r
+ \r
+ /* Clear short circuit detection flag */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start short circuit detection in interrupt mode.\r
+ * @note Same mode has to be used for all channels\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @param Threshold : Short circuit detector threshold.\r
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r
+ * @param BreakSignal : Break signals assigned to short circuit event.\r
+ * This parameter can be a values combination of @ref DFSDM_BreakSignals.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+ uint32_t Threshold,\r
+ uint32_t BreakSignal)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r
+ assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Activate short circuit detection interrupt */\r
+ DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;\r
+\r
+ /* Configure threshold and break signals */\r
+ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \\r
+ Threshold);\r
+ \r
+ /* Start short circuit detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Short circuit detection callback. \r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_channel);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_ChannelScdCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop short circuit detection in interrupt mode.\r
+ * @note Interrupt will be disabled for all channels\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t channel;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop short circuit detection */\r
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r
+ \r
+ /* Clear short circuit detection flag */\r
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r
+\r
+ /* Disable short circuit detection interrupt */\r
+ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get channel analog watchdog value.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval Channel analog watchdog value.\r
+ */\r
+int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ return (int16_t) hdfsdm_channel->Instance->CHWDATAR;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to modify channel offset value.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @param Offset : DFSDM channel offset.\r
+ * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+ int32_t Offset)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+ assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));\r
+ \r
+ /* Check DFSDM channel state */\r
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Modify channel offset */\r
+ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);\r
+ hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r
+ * @brief Channel state function\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Channel state function #####\r
+ ==============================================================================\r
+ [..] This section provides function allowing to:\r
+ (+) Get channel handle state.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function allows to get the current DFSDM channel handle state.\r
+ * @param hdfsdm_channel : DFSDM channel handle.\r
+ * @retval DFSDM channel state.\r
+ */\r
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+ /* Return DFSDM channel handle state */\r
+ return hdfsdm_channel->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r
+ * @brief Filter initialization and de-initialization functions \r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Filter initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the DFSDM filter.\r
+ (+) De-initialize the DFSDM filter.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the DFSDM filter according to the specified parameters\r
+ * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Check DFSDM Channel handle */\r
+ if(hdfsdm_filter == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));\r
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));\r
+ assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));\r
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));\r
+ assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));\r
+ assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));\r
+ assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));\r
+\r
+ /* Check parameters compatibility */\r
+ if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \r
+ ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || \r
+ (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Initialize DFSDM filter variables with default values */\r
+ hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;\r
+ hdfsdm_filter->InjectedChannelsNbr = 1;\r
+ hdfsdm_filter->InjConvRemaining = 1;\r
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;\r
+ \r
+ /* Call MSP init function */\r
+ HAL_DFSDM_FilterMspInit(hdfsdm_filter);\r
+\r
+ /* Set regular parameters */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r
+ if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;\r
+ }\r
+ else\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);\r
+ }\r
+\r
+ if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;\r
+ }\r
+ else\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);\r
+ }\r
+\r
+ /* Set injected parameters */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);\r
+ if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)\r
+ {\r
+ assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));\r
+ assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));\r
+ hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);\r
+ }\r
+\r
+ if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;\r
+ }\r
+ else\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);\r
+ }\r
+\r
+ if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;\r
+ }\r
+ else\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);\r
+ }\r
+ \r
+ /* Set filter parameters */\r
+ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);\r
+ hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |\r
+ ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |\r
+ (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));\r
+\r
+ /* Store regular and injected triggers and injected scan mode*/\r
+ hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;\r
+ hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;\r
+ hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;\r
+ hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;\r
+ \r
+ /* Enable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+\r
+ /* Set DFSDM filter to ready state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the DFSDM filter.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Check DFSDM filter handle */\r
+ if(hdfsdm_filter == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ \r
+ /* Disable the DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+ \r
+ /* Call MSP deinit function */\r
+ HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);\r
+\r
+ /* Set DFSDM filter in reset state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DFSDM filter MSP.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ \r
+ /* NOTE : This function should not be modified, when the function is needed,\r
+ the HAL_DFSDM_FilterMspInit could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the DFSDM filter MSP.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ \r
+ /* NOTE : This function should not be modified, when the function is needed,\r
+ the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r
+ * @brief Filter control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Filter control functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Select channel and enable/disable continuous mode for regular conversion.\r
+ (+) Select channels for injected conversion.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function allows to select channel and to enable/disable\r
+ * continuous mode for regular conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Channel for regular conversion.\r
+ * This parameter can be a value of @ref DFSDM_Channel_Selection.\r
+ * @param ContinuousMode : Enable/disable continuous mode for regular conversion.\r
+ * This parameter can be a value of @ref DFSDM_ContinuousMode.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Channel,\r
+ uint32_t ContinuousMode)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));\r
+ assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));\r
+ \r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && \r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r
+ {\r
+ /* Configure channel and continuous mode for regular conversion */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);\r
+ if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |\r
+ DFSDM_FLTCR1_RCONT);\r
+ }\r
+ else\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);\r
+ }\r
+ /* Store continuous mode information */\r
+ hdfsdm_filter->RegularContMode = ContinuousMode;\r
+ } \r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to select channels for injected conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Channels for injected conversion.\r
+ * This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r
+ \r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && \r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r
+ {\r
+ /* Configure channel for injected conversion */\r
+ hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);\r
+ /* Store number of injected channels */\r
+ hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);\r
+ /* Update number of injected channels remaining */\r
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+ hdfsdm_filter->InjectedChannelsNbr : 1;\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r
+ * @brief Filter operation functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Filter operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion of regular/injected channel.\r
+ (+) Poll for the end of regular/injected conversion.\r
+ (+) Stop conversion of regular/injected channel.\r
+ (+) Start conversion of regular/injected channel and enable interrupt.\r
+ (+) Call the callback functions at the end of regular/injected conversions.\r
+ (+) Stop conversion of regular/injected channel and disable interrupt.\r
+ (+) Start conversion of regular/injected channel and enable DMA transfer.\r
+ (+) Stop conversion of regular/injected channel and disable DMA transfer.\r
+ (+) Start analog watchdog and enable interrupt.\r
+ (+) Call the callback function when analog watchdog occurs.\r
+ (+) Stop analog watchdog and disable interrupt.\r
+ (+) Start extreme detector.\r
+ (+) Stop extreme detector.\r
+ (+) Get result of regular channel conversion.\r
+ (+) Get result of injected channel conversion.\r
+ (+) Get extreme detector maximum and minimum values.\r
+ (+) Get conversion time.\r
+ (+) Handle DFSDM interrupt request.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function allows to start regular conversion in polling mode.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if injected conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+ {\r
+ /* Start regular conversion */\r
+ DFSDM_RegConvStart(hdfsdm_filter);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to poll for the end of regular conversion.\r
+ * @note This function should be called only if regular conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Timeout : Timeout value in milliseconds.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Get timeout */\r
+ tickstart = HAL_GetTick(); \r
+\r
+ /* Wait end of regular conversion */\r
+ while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)\r
+ {\r
+ /* Check the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r
+ {\r
+ /* Return timeout status */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Check if overrun occurs */\r
+ if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)\r
+ {\r
+ /* Update error code and call error callback */\r
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+\r
+ /* Clear regular overrun flag */\r
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r
+ }\r
+ /* Update DFSDM filter state only if not continuous conversion and SW trigger */\r
+ if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+ {\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop regular conversion in polling mode.\r
+ * @note This function should be called only if regular conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop regular conversion */\r
+ DFSDM_RegConvStop(hdfsdm_filter);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start regular conversion in interrupt mode.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if injected conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+ {\r
+ /* Enable interrupts for regular conversions */\r
+ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r
+ \r
+ /* Start regular conversion */\r
+ DFSDM_RegConvStart(hdfsdm_filter);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop regular conversion in interrupt mode.\r
+ * @note This function should be called only if regular conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable interrupts for regular conversions */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r
+ \r
+ /* Stop regular conversion */\r
+ DFSDM_RegConvStop(hdfsdm_filter);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start regular conversion in DMA mode.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if injected conversion is ongoing.\r
+ * Please note that data on buffer will contain signed regular conversion\r
+ * value on 24 most significant bits and corresponding channel on 3 least\r
+ * significant bits.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param pData : The destination buffer address.\r
+ * @param Length : The length of data to be transferred from DFSDM filter to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ int32_t *pData,\r
+ uint32_t Length)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check destination address and length */\r
+ if((pData == NULL) || (Length == 0))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check that DMA is enabled for regular conversion */\r
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check parameters compatibility */\r
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\r
+ (Length != 1))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check DFSDM filter state */\r
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+ {\r
+ /* Set callbacks on DMA handler */\r
+ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r
+ hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r
+ hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\\r
+ DFSDM_DMARegularHalfConvCplt : NULL;\r
+ \r
+ /* Start DMA in interrupt mode */\r
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \\r
+ (uint32_t) pData, Length) != HAL_OK)\r
+ {\r
+ /* Set DFSDM filter in error state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Start regular conversion */\r
+ DFSDM_RegConvStart(hdfsdm_filter);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start regular conversion in DMA mode and to get\r
+ * only the 16 most significant bits of conversion.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if injected conversion is ongoing.\r
+ * Please note that data on buffer will contain signed 16 most significant\r
+ * bits of regular conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param pData : The destination buffer address.\r
+ * @param Length : The length of data to be transferred from DFSDM filter to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ int16_t *pData,\r
+ uint32_t Length)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check destination address and length */\r
+ if((pData == NULL) || (Length == 0))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check that DMA is enabled for regular conversion */\r
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check parameters compatibility */\r
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\r
+ (Length != 1))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check DFSDM filter state */\r
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+ {\r
+ /* Set callbacks on DMA handler */\r
+ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r
+ hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r
+ hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\\r
+ DFSDM_DMARegularHalfConvCplt : NULL;\r
+ \r
+ /* Start DMA in interrupt mode */\r
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \\r
+ (uint32_t) pData, Length) != HAL_OK)\r
+ {\r
+ /* Set DFSDM filter in error state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Start regular conversion */\r
+ DFSDM_RegConvStart(hdfsdm_filter);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop regular conversion in DMA mode.\r
+ * @note This function should be called only if regular conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop current DMA transfer */\r
+ if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)\r
+ {\r
+ /* Set DFSDM filter in error state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop regular conversion */\r
+ DFSDM_RegConvStop(hdfsdm_filter);\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get regular conversion value.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Corresponding channel of regular conversion.\r
+ * @retval Regular conversion value\r
+ */\r
+int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t *Channel)\r
+{\r
+ uint32_t reg = 0;\r
+ int32_t value = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(Channel != NULL);\r
+\r
+ /* Get value of data register for regular channel */\r
+ reg = hdfsdm_filter->Instance->FLTRDATAR;\r
+ \r
+ /* Extract channel and regular conversion value */\r
+ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);\r
+ value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);\r
+\r
+ /* return regular conversion value */\r
+ return value;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start injected conversion in polling mode.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if regular conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+ {\r
+ /* Start injected conversion */\r
+ DFSDM_InjConvStart(hdfsdm_filter);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to poll for the end of injected conversion.\r
+ * @note This function should be called only if injected conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Timeout : Timeout value in milliseconds.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Get timeout */\r
+ tickstart = HAL_GetTick(); \r
+\r
+ /* Wait end of injected conversions */\r
+ while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)\r
+ {\r
+ /* Check the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r
+ {\r
+ /* Return timeout status */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Check if overrun occurs */\r
+ if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)\r
+ {\r
+ /* Update error code and call error callback */\r
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+\r
+ /* Clear injected overrun flag */\r
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r
+ }\r
+\r
+ /* Update remaining injected conversions */\r
+ hdfsdm_filter->InjConvRemaining--;\r
+ if(hdfsdm_filter->InjConvRemaining == 0)\r
+ {\r
+ /* Update DFSDM filter state only if trigger is software */\r
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+ {\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
+ }\r
+ \r
+ /* end of injected sequence, reset the value */\r
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+ hdfsdm_filter->InjectedChannelsNbr : 1;\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop injected conversion in polling mode.\r
+ * @note This function should be called only if injected conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop injected conversion */\r
+ DFSDM_InjConvStop(hdfsdm_filter);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start injected conversion in interrupt mode.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if regular conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+ {\r
+ /* Enable interrupts for injected conversions */\r
+ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r
+ \r
+ /* Start injected conversion */\r
+ DFSDM_InjConvStart(hdfsdm_filter);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop injected conversion in interrupt mode.\r
+ * @note This function should be called only if injected conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable interrupts for injected conversions */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r
+ \r
+ /* Stop injected conversion */\r
+ DFSDM_InjConvStop(hdfsdm_filter);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start injected conversion in DMA mode.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if regular conversion is ongoing.\r
+ * Please note that data on buffer will contain signed injected conversion\r
+ * value on 24 most significant bits and corresponding channel on 3 least\r
+ * significant bits.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param pData : The destination buffer address.\r
+ * @param Length : The length of data to be transferred from DFSDM filter to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ int32_t *pData,\r
+ uint32_t Length)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check destination address and length */\r
+ if((pData == NULL) || (Length == 0))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check that DMA is enabled for injected conversion */\r
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check parameters compatibility */\r
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\r
+ (Length > hdfsdm_filter->InjConvRemaining))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check DFSDM filter state */\r
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+ {\r
+ /* Set callbacks on DMA handler */\r
+ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r
+ hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r
+ hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\\r
+ DFSDM_DMAInjectedHalfConvCplt : NULL;\r
+ \r
+ /* Start DMA in interrupt mode */\r
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \\r
+ (uint32_t) pData, Length) != HAL_OK)\r
+ {\r
+ /* Set DFSDM filter in error state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Start injected conversion */\r
+ DFSDM_InjConvStart(hdfsdm_filter);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start injected conversion in DMA mode and to get\r
+ * only the 16 most significant bits of conversion.\r
+ * @note This function should be called only when DFSDM filter instance is \r
+ * in idle state or if regular conversion is ongoing.\r
+ * Please note that data on buffer will contain signed 16 most significant\r
+ * bits of injected conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param pData : The destination buffer address.\r
+ * @param Length : The length of data to be transferred from DFSDM filter to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ int16_t *pData,\r
+ uint32_t Length)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check destination address and length */\r
+ if((pData == NULL) || (Length == 0))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check that DMA is enabled for injected conversion */\r
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check parameters compatibility */\r
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\r
+ (Length > hdfsdm_filter->InjConvRemaining))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Check DFSDM filter state */\r
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+ {\r
+ /* Set callbacks on DMA handler */\r
+ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r
+ hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r
+ hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\\r
+ DFSDM_DMAInjectedHalfConvCplt : NULL;\r
+ \r
+ /* Start DMA in interrupt mode */\r
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \\r
+ (uint32_t) pData, Length) != HAL_OK)\r
+ {\r
+ /* Set DFSDM filter in error state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Start injected conversion */\r
+ DFSDM_InjConvStart(hdfsdm_filter);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop injected conversion in DMA mode.\r
+ * @note This function should be called only if injected conversion is ongoing.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop current DMA transfer */\r
+ if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)\r
+ {\r
+ /* Set DFSDM filter in error state */\r
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Stop regular conversion */\r
+ DFSDM_InjConvStop(hdfsdm_filter);\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get injected conversion value.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Corresponding channel of injected conversion.\r
+ * @retval Injected conversion value\r
+ */\r
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, \r
+ uint32_t *Channel)\r
+{\r
+ uint32_t reg = 0;\r
+ int32_t value = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(Channel != NULL);\r
+\r
+ /* Get value of data register for injected channel */\r
+ reg = hdfsdm_filter->Instance->FLTJDATAR;\r
+ \r
+ /* Extract channel and injected conversion value */\r
+ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);\r
+ value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);\r
+\r
+ /* return regular conversion value */\r
+ return value;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start filter analog watchdog in interrupt mode.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param awdParam : DFSDM filter analog watchdog parameters.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ DFSDM_Filter_AwdParamTypeDef *awdParam)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));\r
+ assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));\r
+ assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));\r
+ assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));\r
+ assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));\r
+ assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));\r
+ \r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Set analog watchdog data source */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r
+ hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;\r
+\r
+ /* Set thresholds and break signals */\r
+ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r
+ hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \\r
+ awdParam->HighBreakSignal);\r
+ hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r
+ hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \\r
+ awdParam->LowBreakSignal);\r
+\r
+ /* Set channels and interrupt for analog watchdog */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);\r
+ hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \\r
+ DFSDM_FLTCR2_AWDIE);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop filter analog watchdog in interrupt mode.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ \r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Reset channels for analog watchdog and deactivate interrupt */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);\r
+\r
+ /* Clear all analog watchdog flags */\r
+ hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);\r
+ \r
+ /* Reset thresholds and break signals */\r
+ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r
+ hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r
+\r
+ /* Reset analog watchdog data source */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to start extreme detector feature.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Channels where extreme detector is enabled.\r
+ * This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r
+ \r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Set channels for extreme detector */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r
+ hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET); \r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to stop extreme detector feature.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ __IO uint32_t reg1;\r
+ __IO uint32_t reg2;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ \r
+ /* Check DFSDM filter state */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Reset channels for extreme detector */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r
+\r
+ /* Clear extreme detector values */\r
+ reg1 = hdfsdm_filter->Instance->FLTEXMAX;\r
+ reg2 = hdfsdm_filter->Instance->FLTEXMIN; \r
+ UNUSED(reg1); /* To avoid GCC warning */\r
+ UNUSED(reg2); /* To avoid GCC warning */\r
+ }\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get extreme detector maximum value.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Corresponding channel.\r
+ * @retval Extreme detector maximum value\r
+ * This value is between Min_Data = -8388608 and Max_Data = 8388607.\r
+ */\r
+int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t *Channel)\r
+{\r
+ uint32_t reg = 0;\r
+ int32_t value = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(Channel != NULL);\r
+\r
+ /* Get value of extreme detector maximum register */\r
+ reg = hdfsdm_filter->Instance->FLTEXMAX;\r
+ \r
+ /* Extract channel and extreme detector maximum value */\r
+ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);\r
+ value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);\r
+\r
+ /* return extreme detector maximum value */\r
+ return value;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get extreme detector minimum value.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Corresponding channel.\r
+ * @retval Extreme detector minimum value\r
+ * This value is between Min_Data = -8388608 and Max_Data = 8388607.\r
+ */\r
+int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t *Channel)\r
+{\r
+ uint32_t reg = 0;\r
+ int32_t value = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+ assert_param(Channel != NULL);\r
+\r
+ /* Get value of extreme detector minimum register */\r
+ reg = hdfsdm_filter->Instance->FLTEXMIN;\r
+ \r
+ /* Extract channel and extreme detector minimum value */\r
+ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);\r
+ value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);\r
+\r
+ /* return extreme detector minimum value */\r
+ return value;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get conversion time value.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval Conversion time value\r
+ * @note To get time in second, this value has to be divided by DFSDM clock frequency.\r
+ */\r
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ uint32_t reg = 0;\r
+ uint32_t value = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+ /* Get value of conversion timer register */\r
+ reg = hdfsdm_filter->Instance->FLTCNVTIMR;\r
+ \r
+ /* Extract conversion time value */\r
+ value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);\r
+\r
+ /* return extreme detector minimum value */\r
+ return value;\r
+}\r
+\r
+/**\r
+ * @brief This function handles the DFSDM interrupts.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Check if overrun occurs during regular conversion */\r
+ if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \\r
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))\r
+ {\r
+ /* Clear regular overrun flag */\r
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r
+\r
+ /* Update error code */\r
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r
+\r
+ /* Call error callback */\r
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+ }\r
+ /* Check if overrun occurs during injected conversion */\r
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \\r
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))\r
+ {\r
+ /* Clear injected overrun flag */\r
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r
+\r
+ /* Update error code */\r
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r
+\r
+ /* Call error callback */\r
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+ }\r
+ /* Check if end of regular conversion */\r
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \\r
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))\r
+ {\r
+ /* Call regular conversion complete callback */\r
+ HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r
+\r
+ /* End of conversion if mode is not continuous and software trigger */\r
+ if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+ {\r
+ /* Disable interrupts for regular conversions */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);\r
+\r
+ /* Update DFSDM filter state */\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
+ }\r
+ }\r
+ /* Check if end of injected conversion */\r
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \\r
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))\r
+ {\r
+ /* Call injected conversion complete callback */\r
+ HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r
+\r
+ /* Update remaining injected conversions */\r
+ hdfsdm_filter->InjConvRemaining--;\r
+ if(hdfsdm_filter->InjConvRemaining == 0)\r
+ {\r
+ /* End of conversion if trigger is software */\r
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+ {\r
+ /* Disable interrupts for injected conversions */\r
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);\r
+\r
+ /* Update DFSDM filter state */\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
+ }\r
+ /* end of injected sequence, reset the value */\r
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+ hdfsdm_filter->InjectedChannelsNbr : 1;\r
+ }\r
+ }\r
+ /* Check if analog watchdog occurs */\r
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \\r
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))\r
+ {\r
+ uint32_t reg = 0;\r
+ uint32_t threshold = 0;\r
+ uint32_t channel = 0;\r
+ \r
+ /* Get channel and threshold */\r
+ reg = hdfsdm_filter->Instance->FLTAWSR;\r
+ threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;\r
+ if(threshold == DFSDM_AWD_HIGH_THRESHOLD)\r
+ {\r
+ reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;\r
+ }\r
+ while((reg & 1) == 0)\r
+ {\r
+ channel++;\r
+ reg = reg >> 1;\r
+ }\r
+ /* Clear analog watchdog flag */\r
+ hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \\r
+ (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \\r
+ (1 << channel);\r
+\r
+ /* Call analog watchdog callback */\r
+ HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);\r
+ }\r
+ /* Check if clock absence occurs */\r
+ else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\r
+ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \\r
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))\r
+ {\r
+ uint32_t reg = 0;\r
+ uint32_t channel = 0;\r
+ \r
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);\r
+\r
+ while(channel < DFSDM1_CHANNEL_NUMBER)\r
+ {\r
+ /* Check if flag is set and corresponding channel is enabled */\r
+ if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))\r
+ {\r
+ /* Check clock absence has been enabled for this channel */\r
+ if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)\r
+ {\r
+ /* Clear clock absence flag */\r
+ hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r
+\r
+ /* Call clock absence callback */\r
+ HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);\r
+ }\r
+ }\r
+ channel++;\r
+ reg = reg >> 1;\r
+ }\r
+ }\r
+ /* Check if short circuit detection occurs */\r
+ else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\r
+ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \\r
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))\r
+ {\r
+ uint32_t reg = 0;\r
+ uint32_t channel = 0;\r
+ \r
+ /* Get channel */\r
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);\r
+ while((reg & 1) == 0)\r
+ {\r
+ channel++;\r
+ reg = reg >> 1;\r
+ }\r
+ \r
+ /* Clear short circuit detection flag */\r
+ hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r
+\r
+ /* Call short circuit detection callback */\r
+ HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Regular conversion complete callback. \r
+ * @note In interrupt mode, user has to read conversion value in this function\r
+ * using HAL_DFSDM_FilterGetRegularValue.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Half regular conversion complete callback. \r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Injected conversion complete callback. \r
+ * @note In interrupt mode, user has to read conversion value in this function\r
+ * using HAL_DFSDM_FilterGetInjectedValue.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Half injected conversion complete callback. \r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Filter analog watchdog callback. \r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @param Channel : Corresponding channel.\r
+ * @param Threshold : Low or high threshold has been reached.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Channel, uint32_t Threshold)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ UNUSED(Channel);\r
+ UNUSED(Threshold);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error callback. \r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdfsdm_filter);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r
+ * @brief Filter state functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Filter state functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Get the DFSDM filter state.\r
+ (+) Get the DFSDM filter error.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function allows to get the current DFSDM filter handle state.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval DFSDM filter state.\r
+ */\r
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ /* Return DFSDM filter handle state */\r
+ return hdfsdm_filter->State;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get the current DFSDM filter error.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval DFSDM filter error code.\r
+ */\r
+uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+ return hdfsdm_filter->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback for regular conversion. \r
+ * @param hdma : DMA handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ /* Get DFSDM filter handle */\r
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ /* Call regular half conversion complete callback */\r
+ HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);\r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback for regular conversion. \r
+ * @param hdma : DMA handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ /* Get DFSDM filter handle */\r
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ /* Call regular conversion complete callback */\r
+ HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback for injected conversion. \r
+ * @param hdma : DMA handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ /* Get DFSDM filter handle */\r
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ /* Call injected half conversion complete callback */\r
+ HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);\r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback for injected conversion. \r
+ * @param hdma : DMA handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ /* Get DFSDM filter handle */\r
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ /* Call injected conversion complete callback */\r
+ HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r
+}\r
+\r
+/**\r
+ * @brief DMA error callback. \r
+ * @param hdma : DMA handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ /* Get DFSDM filter handle */\r
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ /* Update error code */\r
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;\r
+\r
+ /* Call error callback */\r
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get the number of injected channels.\r
+ * @param Channels : bitfield of injected channels.\r
+ * @retval Number of injected channels.\r
+ */\r
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)\r
+{\r
+ uint32_t nbChannels = 0;\r
+ uint32_t tmp;\r
+ \r
+ /* Get the number of channels from bitfield */\r
+ tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);\r
+ while(tmp != 0)\r
+ {\r
+ if((tmp & 1) != 0)\r
+ {\r
+ nbChannels++;\r
+ }\r
+ tmp = (uint32_t) (tmp >> 1);\r
+ }\r
+ return nbChannels;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to get the channel number from channel instance.\r
+ * @param Instance : DFSDM channel instance.\r
+ * @retval Channel number.\r
+ */\r
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)\r
+{\r
+ uint32_t channel = 0xFF;\r
+ \r
+ /* Get channel from instance */\r
+ if(Instance == DFSDM1_Channel0)\r
+ {\r
+ channel = 0;\r
+ }\r
+ else if(Instance == DFSDM1_Channel1)\r
+ {\r
+ channel = 1;\r
+ }\r
+ else if(Instance == DFSDM1_Channel2)\r
+ {\r
+ channel = 2;\r
+ }\r
+ else if(Instance == DFSDM1_Channel3)\r
+ {\r
+ channel = 3;\r
+ }\r
+ else if(Instance == DFSDM1_Channel4)\r
+ {\r
+ channel = 4;\r
+ }\r
+ else if(Instance == DFSDM1_Channel5)\r
+ {\r
+ channel = 5;\r
+ }\r
+ else if(Instance == DFSDM1_Channel6)\r
+ {\r
+ channel = 6;\r
+ }\r
+ else if(Instance == DFSDM1_Channel7)\r
+ {\r
+ channel = 7;\r
+ }\r
+\r
+ return channel;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to really start regular conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r
+{\r
+ /* Check regular trigger */\r
+ if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+ {\r
+ /* Software start of regular conversion */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
+ }\r
+ else /* synchronous trigger */\r
+ {\r
+ /* Disable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+ \r
+ /* Set RSYNC bit in DFSDM_FLTCR1 register */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;\r
+\r
+ /* Enable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+ \r
+ /* If injected conversion was in progress, restart it */\r
+ if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)\r
+ {\r
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
+ }\r
+ /* Update remaining injected conversions */\r
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+ hdfsdm_filter->InjectedChannelsNbr : 1;\r
+ }\r
+ }\r
+ /* Update DFSDM filter state */\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\r
+ HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to really stop regular conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r
+{\r
+ /* Disable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+\r
+ /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */\r
+ if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r
+ }\r
+\r
+ /* Enable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+ \r
+ /* If injected conversion was in progress, restart it */\r
+ if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)\r
+ {\r
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
+ }\r
+ /* Update remaining injected conversions */\r
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+ hdfsdm_filter->InjectedChannelsNbr : 1;\r
+ }\r
+ \r
+ /* Update DFSDM filter state */\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to really start injected conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r
+{\r
+ /* Check injected trigger */\r
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+ {\r
+ /* Software start of injected conversion */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
+ }\r
+ else /* external or synchronous trigger */\r
+ {\r
+ /* Disable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+ \r
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
+ {\r
+ /* Set JSYNC bit in DFSDM_FLTCR1 register */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;\r
+ }\r
+ else /* external trigger */\r
+ {\r
+ /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r
+ hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;\r
+ }\r
+ \r
+ /* Enable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+\r
+ /* If regular conversion was in progress, restart it */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \\r
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
+ }\r
+ }\r
+ /* Update DFSDM filter state */\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\r
+ HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;\r
+}\r
+\r
+/**\r
+ * @brief This function allows to really stop injected conversion.\r
+ * @param hdfsdm_filter : DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r
+{\r
+ /* Disable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+\r
+ /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */\r
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);\r
+ }\r
+ else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)\r
+ {\r
+ /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);\r
+ }\r
+\r
+ /* Enable DFSDM filter */\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+ \r
+ /* If regular conversion was in progress, restart it */\r
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \\r
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+ {\r
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
+ }\r
+\r
+ /* Update remaining injected conversions */\r
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+ hdfsdm_filter->InjectedChannelsNbr : 1;\r
+\r
+ /* Update DFSDM filter state */\r
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#endif /* HAL_DFSDM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief DMA HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Direct Memory Access (DMA) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and errors functions\r
+ @verbatim \r
+ ============================================================================== \r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ (#) Enable and configure the peripheral to be connected to the DMA Stream\r
+ (except for internal SRAM/FLASH memories: no initialization is \r
+ necessary) please refer to Reference manual for connection between peripherals\r
+ and DMA requests . \r
+ \r
+ (#) For a given Stream, program the required configuration through the following parameters: \r
+ Transfer Direction, Source and Destination data formats, \r
+ Circular, Normal or peripheral flow control mode, Stream Priority level, \r
+ Source and Destination Increment mode, FIFO mode and its Threshold (if needed), \r
+ Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.\r
+ \r
+ *** Polling mode IO operation ***\r
+ ================================= \r
+ [..] \r
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source \r
+ address and destination address and the Length of data to be transferred\r
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this \r
+ case a fixed Timeout can be configured by User depending from his application.\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ =================================== \r
+ [..] \r
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() \r
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of \r
+ Source address and destination address and the Length of data to be transferred. In this \r
+ case the DMA interrupt is configured \r
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can \r
+ add his own function by customization of function pointer XferCpltCallback and \r
+ XferErrorCallback (i.e a member of DMA handle structure). \r
+ [..] \r
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error \r
+ detection.\r
+ \r
+ (#) Use HAL_DMA_Abort() function to abort the current transfer\r
+ \r
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
+ \r
+ -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\r
+ possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\r
+ Half-Word data size for the peripheral to access its data register and set Word data size\r
+ for the Memory to gain in access time. Each two half words will be packed and written in\r
+ a single access to a Word in the Memory).\r
+ \r
+ -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\r
+ and Destination. In this case the Peripheral Data Size will be applied to both Source\r
+ and Destination. \r
+ \r
+ *** DMA HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DMA HAL driver.\r
+ \r
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.\r
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.\r
+ (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.\r
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.\r
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.\r
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. \r
+ \r
+ [..] \r
+ (@) You can refer to the DMA HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA DMA\r
+ * @brief DMA HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< DMA interrupt status register */\r
+ __IO uint32_t Reserved0;\r
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */\r
+} DMA_Base_Registers;\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Constants\r
+ * @{\r
+ */\r
+ #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group1\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This section provides functions allowing to initialize the DMA Stream source\r
+ and destination addresses, incrementation and data sizes, transfer direction, \r
+ circular/normal mode selection, memory-to-memory mode selection and Stream priority value.\r
+ [..]\r
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
+ reference manual. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initialize the DMA according to the specified\r
+ * parameters in the DMA_InitTypeDef and create the associated handle.\r
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmp = 0U;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ DMA_Base_Registers *regs;\r
+\r
+ /* Check the DMA peripheral state */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\r
+ assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));\r
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
+ assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));\r
+ /* Check the memory burst, peripheral burst and FIFO threshold parameters only\r
+ when FIFO mode is enabled */\r
+ if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)\r
+ {\r
+ assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));\r
+ assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));\r
+ assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));\r
+ }\r
+ \r
+ /* Allocate lock resource */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ \r
+ /* Check if the DMA Stream is effectively disabled */\r
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Get the CR register value */\r
+ tmp = hdma->Instance->CR;\r
+\r
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */\r
+ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\r
+ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \\r
+ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \\r
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));\r
+\r
+ /* Prepare the DMA Stream configuration */\r
+ tmp |= hdma->Init.Channel | hdma->Init.Direction |\r
+ hdma->Init.PeriphInc | hdma->Init.MemInc |\r
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
+ hdma->Init.Mode | hdma->Init.Priority;\r
+\r
+ /* the Memory burst and peripheral burst are not used when the FIFO is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get memory burst and peripheral burst */\r
+ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;\r
+ }\r
+ \r
+ /* Write to DMA Stream CR register */\r
+ hdma->Instance->CR = tmp; \r
+\r
+ /* Get the FCR register value */\r
+ tmp = hdma->Instance->FCR;\r
+\r
+ /* Clear Direct mode and FIFO threshold bits */\r
+ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\r
+\r
+ /* Prepare the DMA Stream FIFO configuration */\r
+ tmp |= hdma->Init.FIFOMode;\r
+\r
+ /* the FIFO threshold is not used when the FIFO mode is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get the FIFO threshold */\r
+ tmp |= hdma->Init.FIFOThreshold;\r
+ \r
+ if (DMA_CheckFifoParam(hdma) != HAL_OK)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ \r
+ return HAL_ERROR; \r
+ }\r
+ }\r
+ \r
+ /* Write to DMA Stream FCR */\r
+ hdma->Instance->FCR = tmp;\r
+\r
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate\r
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */\r
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+ \r
+ /* Clear all interrupt flags */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+ \r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DMA peripheral \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
+{\r
+ DMA_Base_Registers *regs;\r
+\r
+ /* Check the DMA peripheral state */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the DMA peripheral state */\r
+ if(hdma->State == HAL_DMA_STATE_BUSY)\r
+ {\r
+ /* Return error status */\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Disable the selected DMA Streamx */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Reset DMA Streamx control register */\r
+ hdma->Instance->CR = 0U;\r
+\r
+ /* Reset DMA Streamx number of data to transfer register */\r
+ hdma->Instance->NDTR = 0U;\r
+\r
+ /* Reset DMA Streamx peripheral address register */\r
+ hdma->Instance->PAR = 0U;\r
+\r
+ /* Reset DMA Streamx memory 0 address register */\r
+ hdma->Instance->M0AR = 0U;\r
+ \r
+ /* Reset DMA Streamx memory 1 address register */\r
+ hdma->Instance->M1AR = 0U;\r
+ \r
+ /* Reset DMA Streamx FIFO control register */\r
+ hdma->Instance->FCR = (uint32_t)0x00000021U;\r
+ \r
+ /* Get DMA steam Base Address */ \r
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+ \r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group2\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and Start DMA transfer\r
+ (+) Configure the source, destination address and data length and \r
+ Start DMA transfer with interrupt\r
+ (+) Abort DMA transfer\r
+ (+) Poll for transfer complete\r
+ (+) Handle DMA interrupt request \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE; \r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ } \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Start the DMA Transfer with interrupt enabled.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+ \r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+ \r
+ /* Enable Common interrupts*/\r
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r
+ hdma->Instance->FCR |= DMA_IT_FE;\r
+ \r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ hdma->Instance->CR |= DMA_IT_HT;\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma); \r
+ \r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * \r
+ * @note After disabling a DMA Stream, a check for wait until the DMA Stream is \r
+ * effectively disabled is added. If a Stream is disabled \r
+ * while a data transfer is ongoing, the current data will be transferred\r
+ * and the Stream will be effectively disabled only after the transfer of\r
+ * this single data is finished. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ \r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ if(hdma->State != HAL_DMA_STATE_BUSY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable all the transfer interrupts */\r
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r
+ hdma->Instance->FCR &= ~(DMA_IT_FE);\r
+ \r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ hdma->Instance->CR &= ~(DMA_IT_HT);\r
+ }\r
+ \r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ \r
+ /* Check if the DMA Stream is effectively disabled */\r
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state*/\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer in Interrupt mode.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r
+{\r
+ if(hdma->State != HAL_DMA_STATE_BUSY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Set Abort State */\r
+ hdma->State = HAL_DMA_STATE_ABORT;\r
+ \r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Polling for transfer complete.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CompleteLevel: Specifies the DMA level complete.\r
+ * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.\r
+ * This model could be used for debug purpose.\r
+ * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). \r
+ * @param Timeout: Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK; \r
+ uint32_t temp;\r
+ uint32_t tickstart = HAL_GetTick(); \r
+ uint32_t tmpisr;\r
+ \r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs;\r
+ \r
+ /* Polling mode not supported in circular mode and double buffering mode */\r
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Transfer Complete flag */\r
+ temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r
+ }\r
+ else\r
+ {\r
+ /* Half Transfer Complete flag */\r
+ temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r
+ }\r
+ \r
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ tmpisr = regs->ISR;\r
+ \r
+ while((tmpisr & temp) == RESET )\r
+ {\r
+ /* Check for the Timeout (Not applicable in circular mode)*/\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+ \r
+ /* Clear the transfer error flag */\r
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r
+ }\r
+ \r
+ if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+ \r
+ /* Clear the FIFO error flag */\r
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r
+ }\r
+ \r
+ if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+ \r
+ /* Clear the Direct Mode error flag */\r
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r
+ }\r
+ }\r
+ \r
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r
+ {\r
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r
+ {\r
+ HAL_DMA_Abort(hdma);\r
+ \r
+ /* Clear the half transfer and transfer complete flags */\r
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State= HAL_DMA_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Clear the half transfer and transfer complete flags */\r
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the half transfer and transfer complete flags */\r
+ regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Handles DMA interrupt request.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval None\r
+ */\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmpisr;\r
+ __IO uint32_t count = 0;\r
+ uint32_t timeout = SystemCoreClock / 9600;\r
+\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+\r
+ tmpisr = regs->ISR;\r
+\r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)\r
+ {\r
+ /* Disable the transfer error interrupt */\r
+ hdma->Instance->CR &= ~(DMA_IT_TE);\r
+ \r
+ /* Clear the transfer error flag */\r
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r
+ \r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+ }\r
+ }\r
+ /* FIFO Error Interrupt management ******************************************/\r
+ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)\r
+ {\r
+ /* Clear the FIFO error flag */\r
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+ }\r
+ }\r
+ /* Direct Mode Error Interrupt management ***********************************/\r
+ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)\r
+ {\r
+ /* Clear the direct mode error flag */\r
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+ }\r
+ }\r
+ /* Half Transfer Complete Interrupt management ******************************/\r
+ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r
+ \r
+ /* Multi_Buffering mode enabled */\r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r
+ {\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferM1HalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferM1HalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r
+ {\r
+ /* Disable the half transfer interrupt */\r
+ hdma->Instance->CR &= ~(DMA_IT_HT);\r
+ }\r
+ \r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Transfer Complete Interrupt management ***********************************/\r
+ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)\r
+ {\r
+ /* Clear the transfer complete flag */\r
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r
+ \r
+ if(HAL_DMA_STATE_ABORT == hdma->State)\r
+ {\r
+ /* Disable all the transfer interrupts */\r
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r
+ hdma->Instance->FCR &= ~(DMA_IT_FE);\r
+ \r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ hdma->Instance->CR &= ~(DMA_IT_HT);\r
+ }\r
+\r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ \r
+ if(hdma->XferAbortCallback != NULL)\r
+ {\r
+ hdma->XferAbortCallback(hdma);\r
+ }\r
+ return;\r
+ }\r
+ \r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r
+ {\r
+ if(hdma->XferM1CpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory1 */\r
+ hdma->XferM1CpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory0 */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r
+ else\r
+ {\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r
+ {\r
+ /* Disable the transfer complete interrupt */\r
+ hdma->Instance->CR &= ~(DMA_IT_TC);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ \r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete callback */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* manage error case */\r
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r
+ {\r
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r
+ {\r
+ hdma->State = HAL_DMA_STATE_ABORT;\r
+ \r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ \r
+ do\r
+ {\r
+ if (++count > timeout)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ \r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Register callbacks\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CallbackID: User Callback identifer\r
+ * a DMA_HandleTypeDef structure as parameter.\r
+ * @param pCallback: pointer to private callbacsk function which has pointer to \r
+ * a DMA_HandleTypeDef structure as parameter.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))\r
+{\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = pCallback;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = pCallback;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_M1CPLT_CB_ID:\r
+ hdma->XferM1CpltCallback = pCallback;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r
+ hdma->XferM1HalfCpltCallback = pCallback;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = pCallback;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = pCallback;\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief UnRegister callbacks\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CallbackID: User Callback identifer\r
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_M1CPLT_CB_ID:\r
+ hdma->XferM1CpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = NULL;\r
+ break; \r
+ \r
+ case HAL_DMA_XFER_ALL_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ hdma->XferM1CpltCallback = NULL;\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ hdma->XferErrorCallback = NULL;\r
+ hdma->XferAbortCallback = NULL;\r
+ break; \r
+ \r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group3\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DMA state\r
+ (+) Get error code\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the DMA state.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL state\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the DMA error code\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval DMA Error Code\r
+ */\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the DMA Transfer parameter.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Clear DBM bit */\r
+ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);\r
+\r
+ /* Configure DMA Stream data length */\r
+ hdma->Instance->NDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->PAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->PAR = SrcAddress;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M0AR = DstAddress;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the DMA Stream base address depending on stream number\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval Stream base address\r
+ */\r
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;\r
+ \r
+ /* lookup table for necessary bitshift of flags within status registers */\r
+ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};\r
+ hdma->StreamIndex = flagBitshiftOffset[stream_number];\r
+ \r
+ if (stream_number > 3U)\r
+ {\r
+ /* return pointer to HISR and HIFCR */\r
+ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);\r
+ }\r
+ else\r
+ {\r
+ /* return pointer to LISR and LIFCR */\r
+ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));\r
+ }\r
+ \r
+ return hdma->StreamBaseAddress;\r
+}\r
+\r
+/**\r
+ * @brief Check compatibility between FIFO threshold level and size of the memory burst\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tmp = hdma->Init.FIFOThreshold;\r
+ \r
+ /* Memory Data size equal to Byte */\r
+ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)\r
+ {\r
+ switch (tmp)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Memory Data size equal to Half-Word */\r
+ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+ {\r
+ switch (tmp)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ status = HAL_ERROR;\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ status = HAL_ERROR;\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break; \r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Memory Data size equal to Word */\r
+ else\r
+ {\r
+ switch (tmp)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ status = HAL_ERROR;\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ } \r
+ \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma2d.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief DMA2D HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the DMA2D peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Program the required configuration through the following parameters: \r
+ the transfer mode, the output color mode and the output offset using \r
+ HAL_DMA2D_Init() function.\r
+\r
+ (#) Program the required configuration through the following parameters: \r
+ the input color mode, the input color, the input alpha value, the alpha mode,\r
+ the red/blue swap mode, the inverted alpha mode and the input offset using \r
+ HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.\r
+ \r
+ *** Polling mode IO operation ***\r
+ ================================= \r
+ [..] \r
+ (#) Configure pdata parameter (explained hereafter), destination and data length \r
+ and enable the transfer using HAL_DMA2D_Start(). \r
+ (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage\r
+ user can specify the value of timeout according to his end application.\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (#) Configure pdata parameter, destination and data length and enable \r
+ the transfer using HAL_DMA2D_Start_IT(). \r
+ (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.\r
+ (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can \r
+ add his own function by customization of function pointer XferCpltCallback (member \r
+ of DMA2D handle structure). \r
+ (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback \r
+ XferErrorCallback. \r
+\r
+ -@- In Register-to-Memory transfer mode, pdata parameter is the register\r
+ color, in Memory-to-memory or Memory-to-Memory with pixel format\r
+ conversion pdata is the source address.\r
+\r
+ -@- Configure the foreground source address, the background source address, \r
+ the destination and data length then Enable the transfer using \r
+ HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()\r
+ in interrupt mode.\r
+ \r
+ -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions\r
+ are used if the memory to memory with blending transfer mode is selected.\r
+ \r
+ (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling\r
+ mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.\r
+\r
+ (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()\r
+ \r
+ (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two \r
+ consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()\r
+ and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or\r
+ HAL_DMA2D_DisableDeadTime(). \r
+ \r
+ (#) The transfer can be suspended, resumed and aborted using the following\r
+ functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().\r
+ \r
+ (#) The CLUT loading can be suspended, resumed and aborted using the following\r
+ functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), \r
+ HAL_DMA2D_CLUTLoading_Abort(). \r
+ \r
+ (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). \r
+ \r
+ (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). \r
+\r
+ *** DMA2D HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DMA2D HAL driver :\r
+ \r
+ (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.\r
+ (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.\r
+ (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.\r
+ (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.\r
+ (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.\r
+ (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. \r
+ \r
+ [..] \r
+ (@) You can refer to the DMA2D HAL driver header file for more useful macros\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA2D DMA2D\r
+ * @brief DMA2D HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup DMA2D_TimeOut DMA2D Time Out \r
+ * @{\r
+ */ \r
+#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */\r
+#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Shifts DMA2D Shifts \r
+ * @{\r
+ */ \r
+#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */\r
+#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */\r
+ \r
+#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */\r
+#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */\r
+ \r
+#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */\r
+#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */ \r
+#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */ \r
+\r
+#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */ \r
+#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */\r
+#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */\r
+ \r
+#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */\r
+ \r
+#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */\r
+#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */\r
+\r
+#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */\r
+#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */\r
+\r
+#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup DMA2D_Private_Functions_Prototypes\r
+ * @{\r
+ */\r
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DMA2D\r
+ (+) De-initialize the DMA2D \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initialize the DMA2D according to the specified\r
+ * parameters in the DMA2D_InitTypeDef and create the associated handle.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)\r
+{ \r
+ /* Check the DMA2D peripheral state */\r
+ if(hdma2d == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));\r
+ assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));\r
+ assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));\r
+ assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));\r
+\r
+ if(hdma2d->State == HAL_DMA2D_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hdma2d->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_DMA2D_MspInit(hdma2d);\r
+ }\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+\r
+ /* DMA2D CR register configuration -------------------------------------------*/\r
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);\r
+\r
+ /* DMA2D OPFCCR register configuration ---------------------------------------*/\r
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);\r
+\r
+ /* DMA2D OOR register configuration ------------------------------------------*/ \r
+ MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); \r
+\r
+#if defined (DMA2D_OPFCCR_AI)\r
+ /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/\r
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));\r
+#endif /* DMA2D_OPFCCR_AI */ \r
+ \r
+#if defined (DMA2D_OPFCCR_RBS) \r
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));\r
+#endif /* DMA2D_OPFCCR_RBS */\r
+ \r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r
+\r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the DMA2D peripheral registers to their default reset\r
+ * values.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ \r
+ /* Check the DMA2D peripheral state */\r
+ if(hdma2d == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Before aborting any DMA2D transfer or CLUT loading, check\r
+ first whether or not DMA2D clock is enabled */\r
+ if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())\r
+ {\r
+ /* Abort DMA2D transfer if any */\r
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)\r
+ {\r
+ if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)\r
+ {\r
+ /* Issue when aborting DMA2D transfer */ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Abort background CLUT loading if any */\r
+ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)\r
+ { \r
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK) \r
+ {\r
+ /* Issue when aborting background CLUT loading */ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Abort foreground CLUT loading if any */\r
+ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)\r
+ {\r
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK) \r
+ {\r
+ /* Issue when aborting foreground CLUT loading */ \r
+ return HAL_ERROR;\r
+ } \r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ \r
+ /* Carry on with de-initialization of low level hardware */\r
+ HAL_DMA2D_MspDeInit(hdma2d);\r
+ \r
+ /* Reset DMA2D control registers*/\r
+ hdma2d->Instance->CR = 0;\r
+ hdma2d->Instance->FGOR = 0;\r
+ hdma2d->Instance->BGOR = 0; \r
+ hdma2d->Instance->FGPFCCR = 0;\r
+ hdma2d->Instance->BGPFCCR = 0; \r
+ hdma2d->Instance->OPFCCR = 0;\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r
+ \r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA2D MSP.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma2d);\r
+\r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ the HAL_DMA2D_MspInit can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DMA2D MSP.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma2d);\r
+\r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ the HAL_DMA2D_MspDeInit can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the pdata, destination address and data size then \r
+ start the DMA2D transfer.\r
+ (+) Configure the source for foreground and background, destination address \r
+ and data size then start a MultiBuffer DMA2D transfer.\r
+ (+) Configure the pdata, destination address and data size then \r
+ start the DMA2D transfer with interrupt.\r
+ (+) Configure the source for foreground and background, destination address \r
+ and data size then start a MultiBuffer DMA2D transfer with interrupt.\r
+ (+) Abort DMA2D transfer.\r
+ (+) Suspend DMA2D transfer.\r
+ (+) Resume DMA2D transfer. \r
+ (+) Enable CLUT transfer. \r
+ (+) Configure CLUT loading then start transfer in polling mode.\r
+ (+) Configure CLUT loading then start transfer in interrupt mode.\r
+ (+) Abort DMA2D CLUT loading.\r
+ (+) Suspend DMA2D CLUT loading.\r
+ (+) Resume DMA2D CLUT loading. \r
+ (+) Poll for transfer complete.\r
+ (+) handle DMA2D interrupt request.\r
+ (+) Transfer watermark callback.\r
+ (+) CLUT Transfer Complete callback.\r
+ \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start the DMA2D Transfer.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param pdata: Configure the source memory Buffer address if \r
+ * Memory-to-Memory or Memory-to-Memory with pixel format \r
+ * conversion mode is selected, or configure \r
+ * the color value if Register-to-Memory mode is selected.\r
+ * @param DstAddress: The destination memory Buffer address.\r
+ * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).\r
+ * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+ \r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start the DMA2D Transfer with interrupt enabled.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param pdata: Configure the source memory Buffer address if \r
+ * the Memory-to-Memory or Memory-to-Memory with pixel format \r
+ * conversion mode is selected, or configure \r
+ * the color value if Register-to-Memory mode is selected.\r
+ * @param DstAddress: The destination memory Buffer address.\r
+ * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).\r
+ * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r
+\r
+ /* Enable the transfer complete, transfer error and configuration error interrupts */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start the multi-source DMA2D Transfer.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param SrcAddress1: The source memory Buffer address for the foreground layer.\r
+ * @param SrcAddress2: The source memory Buffer address for the background layer.\r
+ * @param DstAddress: The destination memory Buffer address.\r
+ * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).\r
+ * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width)); \r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+\r
+ /* Configure DMA2D Stream source2 address */\r
+ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);\r
+\r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start the multi-source DMA2D Transfer with interrupt enabled.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param SrcAddress1: The source memory Buffer address for the foreground layer.\r
+ * @param SrcAddress2: The source memory Buffer address for the background layer.\r
+ * @param DstAddress: The destination memory Buffer address.\r
+ * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).\r
+ * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+ \r
+ /* Configure DMA2D Stream source2 address */\r
+ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);\r
+\r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r
+ \r
+ /* Enable the transfer complete, transfer error and configuration error interrupts */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort the DMA2D Transfer.\r
+ * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Abort the DMA2D transfer */\r
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it\r
+ between the register read and the register write by the CPU (writing \910\92 has no \r
+ effect on START bitvalue). */\r
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the DMA2D is effectively disabled */\r
+ while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); \r
+\r
+ /* Change the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Suspend the DMA2D Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Suspend the DMA2D transfer */\r
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it\r
+ between the register read and the register write by the CPU (writing \910\92 has no \r
+ effect on START bitvalue). */\r
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the DMA2D is effectively suspended */\r
+ while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \\r
+ && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */\r
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r
+ { \r
+ hdma2d->State = HAL_DMA2D_STATE_SUSPEND;\r
+ }\r
+ else\r
+ {\r
+ /* Make sure SUSP bit is cleared since it is meaningless \r
+ when no tranfer is on-going */\r
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the DMA2D Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ /* Check the SUSP and START bits */\r
+ if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))\r
+ {\r
+ /* Ongoing transfer is suspended: change the DMA2D state before resuming */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+ }\r
+\r
+ /* Resume the DMA2D transfer */\r
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it\r
+ between the register read and the register write by the CPU (writing \910\92 has no \r
+ effect on START bitvalue). */\r
+ CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable the DMA2D CLUT Transfer.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+ \r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Enable the background CLUT loading */\r
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r
+ }\r
+ else\r
+ {\r
+ /* Enable the foreground CLUT loading */\r
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start DMA2D CLUT Loading.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r
+ * the configuration information for the color look up table.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx)); \r
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+ \r
+ /* Configure the CLUT of the background DMA2D layer */\r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Write background CLUT memory address */\r
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r
+ \r
+ /* Write background CLUT size and CLUT color mode */\r
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));\r
+\r
+ /* Enable the CLUT loading for the background */\r
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r
+ }\r
+ /* Configure the CLUT of the foreground DMA2D layer */\r
+ else\r
+ {\r
+ /* Write foreground CLUT memory address */\r
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r
+ \r
+ /* Write foreground CLUT size and CLUT color mode */\r
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); \r
+ \r
+ /* Enable the CLUT loading for the foreground */\r
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start DMA2D CLUT Loading with interrupt enabled.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r
+ * the configuration information for the color look up table.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx)); \r
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+ \r
+ /* Configure the CLUT of the background DMA2D layer */\r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Write background CLUT memory address */\r
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r
+ \r
+ /* Write background CLUT size and CLUT color mode */\r
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));\r
+ \r
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); \r
+\r
+ /* Enable the CLUT loading for the background */\r
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r
+ }\r
+ /* Configure the CLUT of the foreground DMA2D layer */\r
+ else\r
+ {\r
+ /* Write foreground CLUT memory address */\r
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r
+ \r
+ /* Write foreground CLUT size and CLUT color mode */\r
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));\r
+ \r
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); \r
+ \r
+ /* Enable the CLUT loading for the foreground */\r
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort the DMA2D CLUT loading.\r
+ * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground) \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{\r
+ uint32_t tickstart = 0;\r
+ __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */\r
+\r
+ /* Abort the CLUT loading */\r
+ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);\r
+ \r
+ /* If foreground CLUT loading is considered, update local variables */ \r
+ if(LayerIdx == 1)\r
+ {\r
+ reg = &(hdma2d->Instance->FGPFCCR);\r
+ }\r
+\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check if the CLUT loading is aborted */ \r
+ while((*reg & DMA2D_BGPFCCR_START) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); \r
+ \r
+ /* Change the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Suspend the DMA2D CLUT loading.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground) \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{\r
+ uint32_t tickstart = 0;\r
+ __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ \r
+\r
+ /* Suspend the CLUT loading */\r
+ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); \r
+ \r
+ /* If foreground CLUT loading is considered, update local variables */ \r
+ if(LayerIdx == 1)\r
+ {\r
+ reg = &(hdma2d->Instance->FGPFCCR);\r
+ } \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check if the CLUT loading is suspended */\r
+ while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \\r
+ && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */\r
+ if ((*reg & DMA2D_BGPFCCR_START) != RESET)\r
+ { \r
+ hdma2d->State = HAL_DMA2D_STATE_SUSPEND;\r
+ }\r
+ else\r
+ {\r
+ /* Make sure SUSP bit is cleared since it is meaningless \r
+ when no tranfer is on-going */\r
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);\r
+ } \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the DMA2D CLUT loading.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground) \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{\r
+ /* Check the SUSP and START bits for background or foreground CLUT loading */\r
+ if(LayerIdx == 0)\r
+ { \r
+ /* Background CLUT loading suspension check */\r
+ if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)\r
+ && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))\r
+ {\r
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Foreground CLUT loading suspension check */\r
+ if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)\r
+ && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))\r
+ {\r
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+ } \r
+ }\r
+\r
+ /* Resume the CLUT loading */\r
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+\r
+ * @brief Polling for transfer complete or CLUT loading.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ __IO uint32_t isrflags = 0x0; \r
+\r
+ /* Polling for DMA2D transfer */\r
+ if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)\r
+ {\r
+ isrflags = READ_REG(hdma2d->Instance->ISR); \r
+ if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)\r
+ {\r
+ if ((isrflags & DMA2D_FLAG_CE) != RESET)\r
+ {\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; \r
+ }\r
+ if ((isrflags & DMA2D_FLAG_TE) != RESET) \r
+ {\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; \r
+ }\r
+ /* Clear the transfer and configuration error flags */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);\r
+\r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+\r
+ /* Change the DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ }\r
+ /* Polling for CLUT loading (foreground or background) */\r
+ if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) || \r
+ ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)\r
+ {\r
+ isrflags = READ_REG(hdma2d->Instance->ISR); \r
+ if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) \r
+ { \r
+ if ((isrflags & DMA2D_FLAG_CAE) != RESET)\r
+ {\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; \r
+ } \r
+ if ((isrflags & DMA2D_FLAG_CE) != RESET) \r
+ {\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; \r
+ }\r
+ if ((isrflags & DMA2D_FLAG_TE) != RESET) \r
+ {\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; \r
+ }\r
+ /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);\r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_ERROR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_ERROR; \r
+ } \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ }\r
+\r
+ /* Clear the transfer complete and CLUT loading flags */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);\r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Handle DMA2D interrupt request.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL status\r
+ */\r
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);\r
+ uint32_t crflags = READ_REG(hdma2d->Instance->CR);\r
+ \r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if ((isrflags & DMA2D_FLAG_TE) != RESET)\r
+ {\r
+ if ((crflags & DMA2D_IT_TE) != RESET) \r
+ {\r
+ /* Disable the transfer Error interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); \r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;\r
+ \r
+ /* Clear the transfer error flag */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);\r
+\r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ if(hdma2d->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error Callback */\r
+ hdma2d->XferErrorCallback(hdma2d);\r
+ }\r
+ }\r
+ }\r
+ /* Configuration Error Interrupt management **********************************/\r
+ if ((isrflags & DMA2D_FLAG_CE) != RESET)\r
+ {\r
+ if ((crflags & DMA2D_IT_CE) != RESET) \r
+ { \r
+ /* Disable the Configuration Error interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);\r
+ \r
+ /* Clear the Configuration error flag */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; \r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ if(hdma2d->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error Callback */\r
+ hdma2d->XferErrorCallback(hdma2d);\r
+ }\r
+ }\r
+ }\r
+ /* CLUT access Error Interrupt management ***********************************/\r
+ if ((isrflags & DMA2D_FLAG_CAE) != RESET)\r
+ {\r
+ if ((crflags & DMA2D_IT_CAE) != RESET) \r
+ { \r
+ /* Disable the CLUT access error interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);\r
+ \r
+ /* Clear the CLUT access error flag */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; \r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ if(hdma2d->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error Callback */\r
+ hdma2d->XferErrorCallback(hdma2d);\r
+ }\r
+ }\r
+ } \r
+ /* Transfer watermark Interrupt management **********************************/\r
+ if ((isrflags & DMA2D_FLAG_TW) != RESET)\r
+ {\r
+ if ((crflags & DMA2D_IT_TW) != RESET) \r
+ { \r
+ /* Disable the transfer watermark interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);\r
+ \r
+ /* Clear the transfer watermark flag */ \r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);\r
+\r
+ /* Transfer watermark Callback */\r
+ HAL_DMA2D_LineEventCallback(hdma2d);\r
+ }\r
+ } \r
+ /* Transfer Complete Interrupt management ************************************/\r
+ if ((isrflags & DMA2D_FLAG_TC) != RESET)\r
+ {\r
+ if ((crflags & DMA2D_IT_TC) != RESET) \r
+ { \r
+ /* Disable the transfer complete interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);\r
+ \r
+ /* Clear the transfer complete flag */ \r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; \r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ if(hdma2d->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback */\r
+ hdma2d->XferCpltCallback(hdma2d);\r
+ } \r
+ }\r
+ }\r
+ /* CLUT Transfer Complete Interrupt management ******************************/\r
+ if ((isrflags & DMA2D_FLAG_CTC) != RESET)\r
+ {\r
+ if ((crflags & DMA2D_IT_CTC) != RESET) \r
+ { \r
+ /* Disable the CLUT transfer complete interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);\r
+ \r
+ /* Clear the CLUT transfer complete flag */ \r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; \r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ /* CLUT Transfer complete Callback */\r
+ HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); \r
+ }\r
+ } \r
+ \r
+}\r
+\r
+/**\r
+ * @brief Transfer watermark callback.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma2d);\r
+ \r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ the HAL_DMA2D_LineEventCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief CLUT Transfer Complete callback.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma2d);\r
+ \r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.\r
+ */\r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the DMA2D foreground or background layer parameters.\r
+ (+) Configure the DMA2D CLUT transfer.\r
+ (+) Configure the line watermark\r
+ (+) Configure the dead time value.\r
+ (+) Enable or disable the dead time value functionality. \r
+ \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the DMA2D Layer according to the specified\r
+ * parameters in the DMA2D_InitTypeDef and create the associated handle.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{ \r
+ DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];\r
+ \r
+ uint32_t regMask = 0, regValue = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx)); \r
+ assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); \r
+ if(hdma2d->Init.Mode != DMA2D_R2M)\r
+ { \r
+ assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));\r
+ if(hdma2d->Init.Mode != DMA2D_M2M)\r
+ {\r
+ assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));\r
+ }\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+\r
+ /* DMA2D BGPFCR register configuration -----------------------------------*/\r
+ /* Prepare the value to be written to the BGPFCCR register */\r
+ \r
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM);\r
+ regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;\r
+ \r
+#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)\r
+ regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI);\r
+ regMask |= DMA2D_BGPFCCR_AI; \r
+#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */ \r
+ \r
+#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)\r
+ regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);\r
+ regMask |= DMA2D_BGPFCCR_RBS; \r
+#endif \r
+ \r
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r
+ {\r
+ regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);\r
+ }\r
+ else\r
+ {\r
+ regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);\r
+ }\r
+ \r
+ /* Configure the background DMA2D layer */\r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Write DMA2D BGPFCCR register */\r
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);\r
+ \r
+ /* DMA2D BGOR register configuration -------------------------------------*/ \r
+ WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);\r
+ \r
+ /* DMA2D BGCOLR register configuration -------------------------------------*/ \r
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r
+ { \r
+ WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));\r
+ } \r
+ }\r
+ /* Configure the foreground DMA2D layer */\r
+ else\r
+ {\r
+ /* Write DMA2D FGPFCCR register */\r
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);\r
+ \r
+ /* DMA2D FGOR register configuration -------------------------------------*/\r
+ WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); \r
+ \r
+ /* DMA2D FGCOLR register configuration -------------------------------------*/ \r
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r
+ {\r
+ WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); \r
+ } \r
+ } \r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA2D CLUT Transfer.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r
+ * the configuration information for the color look up table.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx)); \r
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+ \r
+ /* Configure the CLUT of the background DMA2D layer */\r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Write background CLUT memory address */\r
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r
+ \r
+ /* Write background CLUT size and CLUT color mode */\r
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); \r
+ }\r
+ /* Configure the CLUT of the foreground DMA2D layer */\r
+ else\r
+ {\r
+ /* Write foreground CLUT memory address */\r
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r
+ \r
+ /* Write foreground CLUT size and CLUT color mode */\r
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); \r
+ }\r
+ \r
+ /* Set the DMA2D state to Ready*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the line watermark.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param Line: Line Watermark configuration (maximum 16-bit long value expected).\r
+ * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.\r
+ * @note The transfer watermark interrupt is disabled once it has occurred.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINEWATERMARK(Line));\r
+ \r
+ if (Line > DMA2D_LWR_LW)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ { \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+ \r
+ /* Sets the Line watermark configuration */\r
+ WRITE_REG(hdma2d->Instance->LWR, Line);\r
+ \r
+ /* Enable the Line interrupt */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);\r
+ \r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ return HAL_OK;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enable DMA2D dead time feature.\r
+ * @param hdma2d: DMA2D handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ /* Set DMA2D_AMTCR EN bit */\r
+ SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);\r
+\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable DMA2D dead time feature.\r
+ * @param hdma2d: DMA2D handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ /* Clear DMA2D_AMTCR EN bit */\r
+ CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);\r
+\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure dead time.\r
+ * @note The dead time value represents the guaranteed minimum number of cycles between \r
+ * two consecutive transactions on the AHB bus.\r
+ * @param hdma2d: DMA2D handle.\r
+ * @param DeadTime: dead time value.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma2d); \r
+ \r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ /* Set DMA2D_AMTCR DT field */\r
+ MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));\r
+\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to :\r
+ (+) Get the DMA2D state\r
+ (+) Get the DMA2D error code \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Return the DMA2D state\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL state\r
+ */\r
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)\r
+{ \r
+ return hdma2d->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the DMA2D error code\r
+ * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for DMA2D.\r
+ * @retval DMA2D Error Code\r
+ */\r
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ return hdma2d->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the DMA2D transfer parameters.\r
+ * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA2D. \r
+ * @param pdata: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param Width: The width of data to be transferred from source to destination.\r
+ * @param Height: The height of data to be transferred from source to destination.\r
+ * @retval HAL status\r
+ */\r
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{ \r
+ uint32_t tmp = 0;\r
+ uint32_t tmp1 = 0;\r
+ uint32_t tmp2 = 0;\r
+ uint32_t tmp3 = 0;\r
+ uint32_t tmp4 = 0;\r
+ \r
+ /* Configure DMA2D data size */\r
+ MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); \r
+ \r
+ /* Configure DMA2D destination address */\r
+ WRITE_REG(hdma2d->Instance->OMAR, DstAddress);\r
+ \r
+ /* Register to memory DMA2D mode selected */\r
+ if (hdma2d->Init.Mode == DMA2D_R2M)\r
+ { \r
+ tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;\r
+ tmp2 = pdata & DMA2D_OCOLR_RED_1;\r
+ tmp3 = pdata & DMA2D_OCOLR_GREEN_1;\r
+ tmp4 = pdata & DMA2D_OCOLR_BLUE_1;\r
+ \r
+ /* Prepare the value to be written to the OCOLR register according to the color mode */\r
+ if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)\r
+ {\r
+ tmp = (tmp3 | tmp2 | tmp1| tmp4);\r
+ }\r
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)\r
+ {\r
+ tmp = (tmp3 | tmp2 | tmp4); \r
+ }\r
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)\r
+ {\r
+ tmp2 = (tmp2 >> 19);\r
+ tmp3 = (tmp3 >> 10);\r
+ tmp4 = (tmp4 >> 3 );\r
+ tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); \r
+ }\r
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)\r
+ { \r
+ tmp1 = (tmp1 >> 31);\r
+ tmp2 = (tmp2 >> 19);\r
+ tmp3 = (tmp3 >> 11);\r
+ tmp4 = (tmp4 >> 3 ); \r
+ tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); \r
+ } \r
+ else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */\r
+ {\r
+ tmp1 = (tmp1 >> 28);\r
+ tmp2 = (tmp2 >> 20);\r
+ tmp3 = (tmp3 >> 12);\r
+ tmp4 = (tmp4 >> 4 );\r
+ tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);\r
+ } \r
+ /* Write to DMA2D OCOLR register */\r
+ WRITE_REG(hdma2d->Instance->OCOLR, tmp); \r
+ } \r
+ else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */\r
+ {\r
+ /* Configure DMA2D source address */\r
+ WRITE_REG(hdma2d->Instance->FGMAR, pdata);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief DMA Extension HAL module driver\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the DMA Extension peripheral:\r
+ * + Extended features functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The DMA Extension HAL driver can be used as follows:\r
+ (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\r
+ for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\r
+\r
+ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r
+ -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r
+ -@- In Multi (Double) buffer mode, it is possible to update the base address for \r
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx DMAEx\r
+ * @brief DMA Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup DMAEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @addtogroup DMAEx_Exported_Functions_Group1\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and \r
+ Start MultiBuffer DMA transfer\r
+ (+) Configure the source, destination address and data length and \r
+ Start MultiBuffer DMA transfer with interrupt\r
+ (+) Change on the fly the memory0 or memory1 address.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer \r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ \r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY; \r
+ \r
+ /* Enable the double buffer mode */\r
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M1AR = SecondMemAddress;\r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+ \r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer \r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ \r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+ \r
+ /* Enable the Double buffer mode */\r
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M1AR = SecondMemAddress;\r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); \r
+ \r
+ /* Clear all flags */\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r
+ \r
+ /* Enable Common interrupts*/\r
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r
+ hdma->Instance->FCR |= DMA_IT_FE;\r
+ \r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ hdma->Instance->CR |= DMA_IT_HT;\r
+ }\r
+ \r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma); \r
+ }\r
+ else\r
+ { \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma); \r
+ \r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ } \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Change the memory0 or memory1 address on the fly.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param Address: The new address\r
+ * @param memory: the memory to be changed, This parameter can be one of \r
+ * the following values:\r
+ * MEMORY0 /\r
+ * MEMORY1\r
+ * @note The MEMORY0 address can be changed only when the current transfer use\r
+ * MEMORY1 and the MEMORY1 address can be changed only when the current \r
+ * transfer use MEMORY0.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\r
+{\r
+ if(memory == MEMORY0)\r
+ {\r
+ /* change the memory0 address */\r
+ hdma->Instance->M0AR = Address;\r
+ }\r
+ else\r
+ {\r
+ /* change the memory1 address */\r
+ hdma->Instance->M1AR = Address;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the DMA Transfer parameter.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Configure DMA Stream data length */\r
+ hdma->Instance->NDTR = DataLength;\r
+ \r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->PAR = DstAddress;\r
+ \r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->PAR = SrcAddress;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M0AR = DstAddress;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dsi.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief DSI HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the DSI peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @addtogroup DSI\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DSI_MODULE_ENABLED\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @addtogroup DSI_Private_Constants\r
+ * @{\r
+ */\r
+#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */\r
+\r
+#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \\r
+ DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \\r
+ DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \\r
+ DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)\r
+#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)\r
+#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX\r
+#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX\r
+#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)\r
+#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE\r
+#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE\r
+#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE\r
+#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE\r
+#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/**\r
+ * @brief Generic DSI packet header configuration\r
+ * @param DSIx: Pointer to DSI register base\r
+ * @param ChannelID: Virtual channel ID of the header packet\r
+ * @param DataType: Packet data type of the header packet\r
+ * This parameter can be any value of :\r
+ * @ref DSI_SHORT_WRITE_PKT_Data_Type\r
+ * or @ref DSI_LONG_WRITE_PKT_Data_Type\r
+ * or @ref DSI_SHORT_READ_PKT_Data_Type\r
+ * or DSI_MAX_RETURN_PKT_SIZE\r
+ * @param Data0: Word count LSB\r
+ * @param Data1: Word count MSB\r
+ * @retval None\r
+ */\r
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,\r
+ uint32_t ChannelID,\r
+ uint32_t DataType,\r
+ uint32_t Data0,\r
+ uint32_t Data1)\r
+{\r
+ /* Update the DSI packet header with new information */\r
+ DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));\r
+}\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DSI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DSI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DSI\r
+ (+) De-initialize the DSI \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the DSI according to the specified\r
+ * parameters in the DSI_InitTypeDef and create the associated handle.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains\r
+ * the PLL Clock structure definition for the DSI. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t unitIntervalx4 = 0;\r
+ uint32_t tempIDF = 0;\r
+ \r
+ /* Check the DSI handle allocation */\r
+ if(hdsi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));\r
+ assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));\r
+ assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));\r
+ assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));\r
+ assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));\r
+ \r
+ if(hdsi->State == HAL_DSI_STATE_RESET)\r
+ {\r
+ /* Initialize the low level hardware */\r
+ HAL_DSI_MspInit(hdsi);\r
+ }\r
+ \r
+ /* Change DSI peripheral state */\r
+ hdsi->State = HAL_DSI_STATE_BUSY;\r
+ \r
+ /**************** Turn on the regulator and enable the DSI PLL ****************/\r
+ \r
+ /* Enable the regulator */\r
+ __HAL_DSI_REG_ENABLE(hdsi);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until the regulator is ready */\r
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the PLL division factors */\r
+ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);\r
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));\r
+ \r
+ /* Enable the DSI PLL */\r
+ __HAL_DSI_PLL_ENABLE(hdsi);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait for the lock of the PLL */\r
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /*************************** Set the PHY parameters ***************************/\r
+ \r
+ /* D-PHY clock and digital enable*/\r
+ hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);\r
+ \r
+ /* Clock lane configuration */\r
+ hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);\r
+ hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);\r
+ \r
+ /* Configure the number of active data lanes */\r
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;\r
+ hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;\r
+ \r
+ /************************ Set the DSI clock parameters ************************/\r
+ \r
+ /* Set the TX escape clock division factor */\r
+ hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;\r
+ hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;\r
+ \r
+ /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */\r
+ /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */\r
+ /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */\r
+ tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;\r
+ unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);\r
+ \r
+ /* Set the bit period in high-speed mode */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;\r
+ hdsi->Instance->WPCR[0] |= unitIntervalx4;\r
+ \r
+ /****************************** Error management *****************************/\r
+ \r
+ /* Disable all error interrupts and reset the Error Mask */\r
+ hdsi->Instance->IER[0] = 0;\r
+ hdsi->Instance->IER[1] = 0;\r
+ hdsi->ErrorMsk = 0;\r
+ \r
+ /* Initialise the error code */\r
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;\r
+ \r
+ /* Initialize the DSI state*/\r
+ hdsi->State = HAL_DSI_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the DSI peripheral registers to their default reset\r
+ * values.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Check the DSI handle allocation */\r
+ if(hdsi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change DSI peripheral state */\r
+ hdsi->State = HAL_DSI_STATE_BUSY;\r
+ \r
+ /* Disable the DSI wrapper */\r
+ __HAL_DSI_WRAPPER_DISABLE(hdsi);\r
+ \r
+ /* Disable the DSI host */\r
+ __HAL_DSI_DISABLE(hdsi);\r
+ \r
+ /* D-PHY clock and digital disable */\r
+ hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);\r
+ \r
+ /* Turn off the DSI PLL */\r
+ __HAL_DSI_PLL_DISABLE(hdsi);\r
+ \r
+ /* Disable the regulator */\r
+ __HAL_DSI_REG_DISABLE(hdsi);\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_DSI_MspDeInit(hdsi); \r
+ \r
+ /* Initialise the error code */\r
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;\r
+ \r
+ /* Initialize the DSI state*/\r
+ hdsi->State = HAL_DSI_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Return the DSI error code\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval DSI Error Code\r
+ */\r
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Get the error code */\r
+ return hdsi->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @brief Enable the error monitor flags \r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param ActiveErrors: indicates which error interrupts will be enabled.\r
+ * This parameter can be any combination of @ref DSI_Error_Data_Type.\r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ hdsi->Instance->IER[0] = 0;\r
+ hdsi->Instance->IER[1] = 0;\r
+ \r
+ /* Store active errors to the handle */\r
+ hdsi->ErrorMsk = ActiveErrors;\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_PHY ) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;\r
+ }\r
+ \r
+ if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)\r
+ {\r
+ /* Enable the interrupt generation on selected errors */\r
+ hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DSI MSP.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdsi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DSI_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief De-initializes the DSI MSP.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdsi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DSI_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DSI_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides function allowing to:\r
+ (+) Handle DSI interrupt request\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Handles DSI interrupt request.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI. \r
+ * @retval HAL status\r
+ */\r
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)\r
+{\r
+ uint32_t ErrorStatus0, ErrorStatus1;\r
+ \r
+ /* Tearing Effect Interrupt management ***************************************/\r
+ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)\r
+ {\r
+ if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)\r
+ {\r
+ /* Clear the Tearing Effect Interrupt Flag */\r
+ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);\r
+ \r
+ /* Tearing Effect Callback */\r
+ HAL_DSI_TearingEffectCallback(hdsi);\r
+ }\r
+ }\r
+ \r
+ /* End of Refresh Interrupt management ***************************************/\r
+ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)\r
+ {\r
+ if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)\r
+ {\r
+ /* Clear the End of Refresh Interrupt Flag */\r
+ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);\r
+ \r
+ /* End of Refresh Callback */\r
+ HAL_DSI_EndOfRefreshCallback(hdsi);\r
+ }\r
+ }\r
+ \r
+ /* Error Interrupts management ***********************************************/\r
+ if(hdsi->ErrorMsk != 0)\r
+ {\r
+ ErrorStatus0 = hdsi->Instance->ISR[0];\r
+ ErrorStatus0 &= hdsi->Instance->IER[0];\r
+ ErrorStatus1 = hdsi->Instance->ISR[1];\r
+ ErrorStatus1 &= hdsi->Instance->IER[1];\r
+ \r
+ if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;\r
+ }\r
+ \r
+ if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_TX;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_RX;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;\r
+ }\r
+ \r
+ if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)\r
+ {\r
+ hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;\r
+ }\r
+ \r
+ /* Check only selected errors */\r
+ if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)\r
+ {\r
+ /* DSI error interrupt user callback */\r
+ HAL_DSI_ErrorCallback(hdsi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tearing Effect DSI callback.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdsi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DSI_TearingEffectCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief End of Refresh DSI callback.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdsi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DSI_EndOfRefreshCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Operation Error DSI callback.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdsi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DSI_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DSI_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) \r
+ (+) \r
+ (+) \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the Generic interface read-back Virtual Channel ID.\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param VirtualChannelID: Virtual channel ID\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Update the GVCID register */\r
+ hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;\r
+ hdsi->Instance->GVCIDR |= VirtualChannelID;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Select video mode and configure the corresponding parameters\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains\r
+ * the DSI video mode configuration parameters\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));\r
+ assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));\r
+ assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));\r
+ assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));\r
+ assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));\r
+ assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));\r
+ assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));\r
+ assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));\r
+ assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));\r
+ assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));\r
+ assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));\r
+ assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));\r
+ assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));\r
+ /* Check the LooselyPacked variant only in 18-bit mode */\r
+ if(VidCfg->ColorCoding == DSI_RGB666)\r
+ {\r
+ assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));\r
+ }\r
+ \r
+ /* Select video mode by resetting CMDM and DSIM bits */\r
+ hdsi->Instance->MCR &= ~DSI_MCR_CMDM;\r
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;\r
+ \r
+ /* Configure the video mode transmission type */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;\r
+ hdsi->Instance->VMCR |= VidCfg->Mode;\r
+ \r
+ /* Configure the video packet size */\r
+ hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;\r
+ hdsi->Instance->VPCR |= VidCfg->PacketSize;\r
+ \r
+ /* Set the chunks number to be transmitted through the DSI link */\r
+ hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;\r
+ hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;\r
+ \r
+ /* Set the size of the null packet */\r
+ hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;\r
+ hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;\r
+ \r
+ /* Select the virtual channel for the LTDC interface traffic */\r
+ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;\r
+ hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;\r
+ \r
+ /* Configure the polarity of control signals */\r
+ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);\r
+ hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);\r
+ \r
+ /* Select the color coding for the host */\r
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;\r
+ hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;\r
+ \r
+ /* Select the color coding for the wrapper */\r
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;\r
+ hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);\r
+ \r
+ /* Enable/disable the loosely packed variant to 18-bit configuration */\r
+ if(VidCfg->ColorCoding == DSI_RGB666)\r
+ {\r
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;\r
+ hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;\r
+ }\r
+ \r
+ /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */\r
+ hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;\r
+ hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;\r
+ \r
+ /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */\r
+ hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;\r
+ hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;\r
+ \r
+ /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */\r
+ hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;\r
+ hdsi->Instance->VLCR |= VidCfg->HorizontalLine;\r
+ \r
+ /* Set the Vertical Synchronization Active (VSA) */\r
+ hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;\r
+ hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;\r
+ \r
+ /* Set the Vertical Back Porch (VBP)*/\r
+ hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;\r
+ hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;\r
+ \r
+ /* Set the Vertical Front Porch (VFP)*/\r
+ hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;\r
+ hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;\r
+ \r
+ /* Set the Vertical Active period*/\r
+ hdsi->Instance->VVACR &= ~DSI_VVACR_VA;\r
+ hdsi->Instance->VVACR |= VidCfg->VerticalActive;\r
+ \r
+ /* Configure the command transmission mode */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;\r
+ hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;\r
+ \r
+ /* Low power largest packet size */\r
+ hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;\r
+ hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);\r
+ \r
+ /* Low power VACT largest packet size */\r
+ hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;\r
+ hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;\r
+ \r
+ /* Enable LP transition in HFP period */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;\r
+ hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;\r
+ \r
+ /* Enable LP transition in HBP period */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;\r
+ hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;\r
+ \r
+ /* Enable LP transition in VACT period */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;\r
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;\r
+ \r
+ /* Enable LP transition in VFP period */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;\r
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;\r
+ \r
+ /* Enable LP transition in VBP period */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;\r
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;\r
+ \r
+ /* Enable LP transition in vertical sync period */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;\r
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;\r
+ \r
+ /* Enable the request for an acknowledge response at the end of a frame */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;\r
+ hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Select adapted command mode and configure the corresponding parameters\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains\r
+ * the DSI command mode configuration parameters\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));\r
+ assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));\r
+ assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));\r
+ assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));\r
+ assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));\r
+ assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));\r
+ assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));\r
+ assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));\r
+ assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));\r
+ \r
+ /* Select command mode by setting CMDM and DSIM bits */\r
+ hdsi->Instance->MCR |= DSI_MCR_CMDM;\r
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;\r
+ hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;\r
+ \r
+ /* Select the virtual channel for the LTDC interface traffic */\r
+ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;\r
+ hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;\r
+ \r
+ /* Configure the polarity of control signals */\r
+ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);\r
+ hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);\r
+ \r
+ /* Select the color coding for the host */\r
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;\r
+ hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;\r
+ \r
+ /* Select the color coding for the wrapper */\r
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;\r
+ hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);\r
+ \r
+ /* Configure the maximum allowed size for write memory command */\r
+ hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;\r
+ hdsi->Instance->LCCR |= CmdCfg->CommandSize;\r
+ \r
+ /* Configure the tearing effect source and polarity and select the refresh mode */\r
+ hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);\r
+ hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);\r
+ \r
+ /* Configure the tearing effect acknowledge request */\r
+ hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;\r
+ hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;\r
+ \r
+ /* Enable the Tearing Effect interrupt */\r
+ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);\r
+ \r
+ /* Enable the End of Refresh interrupt */\r
+ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure command transmission mode: High-speed or Low-power\r
+ * and enable/disable acknowledge request after packet transmission\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains\r
+ * the DSI command transmission mode configuration parameters\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));\r
+ assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));\r
+ assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));\r
+ assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));\r
+ assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));\r
+ assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));\r
+ assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));\r
+ assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));\r
+ assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));\r
+ assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));\r
+ assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));\r
+ assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));\r
+ assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));\r
+ \r
+ /* Select High-speed or Low-power for command transmission */\r
+ hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\\r
+ DSI_CMCR_GSW1TX |\\r
+ DSI_CMCR_GSW2TX |\\r
+ DSI_CMCR_GSR0TX |\\r
+ DSI_CMCR_GSR1TX |\\r
+ DSI_CMCR_GSR2TX |\\r
+ DSI_CMCR_GLWTX |\\r
+ DSI_CMCR_DSW0TX |\\r
+ DSI_CMCR_DSW1TX |\\r
+ DSI_CMCR_DSR0TX |\\r
+ DSI_CMCR_DLWTX |\\r
+ DSI_CMCR_MRDPS);\r
+ hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\\r
+ LPCmd->LPGenShortWriteOneP |\\r
+ LPCmd->LPGenShortWriteTwoP |\\r
+ LPCmd->LPGenShortReadNoP |\\r
+ LPCmd->LPGenShortReadOneP |\\r
+ LPCmd->LPGenShortReadTwoP |\\r
+ LPCmd->LPGenLongWrite |\\r
+ LPCmd->LPDcsShortWriteNoP |\\r
+ LPCmd->LPDcsShortWriteOneP |\\r
+ LPCmd->LPDcsShortReadNoP |\\r
+ LPCmd->LPDcsLongWrite |\\r
+ LPCmd->LPMaxReadPacket);\r
+ \r
+ /* Configure the acknowledge request after each packet transmission */\r
+ hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;\r
+ hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the flow control parameters\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param FlowControl: flow control feature(s) to be enabled.\r
+ * This parameter can be any combination of @ref DSI_FlowControl.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_FLOW_CONTROL(FlowControl));\r
+ \r
+ /* Set the DSI Host Protocol Configuration Register */\r
+ hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;\r
+ hdsi->Instance->PCR |= FlowControl;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DSI PHY timer parameters\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains\r
+ * the DSI PHY timing parameters\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)\r
+{\r
+ uint32_t maxTime;\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;\r
+\r
+ /* Clock lane timer configuration */\r
+\r
+ /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two\r
+ High-Speed transmission.\r
+ To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed\r
+ to Low-Power and from Low-Power to High-Speed.\r
+ This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).\r
+ But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.\r
+\r
+ Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.\r
+ */\r
+ hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);\r
+ hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));\r
+ \r
+ /* Data lane timer configuration */\r
+ hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);\r
+ hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));\r
+ \r
+ /* Configure the wait period to request HS transmission after a stop state */\r
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;\r
+ hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DSI HOST timeout parameters\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains\r
+ * the DSI host timeout parameters\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Set the timeout clock division factor */\r
+ hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;\r
+ hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);\r
+ \r
+ /* High-speed transmission timeout */\r
+ hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;\r
+ hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);\r
+ \r
+ /* Low-power reception timeout */\r
+ hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;\r
+ hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;\r
+ \r
+ /* High-speed read timeout */\r
+ hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;\r
+ hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;\r
+ \r
+ /* Low-power read timeout */\r
+ hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;\r
+ hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;\r
+ \r
+ /* High-speed write timeout */\r
+ hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;\r
+ hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;\r
+ \r
+ /* High-speed write presp mode */\r
+ hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;\r
+ hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;\r
+ \r
+ /* Low-speed write timeout */\r
+ hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;\r
+ hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;\r
+ \r
+ /* BTA timeout */\r
+ hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;\r
+ hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start the DSI module\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Enable the DSI host */\r
+ __HAL_DSI_ENABLE(hdsi);\r
+ \r
+ /* Enable the DSI wrapper */\r
+ __HAL_DSI_WRAPPER_ENABLE(hdsi);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DSI module\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Disable the DSI host */\r
+ __HAL_DSI_DISABLE(hdsi);\r
+ \r
+ /* Disable the DSI wrapper */\r
+ __HAL_DSI_WRAPPER_DISABLE(hdsi);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Refresh the display in command mode\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Update the display */\r
+ hdsi->Instance->WCR |= DSI_WCR_LTDCEN;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Controls the display color mode in Video mode\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param ColorMode: Color mode (full or 8-colors).\r
+ * This parameter can be any value of @ref DSI_Color_Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_COLOR_MODE(ColorMode));\r
+ \r
+ /* Update the display color mode */\r
+ hdsi->Instance->WCR &= ~DSI_WCR_COLM;\r
+ hdsi->Instance->WCR |= ColorMode;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Control the display shutdown in Video mode\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param Shutdown: Shut-down (Display-ON or Display-OFF).\r
+ * This parameter can be any value of @ref DSI_ShutDown\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_SHUT_DOWN(Shutdown));\r
+ \r
+ /* Update the display Shutdown */\r
+ hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;\r
+ hdsi->Instance->WCR |= Shutdown;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DCS or Generic short write command\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param ChannelID: Virtual channel ID.\r
+ * @param Mode: DSI short packet data type.\r
+ * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.\r
+ * @param Param1: DSC command or first generic parameter.\r
+ * This parameter can be any value of @ref DSI_DCS_Command or a\r
+ * generic command code.\r
+ * @param Param2: DSC parameter or second generic parameter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,\r
+ uint32_t ChannelID,\r
+ uint32_t Mode,\r
+ uint32_t Param1,\r
+ uint32_t Param2)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait for Command FIFO Empty */\r
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Configure the packet to send a short DCS command with 0 or 1 parameter */\r
+ DSI_ConfigPacketHeader(hdsi->Instance,\r
+ ChannelID,\r
+ Mode,\r
+ Param1,\r
+ Param2);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DCS or Generic long write command\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param ChannelID: Virtual channel ID.\r
+ * @param Mode: DSI long packet data type.\r
+ * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.\r
+ * @param NbParams: Number of parameters.\r
+ * @param Param1: DSC command or first generic parameter.\r
+ * This parameter can be any value of @ref DSI_DCS_Command or a \r
+ * generic command code\r
+ * @param ParametersTable: Pointer to parameter values table.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,\r
+ uint32_t ChannelID,\r
+ uint32_t Mode,\r
+ uint32_t NbParams,\r
+ uint32_t Param1,\r
+ uint8_t* ParametersTable)\r
+{\r
+ uint32_t uicounter = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait for Command FIFO Empty */\r
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/\r
+ while(uicounter < NbParams)\r
+ {\r
+ if(uicounter == 0x00)\r
+ {\r
+ hdsi->Instance->GPDR=(Param1 | \\r
+ ((uint32_t)(*(ParametersTable + uicounter)) << 8) | \\r
+ ((uint32_t)(*(ParametersTable + uicounter+1))<<16) | \\r
+ ((uint32_t)(*(ParametersTable + uicounter+2))<<24));\r
+ uicounter += 3;\r
+ }\r
+ else\r
+ {\r
+ hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \\r
+ ((uint32_t)(*(ParametersTable + uicounter+1)) << 8) | \\r
+ ((uint32_t)(*(ParametersTable + uicounter+2)) << 16) | \\r
+ ((uint32_t)(*(ParametersTable + uicounter+3)) << 24));\r
+ uicounter+=4;\r
+ }\r
+ }\r
+ \r
+ /* Configure the packet to send a long DCS command */\r
+ DSI_ConfigPacketHeader(hdsi->Instance,\r
+ ChannelID,\r
+ Mode,\r
+ ((NbParams+1)&0x00FF),\r
+ (((NbParams+1)&0xFF00)>>8));\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read command (DCS or generic)\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param ChannelNbr: Virtual channel ID\r
+ * @param Array: pointer to a buffer to store the payload of a read back operation.\r
+ * @param Size: Data size to be read (in byte).\r
+ * @param Mode: DSI read packet data type.\r
+ * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.\r
+ * @param DCSCmd: DCS get/read command.\r
+ * @param ParametersTable: Pointer to parameter values table.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,\r
+ uint32_t ChannelNbr,\r
+ uint8_t* Array,\r
+ uint32_t Size,\r
+ uint32_t Mode,\r
+ uint32_t DCSCmd,\r
+ uint8_t* ParametersTable)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DSI_READ_PACKET_TYPE(Mode));\r
+ \r
+ if(Size > 2)\r
+ {\r
+ /* set max return packet size */\r
+ HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));\r
+ }\r
+ \r
+ /* Configure the packet to read command */\r
+ if (Mode == DSI_DCS_SHORT_PKT_READ)\r
+ {\r
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);\r
+ }\r
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)\r
+ {\r
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);\r
+ }\r
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)\r
+ {\r
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);\r
+ }\r
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)\r
+ {\r
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check that the payload read FIFO is not empty */\r
+ while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Get the first byte */\r
+ *((uint32_t *)Array) = (hdsi->Instance->GPDR);\r
+ if (Size > 4)\r
+ {\r
+ Size -= 4;\r
+ Array += 4;\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Get the remaining bytes if any */\r
+ while(((int)(Size)) > 0)\r
+ {\r
+ if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)\r
+ {\r
+ *((uint32_t *)Array) = (hdsi->Instance->GPDR);\r
+ Size -= 4;\r
+ Array += 4;\r
+ }\r
+ \r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running\r
+ * (only data lanes are in ULPM)\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* ULPS Request on Data Lanes */\r
+ hdsi->Instance->PUCR |= DSI_PUCR_URDL;\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until the D-PHY active lanes enter into ULPM */\r
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r
+ {\r
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r
+ {\r
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running\r
+ * (only data lanes are in ULPM)\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Exit ULPS on Data Lanes */\r
+ hdsi->Instance->PUCR |= DSI_PUCR_UEDL;\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until all active lanes exit ULPM */\r
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r
+ {\r
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r
+ {\r
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* De-assert the ULPM requests and the ULPM exit bits */\r
+ hdsi->Instance->PUCR = 0;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off\r
+ * (both data and clock lanes are in ULPM)\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Clock lane configuration: no more HS request */\r
+ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;\r
+ \r
+ /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */\r
+ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);\r
+ \r
+ /* ULPS Request on Clock and Data Lanes */\r
+ hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until all active lanes exit ULPM */\r
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r
+ {\r
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r
+ {\r
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Turn off the DSI PLL */\r
+ __HAL_DSI_PLL_DISABLE(hdsi);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off\r
+ * (both data and clock lanes are in ULPM)\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Turn on the DSI PLL */\r
+ __HAL_DSI_PLL_ENABLE(hdsi);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait for the lock of the PLL */\r
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Exit ULPS on Clock and Data Lanes */\r
+ hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until all active lanes exit ULPM */\r
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r
+ {\r
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r
+ {\r
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* De-assert the ULPM requests and the ULPM exit bits */\r
+ hdsi->Instance->PUCR = 0;\r
+ \r
+ /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */\r
+ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);\r
+ \r
+ /* Restore clock lane configuration to HS */\r
+ hdsi->Instance->CLCR |= DSI_CLCR_DPCC;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start test pattern generation\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param Mode: Pattern generator mode\r
+ * This parameter can be one of the following values:\r
+ * 0 : Color bars (horizontal or vertical)\r
+ * 1 : BER pattern (vertical only)\r
+ * @param Orientation: Pattern generator orientation\r
+ * This parameter can be one of the following values:\r
+ * 0 : Vertical color bars\r
+ * 1 : Horizontal color bars\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Configure pattern generator mode and orientation */\r
+ hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);\r
+ hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));\r
+ \r
+ /* Enable pattern generator by setting PGE bit */\r
+ hdsi->Instance->VMCR |= DSI_VMCR_PGE;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop test pattern generation\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Disable pattern generator by clearing PGE bit */\r
+ hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set Slew-Rate And Delay Tuning\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param CommDelay: Communication delay to be adjusted.\r
+ * This parameter can be any value of @ref DSI_Communication_Delay\r
+ * @param Lane: select between clock or data lanes.\r
+ * This parameter can be any value of @ref DSI_Lane_Group\r
+ * @param Value: Custom value of the slew-rate or delay\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));\r
+ assert_param(IS_DSI_LANE_GROUP(Lane));\r
+ \r
+ switch(CommDelay)\r
+ {\r
+ case DSI_SLEW_RATE_HSTX:\r
+ if(Lane == DSI_CLOCK_LANE)\r
+ {\r
+ /* High-Speed Transmission Slew Rate Control on Clock Lane */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;\r
+ hdsi->Instance->WPCR[1] |= Value<<16;\r
+ }\r
+ else if(Lane == DSI_DATA_LANES)\r
+ {\r
+ /* High-Speed Transmission Slew Rate Control on Data Lanes */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;\r
+ hdsi->Instance->WPCR[1] |= Value<<18;\r
+ }\r
+ break;\r
+ case DSI_SLEW_RATE_LPTX:\r
+ if(Lane == DSI_CLOCK_LANE)\r
+ {\r
+ /* Low-Power transmission Slew Rate Compensation on Clock Lane */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;\r
+ hdsi->Instance->WPCR[1] |= Value<<6;\r
+ }\r
+ else if(Lane == DSI_DATA_LANES)\r
+ {\r
+ /* Low-Power transmission Slew Rate Compensation on Data Lanes */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;\r
+ hdsi->Instance->WPCR[1] |= Value<<8;\r
+ }\r
+ break;\r
+ case DSI_HS_DELAY:\r
+ if(Lane == DSI_CLOCK_LANE)\r
+ {\r
+ /* High-Speed Transmission Delay on Clock Lane */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;\r
+ hdsi->Instance->WPCR[1] |= Value;\r
+ }\r
+ else if(Lane == DSI_DATA_LANES)\r
+ {\r
+ /* High-Speed Transmission Delay on Data Lanes */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;\r
+ hdsi->Instance->WPCR[1] |= Value<<2;\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Low-Power Reception Filter Tuning\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Low-Power RX low-pass Filtering Tuning */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;\r
+ hdsi->Instance->WPCR[1] |= Frequency<<25;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Activate an additional current path on all lanes to meet the SDDTx parameter\r
+ * defined in the MIPI D-PHY specification\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param State: ENABLE or DISABLE\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ /* Activate/Disactivate additional current path on all lanes */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;\r
+ hdsi->Instance->WPCR[1] |= ((uint32_t)State << 12);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Custom lane pins configuration\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param CustomLane: Function to be applyed on selected lane.\r
+ * This parameter can be any value of @ref DSI_CustomLane\r
+ * @param Lane: select between clock or data lane 0 or data lane 1.\r
+ * This parameter can be any value of @ref DSI_Lane_Select\r
+ * @param State: ENABLE or DISABLE\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DSI_CUSTOM_LANE(CustomLane));\r
+ assert_param(IS_DSI_LANE(Lane));\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ switch(CustomLane)\r
+ {\r
+ case DSI_SWAP_LANE_PINS:\r
+ if(Lane == DSI_CLOCK_LANE)\r
+ {\r
+ /* Swap pins on clock lane */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 6);\r
+ }\r
+ else if(Lane == DSI_DATA_LANE0)\r
+ {\r
+ /* Swap pins on data lane 0 */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 7);\r
+ }\r
+ else if(Lane == DSI_DATA_LANE1)\r
+ {\r
+ /* Swap pins on data lane 1 */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 8);\r
+ }\r
+ break;\r
+ case DSI_INVERT_HS_SIGNAL:\r
+ if(Lane == DSI_CLOCK_LANE)\r
+ {\r
+ /* Invert HS signal on clock lane */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 9);\r
+ }\r
+ else if(Lane == DSI_DATA_LANE0)\r
+ {\r
+ /* Invert HS signal on data lane 0 */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 10);\r
+ }\r
+ else if(Lane == DSI_DATA_LANE1)\r
+ {\r
+ /* Invert HS signal on data lane 1 */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 11);\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set custom timing for the PHY\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param Timing: PHY timing to be adjusted.\r
+ * This parameter can be any value of @ref DSI_PHY_Timing\r
+ * @param State: ENABLE or DISABLE\r
+ * @param Value: Custom value of the timing\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DSI_PHY_TIMING(Timing));\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ switch(Timing)\r
+ {\r
+ case DSI_TCLK_POST:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 27);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;\r
+ hdsi->Instance->WPCR[4] |= Value & DSI_WPCR4_TCLKPOST;\r
+ }\r
+ \r
+ break;\r
+ case DSI_TLPX_CLK:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 26);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;\r
+ hdsi->Instance->WPCR[3] |= (Value << 24) & DSI_WPCR3_TLPXC;\r
+ }\r
+ \r
+ break;\r
+ case DSI_THS_EXIT:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 25);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;\r
+ hdsi->Instance->WPCR[3] |= (Value << 16) & DSI_WPCR3_THSEXIT;\r
+ }\r
+ \r
+ break;\r
+ case DSI_TLPX_DATA:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 24);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;\r
+ hdsi->Instance->WPCR[3] |= (Value << 8) & DSI_WPCR3_TLPXD;\r
+ }\r
+ \r
+ break;\r
+ case DSI_THS_ZERO:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 23);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;\r
+ hdsi->Instance->WPCR[3] |= Value & DSI_WPCR3_THSZERO;\r
+ }\r
+ \r
+ break;\r
+ case DSI_THS_TRAIL:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 22);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;\r
+ hdsi->Instance->WPCR[2] |= (Value << 24) & DSI_WPCR2_THSTRAIL;\r
+ }\r
+ \r
+ break;\r
+ case DSI_THS_PREPARE:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 21);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;\r
+ hdsi->Instance->WPCR[2] |= (Value << 16) & DSI_WPCR2_THSPREP;\r
+ }\r
+ \r
+ break;\r
+ case DSI_TCLK_ZERO:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 20);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;\r
+ hdsi->Instance->WPCR[2] |= (Value << 8) & DSI_WPCR2_TCLKZERO;\r
+ }\r
+ \r
+ break;\r
+ case DSI_TCLK_PREPARE:\r
+ /* Enable/Disable custom timing setting */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 19);\r
+ \r
+ if(State)\r
+ {\r
+ /* Set custom value */\r
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;\r
+ hdsi->Instance->WPCR[2] |= Value & DSI_WPCR2_TCLKPREP;\r
+ }\r
+ \r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Force the Clock/Data Lane in TX Stop Mode\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param Lane: select between clock or data lanes.\r
+ * This parameter can be any value of @ref DSI_Lane_Group\r
+ * @param State: ENABLE or DISABLE\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DSI_LANE_GROUP(Lane));\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ if(Lane == DSI_CLOCK_LANE)\r
+ {\r
+ /* Force/Unforce the Clock Lane in TX Stop Mode */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 12);\r
+ }\r
+ else if(Lane == DSI_DATA_LANES)\r
+ {\r
+ /* Force/Unforce the Data Lanes in TX Stop Mode */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 13);\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Forces LP Receiver in Low-Power Mode\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param State: ENABLE or DISABLE\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ /* Force/Unforce LP Receiver in Low-Power Mode */\r
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;\r
+ hdsi->Instance->WPCR[1] |= ((uint32_t)State << 22);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Force Data Lanes in RX Mode after a BTA\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param State: ENABLE or DISABLE\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ /* Force Data Lanes in RX Mode */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 16);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable a pull-down on the lanes to prevent from floating states when unused\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param State: ENABLE or DISABLE\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ /* Enable/Disable pull-down on lanes */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 18);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Switch off the contention detection on data lanes\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @param State: ENABLE or DISABLE\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdsi);\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(State));\r
+ \r
+ /* Contention Detection on Data Lanes OFF */\r
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;\r
+ hdsi->Instance->WPCR[0] |= ((uint32_t)State << 14);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdsi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DSI_Group4 Peripheral State and Errors functions\r
+ * @brief Peripheral State and Errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DSI state.\r
+ (+) Get error code. \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Return the DSI state\r
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains\r
+ * the configuration information for the DSI.\r
+ * @retval HAL state\r
+ */\r
+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)\r
+{\r
+ return hdsi->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /*STM32F769xx | STM32F779xx */ \r
+#endif /* HAL_DSI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_eth.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief ETH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Ethernet (ETH) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:\r
+ ETH_HandleTypeDef heth;\r
+ \r
+ (#)Fill parameters of Init structure in heth handle\r
+ \r
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) \r
+\r
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:\r
+ (##) Enable the Ethernet interface clock using \r
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();\r
+ \r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure Ethernet pin-out\r
+ (##) Configure Ethernet NVIC interrupt (IT mode) \r
+ \r
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:\r
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process\r
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process\r
+\r
+ (#)Enable MAC and DMA transmission and reception:\r
+ (##) HAL_ETH_Start();\r
+\r
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer \r
+ the frame to MAC TX FIFO:\r
+ (##) HAL_ETH_TransmitFrame();\r
+\r
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received \r
+ frame parameters\r
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)\r
+\r
+ (#) Get a received frame when an ETH RX interrupt occurs:\r
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)\r
+\r
+ (#) Communicate with external PHY device:\r
+ (##) Read a specific register from the PHY \r
+ HAL_ETH_ReadPHYRegister();\r
+ (##) Write data to a specific RHY register:\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ (#) Configure the Ethernet MAC after ETH peripheral initialization\r
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.\r
+ \r
+ (#) Configure the Ethernet DMA after ETH peripheral initialization\r
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH ETH \r
+ * @brief ETH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup ETH_Private_Constants ETH Private Constants\r
+ * @{\r
+ */\r
+#define ETH_TIMEOUT_SWRESET ((uint32_t)500) \r
+#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000) \r
+#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000) \r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup ETH_Private_Functions ETH Private Functions\r
+ * @{\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ETH_Exported_Functions ETH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the Ethernet peripheral\r
+ (+) De-initialize the Ethernet peripheral\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the Ethernet MAC and DMA according to default\r
+ * parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tempreg = 0, phyreg = 0;\r
+ uint32_t hclk = 60000000;\r
+ uint32_t tickstart = 0;\r
+ uint32_t err = ETH_SUCCESS;\r
+ \r
+ /* Check the ETH peripheral state */\r
+ if(heth == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));\r
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));\r
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));\r
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); \r
+ \r
+ if(heth->State == HAL_ETH_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ heth->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspInit(heth);\r
+ }\r
+ \r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+ \r
+ /* Select MII or RMII Mode*/\r
+ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);\r
+ SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;\r
+ \r
+ /* Ethernet Software reset */\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ (heth->Instance)->DMABMR |= ETH_DMABMR_SR;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait for software reset */\r
+ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)\r
+ { \r
+ heth->State= HAL_ETH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are \r
+ not available, please check your external PHY or the IO configuration */\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /*-------------------------------- MAC Initialization ----------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tempreg = (heth->Instance)->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tempreg &= ETH_MACMIIAR_CR_MASK;\r
+ \r
+ /* Get hclk frequency value */\r
+ hclk = HAL_RCC_GetHCLKFreq();\r
+ \r
+ /* Set CR bits depending on hclk value */\r
+ if((hclk >= 20000000)&&(hclk < 35000000))\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if((hclk >= 35000000)&&(hclk < 60000000))\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;\r
+ } \r
+ else if((hclk >= 60000000)&&(hclk < 100000000))\r
+ {\r
+ /* CSR Clock Range between 60-100 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r
+ } \r
+ else if((hclk >= 100000000)&&(hclk < 150000000))\r
+ {\r
+ /* CSR Clock Range between 100-150 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r
+ }\r
+ else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */\r
+ {\r
+ /* CSR Clock Range between 150-216 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; \r
+ }\r
+ \r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ (heth->Instance)->MACMIIAR = (uint32_t)tempreg;\r
+ \r
+ /*-------------------- PHY initialization and configuration ----------------*/\r
+ /* Put the PHY in reset mode */\r
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Delay to assure PHY reset */\r
+ HAL_Delay(PHY_RESET_DELAY);\r
+ \r
+ if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* We wait for linked status */\r
+ do\r
+ {\r
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);\r
+ \r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));\r
+\r
+ \r
+ /* Enable Auto-Negotiation */\r
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until the auto-negotiation will be completed */\r
+ do\r
+ {\r
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);\r
+ \r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));\r
+ \r
+ /* Read the result of the auto-negotiation */\r
+ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */\r
+ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */\r
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; \r
+ }\r
+ else\r
+ {\r
+ /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */\r
+ (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; \r
+ }\r
+ /* Configure the MAC with the speed fixed by the auto-negotiation process */\r
+ if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)\r
+ { \r
+ /* Set Ethernet speed to 10M following the auto-negotiation */\r
+ (heth->Init).Speed = ETH_SPEED_10M; \r
+ }\r
+ else\r
+ { \r
+ /* Set Ethernet speed to 100M following the auto-negotiation */ \r
+ (heth->Init).Speed = ETH_SPEED_100M;\r
+ }\r
+ }\r
+ else /* AutoNegotiation Disable */\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));\r
+ \r
+ /* Set MAC Speed and Duplex Mode */\r
+ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |\r
+ (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ /* Delay to assure PHY configuration */\r
+ HAL_Delay(PHY_CONFIG_DELAY);\r
+ }\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the ETH peripheral. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspDeInit(heth);\r
+ \r
+ /* Set ETH HAL state to Disabled */\r
+ heth->State= HAL_ETH_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(heth);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param DMATxDescTab: Pointer to the first Tx desc list \r
+ * @param TxBuff: Pointer to the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *dmatxdesc;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ heth->TxDesc = DMATxDescTab;\r
+ \r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ dmatxdesc = DMATxDescTab + i;\r
+ \r
+ /* Set Second Address Chained bit */\r
+ dmatxdesc->Status = ETH_DMATXDESC_TCH; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);\r
+ \r
+ if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ /* Set the DMA Tx descriptors checksum insertion */\r
+ dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
+ }\r
+ \r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; \r
+ }\r
+ }\r
+ \r
+ /* Set Transmit Descriptor List Address Register */\r
+ (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param DMARxDescTab: Pointer to the first Rx desc list \r
+ * @param RxBuff: Pointer to the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *DMARxDesc;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */\r
+ heth->RxDesc = DMARxDescTab; \r
+ \r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+ \r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARXDESC_OWN;\r
+ \r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);\r
+ \r
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable Ethernet DMA Rx Descriptor interrupt */\r
+ DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r
+ }\r
+ \r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); \r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); \r
+ }\r
+ }\r
+ \r
+ /* Set Receive Descriptor List Address Register */\r
+ (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(heth);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(heth);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a frame\r
+ HAL_ETH_TransmitFrame();\r
+ (+) Receive a frame\r
+ HAL_ETH_GetReceivedFrame();\r
+ HAL_ETH_GetReceivedFrame_IT();\r
+ (+) Read from an External PHY register\r
+ HAL_ETH_ReadPHYRegister();\r
+ (+) Write to an External PHY register\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ @endverbatim\r
+ \r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an Ethernet frame. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param FrameLength: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r
+{\r
+ uint32_t bufcount = 0, size = 0, i = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ if (FrameLength == 0) \r
+ {\r
+ /* Set ETH HAL state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)\r
+ { \r
+ /* OWN bit set */\r
+ heth->State = HAL_ETH_STATE_BUSY_TX;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get the number of needed Tx buffers for the current frame */\r
+ if (FrameLength > ETH_TX_BUF_SIZE)\r
+ {\r
+ bufcount = FrameLength/ETH_TX_BUF_SIZE;\r
+ if (FrameLength % ETH_TX_BUF_SIZE) \r
+ {\r
+ bufcount++;\r
+ }\r
+ }\r
+ else \r
+ { \r
+ bufcount = 1;\r
+ }\r
+ if (bufcount == 1)\r
+ {\r
+ /* Set LAST and FIRST segment */\r
+ heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;\r
+ /* Set frame size */\r
+ heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* Point to next descriptor */\r
+ heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);\r
+ }\r
+ else\r
+ {\r
+ for (i=0; i< bufcount; i++)\r
+ {\r
+ /* Clear FIRST and LAST segment bits */\r
+ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);\r
+ \r
+ if (i == 0) \r
+ {\r
+ /* Setting the first segment bit */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_FS; \r
+ }\r
+ \r
+ /* Program size */\r
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r
+ \r
+ if (i == (bufcount-1))\r
+ {\r
+ /* Setting the last segment bit */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_LS;\r
+ size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r
+ }\r
+ \r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* point to next descriptor */\r
+ heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);\r
+ }\r
+ }\r
+ \r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ (heth->Instance)->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ (heth->Instance)->DMATPDR = 0;\r
+ }\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Checks for received frames. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t framelength = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Check the ETH state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Check if segment is not owned by DMA */\r
+ /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */\r
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))\r
+ {\r
+ /* Check if last segment */\r
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) \r
+ {\r
+ /* increment segment count */\r
+ (heth->RxFrameInfos).SegCount++;\r
+ \r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if ((heth->RxFrameInfos).SegCount == 1)\r
+ {\r
+ (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;\r
+ }\r
+ \r
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;\r
+ \r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;\r
+ heth->RxFrameInfos.length = framelength;\r
+ \r
+ /* Get the address of the buffer start address */\r
+ heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;\r
+ /* point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);\r
+ \r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ /* Check if first segment */\r
+ else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)\r
+ {\r
+ (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;\r
+ (heth->RxFrameInfos).LSRxDesc = NULL;\r
+ (heth->RxFrameInfos).SegCount = 1;\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ }\r
+ /* Check if intermediate segment */ \r
+ else\r
+ {\r
+ (heth->RxFrameInfos).SegCount++;\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ } \r
+ }\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Gets the Received frame in interrupt mode. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t descriptorscancounter = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set ETH HAL State to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Scan descriptors owned by CPU */\r
+ while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))\r
+ {\r
+ /* Just for security */\r
+ descriptorscancounter++;\r
+ \r
+ /* Check if first segment in frame */\r
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ \r
+ if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)\r
+ { \r
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;\r
+ heth->RxFrameInfos.SegCount = 1; \r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ }\r
+ /* Check if intermediate segment */\r
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */\r
+ else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)\r
+ {\r
+ /* Increment segment count */\r
+ (heth->RxFrameInfos.SegCount)++;\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);\r
+ }\r
+ /* Should be last segment */\r
+ else\r
+ { \r
+ /* Last segment */\r
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;\r
+ \r
+ /* Increment segment count */\r
+ (heth->RxFrameInfos.SegCount)++;\r
+ \r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if ((heth->RxFrameInfos.SegCount) == 1)\r
+ {\r
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;\r
+ }\r
+ \r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;\r
+ \r
+ /* Get the address of the buffer start address */ \r
+ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;\r
+ \r
+ /* Point to next descriptor */ \r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ \r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ }\r
+\r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief This function handles ETH interrupt request.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Frame received */\r
+ if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) \r
+ {\r
+ /* Receive complete callback */\r
+ HAL_ETH_RxCpltCallback(heth);\r
+ \r
+ /* Clear the Eth DMA Rx IT pending bits */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);\r
+\r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+\r
+ }\r
+ /* Frame transmitted */\r
+ else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) \r
+ {\r
+ /* Transfer complete callback */\r
+ HAL_ETH_TxCpltCallback(heth);\r
+ \r
+ /* Clear the Eth DMA Tx IT pending bits */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);\r
+\r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ }\r
+ \r
+ /* Clear the interrupt flags */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);\r
+ \r
+ /* ETH DMA Error */\r
+ if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))\r
+ {\r
+ /* Ethernet Error callback */\r
+ HAL_ETH_ErrorCallback(heth);\r
+\r
+ /* Clear the interrupt flags */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);\r
+ \r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(heth);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(heth);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Ethernet transfer error callbacks\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(heth);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Reads a PHY register\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * PHY_BCR: Transceiver Basic Control Register, \r
+ * PHY_BSR: Transceiver Basic Status Register. \r
+ * More PHY register could be read depending on the used PHY\r
+ * @param RegValue: PHY register value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r
+{\r
+ uint32_t tmpreg = 0; \r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+ \r
+ /* Check the ETH peripheral state */\r
+ if(heth->State == HAL_ETH_STATE_BUSY_RD)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ /* Set ETH HAL State to BUSY_RD */\r
+ heth->State = HAL_ETH_STATE_BUSY_RD;\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ \r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+ \r
+ /* Prepare the MII address register value */\r
+ tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ \r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check for the Busy flag */\r
+ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > PHY_READ_TO)\r
+ {\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ }\r
+ \r
+ /* Get MACMIIDR value */\r
+ *RegValue = (uint16_t)(heth->Instance->MACMIIDR);\r
+ \r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Writes to a PHY register.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * PHY_BCR: Transceiver Control Register. \r
+ * More PHY register could be written depending on the used PHY\r
+ * @param RegValue: the value to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+ \r
+ /* Check the ETH peripheral state */\r
+ if(heth->State == HAL_ETH_STATE_BUSY_WR)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ /* Set ETH HAL State to BUSY_WR */\r
+ heth->State = HAL_ETH_STATE_BUSY_WR;\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ \r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+ \r
+ /* Prepare the MII register address value */\r
+ tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ \r
+ /* Give the value to the MII data register */\r
+ heth->Instance->MACMIIDR = (uint16_t)RegValue;\r
+ \r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check for the Busy flag */\r
+ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)\r
+ {\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ }\r
+ \r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Enable MAC and DMA transmission and reception.\r
+ HAL_ETH_Start();\r
+ (+) Disable MAC and DMA transmission and reception. \r
+ HAL_ETH_Stop();\r
+ (+) Set the MAC configuration in runtime mode\r
+ HAL_ETH_ConfigMAC();\r
+ (+) Set the DMA configuration in runtime mode\r
+ HAL_ETH_ConfigDMA();\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ /**\r
+ * @brief Enables Ethernet MAC and DMA reception/transmission \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Enable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionEnable(heth);\r
+ \r
+ /* Enable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionEnable(heth);\r
+ \r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO(heth);\r
+ \r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionEnable(heth);\r
+ \r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionEnable(heth);\r
+ \r
+ /* Set the ETH state to READY*/\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop Ethernet MAC and DMA reception/transmission \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Stop DMA transmission */\r
+ ETH_DMATransmissionDisable(heth);\r
+ \r
+ /* Stop DMA reception */\r
+ ETH_DMAReceptionDisable(heth);\r
+ \r
+ /* Disable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionDisable(heth);\r
+ \r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO(heth);\r
+ \r
+ /* Disable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionDisable(heth);\r
+ \r
+ /* Set the ETH state*/\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set ETH MAC Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param macconf: MAC Configuration structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+ \r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); \r
+ \r
+ if (macconf != NULL)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));\r
+ assert_param(IS_ETH_JABBER(macconf->Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));\r
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));\r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));\r
+ \r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ \r
+ tmpreg |= (uint32_t)(macconf->Watchdog | \r
+ macconf->Jabber | \r
+ macconf->InterFrameGap |\r
+ macconf->CarrierSense |\r
+ (heth->Init).Speed | \r
+ macconf->ReceiveOwn |\r
+ macconf->LoopbackMode |\r
+ (heth->Init).DuplexMode | \r
+ macconf->ChecksumOffload | \r
+ macconf->RetryTransmission | \r
+ macconf->AutomaticPadCRCStrip | \r
+ macconf->BackOffLimit | \r
+ macconf->DeferralCheck);\r
+ \r
+ /* Write to ETHERNET MACCR */\r
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg; \r
+ \r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r
+ /* Write to ETHERNET MACFFR */ \r
+ (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | \r
+ macconf->SourceAddrFilter |\r
+ macconf->PassControlFrames |\r
+ macconf->BroadcastFramesReception | \r
+ macconf->DestinationAddrFilter |\r
+ macconf->PromiscuousMode |\r
+ macconf->MulticastFramesFilter |\r
+ macconf->UnicastFramesFilter);\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFFR = tmpreg;\r
+ \r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;\r
+ \r
+ /* Write to ETHERNET MACHTLR */\r
+ (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+ \r
+ /* Get the ETHERNET MACFCR value */ \r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+ \r
+ tmpreg |= (uint32_t)((macconf->PauseTime << 16) | \r
+ macconf->ZeroQuantaPause |\r
+ macconf->PauseLowThreshold |\r
+ macconf->UnicastPauseFrameDetect | \r
+ macconf->ReceiveFlowControl |\r
+ macconf->TransmitFlowControl); \r
+ \r
+ /* Write to ETHERNET MACFCR */\r
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFCR = tmpreg;\r
+ \r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | \r
+ macconf->VLANTagIdentifier);\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACVLANTR = tmpreg;\r
+ }\r
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */\r
+ {\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ \r
+ /* Clear FES and DM bits */\r
+ tmpreg &= ~((uint32_t)0x00004800);\r
+ \r
+ tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r
+ \r
+ /* Write to ETHERNET MACCR */\r
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+ }\r
+ \r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Sets ETH DMA Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param dmaconf: DMA Configuration structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));\r
+ assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));\r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));\r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));\r
+ \r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | \r
+ dmaconf->ReceiveStoreForward |\r
+ dmaconf->FlushReceivedFrame |\r
+ dmaconf->TransmitStoreForward | \r
+ dmaconf->TransmitThresholdControl |\r
+ dmaconf->ForwardErrorFrames |\r
+ dmaconf->ForwardUndersizedGoodFrames |\r
+ dmaconf->ReceiveThresholdControl |\r
+ dmaconf->SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMAOMR = tmpreg;\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/\r
+ (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | \r
+ dmaconf->FixedBurst |\r
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmaconf->TxDMABurstLength |\r
+ dmaconf->EnhancedDescriptorFormat |\r
+ (dmaconf->DescriptorSkipLength << 2) |\r
+ dmaconf->DMAArbitration | \r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMABMR = tmpreg;\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+ (+) Get the ETH handle state:\r
+ HAL_ETH_GetState();\r
+ \r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the ETH HAL state\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL state\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Return ETH state */\r
+ return heth->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures Ethernet MAC and DMA with default parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param err: Ethernet Init error\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)\r
+{\r
+ ETH_MACInitTypeDef macinit;\r
+ ETH_DMAInitTypeDef dmainit;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex */\r
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;\r
+ \r
+ /* Set Ethernet speed to 100M */\r
+ (heth->Init).Speed = ETH_SPEED_100M;\r
+ }\r
+ \r
+ /* Ethernet MAC default initialization **************************************/\r
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;\r
+ macinit.Jabber = ETH_JABBER_ENABLE;\r
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;\r
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;\r
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;\r
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;\r
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;\r
+ }\r
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;\r
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;\r
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;\r
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;\r
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;\r
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;\r
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;\r
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;\r
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;\r
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r
+ macinit.HashTableHigh = 0x0;\r
+ macinit.HashTableLow = 0x0;\r
+ macinit.PauseTime = 0x0;\r
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r
+ macinit.VLANTagIdentifier = 0x0;\r
+ \r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH Watchdog value */\r
+ /* Set the JD: bit according to ETH Jabber value */\r
+ /* Set the IFG bit according to ETH InterFrameGap value */\r
+ /* Set the DCRS bit according to ETH CarrierSense value */\r
+ /* Set the FES bit according to ETH Speed value */ \r
+ /* Set the DO bit according to ETH ReceiveOwn value */ \r
+ /* Set the LM bit according to ETH LoopbackMode value */\r
+ /* Set the DM bit according to ETH Mode value */ \r
+ /* Set the IPCO bit according to ETH ChecksumOffload value */\r
+ /* Set the DR bit according to ETH RetryTransmission value */\r
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */\r
+ /* Set the BL bit according to ETH BackOffLimit value */\r
+ /* Set the DC bit according to ETH DeferralCheck value */\r
+ tmpreg |= (uint32_t)(macinit.Watchdog | \r
+ macinit.Jabber | \r
+ macinit.InterFrameGap |\r
+ macinit.CarrierSense |\r
+ (heth->Init).Speed | \r
+ macinit.ReceiveOwn |\r
+ macinit.LoopbackMode |\r
+ (heth->Init).DuplexMode | \r
+ macinit.ChecksumOffload | \r
+ macinit.RetryTransmission | \r
+ macinit.AutomaticPadCRCStrip | \r
+ macinit.BackOffLimit | \r
+ macinit.DeferralCheck);\r
+ \r
+ /* Write to ETHERNET MACCR */\r
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg; \r
+ \r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r
+ /* Set the RA bit according to ETH ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH PassControlFrames value */\r
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */ \r
+ (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | \r
+ macinit.SourceAddrFilter |\r
+ macinit.PassControlFrames |\r
+ macinit.BroadcastFramesReception | \r
+ macinit.DestinationAddrFilter |\r
+ macinit.PromiscuousMode |\r
+ macinit.MulticastFramesFilter |\r
+ macinit.UnicastFramesFilter);\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFFR = tmpreg;\r
+ \r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;\r
+ \r
+ /* Write to ETHERNET MACHTLR */\r
+ (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/\r
+ \r
+ /* Get the ETHERNET MACFCR value */ \r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+ \r
+ /* Set the PT bit according to ETH PauseTime value */\r
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH TransmitFlowControl value */ \r
+ tmpreg |= (uint32_t)((macinit.PauseTime << 16) | \r
+ macinit.ZeroQuantaPause |\r
+ macinit.PauseLowThreshold |\r
+ macinit.UnicastPauseFrameDetect | \r
+ macinit.ReceiveFlowControl |\r
+ macinit.TransmitFlowControl); \r
+ \r
+ /* Write to ETHERNET MACFCR */\r
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFCR = tmpreg;\r
+ \r
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/\r
+ /* Set the ETV bit according to ETH VLANTagComparison value */\r
+ /* Set the VL bit according to ETH VLANTagIdentifier value */ \r
+ (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | \r
+ macinit.VLANTagIdentifier);\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACVLANTR = tmpreg;\r
+ \r
+ /* Ethernet DMA default initialization ************************************/\r
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;\r
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;\r
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;\r
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; \r
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;\r
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;\r
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;\r
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;\r
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;\r
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r
+ dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r
+ dmainit.DescriptorSkipLength = 0x0;\r
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r
+ \r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+ \r
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | \r
+ dmainit.ReceiveStoreForward |\r
+ dmainit.FlushReceivedFrame |\r
+ dmainit.TransmitStoreForward | \r
+ dmainit.TransmitThresholdControl |\r
+ dmainit.ForwardErrorFrames |\r
+ dmainit.ForwardUndersizedGoodFrames |\r
+ dmainit.ReceiveThresholdControl |\r
+ dmainit.SecondFrameOperate);\r
+ \r
+ /* Write to ETHERNET DMAOMR */\r
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMAOMR = tmpreg;\r
+ \r
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/\r
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */\r
+ /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/\r
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH DMAArbitration value */\r
+ (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | \r
+ dmainit.FixedBurst |\r
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmainit.TxDMABurstLength |\r
+ dmainit.EnhancedDescriptorFormat |\r
+ (dmainit.DescriptorSkipLength << 2) |\r
+ dmainit.DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMABMR = tmpreg;\r
+\r
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable the Ethernet Rx Interrupt */\r
+ __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);\r
+ }\r
+\r
+ /* Initialize MAC address in ethernet MAC */ \r
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param MacAddr: The MAC address to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0: MAC Address0 \r
+ * @arg ETH_MAC_Address1: MAC Address1 \r
+ * @arg ETH_MAC_Address2: MAC Address2\r
+ * @arg ETH_MAC_Address3: MAC Address3\r
+ * @param Addr: Pointer to MAC address buffer data (6 bytes)\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+ \r
+ /* Calculate the selected MAC address high register */\r
+ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];\r
+ /* Load the selected MAC address high register */\r
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;\r
+ /* Calculate the selected MAC address low register */\r
+ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];\r
+ \r
+ /* Load the selected MAC address low register */\r
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Enable the MAC transmission */\r
+ (heth->Instance)->MACCR |= ETH_MACCR_TE;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Disable the MAC transmission */\r
+ (heth->Instance)->MACCR &= ~ETH_MACCR_TE;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Enable the MAC reception */\r
+ (heth->Instance)->MACCR |= ETH_MACCR_RE;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Disable the MAC reception */\r
+ (heth->Instance)->MACCR &= ~ETH_MACCR_RE; \r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA transmission */\r
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; \r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Disable the DMA transmission */\r
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Enable the DMA reception */\r
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; \r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Disable the DMA reception */\r
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Set the Flush Transmit FIFO bit */\r
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMAOMR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief FLASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the internal FLASH memory:\r
+ * + Program operations functions\r
+ * + Memory Control functions \r
+ * + Peripheral Errors functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### FLASH peripheral features #####\r
+ ==============================================================================\r
+ \r
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \r
+ to the Flash memory. It implements the erase and program Flash memory operations \r
+ and the read and write protection mechanisms.\r
+ \r
+ [..] The Flash memory interface accelerates code execution with a system of instruction\r
+ prefetch and cache lines. \r
+\r
+ [..] The FLASH main features are:\r
+ (+) Flash memory read operations\r
+ (+) Flash memory program/erase operations\r
+ (+) Read / write protections\r
+ (+) Prefetch on I-Code\r
+ (+) 64 cache lines of 128 bits on I-Code\r
+ (+) 8 cache lines of 128 bits on D-Code\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ This driver provides functions and macros to configure and program the FLASH \r
+ memory of all STM32F7xx devices.\r
+ \r
+ (#) FLASH Memory IO Programming functions: \r
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r
+ HAL_FLASH_Lock() functions\r
+ (++) Program functions: byte, half word, word and double word\r
+ (++) There Two modes of programming :\r
+ (+++) Polling mode using HAL_FLASH_Program() function\r
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function\r
+ \r
+ (#) Interrupts and flags management functions : \r
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\r
+ (++) Wait for last FLASH operation according to its status\r
+ (++) Get error flag status by calling HAL_SetErrorCode() \r
+ [..] \r
+ In addition to these functions, this driver includes a set of macros allowing\r
+ to handle the following operations:\r
+ (+) Set the latency\r
+ (+) Enable/Disable the prefetch buffer\r
+ (+) Enable/Disable the Instruction cache and the Data cache\r
+ (+) Reset the Instruction cache and the Data cache\r
+ (+) Enable/Disable the FLASH interrupts\r
+ (+) Monitor the FLASH flags status\r
+ [..] \r
+ (@) For any Flash memory program operation (erase or program), the CPU clock frequency\r
+ (HCLK) must be at least 1MHz. \r
+ (@) The contents of the Flash memory are not guaranteed if a device reset occurs during \r
+ a Flash memory operation.\r
+ (@) Any attempt to read the Flash memory while it is being written or erased, causes the \r
+ bus to stall. Read operations are processed correctly once the program operation has \r
+ completed. This means that code or data fetches cannot be performed while a write/erase \r
+ operation is ongoing.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH FLASH\r
+ * @brief FLASH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Constants\r
+ * @{\r
+ */\r
+#define SECTOR_MASK ((uint32_t)0xFFFFFF07U)\r
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */\r
+/**\r
+ * @}\r
+ */ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+/* Variable used for Erase sectors under interruption */\r
+FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+/* Program operations */\r
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\r
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data);\r
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);\r
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);\r
+static void FLASH_SetErrorCode(void);\r
+\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \r
+ * @brief Programming operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Programming operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the FLASH \r
+ program operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Program byte, halfword, word or double word at a specified address\r
+ * @param TypeProgram: Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ switch(TypeProgram)\r
+ {\r
+ case FLASH_TYPEPROGRAM_BYTE :\r
+ {\r
+ /*Program byte (8-bit) at a specified address.*/\r
+ FLASH_Program_Byte(Address, (uint8_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_HALFWORD :\r
+ {\r
+ /*Program halfword (16-bit) at a specified address.*/\r
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_WORD :\r
+ {\r
+ /*Program word (32-bit) at a specified address.*/\r
+ FLASH_Program_Word(Address, (uint32_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_DOUBLEWORD :\r
+ {\r
+ /*Program double word (64-bit) at a specified address.*/\r
+ FLASH_Program_DoubleWord(Address, Data);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the program operation is completed, disable the PG Bit */\r
+ FLASH->CR &= (~FLASH_CR_PG);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.\r
+ * @param TypeProgram: Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+ /* Enable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r
+ \r
+ /* Enable Error source interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r
+ \r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\r
+ FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); \r
+\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r
+ pFlash.Address = Address;\r
+ \r
+ switch(TypeProgram)\r
+ {\r
+ case FLASH_TYPEPROGRAM_BYTE :\r
+ {\r
+ /*Program byte (8-bit) at a specified address.*/\r
+ FLASH_Program_Byte(Address, (uint8_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_HALFWORD :\r
+ {\r
+ /*Program halfword (16-bit) at a specified address.*/\r
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_WORD :\r
+ {\r
+ /*Program word (32-bit) at a specified address.*/\r
+ FLASH_Program_Word(Address, (uint32_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_DOUBLEWORD :\r
+ {\r
+ /*Program double word (64-bit) at a specified address.*/\r
+ FLASH_Program_DoubleWord(Address, Data);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function handles FLASH interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_FLASH_IRQHandler(void)\r
+{\r
+ uint32_t temp = 0;\r
+ \r
+ /* If the program operation is completed, disable the PG Bit */\r
+ FLASH->CR &= (~FLASH_CR_PG);\r
+\r
+ /* If the erase operation is completed, disable the SER Bit */\r
+ FLASH->CR &= (~FLASH_CR_SER);\r
+ FLASH->CR &= SECTOR_MASK; \r
+\r
+ /* if the erase operation is completed, disable the MER Bit */\r
+ FLASH->CR &= (~FLASH_MER_BIT);\r
+\r
+ /* Check FLASH End of Operation flag */\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\r
+ {\r
+ switch (pFlash.ProcedureOnGoing)\r
+ {\r
+ case FLASH_PROC_SECTERASE :\r
+ {\r
+ /* Nb of sector to erased can be decreased */\r
+ pFlash.NbSectorsToErase--;\r
+\r
+ /* Check if there are still sectors to erase */\r
+ if(pFlash.NbSectorsToErase != 0)\r
+ {\r
+ temp = pFlash.Sector;\r
+ /* Indicate user which sector has been erased */\r
+ HAL_FLASH_EndOfOperationCallback(temp);\r
+\r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); \r
+\r
+ /* Increment sector number */\r
+ temp = ++pFlash.Sector;\r
+ FLASH_Erase_Sector(temp, pFlash.VoltageForErase);\r
+ }\r
+ else\r
+ {\r
+ /* No more sectors to Erase, user callback can be called.*/\r
+ /* Reset Sector and stop Erase sectors procedure */\r
+ pFlash.Sector = temp = 0xFFFFFFFFU;\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(temp);\r
+ /* Sector Erase procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ }\r
+ break;\r
+ }\r
+ \r
+ case FLASH_PROC_MASSERASE :\r
+ {\r
+ /* MassErase ended. Return the selected bank : in this product we don't have Banks */\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(0);\r
+ /* MAss Erase procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ break;\r
+ }\r
+\r
+ case FLASH_PROC_PROGRAM :\r
+ {\r
+ /*Program ended. Return the selected address*/\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
+ /* Programming procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Check FLASH operation error flags */\r
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)\r
+ {\r
+ switch (pFlash.ProcedureOnGoing)\r
+ {\r
+ case FLASH_PROC_SECTERASE :\r
+ {\r
+ /* return the faulty sector */\r
+ temp = pFlash.Sector;\r
+ pFlash.Sector = 0xFFFFFFFFU;\r
+ break;\r
+ }\r
+ case FLASH_PROC_MASSERASE :\r
+ {\r
+ /* No return in case of Mass Erase */\r
+ temp = 0;\r
+ break;\r
+ }\r
+ case FLASH_PROC_PROGRAM :\r
+ {\r
+ /*return the faulty address*/\r
+ temp = pFlash.Address;\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ /*Save the Error code*/\r
+ FLASH_SetErrorCode();\r
+\r
+ /* FLASH error interrupt user callback */\r
+ HAL_FLASH_OperationErrorCallback(temp);\r
+ /* Clear FLASH error pending bits */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR );\r
+\r
+ /*Stop the procedure ongoing */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ }\r
+ \r
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r
+ {\r
+ /* Disable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);\r
+\r
+ /* Disable Error source interrupt */\r
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief FLASH end of operation interrupt callback\r
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
+ * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r
+ * all the selected sectors have been erased)\r
+ * - Program : Address which was selected for data program\r
+ * - Mass Erase : No return value expected\r
+ * @retval None\r
+ */\r
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(ReturnValue);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief FLASH operation error interrupt callback\r
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
+ * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r
+ * all the selected sectors have been erased)\r
+ * - Program : Address which was selected for data program\r
+ * - Mass Erase : No return value expected\r
+ * @retval None\r
+ */\r
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(ReturnValue);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the FLASH \r
+ memory operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlock the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)\r
+{\r
+ if((FLASH->CR & FLASH_CR_LOCK) != RESET)\r
+ {\r
+ /* Authorize the FLASH Registers access */\r
+ FLASH->KEYR = FLASH_KEY1;\r
+ FLASH->KEYR = FLASH_KEY2;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Locks the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void)\r
+{\r
+ /* Set the LOCK Bit to lock the FLASH Registers access */\r
+ FLASH->CR |= FLASH_CR_LOCK;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Unlock the FLASH Option Control Registers access.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r
+{\r
+ if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)\r
+ {\r
+ /* Authorizes the Option Byte register programming */\r
+ FLASH->OPTKEYR = FLASH_OPT_KEY1;\r
+ FLASH->OPTKEYR = FLASH_OPT_KEY2;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Lock the FLASH Option Control Registers access.\r
+ * @retval HAL Status \r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r
+ FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OPTSTRT bit in OPTCR register */\r
+ FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;\r
+\r
+ /* Wait for last operation to be completed */\r
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief Peripheral Errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time Errors of the FLASH peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Get the specific FLASH error flag.\r
+ * @retval FLASH_ErrorCode: The returned value can be:\r
+ * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag \r
+ * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag \r
+ * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag\r
+ * @arg FLASH_ERROR_WRP: FLASH Write protected error flag\r
+ * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag \r
+ */\r
+uint32_t HAL_FLASH_GetError(void)\r
+{ \r
+ return pFlash.ErrorCode;\r
+} \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @brief Wait for a FLASH operation to complete.\r
+ * @param Timeout: maximum flash operationtimeout\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Clear Error Code */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+ \r
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
+ flag will be set */\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) \r
+ { \r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\r
+ FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)\r
+ {\r
+ /*Save the error code*/\r
+ FLASH_SetErrorCode();\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* If there is an error flag set */\r
+ return HAL_OK;\r
+ \r
+} \r
+\r
+/**\r
+ * @brief Program a double word (64-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V and an External Vpp is present.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+ \r
+ *(__IO uint64_t*)Address = Data;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Program word (32-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint32_t*)Address = Data;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Program a half-word (16-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_HALF_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint16_t*)Address = Data;\r
+\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Program byte (8-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_BYTE;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint8_t*)Address = Data;\r
+\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Set the specific FLASH error flag.\r
+ * @retval None\r
+ */\r
+static void FLASH_SetErrorCode(void)\r
+{ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Extended FLASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the FLASH extension peripheral:\r
+ * + Extended programming operations functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Flash Extension features #####\r
+ ==============================================================================\r
+ \r
+ [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx \r
+ devices contains the following additional features \r
+ \r
+ (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\r
+ capability (RWW)\r
+ (+) Dual bank memory organization \r
+ (+) Dual boot mode\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to configure and program the FLASH memory \r
+ of all STM32F7xx devices. It includes\r
+ (#) FLASH Memory Erase functions: \r
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r
+ HAL_FLASH_Lock() functions\r
+ (++) Erase function: Erase sector, erase all sectors\r
+ (++) There are two modes of erase :\r
+ (+++) Polling Mode using HAL_FLASHEx_Erase()\r
+ (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\r
+ \r
+ (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :\r
+ (++) Set/Reset the write protection\r
+ (++) Set the Read protection Level\r
+ (++) Set the BOR level\r
+ (++) Program the user Option Bytes\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx FLASHEx\r
+ * @brief FLASH HAL Extension module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Constants\r
+ * @{\r
+ */ \r
+#define SECTOR_MASK ((uint32_t)0xFFFFFF07)\r
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Variables\r
+ * @{\r
+ */ \r
+extern FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Functions\r
+ * @{\r
+ */\r
+/* Option bytes control */\r
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);\r
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);\r
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);\r
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);\r
+static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);\r
+static uint32_t FLASH_OB_GetUser(void);\r
+static uint32_t FLASH_OB_GetWRP(void);\r
+static uint8_t FLASH_OB_GetRDP(void);\r
+static uint32_t FLASH_OB_GetBOR(void);\r
+static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\r
+ uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);\r
+#else\r
+static void FLASH_MassErase(uint8_t VoltageRange);\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\r
+ * @brief Extended IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended programming operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the Extension FLASH \r
+ programming operations Operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors \r
+ * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @param[out] SectorError: pointer to variable that\r
+ * contains the configuration information on faulty sector in case of error \r
+ * (0xFFFFFFFF means that all the sectors have been correctly erased)\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t index = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /*Initialization of SectorError variable*/\r
+ *SectorError = 0xFFFFFFFFU;\r
+ \r
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+ {\r
+ /*Mass erase to be done*/\r
+#if defined (FLASH_OPTCR_nDBANK) \r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r
+#else\r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); \r
+#endif /* FLASH_OPTCR_nDBANK */\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* if the erase operation is completed, disable the MER Bit */\r
+ FLASH->CR &= (~FLASH_MER_BIT);\r
+ }\r
+ else\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r
+\r
+ /* Erase by sector by sector to be done*/\r
+ for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)\r
+ {\r
+ FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the erase operation is completed, disable the SER Bit and SNB Bits */\r
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); \r
+\r
+ if(status != HAL_OK) \r
+ {\r
+ /* In case of error, stop erase procedure and return the faulty sector*/\r
+ *SectorError = index;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled\r
+ * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+ /* Enable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r
+ \r
+ /* Enable Error source interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r
+ \r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\r
+ FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); \r
+ \r
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+ {\r
+ /*Mass erase to be done*/\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;\r
+#if defined (FLASH_OPTCR_nDBANK) \r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r
+#else\r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); \r
+#endif /* FLASH_OPTCR_nDBANK */ \r
+ }\r
+ else\r
+ {\r
+ /* Erase by sector to be done*/\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r
+\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;\r
+ pFlash.NbSectorsToErase = pEraseInit->NbSectors;\r
+ pFlash.Sector = pEraseInit->Sector;\r
+ pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;\r
+\r
+ /*Erase 1st sector and wait for IT*/\r
+ FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program option bytes\r
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r
+\r
+ /* Write protection configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\r
+ {\r
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));\r
+ if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)\r
+ {\r
+ /*Enable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_EnableWRP(pOBInit->WRPSector);\r
+ }\r
+ else\r
+ {\r
+ /*Disable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_DisableWRP(pOBInit->WRPSector);\r
+ }\r
+ }\r
+\r
+ /* Read protection configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\r
+ {\r
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);\r
+ }\r
+\r
+ /* USER configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\r
+ {\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r
+ pOBInit->USERConfig & OB_IWDG_SW,\r
+ pOBInit->USERConfig & OB_STOP_NO_RST,\r
+ pOBInit->USERConfig & OB_STDBY_NO_RST, \r
+ pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r
+ pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,\r
+ pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,\r
+ pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);\r
+#else\r
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r
+ pOBInit->USERConfig & OB_IWDG_SW,\r
+ pOBInit->USERConfig & OB_STOP_NO_RST,\r
+ pOBInit->USERConfig & OB_STDBY_NO_RST, \r
+ pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r
+ pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); \r
+#endif /* FLASH_OPTCR_nDBANK */\r
+ }\r
+ \r
+ /* BOR Level configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)\r
+ {\r
+ status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);\r
+ }\r
+ \r
+ /* Boot 0 Address configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)\r
+ {\r
+ status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);\r
+ }\r
+ \r
+ /* Boot 1 Address configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)\r
+ {\r
+ status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Get the Option byte configuration\r
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\r
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;\r
+\r
+ /*Get WRP*/\r
+ pOBInit->WRPSector = FLASH_OB_GetWRP();\r
+\r
+ /*Get RDP Level*/\r
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();\r
+\r
+ /*Get USER*/\r
+ pOBInit->USERConfig = FLASH_OB_GetUser();\r
+\r
+ /*Get BOR Level*/\r
+ pOBInit->BORLevel = FLASH_OB_GetBOR();\r
+ \r
+ /*Get Boot Address when Boot pin = 0 */\r
+ pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);\r
+ \r
+ /*Get Boot Address when Boot pin = 1 */\r
+ pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+/**\r
+ * @brief Full erase of FLASH memory sectors \r
+ * @param VoltageRange: The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ * @param Banks: Banks to be erased\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_BANK_1: Bank1 to be erased\r
+ * @arg FLASH_BANK_2: Bank2 to be erased\r
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\r
+ *\r
+ * @retval HAL Status\r
+ */\r
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+ assert_param(IS_FLASH_BANK(Banks));\r
+\r
+ /* if the previous operation is completed, proceed to erase all sectors */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ if(Banks == FLASH_BANK_BOTH)\r
+ {\r
+ /* bank1 & bank2 will be erased*/\r
+ FLASH->CR |= FLASH_MER_BIT;\r
+ }\r
+ else if(Banks == FLASH_BANK_2)\r
+ {\r
+ /*Only bank2 will be erased*/\r
+ FLASH->CR |= FLASH_CR_MER2;\r
+ }\r
+ else\r
+ {\r
+ /*Only bank1 will be erased*/\r
+ FLASH->CR |= FLASH_CR_MER1; \r
+ }\r
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Erase the specified FLASH memory sector\r
+ * @param Sector: FLASH sector to erase\r
+ * The value of this parameter depend on device used within the same series \r
+ * @param VoltageRange: The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ * \r
+ * @retval None\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r
+{\r
+ uint32_t tmp_psize = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_SECTOR(Sector));\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+ \r
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_BYTE;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_HALF_WORD;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_WORD;\r
+ }\r
+ else\r
+ {\r
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r
+ }\r
+ \r
+ /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */\r
+ if(Sector > FLASH_SECTOR_11) \r
+ {\r
+ Sector += 4;\r
+ } \r
+\r
+ /* If the previous operation is completed, proceed to erase the sector */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= tmp_psize;\r
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);\r
+ FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH Write Protection Option Bytes value.\r
+ * @retval uint32_t FLASH Write Protection Option Bytes value\r
+ */\r
+static uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));\r
+}\r
+\r
+/**\r
+ * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. \r
+ * @param Wwdg: Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_WWDG_SW: Software WWDG selected\r
+ * @arg OB_WWDG_HW: Hardware WWDG selected\r
+ * @param Iwdg: Selects the WWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param Stop: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param Stdby: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r
+ * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r
+ * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r
+ * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY\r
+ * @param NDBank: Flash Single Bank mode enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)\r
+ * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) \r
+ * @param NDBoot: Flash Dual boot mode disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot\r
+ * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot\r
+\r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\r
+ uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)\r
+{\r
+ uint32_t useroptionmask = 0x00;\r
+ uint32_t useroptionvalue = 0x00;\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r
+ assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r
+ assert_param(IS_OB_STOP_SOURCE(Stop));\r
+ assert_param(IS_OB_STDBY_SOURCE(Stdby));\r
+ assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r
+ assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r
+ assert_param(IS_OB_NDBANK(NDBank));\r
+ assert_param(IS_OB_NDBOOT(NDBoot));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\r
+ FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \\r
+ FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);\r
+ \r
+ useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);\r
+ \r
+ /* Update User Option Byte */ \r
+ MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r
+ }\r
+ \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH User Option Byte value.\r
+ * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r
+ * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r
+ */\r
+static uint32_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));\r
+}\r
+#else\r
+\r
+/**\r
+ * @brief Full erase of FLASH memory sectors \r
+ * @param VoltageRange: The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ *\r
+ * @retval HAL Status\r
+ */\r
+static void FLASH_MassErase(uint8_t VoltageRange)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+\r
+ /* if the previous operation is completed, proceed to erase all sectors */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_CR_MER;\r
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Erase the specified FLASH memory sector\r
+ * @param Sector: FLASH sector to erase\r
+ * The value of this parameter depend on device used within the same series \r
+ * @param VoltageRange: The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ * \r
+ * @retval None\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r
+{\r
+ uint32_t tmp_psize = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_SECTOR(Sector));\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+ \r
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_BYTE;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_HALF_WORD;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_WORD;\r
+ }\r
+ else\r
+ {\r
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r
+ }\r
+\r
+ /* If the previous operation is completed, proceed to erase the sector */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= tmp_psize;\r
+ FLASH->CR &= SECTOR_MASK;\r
+ FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH Write Protection Option Bytes value.\r
+ * @retval uint32_t FLASH Write Protection Option Bytes value\r
+ */\r
+static uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));\r
+}\r
+\r
+/**\r
+ * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. \r
+ * @param Wwdg: Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_WWDG_SW: Software WWDG selected\r
+ * @arg OB_WWDG_HW: Hardware WWDG selected\r
+ * @param Iwdg: Selects the WWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param Stop: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param Stdby: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r
+ * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r
+ * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r
+ * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)\r
+{\r
+ uint32_t useroptionmask = 0x00;\r
+ uint32_t useroptionvalue = 0x00;\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r
+ assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r
+ assert_param(IS_OB_STOP_SOURCE(Stop));\r
+ assert_param(IS_OB_STDBY_SOURCE(Stdby));\r
+ assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r
+ assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\r
+ FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);\r
+ \r
+ useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);\r
+ \r
+ /* Update User Option Byte */ \r
+ MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r
+ }\r
+ \r
+ return status; \r
+\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH User Option Byte value.\r
+ * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r
+ * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r
+ */\r
+static uint32_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));\r
+}\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+/**\r
+ * @brief Enable the write protection of the desired bank1 or bank2 sectors\r
+ *\r
+ * @note When the memory read protection level is selected (RDP level = 1), \r
+ * it is not possible to program or erase the flash sector i if CortexM7 \r
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
+ * \r
+ * @param WRPSector: specifies the sector(s) to be write protected.\r
+ * This parameter can be one of the following values:\r
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r
+ * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r
+ * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)\r
+ * @arg OB_WRP_SECTOR_All\r
+ *\r
+ * @retval HAL FLASH State \r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /*Write protection enabled on sectors */\r
+ FLASH->OPTCR &= (~WRPSector); \r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Disable the write protection of the desired bank1 or bank 2 sectors\r
+ *\r
+ * @note When the memory read protection level is selected (RDP level = 1), \r
+ * it is not possible to program or erase the flash sector i if CortexM4 \r
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
+ * \r
+ * @param WRPSector: specifies the sector(s) to be write protected.\r
+ * This parameter can be one of the following values:\r
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r
+ * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r
+ * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) \r
+ * @arg OB_WRP_Sector_All\r
+ *\r
+ *\r
+ * @retval HAL Status \r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /* Write protection disabled on sectors */\r
+ FLASH->OPTCR |= (WRPSector); \r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Set the read protection level.\r
+ * @param Level: specifies the read protection level.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_RDP_LEVEL_0: No protection\r
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory\r
+ * @arg OB_RDP_LEVEL_2: Full chip protection\r
+ * \r
+ * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP_LEVEL(Level));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ { \r
+ *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Set the BOR Level. \r
+ * @param Level: specifies the Option Bytes BOR Reset Level.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r
+ * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r
+ * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r
+ * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V\r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOR_LEVEL(Level));\r
+\r
+ /* Set the BOR Level */\r
+ MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);\r
+ \r
+ return HAL_OK;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Configure Boot base address.\r
+ * \r
+ * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1\r
+ * This parameter can be one of the following values:\r
+ * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 \r
+ * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 \r
+ * @param Address: specifies Boot base address\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) \r
+ * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r
+ * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) \r
+ * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) \r
+ * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) \r
+ * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) \r
+ * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOOT_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ if(BootOption == OPTIONBYTE_BOOTADDR_0)\r
+ { \r
+ MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);\r
+ }\r
+ else\r
+ {\r
+ MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));\r
+ }\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Read Protection level.\r
+ * @retval FlagStatus FLASH ReadOut Protection Status:\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_RDP_LEVEL_0: No protection\r
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory\r
+ * @arg OB_RDP_LEVEL_2: Full chip protection\r
+ */\r
+static uint8_t FLASH_OB_GetRDP(void)\r
+{\r
+ uint8_t readstatus = OB_RDP_LEVEL_0;\r
+ \r
+ if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)\r
+ {\r
+ readstatus = OB_RDP_LEVEL_0;\r
+ }\r
+ else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)\r
+ {\r
+ readstatus = OB_RDP_LEVEL_2;\r
+ }\r
+ else \r
+ {\r
+ readstatus = OB_RDP_LEVEL_1;\r
+ }\r
+\r
+ return readstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH BOR level.\r
+ * @retval uint32_t The FLASH BOR level:\r
+ * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r
+ * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r
+ * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r
+ * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V \r
+ */\r
+static uint32_t FLASH_OB_GetBOR(void)\r
+{\r
+ /* Return the FLASH BOR level */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x0C));\r
+}\r
+\r
+/**\r
+ * @brief Configure Boot base address.\r
+ * \r
+ * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1\r
+ * This parameter can be one of the following values:\r
+ * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 \r
+ * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 \r
+ * \r
+ * @retval uint32_t Boot Base Address:\r
+ * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) \r
+ * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r
+ * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) \r
+ * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) \r
+ * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) \r
+ * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) \r
+ * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r
+ */\r
+static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)\r
+{ \r
+ uint32_t Address = 0;\r
+ \r
+ /* Return the Boot base Address */\r
+ if(BootOption == OPTIONBYTE_BOOTADDR_0)\r
+ { \r
+ Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;\r
+ }\r
+ else\r
+ {\r
+ Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);\r
+ }\r
+\r
+ return Address;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief GPIO HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### GPIO Peripheral features #####\r
+ ==============================================================================\r
+ [..] \r
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each\r
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\r
+ in several modes:\r
+ (+) Input mode \r
+ (+) Analog mode\r
+ (+) Output mode\r
+ (+) Alternate function mode\r
+ (+) External interrupt/event lines\r
+\r
+ [..] \r
+ During and just after reset, the alternate functions and external interrupt \r
+ lines are not active and the I/O ports are configured in input floating mode.\r
+ \r
+ [..] \r
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be \r
+ activated or not.\r
+\r
+ [..]\r
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
+ type and the IO speed can be selected depending on the VDD value.\r
+\r
+ [..] \r
+ All ports have external interrupt/event capability. To use external interrupt \r
+ lines, the port must be configured in input mode. All available GPIO pins are \r
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
+ \r
+ [..]\r
+ The external interrupt/event controller consists of up to 23 edge detectors \r
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each \r
+ input line can be independently configured to select the type (interrupt or event) \r
+ and the corresponding trigger event (rising or falling or both). Each line can \r
+ also be masked independently. \r
+\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). \r
+\r
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef \r
+ structure.\r
+ (++) In case of Output or alternate function mode selection: the speed is \r
+ configured through "Speed" member from GPIO_InitTypeDef structure.\r
+ (++) In alternate mode is selection, the alternate function connected to the IO\r
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.\r
+ (++) Analog mode is required when a pin is to be used as ADC channel \r
+ or DAC output.\r
+ (++) In case of external interrupt/event selection the "Mode" member from \r
+ GPIO_InitTypeDef structure select the type (interrupt or event) and \r
+ the corresponding trigger event (rising or falling or both).\r
+\r
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority \r
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
+ HAL_NVIC_EnableIRQ().\r
+ \r
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
+ \r
+ (#) To set/reset the level of a pin configured in output mode use \r
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
+ \r
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
+\r
+ \r
+ (#) During and just after reset, the alternate functions are not \r
+ active and the GPIO pins are configured in input floating mode (except JTAG\r
+ pins).\r
+ \r
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose \r
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has \r
+ priority over the GPIO function.\r
+ \r
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off. \r
+ The HSE has priority over the GPIO function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO GPIO\r
+ * @brief GPIO HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+#define GPIO_MODE ((uint32_t)0x00000003U)\r
+#define EXTI_MODE ((uint32_t)0x10000000U)\r
+#define GPIO_MODE_IT ((uint32_t)0x00010000U)\r
+#define GPIO_MODE_EVT ((uint32_t)0x00020000U)\r
+#define RISING_EDGE ((uint32_t)0x00100000U)\r
+#define FALLING_EDGE ((uint32_t)0x00200000U)\r
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)\r
+\r
+#define GPIO_NUMBER ((uint32_t)16U)\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to initialize and de-initialize the GPIOs\r
+ to be ready for use.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains\r
+ * the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
+{\r
+ uint32_t position = 0x00;\r
+ uint32_t ioposition = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t temp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r
+\r
+ /* Configure the port pins */\r
+ for(position = 0; position < GPIO_NUMBER; position++)\r
+ {\r
+ /* Get the IO position */\r
+ ioposition = ((uint32_t)0x01) << position;\r
+ /* Get the current IO position */\r
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;\r
+\r
+ if(iocurrent == ioposition)\r
+ {\r
+ /*--------------------- GPIO Mode Configuration ------------------------*/\r
+ /* In case of Alternate function mode selection */\r
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Alternate function parameter */\r
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r
+ \r
+ /* Configure Alternate function mapped with the current IO */\r
+ temp = GPIOx->AFR[position >> 3];\r
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));\r
+ GPIOx->AFR[position >> 3] = temp;\r
+ }\r
+\r
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r
+ temp = GPIOx->MODER;\r
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));\r
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));\r
+ GPIOx->MODER = temp;\r
+\r
+ /* In case of Output or Alternate function mode selection */\r
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Speed parameter */\r
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
+ /* Configure the IO Speed */\r
+ temp = GPIOx->OSPEEDR; \r
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+ temp |= (GPIO_Init->Speed << (position * 2));\r
+ GPIOx->OSPEEDR = temp;\r
+\r
+ /* Configure the IO Output Type */\r
+ temp = GPIOx->OTYPER;\r
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;\r
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);\r
+ GPIOx->OTYPER = temp;\r
+ }\r
+\r
+ /* Activate the Pull-up or Pull down resistor for the current IO */\r
+ temp = GPIOx->PUPDR;\r
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r
+ temp |= ((GPIO_Init->Pull) << (position * 2));\r
+ GPIOx->PUPDR = temp;\r
+\r
+ /*--------------------- EXTI Mode Configuration ------------------------*/\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r
+ {\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ temp = SYSCFG->EXTICR[position >> 2];\r
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));\r
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));\r
+ SYSCFG->EXTICR[position >> 2] = temp;\r
+\r
+ /* Clear EXTI line configuration */\r
+ temp = EXTI->IMR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->IMR = temp;\r
+\r
+ temp = EXTI->EMR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->EMR = temp;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ temp = EXTI->RTSR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->RTSR = temp;\r
+\r
+ temp = EXTI->FTSR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->FTSR = temp;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)\r
+{\r
+ uint32_t position;\r
+ uint32_t ioposition = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ \r
+ /* Configure the port pins */\r
+ for(position = 0; position < GPIO_NUMBER; position++)\r
+ {\r
+ /* Get the IO position */\r
+ ioposition = ((uint32_t)0x01) << position;\r
+ /* Get the current IO position */\r
+ iocurrent = (GPIO_Pin) & ioposition;\r
+\r
+ if(iocurrent == ioposition)\r
+ {\r
+ /*------------------------- GPIO Mode Configuration --------------------*/\r
+ /* Configure IO Direction in Input Floating Mode */\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));\r
+\r
+ /* Configure the default Alternate Function in current IO */\r
+ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r
+\r
+ /* Configure the default value for IO Speed */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+\r
+ /* Configure the default value IO Output Type */\r
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;\r
+\r
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r
+\r
+ /*------------------------- EXTI Mode Configuration --------------------*/\r
+ tmp = SYSCFG->EXTICR[position >> 2];\r
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));\r
+ if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))\r
+ {\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));\r
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;\r
+\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~((uint32_t)iocurrent);\r
+ EXTI->EMR &= ~((uint32_t)iocurrent);\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~((uint32_t)iocurrent);\r
+ EXTI->FTSR &= ~((uint32_t)iocurrent);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions \r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_PIN_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ GPIO_PinState bitstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\r
+ {\r
+ bitstatus = GPIO_PIN_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = GPIO_PIN_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ *\r
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify\r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ *\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @param PinState: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the GPIO_PinState enum values:\r
+ * @arg GPIO_PIN_RESET: to clear the port pin\r
+ * @arg GPIO_PIN_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_PIN_ACTION(PinState));\r
+\r
+ if(PinState != GPIO_PIN_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Toggles the specified GPIO pins.\r
+ * @param GPIOx: Where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the pins to be toggled.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ GPIOx->ODR ^= GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * @note The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family\r
+ * @param GPIO_Pin: specifies the port bit to be locked.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ /* Apply lock key write sequence */\r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+\r
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)\r
+ {\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles EXTI interrupt request.\r
+ * @param GPIO_Pin: Specifies the pins connected EXTI line\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
+{\r
+ /* EXTI line interrupt detected */\r
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)\r
+ {\r
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief EXTI line detection callbacks.\r
+ * @param GPIO_Pin: Specifies the pins connected EXTI line\r
+ * @retval None\r
+ */\r
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(GPIO_Pin);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hash.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief HASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the HASH peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + HASH/HMAC Processing functions by algorithm using polling mode\r
+ * + HASH/HMAC functions by algorithm using interrupt mode\r
+ * + HASH/HMAC functions by algorithm using DMA mode\r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The HASH HAL driver can be used as follows:\r
+ (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r
+ (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())\r
+ (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable one DMA stream one for managing data transfer from\r
+ memory to peripheral (input stream). Managing data transfer from\r
+ peripheral to memory can be performed only using CPU\r
+ (+++) Associate the initialized DMA handle to the HASH DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r
+ (##) For HMAC, the encryption key.\r
+ (##) For HMAC, the key size used for encryption.\r
+ (#)Three processing functions are available:\r
+ (##) Polling mode: processing APIs are blocking functions\r
+ i.e. they process the data and wait till the digest computation is finished\r
+ e.g. HAL_HASH_SHA1_Start()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt\r
+ e.g. HAL_HASH_SHA1_Start_IT()\r
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is\r
+ not used for data transfer i.e. the data transfer is ensured by DMA\r
+ e.g. HAL_HASH_SHA1_Start_DMA()\r
+ (#)When the processing function is called at first time after HAL_HASH_Init()\r
+ the HASH peripheral is initialized and processes the buffer in input.\r
+ After that, the digest computation is started.\r
+ When processing multi-buffer use the accumulate function to write the\r
+ data in the peripheral without starting the digest computation. In last \r
+ buffer use the start function to input the last buffer ans start the digest\r
+ computation.\r
+ (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r
+ (##) write (n-1)th data buffer in the peripheral without starting the digest computation\r
+ (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation\r
+ (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r
+ (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().\r
+ After that, call the finish function in order to get the digest value\r
+ e.g. HAL_HASH_SHA1_Finish()\r
+ (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+\r
+/** @defgroup HASH HASH\r
+ * @brief HASH HAL module driver.\r
+ * @{\r
+ */\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup HASH_Private_Functions HASH Private Functions\r
+ * @{\r
+ */\r
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);\r
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);\r
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup HASH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA HASH Input Data complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ uint32_t inputaddr = 0;\r
+ uint32_t buffersize = 0;\r
+ \r
+ if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ else\r
+ {\r
+ /* Increment Interrupt counter */\r
+ hhash->HashInCount++;\r
+ /* Disable the DMA transfer before starting the next transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ if(hhash->HashInCount <= 2)\r
+ {\r
+ /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r
+ if(hhash->HashInCount == 1)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ buffersize = hhash->HashBuffSize;\r
+ }\r
+ /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r
+ else if(hhash->HashInCount == 2)\r
+ {\r
+ inputaddr = (uint32_t)hhash->Init.pKey;\r
+ buffersize = hhash->Init.KeySize;\r
+ }\r
+ /* Configure the number of valid bits in last word of the message */\r
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));\r
+ \r
+ /* Set the HASH DMA transfer complete */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Reset the InCount */\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA HASH communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hhash->State= HAL_HASH_STATE_READY;\r
+ HAL_HASH_ErrorCallback(hhash);\r
+}\r
+\r
+/**\r
+ * @brief Writes the input buffer in data register.\r
+ * @param pInBuffer: Pointer to input buffer\r
+ * @param Size: The size of input buffer\r
+ * @retval None\r
+ */\r
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t buffercounter;\r
+ uint32_t inputaddr = (uint32_t) pInBuffer;\r
+ \r
+ for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Provides the message digest result.\r
+ * @param pMsgDigest: Pointer to the message digest\r
+ * @param Size: The size of the message digest in bytes\r
+ * @retval None\r
+ */\r
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r
+{\r
+ uint32_t msgdigest = (uint32_t)pMsgDigest;\r
+ \r
+ switch(Size)\r
+ {\r
+ case 16:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ break;\r
+ case 20:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ break;\r
+ case 28:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ break;\r
+ case 32:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HASH_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the HASH according to the specified parameters \r
+ in the HASH_InitTypeDef and creates the associated handle.\r
+ (+) DeInitialize the HASH peripheral.\r
+ (+) Initialize the HASH MSP.\r
+ (+) DeInitialize HASH MSP. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH according to the specified parameters in the\r
+ HASH_HandleTypeDef and creates the associated handle.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* Check the hash handle allocation */\r
+ if(hhash == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));\r
+ \r
+ if(hhash->State == HAL_HASH_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hhash->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_HASH_MspInit(hhash);\r
+ }\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Reset HashInCount, HashBuffSize and HashITCounter */\r
+ hhash->HashInCount = 0;\r
+ hhash->HashBuffSize = 0;\r
+ hhash->HashITCounter = 0;\r
+ \r
+ /* Set the data type */\r
+ HASH->CR |= (uint32_t) (hhash->Init.DataType);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Set the default HASH phase */\r
+ hhash->Phase = HAL_HASH_PHASE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the HASH peripheral.\r
+ * @note This API must be called before starting a new processing. \r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)\r
+{ \r
+ /* Check the HASH handle allocation */\r
+ if(hhash == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Set the default HASH phase */\r
+ hhash->Phase = HAL_HASH_PHASE_READY;\r
+ \r
+ /* Reset HashInCount, HashBuffSize and HashITCounter */\r
+ hhash->HashInCount = 0;\r
+ hhash->HashBuffSize = 0;\r
+ hhash->HashITCounter = 0;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_HASH_MspDeInit(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hhash);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH MSP.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhash);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes HASH MSP.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhash);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input data transfer complete callback.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhash);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_InCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Data transfer Error callback.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhash);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Digest computation complete callback. It is used only with interrupt.\r
+ * @note This callback is not relevant with DMA.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhash);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_DgstCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode \r
+ * @brief processing functions using polling mode \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using polling mode functions#####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the hash value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware\r
+ * and appending the input buffer is no more possible.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r
+ * @param Timeout: Timeout value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 16);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware\r
+ * and appending the input buffer is no more possible.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 20);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode\r
+ * @brief processing functions using interrupt mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using interrupt mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in interrupt mode\r
+ the hash value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+\r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Reset interrupt counter */\r
+ hhash->HashITCounter = 0;\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r
+ \r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ \r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount = 0;\r
+ hhash->pHashInBuffPtr+= hhash->HashInCount;\r
+ }\r
+ /* Set Interrupt counter */\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ else if ((inputcounter < 4) && (inputcounter != 0))\r
+ {\r
+ inputcounter = 4;\r
+ }\r
+ \r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Reset interrupt counter */\r
+ hhash->HashITCounter = 0;\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);\r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ \r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount = 0;\r
+ hhash->pHashInBuffPtr+= hhash->HashInCount;\r
+ }\r
+ /* Set Interrupt counter */\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ else if ((inputcounter < 4) && (inputcounter != 0))\r
+ {\r
+ inputcounter = 4;\r
+ }\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles HASH interrupt request.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)\r
+{\r
+ switch(HASH->CR & HASH_CR_ALGO)\r
+ {\r
+ case HASH_ALGOSELECTION_MD5:\r
+ HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case HASH_ALGOSELECTION_SHA1:\r
+ HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode\r
+ * @brief processing functions using DMA mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using DMA mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the hash value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in MD5 mode\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 16);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in SHA1 mode.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. \r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 20);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process UnLock */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode \r
+ * @brief HMAC processing functions using polling mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using polling mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 16);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */ \r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 20);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode \r
+ * @brief HMAC processing functions using DMA mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using DMA mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the HASH state\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval HAL state\r
+ */\r
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)\r
+{\r
+ return hhash->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hash_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief HASH HAL Extension module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of HASH peripheral:\r
+ * + Extended HASH processing functions based on SHA224 Algorithm\r
+ * + Extended HASH processing functions based on SHA256 Algorithm\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The HASH HAL driver can be used as follows:\r
+ (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r
+ (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())\r
+ (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable one DMA stream one for managing data transfer from\r
+ memory to peripheral (input stream). Managing data transfer from\r
+ peripheral to memory can be performed only using CPU\r
+ (+++) Associate the initialized DMA handle to the HASH DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r
+ (##) For HMAC, the encryption key.\r
+ (##) For HMAC, the key size used for encryption.\r
+ (#)Three processing functions are available:\r
+ (##) Polling mode: processing APIs are blocking functions\r
+ i.e. they process the data and wait till the digest computation is finished\r
+ e.g. HAL_HASHEx_SHA224_Start()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt\r
+ e.g. HAL_HASHEx_SHA224_Start_IT()\r
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is\r
+ not used for data transfer i.e. the data transfer is ensured by DMA\r
+ e.g. HAL_HASHEx_SHA224_Start_DMA()\r
+ (#)When the processing function is called at first time after HAL_HASH_Init()\r
+ the HASH peripheral is initialized and processes the buffer in input.\r
+ After that, the digest computation is started.\r
+ When processing multi-buffer use the accumulate function to write the\r
+ data in the peripheral without starting the digest computation. In last \r
+ buffer use the start function to input the last buffer ans start the digest\r
+ computation.\r
+ (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r
+ (##) write (n-1)th data buffer in the peripheral without starting the digest computation\r
+ (##) HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation\r
+ (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r
+ (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().\r
+ After that, call the finish function in order to get the digest value\r
+ e.g. HAL_HASHEx_SHA224_Finish()\r
+ (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+\r
+/** @defgroup HASHEx HASHEx\r
+ * @brief HASH Extension HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup HASHEx_Private_Functions\r
+ * @{\r
+ */\r
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);\r
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);\r
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup HASHEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes the input buffer in data register.\r
+ * @param pInBuffer: Pointer to input buffer\r
+ * @param Size: The size of input buffer\r
+ * @retval None\r
+ */\r
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t buffercounter;\r
+ uint32_t inputaddr = (uint32_t) pInBuffer;\r
+ \r
+ for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Provides the message digest result.\r
+ * @param pMsgDigest: Pointer to the message digest\r
+ * @param Size: The size of the message digest in bytes\r
+ * @retval None\r
+ */\r
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r
+{\r
+ uint32_t msgdigest = (uint32_t)pMsgDigest;\r
+ \r
+ switch(Size)\r
+ {\r
+ case 16:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ break;\r
+ case 20:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ break;\r
+ case 28:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ break;\r
+ case 32:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA HASH Input Data complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ uint32_t inputaddr = 0;\r
+ uint32_t buffersize = 0;\r
+ \r
+ if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ else\r
+ {\r
+ /* Increment Interrupt counter */\r
+ hhash->HashInCount++;\r
+ /* Disable the DMA transfer before starting the next transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ if(hhash->HashInCount <= 2)\r
+ {\r
+ /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r
+ if(hhash->HashInCount == 1)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ buffersize = hhash->HashBuffSize;\r
+ }\r
+ /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r
+ else if(hhash->HashInCount == 2)\r
+ {\r
+ inputaddr = (uint32_t)hhash->Init.pKey;\r
+ buffersize = hhash->Init.KeySize;\r
+ }\r
+ /* Configure the number of valid bits in last word of the message */\r
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));\r
+ \r
+ /* Set the HASH DMA transfer complete */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Reset the InCount */\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA HASH communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hhash->State= HAL_HASH_STATE_READY;\r
+ HAL_HASH_ErrorCallback(hhash);\r
+}\r
+\r
+ /**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HASHEx_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup HASHEx_Group1 HASH processing functions \r
+ * @brief processing functions using polling mode \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using polling mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the hash value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 28);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 32);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode \r
+ * @brief HMAC processing functions using polling mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using polling mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 28);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r
+ }\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 32);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode\r
+ * @brief processing functions using interrupt mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using interrupt functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in interrupt mode\r
+ the hash value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+\r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ /* Reset interrupt counter */\r
+ hhash->HashITCounter = 0;\r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);\r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount = 0;\r
+ hhash->pHashInBuffPtr+= hhash->HashInCount;\r
+ }\r
+ /* Set Interrupt counter */\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ else if ((inputcounter < 4) && (inputcounter != 0))\r
+ {\r
+ inputcounter = 4;\r
+ }\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+\r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Reset interrupt counter */\r
+ hhash->HashITCounter = 0;\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);\r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ \r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount = 0;\r
+ hhash->pHashInBuffPtr+= hhash->HashInCount;\r
+ }\r
+ /* Set Interrupt counter */\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ else if ((inputcounter < 4) && (inputcounter != 0))\r
+ {\r
+ inputcounter = 4;\r
+ }\r
+ \r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles HASH interrupt request.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)\r
+{\r
+ switch(HASH->CR & HASH_CR_ALGO)\r
+ {\r
+ \r
+ case HASH_ALGOSELECTION_SHA224:\r
+ HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case HASH_ALGOSELECTION_SHA256:\r
+ HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode\r
+ * @brief processing functions using DMA mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using DMA functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the hash value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in SHA224\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 28);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process UnLock */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in SHA256.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 32);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode \r
+ * @brief HMAC processing functions using DMA mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using DMA functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r
+ }\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hcd.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief HCD HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a HCD_HandleTypeDef handle structure, for example:\r
+ HCD_HandleTypeDef hhcd;\r
+ \r
+ (#)Fill parameters of Init structure in HCD handle\r
+ \r
+ (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) \r
+\r
+ (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:\r
+ (##) Enable the HCD/USB Low Level interface clock using the following macros\r
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)\r
+ (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)\r
+ \r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure HCD pin-out\r
+ (##) Configure HCD NVIC interrupt\r
+ \r
+ (#)Associate the Upper USB Host stack to the HAL HCD Driver:\r
+ (##) hhcd.pData = phost;\r
+\r
+ (#)Enable HCD transmission and reception:\r
+ (##) HAL_HCD_Start();\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HCD HCD \r
+ * @brief HCD HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function ----------------------------------------------------------*/\r
+/** @defgroup HCD_Private_Functions HCD Private Functions\r
+ * @{\r
+ */\r
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); \r
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);\r
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup HCD_Exported_Functions HCD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the host driver.\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)\r
+{ \r
+ /* Check the HCD handle allocation */\r
+ if(hhcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));\r
+\r
+ hhcd->State = HAL_HCD_STATE_BUSY;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+ HAL_HCD_MspInit(hhcd);\r
+\r
+ /* Disable the Interrupts */\r
+ __HAL_HCD_DISABLE(hhcd);\r
+ \r
+ /*Init the Core (common init.) */\r
+ USB_CoreInit(hhcd->Instance, hhcd->Init);\r
+ \r
+ /* Force Host Mode*/\r
+ USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);\r
+ \r
+ /* Init Host */\r
+ USB_HostInit(hhcd->Instance, hhcd->Init);\r
+ \r
+ hhcd->State= HAL_HCD_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize a host channel.\r
+ * @param hhcd: HCD handle\r
+ * @param ch_num: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param epnum: Endpoint number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param dev_address : Current device address\r
+ * This parameter can be a value from 0 to 255\r
+ * @param speed: Current device speed.\r
+ * This parameter can be one of these values:\r
+ * HCD_SPEED_HIGH: High speed mode,\r
+ * HCD_SPEED_FULL: Full speed mode,\r
+ * HCD_SPEED_LOW: Low speed mode\r
+ * @param ep_type: Endpoint Type.\r
+ * This parameter can be one of these values:\r
+ * EP_TYPE_CTRL: Control type,\r
+ * EP_TYPE_ISOC: Isochronous type,\r
+ * EP_TYPE_BULK: Bulk type,\r
+ * EP_TYPE_INTR: Interrupt type\r
+ * @param mps: Max Packet Size.\r
+ * This parameter can be a value from 0 to32K\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, \r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ __HAL_LOCK(hhcd); \r
+ \r
+ hhcd->hc[ch_num].dev_addr = dev_address;\r
+ hhcd->hc[ch_num].max_packet = mps;\r
+ hhcd->hc[ch_num].ch_num = ch_num;\r
+ hhcd->hc[ch_num].ep_type = ep_type;\r
+ hhcd->hc[ch_num].ep_num = epnum & 0x7F;\r
+ hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);\r
+ hhcd->hc[ch_num].speed = speed;\r
+\r
+ status = USB_HC_Init(hhcd->Instance, \r
+ ch_num,\r
+ epnum,\r
+ dev_address,\r
+ speed,\r
+ ep_type,\r
+ mps);\r
+ __HAL_UNLOCK(hhcd); \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Halt a host channel.\r
+ * @param hhcd: HCD handle\r
+ * @param ch_num: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ __HAL_LOCK(hhcd); \r
+ USB_HC_Halt(hhcd->Instance, ch_num); \r
+ __HAL_UNLOCK(hhcd);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the host driver.\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* Check the HCD handle allocation */\r
+ if(hhcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ hhcd->State = HAL_HCD_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_HCD_MspDeInit(hhcd);\r
+ \r
+ __HAL_HCD_DISABLE(hhcd);\r
+ \r
+ hhcd->State = HAL_HCD_STATE_RESET; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the HCD MSP.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the HCD MSP.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions\r
+ * @brief HCD IO operation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data \r
+ Transfer\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief Submit a new URB for processing. \r
+ * @param hhcd: HCD handle\r
+ * @param ch_num: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param direction: Channel number.\r
+ * This parameter can be one of these values:\r
+ * 0 : Output / 1 : Input\r
+ * @param ep_type: Endpoint Type.\r
+ * This parameter can be one of these values:\r
+ * EP_TYPE_CTRL: Control type/\r
+ * EP_TYPE_ISOC: Isochronous type/\r
+ * EP_TYPE_BULK: Bulk type/\r
+ * EP_TYPE_INTR: Interrupt type/\r
+ * @param token: Endpoint Type.\r
+ * This parameter can be one of these values:\r
+ * 0: HC_PID_SETUP / 1: HC_PID_DATA1\r
+ * @param pbuff: pointer to URB data\r
+ * @param length: Length of URB data\r
+ * @param do_ping: activate do ping protocol (for high speed only).\r
+ * This parameter can be one of these values:\r
+ * 0 : do ping inactive / 1 : do ping active \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,\r
+ uint8_t ch_num, \r
+ uint8_t direction ,\r
+ uint8_t ep_type, \r
+ uint8_t token, \r
+ uint8_t* pbuff, \r
+ uint16_t length,\r
+ uint8_t do_ping) \r
+{\r
+ hhcd->hc[ch_num].ep_is_in = direction;\r
+ hhcd->hc[ch_num].ep_type = ep_type; \r
+ \r
+ if(token == 0)\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_SETUP;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r
+ }\r
+ \r
+ /* Manage Data Toggle */\r
+ switch(ep_type)\r
+ {\r
+ case EP_TYPE_CTRL:\r
+ if((token == 1) && (direction == 0)) /*send data */\r
+ {\r
+ if ( length == 0 )\r
+ { /* For Status OUT stage, Length==0, Status Out PID = 1 */\r
+ hhcd->hc[ch_num].toggle_out = 1;\r
+ }\r
+ \r
+ /* Set the Data Toggle bit as per the Flag */\r
+ if ( hhcd->hc[ch_num].toggle_out == 0)\r
+ { /* Put the PID 0 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; \r
+ }\r
+ else\r
+ { /* Put the PID 1 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r
+ }\r
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)\r
+ {\r
+ hhcd->hc[ch_num].do_ping = do_ping;\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case EP_TYPE_BULK:\r
+ if(direction == 0)\r
+ {\r
+ /* Set the Data Toggle bit as per the Flag */\r
+ if ( hhcd->hc[ch_num].toggle_out == 0)\r
+ { /* Put the PID 0 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; \r
+ }\r
+ else\r
+ { /* Put the PID 1 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r
+ }\r
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)\r
+ {\r
+ hhcd->hc[ch_num].do_ping = do_ping;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( hhcd->hc[ch_num].toggle_in == 0)\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r
+ }\r
+ }\r
+ \r
+ break;\r
+ case EP_TYPE_INTR:\r
+ if(direction == 0)\r
+ {\r
+ /* Set the Data Toggle bit as per the Flag */\r
+ if ( hhcd->hc[ch_num].toggle_out == 0)\r
+ { /* Put the PID 0 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; \r
+ }\r
+ else\r
+ { /* Put the PID 1 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( hhcd->hc[ch_num].toggle_in == 0)\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case EP_TYPE_ISOC: \r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r
+ break; \r
+ }\r
+ \r
+ hhcd->hc[ch_num].xfer_buff = pbuff;\r
+ hhcd->hc[ch_num].xfer_len = length;\r
+ hhcd->hc[ch_num].urb_state = URB_IDLE; \r
+ hhcd->hc[ch_num].xfer_count = 0 ;\r
+ hhcd->hc[ch_num].ch_num = ch_num;\r
+ hhcd->hc[ch_num].state = HC_IDLE;\r
+ \r
+ return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);\r
+}\r
+\r
+/**\r
+ * @brief Handle HCD interrupt request.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r
+ uint32_t i = 0 , interrupt = 0;\r
+ \r
+ /* ensure that we are in device mode */\r
+ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)\r
+ {\r
+ /* avoid spurious interrupt */\r
+ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) \r
+ {\r
+ return;\r
+ }\r
+ \r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r
+ }\r
+ \r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);\r
+ }\r
+\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);\r
+ } \r
+ \r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);\r
+ } \r
+ \r
+ /* Handle Host Disconnect Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))\r
+ {\r
+ \r
+ /* Cleanup HPRT */\r
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ /* Handle Host Port Interrupts */\r
+ HAL_HCD_Disconnect_Callback(hhcd);\r
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);\r
+ }\r
+ \r
+ /* Handle Host Port Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))\r
+ {\r
+ HCD_Port_IRQHandler (hhcd);\r
+ }\r
+ \r
+ /* Handle Host SOF Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))\r
+ {\r
+ HAL_HCD_SOF_Callback(hhcd);\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);\r
+ }\r
+ \r
+ /* Handle Host channel Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))\r
+ {\r
+ interrupt = USB_HC_ReadInterrupt(hhcd->Instance);\r
+ for (i = 0; i < hhcd->Init.Host_channels ; i++)\r
+ {\r
+ if (interrupt & (1 << i))\r
+ {\r
+ if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)\r
+ {\r
+ HCD_HC_IN_IRQHandler (hhcd, i);\r
+ }\r
+ else\r
+ {\r
+ HCD_HC_OUT_IRQHandler (hhcd, i);\r
+ }\r
+ }\r
+ }\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);\r
+ } \r
+ \r
+ /* Handle Rx Queue Level Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))\r
+ {\r
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ \r
+ HCD_RXQLVL_IRQHandler (hhcd);\r
+ \r
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief SOF callback.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_SOF_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Connection Event callback.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_Connect_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Disconnection Event callback.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file\r
+ */\r
+} \r
+\r
+/**\r
+ * @brief Notify URB state change callback.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param urb_state:\r
+ * This parameter can be one of these values:\r
+ * URB_IDLE/\r
+ * URB_DONE/\r
+ * URB_NOTREADY/\r
+ * URB_NYET/ \r
+ * URB_ERROR/ \r
+ * URB_STALL/ \r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hhcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions \r
+ * @brief Management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the HCD data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start the host driver.\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)\r
+{ \r
+ __HAL_LOCK(hhcd); \r
+ __HAL_HCD_ENABLE(hhcd);\r
+ USB_DriveVbus(hhcd->Instance, 1); \r
+ __HAL_UNLOCK(hhcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the host driver.\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)\r
+{ \r
+ __HAL_LOCK(hhcd); \r
+ USB_StopHost(hhcd->Instance);\r
+ __HAL_UNLOCK(hhcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reset the host port.\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return (USB_ResetPort(hhcd->Instance));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the HCD handle state.\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL state\r
+ */\r
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return hhcd->State;\r
+}\r
+\r
+/**\r
+ * @brief Return URB state for a channel.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval URB state.\r
+ * This parameter can be one of these values:\r
+ * URB_IDLE/\r
+ * URB_DONE/\r
+ * URB_NOTREADY/\r
+ * URB_NYET/ \r
+ * URB_ERROR/ \r
+ * URB_STALL\r
+ */\r
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ return hhcd->hc[chnum].urb_state;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the last host transfer size.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval last transfer size in byte\r
+ */\r
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ return hhcd->hc[chnum].xfer_count; \r
+}\r
+ \r
+/**\r
+ * @brief Return the Host Channel state.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval Host channel state\r
+ * This parameter can be one of these values:\r
+ * HC_IDLE/\r
+ * HC_XFRC/\r
+ * HC_HALTED/\r
+ * HC_NYET/ \r
+ * HC_NAK/ \r
+ * HC_STALL/ \r
+ * HC_XACTERR/ \r
+ * HC_BBLERR/ \r
+ * HC_DATATGLERR \r
+ */\r
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ return hhcd->hc[chnum].state;\r
+}\r
+\r
+/**\r
+ * @brief Return the current Host frame number.\r
+ * @param hhcd: HCD handle\r
+ * @retval Current Host frame number\r
+ */\r
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return (USB_GetCurrentFrame(hhcd->Instance));\r
+}\r
+\r
+/**\r
+ * @brief Return the Host enumeration speed.\r
+ * @param hhcd: HCD handle\r
+ * @retval Enumeration speed\r
+ */\r
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return (USB_GetHostSpeed(hhcd->Instance));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HCD_Private_Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Handle Host Channel IN interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval none\r
+ */\r
+static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ } \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) \r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ hhcd->hc[chnum].state = HC_STALL;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ }\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); \r
+ hhcd->hc[chnum].state = HC_DATATGLERR;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);\r
+ } \r
+ \r
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)\r
+ {\r
+ \r
+ if (hhcd->Init.dma_enable)\r
+ {\r
+ hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \\r
+ (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);\r
+ }\r
+ \r
+ hhcd->hc[chnum].state = HC_XFRC;\r
+ hhcd->hc[chnum].ErrCnt = 0;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);\r
+ \r
+ \r
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ \r
+ }\r
+ else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)\r
+ {\r
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;\r
+ hhcd->hc[chnum].urb_state = URB_DONE; \r
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);\r
+ }\r
+ hhcd->hc[chnum].toggle_in ^= 1;\r
+ \r
+ }\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)\r
+ {\r
+ __HAL_HCD_MASK_HALT_HC_INT(chnum); \r
+ \r
+ if(hhcd->hc[chnum].state == HC_XFRC)\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_DONE; \r
+ }\r
+ \r
+ else if (hhcd->hc[chnum].state == HC_STALL) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_STALL;\r
+ } \r
+ \r
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||\r
+ (hhcd->hc[chnum].state == HC_DATATGLERR))\r
+ {\r
+ if(hhcd->hc[chnum].ErrCnt++ > 3)\r
+ { \r
+ hhcd->hc[chnum].ErrCnt = 0;\r
+ hhcd->hc[chnum].urb_state = URB_ERROR;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ }\r
+ \r
+ /* re-activate the channel */\r
+ tmpreg = USBx_HC(chnum)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(chnum)->HCCHAR = tmpreg; \r
+ }\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);\r
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);\r
+ } \r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ hhcd->hc[chnum].ErrCnt++;\r
+ hhcd->hc[chnum].state = HC_XACTERR;\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);\r
+ }\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)\r
+ { \r
+ if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ }\r
+ else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r
+ {\r
+ /* re-activate the channel */\r
+ tmpreg = USBx_HC(chnum)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(chnum)->HCCHAR = tmpreg;\r
+ }\r
+ hhcd->hc[chnum].state = HC_NAK;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle Host Channel OUT interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval none\r
+ */\r
+static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ } \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);\r
+ \r
+ if( hhcd->hc[chnum].do_ping == 1)\r
+ {\r
+ hhcd->hc[chnum].state = HC_NYET; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ }\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)\r
+ {\r
+ hhcd->hc[chnum].state = HC_NYET;\r
+ hhcd->hc[chnum].ErrCnt= 0; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);\r
+ \r
+ } \r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)\r
+ {\r
+ hhcd->hc[chnum].ErrCnt = 0; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);\r
+ hhcd->hc[chnum].state = HC_XFRC;\r
+\r
+ } \r
+\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) \r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].state = HC_STALL; \r
+ }\r
+\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)\r
+ { \r
+ hhcd->hc[chnum].ErrCnt = 0; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].state = HC_NAK;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ }\r
+\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].state = HC_XACTERR; \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); \r
+ hhcd->hc[chnum].state = HC_DATATGLERR;\r
+ }\r
+ \r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)\r
+ {\r
+ __HAL_HCD_MASK_HALT_HC_INT(chnum); \r
+ \r
+ if(hhcd->hc[chnum].state == HC_XFRC)\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_DONE;\r
+ if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)\r
+ {\r
+ hhcd->hc[chnum].toggle_out ^= 1; \r
+ } \r
+ }\r
+ else if (hhcd->hc[chnum].state == HC_NAK) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ } \r
+ \r
+ else if (hhcd->hc[chnum].state == HC_NYET) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ hhcd->hc[chnum].do_ping = 0;\r
+ } \r
+ \r
+ else if (hhcd->hc[chnum].state == HC_STALL) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_STALL;\r
+ } \r
+ \r
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||\r
+ (hhcd->hc[chnum].state == HC_DATATGLERR))\r
+ {\r
+ if(hhcd->hc[chnum].ErrCnt++ > 3)\r
+ { \r
+ hhcd->hc[chnum].ErrCnt = 0;\r
+ hhcd->hc[chnum].urb_state = URB_ERROR;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ }\r
+ \r
+ /* re-activate the channel */\r
+ tmpreg = USBx_HC(chnum)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(chnum)->HCCHAR = tmpreg; \r
+ }\r
+ \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);\r
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); \r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Handle Rx Queue Level interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @retval none\r
+ */\r
+static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; \r
+ uint8_t channelnum =0; \r
+ uint32_t pktsts;\r
+ uint32_t pktcnt; \r
+ uint32_t temp = 0;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ temp = hhcd->Instance->GRXSTSP ;\r
+ channelnum = temp & USB_OTG_GRXSTSP_EPNUM; \r
+ pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;\r
+ pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ \r
+ switch (pktsts)\r
+ {\r
+ case GRXSTS_PKTSTS_IN:\r
+ /* Read the data into the host buffer. */\r
+ if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0))\r
+ { \r
+ \r
+ USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);\r
+ \r
+ /*manage multiple Xfer */\r
+ hhcd->hc[channelnum].xfer_buff += pktcnt; \r
+ hhcd->hc[channelnum].xfer_count += pktcnt;\r
+ \r
+ if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)\r
+ {\r
+ /* re-activate the channel when more packets are expected */\r
+ tmpreg = USBx_HC(channelnum)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(channelnum)->HCCHAR = tmpreg;\r
+ hhcd->hc[channelnum].toggle_in ^= 1;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:\r
+ break;\r
+ case GRXSTS_PKTSTS_IN_XFER_COMP:\r
+ case GRXSTS_PKTSTS_CH_HALTED:\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle Host Port interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; \r
+ __IO uint32_t hprt0, hprt0_dup;\r
+ \r
+ /* Handle Host Port Interrupts */\r
+ hprt0 = USBx_HPRT0;\r
+ hprt0_dup = USBx_HPRT0;\r
+ \r
+ hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ /* Check whether Port Connect detected */\r
+ if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)\r
+ { \r
+ if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)\r
+ {\r
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);\r
+ HAL_HCD_Connect_Callback(hhcd);\r
+ }\r
+ hprt0_dup |= USB_OTG_HPRT_PCDET;\r
+ \r
+ }\r
+ \r
+ /* Check whether Port Enable Changed */\r
+ if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)\r
+ {\r
+ hprt0_dup |= USB_OTG_HPRT_PENCHNG;\r
+ \r
+ if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)\r
+ { \r
+ if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)\r
+ {\r
+ if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))\r
+ {\r
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );\r
+ }\r
+ else\r
+ {\r
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(hhcd->Init.speed == HCD_SPEED_FULL)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)60000;\r
+ }\r
+ }\r
+ HAL_HCD_Connect_Callback(hhcd);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Cleanup HPRT */\r
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); \r
+ } \r
+ }\r
+ \r
+ /* Check For an overcurrent */\r
+ if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)\r
+ {\r
+ hprt0_dup |= USB_OTG_HPRT_POCCHNG;\r
+ }\r
+\r
+ /* Clear Port Interrupts */\r
+ USBx_HPRT0 = hprt0_dup;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief I2C HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The I2C HAL driver can be used as follows:\r
+ \r
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:\r
+ I2C_HandleTypeDef hi2c;\r
+\r
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:\r
+ (##) Enable the I2Cx interface clock\r
+ (##) I2C pins configuration\r
+ (+++) Enable the clock for the I2C GPIOs\r
+ (+++) Configure I2C pins as alternate function open-drain\r
+ (##) NVIC configuration if you need to use interrupt process\r
+ (+++) Configure the I2Cx interrupt priority\r
+ (+++) Enable the NVIC I2C IRQ Channel\r
+ (##) DMA Configuration if you need to use DMA process\r
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream\r
+ (+++) Enable the DMAx interface clock using\r
+ (+++) Configure the DMA handle parameters\r
+ (+++) Configure the DMA Tx or Rx stream\r
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on\r
+ the DMA Tx or Rx stream\r
+\r
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,\r
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.\r
+\r
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware\r
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.\r
+\r
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()\r
+\r
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()\r
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()\r
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()\r
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()\r
+\r
+ *** Polling mode IO MEM operation ***\r
+ =====================================\r
+ [..]\r
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()\r
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()\r
+\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()\r
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()\r
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()\r
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()\r
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r
+ (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()\r
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r
+ This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+\r
+ *** Interrupt mode IO sequential operation ***\r
+ ===================================\r
+ [..]\r
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition\r
+ when a direction change during transfer\r
+ [..]\r
+ (+) A specific option field manage the different steps of a sequential transfer\r
+ (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:\r
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode\r
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address\r
+ and data to transfer without a final stop condition\r
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address\r
+ and with new data to transfer if the direction change or manage only the new data to transfer\r
+ if no direction change and without a final stop condition in both cases\r
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address\r
+ and with new data to transfer if the direction change or manage only the new data to transfer\r
+ if no direction change and with a final stop condition in both cases\r
+\r
+ (+) Differents sequential I2C interfaces are listed below:\r
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()\r
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()\r
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r
+ (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit\r
+ (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive\r
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()\r
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can\r
+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).\r
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()\r
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()\r
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()\r
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r
+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r
+ (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r
+ This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+ *** Interrupt mode IO MEM operation ***\r
+ =======================================\r
+ [..]\r
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using\r
+ HAL_I2C_Mem_Write_IT()\r
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()\r
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using\r
+ HAL_I2C_Mem_Read_IT()\r
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r
+\r
+ *** DMA mode IO operation ***\r
+ ==============================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using\r
+ HAL_I2C_Master_Transmit_DMA()\r
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using\r
+ HAL_I2C_Master_Receive_DMA()\r
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using\r
+ HAL_I2C_Slave_Transmit_DMA()\r
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using\r
+ HAL_I2C_Slave_Receive_DMA()\r
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r
+ (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()\r
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r
+ This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+ *** DMA mode IO MEM operation ***\r
+ =================================\r
+ [..]\r
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using\r
+ HAL_I2C_Mem_Write_DMA()\r
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()\r
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using\r
+ HAL_I2C_Mem_Read_DMA()\r
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r
+\r
+\r
+ *** I2C HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in I2C HAL driver.\r
+\r
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral\r
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral\r
+ (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode\r
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not\r
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag\r
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt\r
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\r
+\r
+ [..]\r
+ (@) You can refer to the I2C HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C I2C\r
+ * @brief I2C HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Define I2C Private Define\r
+ * @{\r
+ */\r
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */\r
+#define I2C_TIMEOUT_ADDR ((uint32_t)10000U) /*!< 10 s */\r
+#define I2C_TIMEOUT_BUSY ((uint32_t)25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_DIR ((uint32_t)25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_RXNE ((uint32_t)25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_STOPF ((uint32_t)25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_TC ((uint32_t)25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_TCR ((uint32_t)25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_TXIS ((uint32_t)25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_FLAG ((uint32_t)25U) /*!< 25 ms */\r
+\r
+#define MAX_NBYTE_SIZE 255U\r
+#define SlaveAddr_SHIFT 7U\r
+#define SlaveAddr_MSK 0x06U\r
+\r
+/* Private define for @ref PreviousState usage */\r
+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */\r
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */\r
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */\r
+\r
+\r
+/* Private define to centralize the enable/disable of Interrupts */\r
+#define I2C_XFER_TX_IT ((uint32_t)0x00000001)\r
+#define I2C_XFER_RX_IT ((uint32_t)0x00000002)\r
+#define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004)\r
+\r
+#define I2C_XFER_ERROR_IT ((uint32_t)0x00000011)\r
+#define I2C_XFER_CPLT_IT ((uint32_t)0x00000012)\r
+#define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \\r
+ ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \\r
+ ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions to handle DMA transfer */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);\r
+\r
+/* Private functions to handle IT transfer */\r
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);\r
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);\r
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);\r
+\r
+/* Private functions to handle IT transfer */\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
+\r
+/* Private functions for I2C transfer IRQ handler */\r
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+\r
+/* Private functions to handle flags during polling transfer */\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+\r
+/* Private functions to centralize the enable/disable of Interrupts */\r
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
+\r
+/* Private functions to flush TXDR register */\r
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);\r
+\r
+/* Private functions to handle start, restart or stop a transfer */\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Functions I2C Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and\r
+ deinitialize the I2Cx peripheral:\r
+\r
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures\r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_I2C_Init() to configure the selected device with\r
+ the selected configuration:\r
+ (++) Clock Timing\r
+ (++) Own Address 1\r
+ (++) Addressing mode (Master, Slave)\r
+ (++) Dual Addressing mode\r
+ (++) Own Address 2\r
+ (++) Own Address 2 Mask\r
+ (++) General call mode\r
+ (++) Nostretch mode\r
+\r
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration\r
+ of the selected I2Cx peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the I2C according to the specified parameters\r
+ * in the I2C_InitTypeDef and initialize the associated handle.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\r
+{ \r
+ /* Check the I2C handle allocation */\r
+ if(hi2c == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\r
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\r
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\r
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\r
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));\r
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\r
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\r
+\r
+ if(hi2c->State == HAL_I2C_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hi2c->Lock = HAL_UNLOCKED;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_I2C_MspInit(hi2c);\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+ \r
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/\r
+ /* Configure I2Cx: Frequency range */\r
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;\r
+ \r
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */\r
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;\r
+ if(hi2c->Init.OwnAddress1 != 0)\r
+ {\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\r
+ {\r
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);\r
+ }\r
+ else /* I2C_ADDRESSINGMODE_10BIT */\r
+ {\r
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);\r
+ }\r
+ }\r
+ \r
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/\r
+ /* Configure I2Cx: Addressing Master mode */\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);\r
+ }\r
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */\r
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);\r
+ \r
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\r
+ /* Configure I2Cx: Dual mode and Own Address2 */\r
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));\r
+\r
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/\r
+ /* Configure I2Cx: Generalcall and NoStretch mode */\r
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);\r
+ \r
+ /* Enable the selected I2C peripheral */\r
+ __HAL_I2C_ENABLE(hi2c);\r
+ \r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the I2C peripheral.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Check the I2C handle allocation */\r
+ if(hi2c == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the I2C Peripheral Clock */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_I2C_MspDeInit(hi2c);\r
+ \r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State = HAL_I2C_STATE_RESET;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the I2C MSP.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the I2C MSP.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the I2C data\r
+ transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode.\r
+ The status of all data processing is returned by the same function \r
+ after finishing transfer.\r
+ (++) No-Blocking mode : The communication is performed using Interrupts\r
+ or DMA. These functions return the status of the transfer startup.\r
+ The end of the data processing will be indicated through the\r
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+\r
+ (#) Blocking mode functions are :\r
+ (++) HAL_I2C_Master_Transmit()\r
+ (++) HAL_I2C_Master_Receive()\r
+ (++) HAL_I2C_Slave_Transmit()\r
+ (++) HAL_I2C_Slave_Receive()\r
+ (++) HAL_I2C_Mem_Write()\r
+ (++) HAL_I2C_Mem_Read()\r
+ (++) HAL_I2C_IsDeviceReady()\r
+\r
+ (#) No-Blocking mode functions with Interrupt are :\r
+ (++) HAL_I2C_Master_Transmit_IT()\r
+ (++) HAL_I2C_Master_Receive_IT()\r
+ (++) HAL_I2C_Slave_Transmit_IT()\r
+ (++) HAL_I2C_Slave_Receive_IT()\r
+ (++) HAL_I2C_Mem_Write_IT()\r
+ (++) HAL_I2C_Mem_Read_IT()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_I2C_Master_Transmit_DMA()\r
+ (++) HAL_I2C_Master_Receive_DMA()\r
+ (++) HAL_I2C_Slave_Transmit_DMA()\r
+ (++) HAL_I2C_Slave_Receive_DMA()\r
+ (++) HAL_I2C_Mem_Write_DMA()\r
+ (++) HAL_I2C_Mem_Read_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+ (++) HAL_I2C_MemTxCpltCallback()\r
+ (++) HAL_I2C_MemRxCpltCallback()\r
+ (++) HAL_I2C_MasterTxCpltCallback()\r
+ (++) HAL_I2C_MasterRxCpltCallback()\r
+ (++) HAL_I2C_SlaveTxCpltCallback()\r
+ (++) HAL_I2C_SlaveRxCpltCallback()\r
+ (++) HAL_I2C_ErrorCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits in master mode an amount of data in blocking mode.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+ }\r
+ \r
+ while(hi2c->XferSize > 0)\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r
+ hi2c->XferCount--;\r
+ hi2c->XferSize--;\r
+ \r
+ if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives in master mode an amount of data in blocking mode.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ \r
+ while(hi2c->XferSize > 0)\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ \r
+ if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits in slave mode an amount of data in blocking mode. \r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ \r
+ /* If 10bit addressing mode is selected */\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ }\r
+ \r
+ /* Wait until DIR flag is set Transmitter mode */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ while(hi2c->XferCount > 0)\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r
+ hi2c->XferCount--;\r
+ }\r
+ \r
+ /* Wait until STOP flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Normal use case for Transmitter mode */\r
+ /* A NACK is generated to confirm the end of transfer */\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);\r
+ \r
+ /* Wait until BUSY flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in blocking mode\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ \r
+ /* Wait until DIR flag is reset Receiver mode */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ while(hi2c->XferCount > 0)\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ /* Store Last receive data if any */\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r
+ {\r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferCount--;\r
+ }\r
+\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferCount--;\r
+ }\r
+ \r
+ /* Wait until STOP flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);\r
+ \r
+ /* Wait until BUSY flag is reset */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt \r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
+ \r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ if(hi2c->XferSize > 0)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+ \r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ }\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_DMA;\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; \r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_DMA;\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Write an amount of data in blocking mode to a specific memory address\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ \r
+ do\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r
+ hi2c->XferCount--;\r
+ hi2c->XferSize--;\r
+ \r
+ if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ \r
+ }while(hi2c->XferCount > 0);\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read an amount of data in blocking mode from a specific memory address\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ \r
+ do\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ \r
+ if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }while(hi2c->XferCount > 0);\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t xfermode = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t xfermode = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ } \r
+}\r
+/**\r
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t xfermode = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+ \r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be read\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t xfermode = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ \r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+ \r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks if target device is ready for communication.\r
+ * @note This function is used with Memory devices\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param Trials: Number of trials\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0;\r
+ \r
+ __IO uint32_t I2C_Trials = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ do\r
+ {\r
+ /* Generate Start */\r
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set or a NACK flag is set*/\r
+ tickstart = HAL_GetTick();\r
+ while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Device is ready */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Check if the NACKF flag has not been set */\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)\r
+ {\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Device is ready */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Clear STOP Flag, auto generated with autoend*/\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ }\r
+ \r
+ /* Check if the maximum allowed number of trials has been reached */\r
+ if (I2C_Trials++ == Trials)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+ \r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ }\r
+ }while(I2C_Trials < Trials);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ uint32_t xfermode = 0;\r
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+ \r
+ /* If size > MAX_NBYTE_SIZE, use reload mode */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = hi2c->XferOptions;\r
+ \r
+ /* If transfer direction not change, do not generate Restart Condition */\r
+ /* Mean Previous state is same as current state */\r
+ if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX)\r
+ {\r
+ xferrequest = I2C_NO_STARTSTOP;\r
+ }\r
+ }\r
+ \r
+ /* Send Slave Address and set NBYTES to write */\r
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ uint32_t xfermode = 0;\r
+ uint32_t xferrequest = I2C_GENERATE_START_READ;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+ \r
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = hi2c->XferOptions;\r
+ \r
+ /* If transfer direction not change, do not generate Restart Condition */\r
+ /* Mean Previous state is same as current state */\r
+ if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)\r
+ {\r
+ xferrequest = I2C_NO_STARTSTOP;\r
+ }\r
+ }\r
+ \r
+ /* Send Slave Address and set NBYTES to read */\r
+ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+ \r
+ if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r
+ {\r
+ /* Clear ADDR flag after prepare the transfer parameters */\r
+ /* This action will generate an acknowledge to the Master */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* REnable ADDR interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+ \r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+ \r
+ if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r
+ {\r
+ /* Clear ADDR flag after prepare the transfer parameters */\r
+ /* This action will generate an acknowledge to the Master */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* REnable ADDR interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the Address listen mode with Interrupt.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+ \r
+ /* Enable the Address Match interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable the Address listen mode with Interrupt.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */\r
+ uint32_t tmp;\r
+ \r
+ /* Disable Address listen mode only if a transfer is not ongoing */\r
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)\r
+ {\r
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;\r
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Disable the Address Match interrupt */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Abort a master I2C IT or DMA process communication with Interrupt.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)\r
+{\r
+ if(hi2c->Mode == HAL_I2C_MODE_MASTER)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ \r
+ /* Set State at HAL_I2C_STATE_ABORT */\r
+ hi2c->State = HAL_I2C_STATE_ABORT;\r
+ \r
+ /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */\r
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */\r
+ I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Wrong usage of abort function */\r
+ /* This function should be used only in case of abort monitored by master device */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief This function handles I2C event interrupt request.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Get current IT Flags and IT sources value */\r
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);\r
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
+ \r
+ /* I2C events treatment -------------------------------------*/\r
+ if(hi2c->XferISR != NULL)\r
+ {\r
+ hi2c->XferISR(hi2c, itflags, itsources);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C error interrupt request.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);\r
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
+ \r
+ /* I2C Bus error interrupt occurred ------------------------------------*/\r
+ if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;\r
+ \r
+ /* Clear BERR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\r
+ }\r
+ \r
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/\r
+ if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;\r
+ \r
+ /* Clear OVR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\r
+ }\r
+ \r
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/\r
+ if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;\r
+ \r
+ /* Clear ARLO flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\r
+ }\r
+ \r
+ /* Call the Error Callback in case of Error detected */\r
+ if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)\r
+ {\r
+ I2C_ITError(hi2c, hi2c->ErrorCode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Master Tx Transfer completed callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MasterTxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Master Rx Transfer completed callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MasterRxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/** @brief Slave Tx Transfer completed callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Slave Rx Transfer completed callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Slave Address Match callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS\r
+ * @param AddrMatchCode: Address Match Code\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ UNUSED(TransferDirection);\r
+ UNUSED(AddrMatchCode);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_AddrCallback() could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Listen Complete callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_ListenCpltCallback() could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Memory Tx Transfer completed callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MemTxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Memory Rx Transfer completed callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MemRxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief I2C error callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief I2C abort callback.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
+ * @brief Peripheral State, Mode and Error functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State, Mode and Error functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permit to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the I2C handle state.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL state\r
+ */\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Return I2C handle state */\r
+ return hi2c->State;\r
+}\r
+\r
+/**\r
+ * @brief Returns the I2C Master, Slave, Memory or no mode.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for I2C module\r
+ * @retval HAL mode\r
+ */\r
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)\r
+{\r
+ return hi2c->Mode;\r
+}\r
+\r
+/**\r
+* @brief Return the I2C error code.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+* @retval I2C Error Code\r
+*/\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\r
+{\r
+ return hi2c->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @param ITSources: Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r
+{\r
+ uint16_t devaddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Set corresponding Error Code */\r
+ /* No need to generate STOP, it is automatically done */\r
+ /* Error callback will be send during stop flag treatment */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ \r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))\r
+ {\r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))\r
+ {\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--; \r
+ }\r
+ else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r
+ {\r
+ if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))\r
+ {\r
+ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+ {\r
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call TxCpltCallback() if no stop mode is set */\r
+ if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))\r
+ {\r
+ /* Call I2C Master Sequential complete process */\r
+ I2C_ITMasterSequentialCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Wrong size Status regarding TCR flag event */\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+ }\r
+ }\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r
+ {\r
+ if(hi2c->XferCount == 0)\r
+ {\r
+ if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))\r
+ {\r
+ /* Call I2C Master Sequential complete process */\r
+ I2C_ITMasterSequentialCplt(hi2c);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wrong size Status regarding TC flag event */\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+ }\r
+ }\r
+ \r
+ if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Master complete process */\r
+ I2C_ITMasterCplt(hi2c, ITFlags);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @param ITSources: Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Check that I2C transfer finished */\r
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
+ /* Mean XferCount == 0*/\r
+ /* So clear Flag NACKF only */\r
+ if(hi2c->XferCount == 0)\r
+ {\r
+ if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \\r
+ (hi2c->State == HAL_I2C_STATE_LISTEN))\r
+ {\r
+ /* Call I2C Listen complete process */\r
+ I2C_ITListenCplt(hi2c, ITFlags);\r
+ }\r
+ else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ \r
+ /* Last Byte is Transmitted */\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSequentialCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))\r
+ {\r
+ if(hi2c->XferCount > 0)\r
+ {\r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+ \r
+ if((hi2c->XferCount == 0) && \\r
+ (hi2c->XferOptions != I2C_NO_OPTION_FRAME))\r
+ {\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSequentialCplt(hi2c);\r
+ }\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))\r
+ {\r
+ I2C_ITAddrCplt(hi2c, ITFlags);\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))\r
+ {\r
+ /* Write data to TXDR only if XferCount not reach "0" */\r
+ /* A TXIS flag can be set, during STOP treatment */\r
+ /* Check if all Datas have already been sent */\r
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */\r
+ if(hi2c->XferCount > 0)\r
+ {\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r
+ hi2c->XferCount--;\r
+ hi2c->XferSize--;\r
+ }\r
+ else\r
+ {\r
+ if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))\r
+ {\r
+ /* Last Byte is Transmitted */\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSequentialCplt(hi2c);\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Check if STOPF is set */\r
+ if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Slave complete process */\r
+ I2C_ITSlaveCplt(hi2c, ITFlags);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @param ITSources: Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r
+{\r
+ uint16_t devaddress = 0;\r
+ uint32_t xfermode = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Set corresponding Error Code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ \r
+ /* No need to generate STOP, it is automatically done */\r
+ /* But enable STOP interrupt, to treat it */\r
+ /* Error callback will be send during stop flag treatment */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+ \r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r
+ {\r
+ /* Disable TC interrupt */\r
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);\r
+ \r
+ if(hi2c->XferCount != 0)\r
+ {\r
+ /* Recover Slave address */\r
+ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ /* Prepare the new XferSize to transfer */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ \r
+ /* Set the new XferSize in Nbytes register */\r
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+ \r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ \r
+ /* Enable DMA Request */\r
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+ {\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wrong size Status regarding TCR flag event */\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+ }\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Master complete process */\r
+ I2C_ITMasterCplt(hi2c, ITFlags);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @param ITSources: Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Check that I2C transfer finished */\r
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
+ /* Mean XferCount == 0 */\r
+ /* So clear Flag NACKF only */\r
+ if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0)\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ }\r
+ else\r
+ {\r
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))\r
+ {\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+ else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Slave complete process */\r
+ I2C_ITSlaveCplt(hi2c, ITFlags);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Master sends target device address followed by internal memory address for write request.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param Timeout: Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* If Memory address size is 8Bit */\r
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+ {\r
+ /* Send Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+ /* If Memory address size is 16Bit */\r
+ else\r
+ {\r
+ /* Send MSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Send LSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+ \r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Master sends target device address followed by internal memory address for read request.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param Timeout: Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);\r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* If Memory address size is 8Bit */\r
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+ {\r
+ /* Send Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+ /* If Memory address size is 16Bit */\r
+ else\r
+ {\r
+ /* Send MSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Send LSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+ \r
+ /* Wait until TC flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief I2C Address complete process callback.\r
+ * @param hi2c: I2C handle.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ uint8_t transferdirection = 0;\r
+ uint16_t slaveaddrcode = 0;\r
+ uint16_t ownadd1code = 0;\r
+ uint16_t ownadd2code = 0;\r
+ \r
+ /* In case of Listen state, need to inform upper layer of address match code event */\r
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)\r
+ {\r
+ transferdirection = I2C_GET_DIR(hi2c);\r
+ slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);\r
+ ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);\r
+ ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);\r
+ \r
+ /* If 10bits addressing mode is selected */\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))\r
+ {\r
+ slaveaddrcode = ownadd1code;\r
+ hi2c->AddrEventCount++;\r
+ if(hi2c->AddrEventCount == 2)\r
+ {\r
+ /* Reset Address Event counter */\r
+ hi2c->AddrEventCount = 0;\r
+ \r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call Slave Addr callback */\r
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ slaveaddrcode = ownadd2code;\r
+ \r
+ /* Disable ADDR Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call Slave Addr callback */\r
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+ }\r
+ }\r
+ /* else 7 bits addressing mode is selected */\r
+ else\r
+ {\r
+ /* Disable ADDR Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call Slave Addr callback */\r
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+ }\r
+ }\r
+ /* Else clear address flag only */\r
+ else\r
+ {\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Master sequential complete process.\r
+ * @param hi2c: I2C handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Reset I2C handle mode */\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* No Generate Stop, to permit restart mode */\r
+ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_MasterTxCpltCallback(hi2c);\r
+ }\r
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
+ else\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_MasterRxCpltCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Slave sequential complete process.\r
+ * @param hi2c: I2C handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Reset I2C handle mode */\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+ {\r
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\r
+ \r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the Tx complete callback to inform upper layer of the end of transmit process */\r
+ HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+ }\r
+ \r
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+ {\r
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\r
+ \r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */\r
+ HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Master complete process.\r
+ * @param hi2c: I2C handle.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ /* Reset handle parameters */\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->XferISR = NULL;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ \r
+ if((ITFlags & I2C_FLAG_AF) != RESET)\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Set acknowledge error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ \r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ \r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, hi2c->ErrorCode);\r
+ }\r
+ /* hi2c->State == HAL_I2C_STATE_BUSY_TX */\r
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_MemTxCpltCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_MasterTxCpltCallback(hi2c);\r
+ }\r
+ }\r
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ HAL_I2C_MemRxCpltCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ HAL_I2C_MasterRxCpltCallback(hi2c);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Slave complete process.\r
+ * @param hi2c: I2C handle.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ \r
+ /* Disable all interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ \r
+ /* If a DMA is ongoing, Update handle size context */\r
+ if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||\r
+ ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))\r
+ {\r
+ if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize)\r
+ {\r
+ hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c);\r
+ hi2c->XferCount += hi2c->XferSize;\r
+ \r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ }\r
+ \r
+ /* Store Last receive data if any */\r
+ if(((ITFlags & I2C_FLAG_RXNE) != RESET))\r
+ {\r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ \r
+ if((hi2c->XferSize > 0))\r
+ {\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ \r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ }\r
+ \r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, hi2c->ErrorCode);\r
+ }\r
+ else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+ {\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+ HAL_I2C_ListenCpltCallback(hi2c);\r
+ }\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the Slave Rx Complete callback */\r
+ HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the Slave Tx Complete callback */\r
+ HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Listen complete process.\r
+ * @param hi2c: I2C handle.\r
+ * @param ITFlags: Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ /* Reset handle parameters */\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferISR = NULL;\r
+ \r
+ /* Store Last receive data if any */\r
+ if(((ITFlags & I2C_FLAG_RXNE) != RESET))\r
+ {\r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ \r
+ if((hi2c->XferSize > 0))\r
+ {\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ \r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ }\r
+ \r
+ /* Disable all Interrupts*/\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+ \r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+ HAL_I2C_ListenCpltCallback(hi2c);\r
+}\r
+\r
+/**\r
+ * @brief I2C interrupts error process.\r
+ * @param hi2c: I2C handle.\r
+ * @param ErrorCode: Error code to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)\r
+{\r
+ /* Reset handle parameters */\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferCount = 0;\r
+ \r
+ /* Set new error code */\r
+ hi2c->ErrorCode |= ErrorCode;\r
+ \r
+ /* Disable Interrupts */\r
+ if((hi2c->State == HAL_I2C_STATE_LISTEN) ||\r
+ (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||\r
+ (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))\r
+ {\r
+ /* Disable all interrupts, except interrupts related to LISTEN state */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+ \r
+ /* keep HAL_I2C_STATE_LISTEN if set */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable all interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+ \r
+ /* Set HAL_I2C_STATE_READY */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->XferISR = NULL;\r
+ }\r
+ \r
+ /* Abort DMA TX transfer if any */\r
+ if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+ \r
+ /* Set the I2C DMA Abort callback : \r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Abort DMA TX */\r
+ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+ }\r
+ }\r
+ /* Abort DMA RX transfer if any */\r
+ else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+ \r
+ /* Set the I2C DMA Abort callback : \r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Abort DMA RX */\r
+ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */\r
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+ }\r
+ }\r
+ else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)\r
+ {\r
+ hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_AbortCpltCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Tx data register flush process.\r
+ * @param hi2c: I2C handle.\r
+ * @retval None\r
+ */\r
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* If a pending TXIS flag is set */\r
+ /* Write a dummy data in TXDR to clear it */\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)\r
+ {\r
+ hi2c->Instance->TXDR = 0x00;\r
+ }\r
+ \r
+ /* Flush TX register if not empty */\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)\r
+ {\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C master transmit process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+ \r
+ /* If last transfer, enable STOP interrupt */\r
+ if(hi2c->XferCount == 0)\r
+ {\r
+ /* Enable STOP interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+ }\r
+ /* else prepare a new DMA transfer and enable TCReload interrupt */\r
+ else\r
+ {\r
+ /* Update Buffer pointer */\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+ \r
+ /* Set the XferSize to transfer */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Enable TC interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C slave transmit process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* No specific action, Master fully manage the generation of STOP condition */\r
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
+ /* So STOP condition should be manage through Interrupt treatment */\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C master receive process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+ \r
+ /* If last transfer, enable STOP interrupt */\r
+ if(hi2c->XferCount == 0)\r
+ {\r
+ /* Enable STOP interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+ }\r
+ /* else prepare a new DMA transfer and enable TCReload interrupt */\r
+ else\r
+ {\r
+ /* Update Buffer pointer */\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+ \r
+ /* Set the XferSize to transfer */\r
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\r
+ \r
+ /* Enable TC interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C slave receive process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* No specific action, Master fully manage the generation of STOP condition */\r
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
+ /* So STOP condition should be manage through Interrupt treatment */\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C communication error callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C communication abort callback\r
+ * (To be called at end of DMA Abort procedure).\r
+ * @param hdma: DMA handle.\r
+ * @retval None\r
+ */\r
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ /* Reset AbortCpltCallback */\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+ \r
+ /* Check if come from abort from user */\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)\r
+ {\r
+ hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;\r
+ \r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_AbortCpltCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Flag: Specifies the I2C flag to check.\r
+ * @param Status: The new Flag status (SET or RESET).\r
+ * @param Timeout: Timeout duration\r
+ * @param Tickstart: Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))\r
+ {\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @param Tickstart: Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @param Tickstart: Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check for the Timeout */\r
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @param Tickstart: Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check if a STOPF is detected */\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+ {\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check for the Timeout */\r
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles Acknowledge failed detection during an I2C Communication.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @param Tickstart: Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r
+ {\r
+ /* Wait until STOP Flag is reset */\r
+ /* AutoEnd should be initiate after AF */\r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r
+ {\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear NACKF Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).\r
+ * @param hi2c: I2C handle.\r
+ * @param DevAddress: Specifies the slave address to be programmed.\r
+ * @param Size: Specifies the number of bytes to be programmed.\r
+ * This parameter must be a value between 0 and 255.\r
+ * @param Mode: New state of the I2C START condition generation.\r
+ * This parameter can be a value of @ref I2C_RELOAD_END_MODE.\r
+ * @param Request: New state of the I2C START condition generation.\r
+ * This parameter can be a value of I2C_START_STOP_MODE.\r
+ * @retval None\r
+ */\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_TRANSFER_MODE(Mode));\r
+ assert_param(IS_TRANSFER_REQUEST(Request));\r
+ \r
+ /* Get the CR2 register value */\r
+ tmpreg = hi2c->Instance->CR2;\r
+ \r
+ /* clear tmpreg specific bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));\r
+ \r
+ /* update tmpreg */\r
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \\r
+ (uint32_t)Mode | (uint32_t)Request);\r
+ \r
+ /* update CR2 register */\r
+ hi2c->Instance->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Manage the enabling of Interrupts.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
+{\r
+ uint32_t tmpisr = 0;\r
+ \r
+ if((hi2c->XferISR == I2C_Master_ISR_DMA) || \\r
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))\r
+ {\r
+ if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+ {\r
+ /* Enable ERR, STOP, NACK and ADDR interrupts */\r
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
+ {\r
+ /* Enable ERR and NACK interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+ {\r
+ /* Enable STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
+ {\r
+ /* Enable TC interrupts */\r
+ tmpisr |= I2C_IT_TCI;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+ {\r
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */\r
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
+ {\r
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
+ {\r
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+ {\r
+ /* Enable STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI;\r
+ }\r
+ }\r
+ \r
+ /* Enable interrupts only at the end */\r
+ /* to avoid the risk of I2C interrupt handle execution before */\r
+ /* all interrupts requested done */\r
+ __HAL_I2C_ENABLE_IT(hi2c, tmpisr);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Manage the disabling of Interrupts.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
+{\r
+ uint32_t tmpisr = 0;\r
+ \r
+ if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
+ {\r
+ /* Disable TC and TXI interrupts */\r
+ tmpisr |= I2C_IT_TCI | I2C_IT_TXI;\r
+ \r
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)\r
+ {\r
+ /* Disable NACK and STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
+ {\r
+ /* Disable TC and RXI interrupts */\r
+ tmpisr |= I2C_IT_TCI | I2C_IT_RXI;\r
+ \r
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)\r
+ {\r
+ /* Disable NACK and STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+ {\r
+ /* Disable ADDR, NACK and STOP interrupts */\r
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
+ {\r
+ /* Enable ERR and NACK interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+ {\r
+ /* Enable STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI;\r
+ }\r
+ \r
+ if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
+ {\r
+ /* Enable TC interrupts */\r
+ tmpisr |= I2C_IT_TCI;\r
+ }\r
+ \r
+ /* Disable interrupts only at the end */\r
+ /* to avoid a breaking situation like at "t" time */\r
+ /* all disable interrupts request are not done */\r
+ __HAL_I2C_DISABLE_IT(hi2c, tmpisr);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief I2C Extended HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of I2C Extended peripheral:\r
+ * + Extended features functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### I2C peripheral Extended features #####\r
+ ==============================================================================\r
+\r
+ [..] Comparing to other previous devices, the I2C interface for STM32F7XX\r
+ devices contains the following additional features\r
+\r
+ (+) Possibility to disable or enable Analog Noise Filter\r
+ (+) Use of a configured Digital Noise Filter\r
+ (+) Disable or enable Fast Mode Plus (available only for STM32F76xxx/STM32F77xxx \r
+ devices)\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to:\r
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()\r
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()\r
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :\r
+ (++) HAL_I2CEx_EnableFastModePlus()\r
+ (++) HAL_I2CEx_DisbleFastModePlus()\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx I2C Extended HAL module driver\r
+ * @brief I2C Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure Noise Filters\r
+ (+) Configure Fast Mode Plus\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure I2C Analog noise filter.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2Cx peripheral.\r
+ * @param AnalogFilter: New state of the Analog filter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+ \r
+ /* Reset I2Cx ANOFF bit */\r
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);\r
+ \r
+ /* Set analog filter bit*/\r
+ hi2c->Instance->CR1 |= AnalogFilter;\r
+ \r
+ __HAL_I2C_ENABLE(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure I2C Digital noise filter.\r
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2Cx peripheral.\r
+ * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+ \r
+ /* Get the old register value */\r
+ tmpreg = hi2c->Instance->CR1;\r
+ \r
+ /* Reset I2Cx DNF bits [11:8] */\r
+ tmpreg &= ~(I2C_CR1_DNF);\r
+ \r
+ /* Set I2Cx DNF coefficient */\r
+ tmpreg |= DigitalFilter << 8;\r
+ \r
+ /* Store the new register value */\r
+ hi2c->Instance->CR1 = tmpreg;\r
+ \r
+ __HAL_I2C_ENABLE(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/**\r
+ * @brief Enable the I2C fast mode plus driving capability.\r
+ * @param ConfigFastModePlus: Selects the pin.\r
+ * This parameter can be one of the @ref I2CEx_FastModePlus values\r
+ * @retval None\r
+ */\r
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
+ \r
+ /* Enable SYSCFG clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+ \r
+ /* Enable fast mode plus driving capability for selected pin */\r
+ SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r
+}\r
+\r
+/**\r
+ * @brief Disable the I2C fast mode plus driving capability.\r
+ * @param ConfigFastModePlus: Selects the pin.\r
+ * This parameter can be one of the @ref I2CEx_FastModePlus values\r
+ * @retval None\r
+ */\r
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
+ \r
+ /* Enable SYSCFG clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+ \r
+ /* Disable fast mode plus driving capability for selected pin */\r
+ CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r
+}\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2s.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief I2S HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and Errors functions\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The I2S HAL driver can be used as follows:\r
+ \r
+ (#) Declare a I2S_HandleTypeDef handle structure.\r
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:\r
+ (##) Enable the SPIx interface clock. \r
+ (##) I2S pins configuration:\r
+ (+++) Enable the clock for the I2S GPIOs.\r
+ (+++) Configure these I2S pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()\r
+ and HAL_I2S_Receive_IT() APIs).\r
+ (+++) Configure the I2Sx interrupt priority.\r
+ (+++) Enable the NVIC I2S IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()\r
+ and HAL_I2S_Receive_DMA() APIs:\r
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Channel.\r
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r
+ DMA Tx/Rx Channel.\r
+ \r
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity\r
+ using HAL_I2S_Init() function.\r
+\r
+ -@- The specific I2S interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.\r
+ -@- Make sure that either:\r
+ (+@) I2S clock is configured based on SYSCLK or \r
+ (+@) External clock source is configured after setting correctly \r
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file. \r
+\r
+ (#) Three mode of operations are available within this driver : \r
+ \r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() \r
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() \r
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() \r
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback\r
+\r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() \r
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() \r
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback\r
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause() \r
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume() \r
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop() \r
+ \r
+ *** I2S HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in I2S HAL driver.\r
+ \r
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) \r
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) \r
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts\r
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts\r
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not\r
+ \r
+ [..] \r
+ (@) You can refer to the I2S HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2S I2S\r
+ * @brief I2S HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup I2S_Private_Functions I2S Private Functions\r
+ * @{\r
+ */\r
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);\r
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);\r
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);\r
+static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);\r
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2S_Exported_Functions I2S Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and \r
+ de-initialize the I2Sx peripheral in simplex mode:\r
+\r
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures \r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_I2S_Init() to configure the selected device with \r
+ the selected configuration:\r
+ (++) Mode\r
+ (++) Standard \r
+ (++) Data Format\r
+ (++) MCLK Output\r
+ (++) Audio frequency\r
+ (++) Polarity\r
+ (++) Full duplex mode\r
+\r
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration \r
+ of the selected I2Sx peripheral. \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the I2S according to the specified parameters \r
+ * in the I2S_InitTypeDef and create the associated handle.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)\r
+{\r
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ uint32_t tmp = 0, i2sclk = 0;\r
+ \r
+ /* Check the I2S handle allocation */\r
+ if(hi2s == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));\r
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));\r
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); \r
+ assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hi2s->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_I2S_MspInit(hi2s);\r
+ }\r
+ \r
+ hi2s->State = HAL_I2S_STATE_BUSY;\r
+ \r
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \\r
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \\r
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); \r
+ hi2s->Instance->I2SPR = 0x0002;\r
+ \r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = hi2s->Instance->I2SCFGR;\r
+ \r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)\r
+ {\r
+ i2sodd = (uint16_t)0;\r
+ i2sdiv = (uint16_t)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) *******************/\r
+ if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+ \r
+ /* Get I2S source Clock frequency ****************************************/\r
+\r
+ /* If an external I2S clock has to be used, the specific define should be set \r
+ in the project configuration or in the stm32f3xx_conf.h file */\r
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)\r
+ { \r
+ /* Set the I2S clock to the external clock value */\r
+ i2sclk = EXTERNAL_CLOCK_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* Get the I2S source clock value */\r
+ i2sclk = I2S_GetClockFreq(hi2s);\r
+ }\r
+ \r
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */\r
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the flatting point */\r
+ tmp = tmp / 10; \r
+ \r
+ /* Check the parity of the divider */\r
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
+ \r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
+ \r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (uint16_t) (i2sodd << 8);\r
+ }\r
+ \r
+ /* Test if the divider is 1 or 0 or greater than 0xFF */\r
+ if((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+ \r
+ /* Write to SPIx I2SPR register the computed value */\r
+ hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));\r
+ \r
+ /* Configure the I2S with the I2S_InitStruct values */\r
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \\r
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \\r
+ (uint16_t)hi2s->Init.CPOL))));\r
+\r
+ /* Write to SPIx I2SCFGR */ \r
+ hi2s->Instance->I2SCFGR = tmpreg; \r
+\r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief DeInitializes the I2S peripheral \r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Check the I2S handle allocation */\r
+ if(hi2s == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r
+\r
+ hi2s->State = HAL_I2S_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_I2S_MspDeInit(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief I2S MSP Init\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2s);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief I2S MSP DeInit\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2s);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the I2S data \r
+ transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode. \r
+ The status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (++) No-Blocking mode : The communication is performed using Interrupts \r
+ or DMA. These functions return the status of the transfer startup.\r
+ The end of the data processing will be indicated through the \r
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+\r
+ (#) Blocking mode functions are :\r
+ (++) HAL_I2S_Transmit()\r
+ (++) HAL_I2S_Receive()\r
+ \r
+ (#) No-Blocking mode functions with Interrupt are :\r
+ (++) HAL_I2S_Transmit_IT()\r
+ (++) HAL_I2S_Receive_IT()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_I2S_Transmit_DMA()\r
+ (++) HAL_I2S_Receive_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+ (++) HAL_I2S_TxCpltCallback()\r
+ (++) HAL_I2S_RxCpltCallback()\r
+ (++) HAL_I2S_ErrorCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmit an amount of data in blocking mode\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @param Timeout: Timeout duration\r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->TxXferSize = (Size << 1);\r
+ hi2s->TxXferCount = (Size << 1);\r
+ }\r
+ else\r
+ {\r
+ hi2s->TxXferSize = Size;\r
+ hi2s->TxXferCount = Size;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ while(hi2s->TxXferCount > 0)\r
+ {\r
+ hi2s->Instance->DR = (*pData++);\r
+ hi2s->TxXferCount--; \r
+ /* Wait until TXE flag is set */\r
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)\r
+ {\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Check if an underrun occurs */\r
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) \r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ } \r
+ \r
+ /* Check if Slave mode is selected */\r
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))\r
+ {\r
+ /* Wait until Busy flag is reset */\r
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) \r
+ {\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode \r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @param Timeout: Timeout duration\r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate\r
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->RxXferSize = (Size << 1);\r
+ hi2s->RxXferCount = (Size << 1);\r
+ }\r
+ else\r
+ {\r
+ hi2s->RxXferSize = Size;\r
+ hi2s->RxXferCount = Size;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Check if Master Receiver mode is selected */\r
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r
+ {\r
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read\r
+ access to the SPI_SR register. */ \r
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s); \r
+ }\r
+ \r
+ /* Receive data */\r
+ while(hi2s->RxXferCount > 0)\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) \r
+ {\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Check if an overrun occurs */\r
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) \r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ (*pData++) = hi2s->Instance->DR;\r
+ hi2s->RxXferCount--;\r
+ } \r
+\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ hi2s->pTxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->TxXferSize = (Size << 1);\r
+ hi2s->TxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->TxXferSize = Size;\r
+ hi2s->TxXferCount = Size;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;\r
+\r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation \r
+ * between Master and Slave otherwise the I2S interrupt should be optimized. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ hi2s->pRxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->RxXferSize = (Size << 1);\r
+ hi2s->RxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->RxXferSize = Size;\r
+ hi2s->RxXferCount = Size;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;\r
+\r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with DMA\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to the Transmit data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ hi2s->pTxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->TxXferSize = (Size << 1);\r
+ hi2s->TxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->TxXferSize = Size;\r
+ hi2s->TxXferCount = Size;\r
+ } \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;\r
+\r
+ /* Set the I2S Tx DMA Half transfer complete callback */\r
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;\r
+\r
+ /* Set the I2S TxDMA transfer complete callback */\r
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;\r
+ \r
+ /* Enable the Tx DMA Channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Enable Tx DMA Request */ \r
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with DMA \r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ hi2s->pRxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->RxXferSize = (Size << 1);\r
+ hi2s->RxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->RxXferSize = Size;\r
+ hi2s->RxXferCount = Size;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;\r
+ \r
+ /* Set the I2S Rx DMA Half transfer complete callback */\r
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;\r
+\r
+ /* Set the I2S Rx DMA transfer complete callback */\r
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;\r
+ \r
+ /* Check if Master Receiver mode is selected */\r
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r
+ {\r
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read\r
+ access to the SPI_SR register. */ \r
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s); \r
+ }\r
+ \r
+ /* Enable the Rx DMA Channel */\r
+ tmp = (uint32_t*)&pData; \r
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Enable Rx DMA Request */ \r
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the audio stream playing from the Media.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+\r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the I2S DMA Tx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r
+ {\r
+ /* Disable the I2S DMA Rx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r
+ {\r
+ if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))\r
+ {\r
+ /* Disable the I2S DMA Tx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the I2S DMA Rx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Resumes the audio stream playing from the Media.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the I2S DMA Tx request */\r
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r
+ {\r
+ /* Enable the I2S DMA Rx request */\r
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r
+ }\r
+ \r
+ /* If the I2S peripheral is still not enabled, enable it */\r
+ if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the audio stream playing from the Media.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ /* Disable the I2S Tx/Rx DMA requests */\r
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r
+ \r
+ /* Abort the I2S DMA Channel tx */\r
+ if(hi2s->hdmatx != NULL)\r
+ {\r
+ /* Disable the I2S DMA channel */\r
+ __HAL_DMA_DISABLE(hi2s->hdmatx);\r
+ HAL_DMA_Abort(hi2s->hdmatx);\r
+ }\r
+ /* Abort the I2S DMA Channel rx */\r
+ if(hi2s->hdmarx != NULL)\r
+ {\r
+ /* Disable the I2S DMA channel */\r
+ __HAL_DMA_DISABLE(hi2s->hdmarx);\r
+ HAL_DMA_Abort(hi2s->hdmarx);\r
+ }\r
+\r
+ /* Disable I2S peripheral */\r
+ __HAL_I2S_DISABLE(hi2s);\r
+ \r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2S interrupt request.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)\r
+{ \r
+ __IO uint32_t i2ssr = hi2s->Instance->SR;\r
+\r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r
+ { \r
+ /* I2S in mode Receiver ----------------------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))\r
+ {\r
+ I2S_Receive_IT(hi2s);\r
+ }\r
+\r
+ /* I2S Overrun error interrupt occurred -------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r
+ {\r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r
+\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ } \r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r
+ { \r
+ /* I2S in mode Transmitter ---------------------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))\r
+ { \r
+ I2S_Transmit_IT(hi2s);\r
+ } \r
+ \r
+ /* I2S Underrun error interrupt occurred ------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r
+ {\r
+ /* Disable TXE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r
+\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2S_Private_Functions I2S Private Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles I2S Communication Timeout.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param Flag: Flag checked\r
+ * @param State: Value of the flag expected\r
+ * @param Timeout: Duration of the timeout\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, \r
+ uint32_t State, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until flag is set */\r
+ if(State == RESET)\r
+ {\r
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions \r
+ * @{\r
+ */\r
+/**\r
+ * @brief Tx Transfer Half completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2s);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2s);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer half completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2s);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2s);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief I2S error callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2s);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the I2S state\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL state\r
+ */\r
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)\r
+{\r
+ return hi2s->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the I2S error code\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval I2S Error Code\r
+ */\r
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)\r
+{\r
+ return hi2s->ErrorCode;\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @brief Get I2S Input Clock based on I2S source clock selection\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module. \r
+ * @retval I2S Clock Input \r
+ */\r
+static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s) \r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* This variable used to store the VCO Input (value in Hz) */\r
+ uint32_t vcoinput = 0;\r
+ /* This variable used to store the I2S_CK_x (value in Hz) */\r
+ uint32_t i2sclocksource = 0;\r
+\r
+ /* Configure I2S Clock based on I2S source clock selection */ \r
+ \r
+ /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */\r
+ switch(hi2s->Init.ClockSource)\r
+ {\r
+ case I2S_CLOCK_PLL :\r
+ {\r
+ /* Configure the PLLI2S division factor */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */\r
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;\r
+ i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r
+ \r
+ break;\r
+ }\r
+ case I2S_CLOCK_EXTERNAL :\r
+ {\r
+ i2sclocksource = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+ default :\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* the return result is the value of I2S clock */\r
+ return i2sclocksource; \r
+}\r
+\r
+/** @addtogroup I2S_Private_Functions I2S Private Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief DMA I2S transmit process complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ hi2s->TxXferCount = 0;\r
+\r
+ /* Disable Tx DMA Request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r
+ {\r
+ if(hi2s->RxXferCount == 0)\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ }\r
+ }\r
+ HAL_I2S_TxCpltCallback(hi2s);\r
+}\r
+\r
+/**\r
+ * @brief DMA I2S transmit process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_I2S_TxHalfCpltCallback(hi2s);\r
+}\r
+\r
+/**\r
+ * @brief DMA I2S receive process complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable Rx DMA Request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+\r
+ hi2s->RxXferCount = 0;\r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r
+ {\r
+ if(hi2s->TxXferCount == 0)\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ }\r
+ }\r
+ HAL_I2S_RxCpltCallback(hi2s); \r
+}\r
+ \r
+/**\r
+ * @brief DMA I2S receive process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_I2S_RxHalfCpltCallback(hi2s); \r
+}\r
+\r
+/**\r
+ * @brief DMA I2S communication error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Rx and Tx DMA Request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));\r
+ hi2s->TxXferCount = 0;\r
+ hi2s->RxXferCount = 0;\r
+ \r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Transmit data */\r
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);\r
+ hi2s->TxXferCount--; \r
+\r
+ if(hi2s->TxXferCount == 0)\r
+ {\r
+ /* Disable TXE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r
+\r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ HAL_I2S_TxCpltCallback(hi2s);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: I2S handle\r
+ * @retval None\r
+ */\r
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Receive data */ \r
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;\r
+ hi2s->RxXferCount--;\r
+\r
+ if(hi2s->RxXferCount == 0)\r
+ { \r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r
+\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ HAL_I2S_RxCpltCallback(hi2s); \r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_irda.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief IRDA HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the IrDA SIR ENDEC block (IrDA):\r
+ * + Initialization and de-initialization methods\r
+ * + IO operation methods\r
+ * + Peripheral Control methods\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The IRDA HAL driver can be used as follows:\r
+\r
+ (#) Declare a IRDA_HandleTypeDef handle structure.\r
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) IRDA pins configuration:\r
+ (+++) Enable the clock for the IRDA GPIOs.\r
+ (+++) Configure these IRDA pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()\r
+ and HAL_IRDA_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()\r
+ and HAL_IRDA_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler\r
+ and Mode(Receiver/Transmitter) in the hirda Init structure.\r
+\r
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:\r
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customized HAL_IRDA_MspInit() API.\r
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,\r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.\r
+\r
+ (#) Three operation modes are available within this driver :\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()\r
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()\r
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()\r
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback\r
+\r
+ *** DMA mode IO operation ***\r
+ =============================\r
+ [..]\r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()\r
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()\r
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback\r
+\r
+ *** IRDA HAL driver macros list ***\r
+ ===================================\r
+ [..]\r
+ Below the list of most used macros in IRDA HAL driver.\r
+\r
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral\r
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral\r
+ (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not\r
+ (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag\r
+ (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt\r
+ (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt\r
+\r
+ (@) You can refer to the IRDA HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IRDA IRDA\r
+ * @brief HAL IRDA module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup IRDA_Private_Constants\r
+ * @{\r
+ */\r
+#define TEACK_REACK_TIMEOUT 1000U\r
+#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U\r
+#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \\r
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup IRDA_Private_Functions\r
+ * @{\r
+ */\r
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);\r
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);\r
+static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup IRDA_Exported_Functions IrDA Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+\r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
+ in IrDA mode.\r
+ (+) For the asynchronous mode only these parameters can be configured:\r
+ (++) BaudRate\r
+ (++) WordLength\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ please refer to Reference manual for possible IRDA frame formats.\r
+ (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may\r
+ not be rejected. The receiver set up time should be managed by software. The IrDA physical layer\r
+ specification specifies a minimum of 10 ms delay between transmission and\r
+ reception (IrDA is a half duplex protocol).\r
+ (++) Mode: Receiver/transmitter modes\r
+ (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.\r
+ [..]\r
+ The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures\r
+ are available in reference manual).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the IRDA mode according to the specified\r
+ * parameters in the IRDA_InitTypeDef and create the associated handle.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Check the IRDA handle allocation */\r
+ if(hirda == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the USART/UART associated to the IRDA handle */\r
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));\r
+\r
+ if(hirda->gState == HAL_IRDA_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hirda->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
+ HAL_IRDA_MspInit(hirda);\r
+ }\r
+\r
+ hirda->gState = HAL_IRDA_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral to update the configuration registers */\r
+ __HAL_IRDA_DISABLE(hirda);\r
+\r
+ /* Set the IRDA Communication parameters */\r
+ IRDA_SetConfig(hirda);\r
+\r
+ /* In IRDA mode, the following bits must be kept cleared:\r
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and HDSEL bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);\r
+\r
+ /* set the UART/USART in IRDA mode */\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_IRDA_ENABLE(hirda);\r
+\r
+ /* TEACK and/or REACK to check before moving hirda->State to Ready */\r
+ return (IRDA_CheckIdleState(hirda));\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the IRDA peripheral\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Check the IRDA handle allocation */\r
+ if(hirda == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));\r
+\r
+ hirda->gState = HAL_IRDA_STATE_BUSY;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_IRDA_MspDeInit(hirda);\r
+ /* Disable the Peripheral */\r
+ __HAL_IRDA_DISABLE(hirda);\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->gState = HAL_IRDA_STATE_RESET;\r
+ hirda->RxState = HAL_IRDA_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief IRDA MSP Init.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hirda);\r
+\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_IRDA_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief IRDA MSP DeInit.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hirda);\r
+\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_IRDA_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions\r
+ * @brief IRDA Transmit/Receive functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.\r
+ [..]\r
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data\r
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver\r
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.\r
+ While receiving data, transmission should be avoided as the data to be transmitted\r
+ could be corrupted.\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode: the communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (++) No-Blocking mode: the communication is performed using Interrupts\r
+ or DMA, these API's return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the Transmit or Receive process\r
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (++) HAL_IRDA_Transmit()\r
+ (++) HAL_IRDA_Receive()\r
+\r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (++) HAL_IRDA_Transmit_IT()\r
+ (++) HAL_IRDA_Receive_IT()\r
+ (++) HAL_IRDA_IRQHandler()\r
+ (++) IRDA_Transmit_IT()\r
+ (++) IRDA_Receive_IT()\r
+\r
+ (#) Non-Blocking mode functions with DMA are :\r
+ (++) HAL_IRDA_Transmit_DMA()\r
+ (++) HAL_IRDA_Receive_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (++) HAL_IRDA_TxCpltCallback()\r
+ (++) HAL_IRDA_RxCpltCallback()\r
+ (++) HAL_IRDA_ErrorCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an amount of data in blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Specify timeout value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Check that a Tx process is not already ongoing */\r
+ if(hirda->gState == HAL_IRDA_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hirda->TxXferSize = Size;\r
+ hirda->TxXferCount = Size;\r
+ while(hirda->TxXferCount > 0U)\r
+ {\r
+ hirda->TxXferCount--;\r
+\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData;\r
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r
+ pData +=2;\r
+ }\r
+ else\r
+ {\r
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);\r
+ }\r
+ }\r
+\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* At end of Tx process, restore hirda->gState to Ready */\r
+ hirda->gState = HAL_IRDA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Specify timeout value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if(hirda->RxState == HAL_IRDA_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hirda->RxXferSize = Size;\r
+ hirda->RxXferCount = Size;\r
+\r
+ /* Computation of the mask to apply to the RDR register\r
+ of the UART associated to the IRDA */\r
+ IRDA_MASK_COMPUTATION(hirda);\r
+ uhMask = hirda->Mask;\r
+\r
+ /* Check data remaining to be received */\r
+ while(hirda->RxXferCount > 0U)\r
+ {\r
+ hirda->RxXferCount--;\r
+\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData ;\r
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);\r
+ pData +=2;\r
+ }\r
+ else\r
+ {\r
+ *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ }\r
+\r
+ /* At end of Rx process, restore hirda->RxState to Ready */\r
+ hirda->RxState = HAL_IRDA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in non blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Tx process is not already ongoing */\r
+ if(hirda->gState == HAL_IRDA_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+\r
+ hirda->pTxBuffPtr = pData;\r
+ hirda->TxXferSize = Size;\r
+ hirda->TxXferCount = Size;\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ /* Enable the IRDA Transmit Complete Interrupt */\r
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in non blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Rx process is not already ongoing */\r
+ if(hirda->RxState == HAL_IRDA_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+\r
+ hirda->pRxBuffPtr = pData;\r
+ hirda->RxXferSize = Size;\r
+ hirda->RxXferCount = Size;\r
+\r
+ /* Computation of the mask to apply to the RDR register\r
+ of the UART associated to the IRDA */\r
+ IRDA_MASK_COMPUTATION(hirda);\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ /* Enable the IRDA Parity Error Interrupt */\r
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the IRDA Data Register not empty Interrupt */\r
+ SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sends an amount of data in non blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ /* Check that a Tx process is not already ongoing */\r
+ if(hirda->gState == HAL_IRDA_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+\r
+ hirda->pTxBuffPtr = pData;\r
+ hirda->TxXferSize = Size;\r
+ hirda->TxXferCount = Size;\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;\r
+\r
+ /* Set the IRDA DMA transfer complete callback */\r
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;\r
+\r
+ /* Set the IRDA DMA half transfer complete callback */\r
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ hirda->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the IRDA transmit DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the IRDA CR3 register */\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in non blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if(hirda->RxState == HAL_IRDA_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+\r
+ hirda->pRxBuffPtr = pData;\r
+ hirda->RxXferSize = Size;\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;\r
+\r
+ /* Set the IRDA DMA transfer complete callback */\r
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;\r
+\r
+ /* Set the IRDA DMA half transfer complete callback */\r
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ hirda->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ /* Enable the IRDA Parity Error Interrupt */\r
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the USART CR3 register */\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the DMA Transfer.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+\r
+ if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)&&\r
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))\r
+ {\r
+ /* Disable the UART DMA Tx request */\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)&&\r
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the UART DMA Rx request */\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+\r
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the UART DMA Tx request */\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);\r
+\r
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the UART DMA Rx request */\r
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /\r
+ HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:\r
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r
+ the stream and the corresponding call back is executed. */\r
+\r
+ /* Stop IRDA DMA Tx request if ongoing */\r
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&\r
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))\r
+ {\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the IRDA DMA Tx channel */\r
+ if(hirda->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hirda->hdmatx);\r
+ }\r
+ IRDA_EndTxTransfer(hirda);\r
+ }\r
+\r
+ /* Stop IRDA DMA Rx request if ongoing */\r
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&\r
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the IRDA DMA Rx channel */\r
+ if(hirda->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hirda->hdmarx);\r
+ }\r
+ IRDA_EndRxTransfer(hirda);\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA communication abort callback, when call by HAL services on Error\r
+ * (To be called at end of DMA Abort procedure following error occurrence).\r
+ * @param hdma: DMA handle.\r
+ * @retval None\r
+ */\r
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hirda->RxXferCount = 0U;\r
+ hirda->TxXferCount = 0U;\r
+\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+}\r
+\r
+/**\r
+ * @brief This function handles IRDA interrupt request.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint32_t isrflags, cr1its, cr3its, errorflags;\r
+\r
+ isrflags = READ_REG(hirda->Instance->ISR);\r
+ cr1its = READ_REG(hirda->Instance->CR1);\r
+ cr3its = READ_REG(hirda->Instance->CR3);\r
+\r
+ /* If no error occurs */\r
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r
+ if (errorflags == RESET)\r
+ {\r
+ /* IRDA in mode Receiver ---------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ IRDA_Receive_IT(hirda);\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);\r
+ }\r
+ }\r
+\r
+ /* If some errors occur */\r
+ if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r
+ {\r
+ /* IRDA parity error interrupt occurred -------------------------------------*/\r
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r
+ {\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;\r
+ }\r
+\r
+ /* IRDA frame error interrupt occurred --------------------------------------*/\r
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;\r
+ }\r
+\r
+ /* IRDA noise error interrupt occurred --------------------------------------*/\r
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;\r
+ }\r
+\r
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/\r
+ if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;\r
+ }\r
+\r
+ /* Call IRDA Error Call back function if need be --------------------------*/\r
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)\r
+ {\r
+ /* IRDA in mode Receiver ---------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ IRDA_Receive_IT(hirda);\r
+ }\r
+\r
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+ consider error as blocking */\r
+ if (((hirda->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||\r
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ /* Blocking error : transfer is aborted\r
+ Set the IRDA state ready to be able to start again the process,\r
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
+ IRDA_EndRxTransfer(hirda);\r
+\r
+ /* Disable the IRDA DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the IRDA DMA Rx channel */\r
+ if(hirda->hdmarx != NULL)\r
+ {\r
+ /* Set the IRDA DMA Abort callback :\r
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */\r
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;\r
+\r
+ /* Abort DMA RX */\r
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */\r
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Non Blocking error : transfer could go on.\r
+ Error is notified to user through user error callback */\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ }\r
+ }\r
+ return;\r
+\r
+ } /* End if some error occurs */\r
+\r
+ /* IRDA in mode Transmitter ------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r
+ {\r
+ IRDA_Transmit_IT(hirda);\r
+ return;\r
+ }\r
+\r
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/\r
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r
+ {\r
+ IRDA_EndTransmit_IT(hirda);\r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).\r
+ * @param hirda: IRDA handle.\r
+ * @retval None\r
+ */\r
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Disable TXEIE and TCIE interrupts */\r
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+\r
+ /* At end of Tx process, restore hirda->gState to Ready */\r
+ hirda->gState = HAL_IRDA_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).\r
+ * @param hirda: IRDA handle.\r
+ * @retval None\r
+ */\r
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ hirda->RxState = HAL_IRDA_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer complete callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hirda);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hirda);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer complete callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hirda);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer complete callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hirda);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief IRDA error callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hirda);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_ErrorCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief IRDA control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the IRDA.\r
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.\r
+ (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the IRDA state.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL state\r
+ */\r
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;\r
+ temp1 = hirda->gState;\r
+ temp2 = hirda->RxState;\r
+\r
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+ * @brief Return the IRDA error code\r
+ * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA.\r
+* @retval IRDA Error Code\r
+*/\r
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;\r
+ temp1 = hirda->gState;\r
+ temp2 = hirda->RxState;\r
+\r
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configure the IRDA peripheral\r
+ * @param hirda: irda handle\r
+ * @retval None\r
+ */\r
+static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint32_t tmpreg = 0x00000000U;\r
+ uint32_t clocksource = 0x00000000U;\r
+\r
+ /* Check the communication parameters */\r
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));\r
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));\r
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));\r
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));\r
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));\r
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Configure the IRDA Word Length, Parity and transfer Mode:\r
+ Set the M bits according to hirda->Init.WordLength value\r
+ Set PCE and PS bits according to hirda->Init.Parity value\r
+ Set TE and RE bits according to hirda->Init.Mode value */\r
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;\r
+\r
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);\r
+\r
+ /*-------------------------- USART GTPR Configuration ----------------------*/\r
+ MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler);\r
+\r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);\r
+ switch (clocksource)\r
+ {\r
+ case IRDA_CLOCKSOURCE_PCLK1:\r
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r
+ break;\r
+ case IRDA_CLOCKSOURCE_PCLK2:\r
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r
+ break;\r
+ case IRDA_CLOCKSOURCE_HSI:\r
+ hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r
+ break;\r
+ case IRDA_CLOCKSOURCE_SYSCLK:\r
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r
+ break;\r
+ case IRDA_CLOCKSOURCE_LSE:\r
+ hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Check the IRDA Idle State\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Initialize the IRDA ErrorCode */\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the Transmitter is enabled */\r
+ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ /* Initialize the IRDA state*/\r
+ hirda->gState= HAL_IRDA_STATE_READY;\r
+ hirda->RxState= HAL_IRDA_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles IRDA Communication Timeout.\r
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param Flag specifies the IRDA flag to check.\r
+ * @param Status The new Flag status (SET or RESET).\r
+ * @param Tickstart Tick start value\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+ /* Wait until flag is set */\r
+ while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ hirda->gState= HAL_IRDA_STATE_READY;\r
+ hirda->RxState= HAL_IRDA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in non blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint16_t* tmp;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)\r
+ {\r
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)\r
+ {\r
+ tmp = (uint16_t*) hirda->pTxBuffPtr;\r
+ hirda->Instance->RDR = (uint16_t)(*tmp & (uint16_t)0x01FFU);\r
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)\r
+ {\r
+ hirda->pTxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ hirda->pTxBuffPtr += 1U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hirda->Instance->RDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU);\r
+ }\r
+\r
+ if(--hirda->TxXferCount == 0U)\r
+ {\r
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */\r
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);\r
+\r
+ /* Enable the IRDA Transmit Complete Interrupt */\r
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Wraps up transmission in non blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Disable the IRDA Transmit Complete Interrupt */\r
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Tx process is ended, restore hirda->gState to Ready */\r
+ hirda->gState = HAL_IRDA_STATE_READY;\r
+\r
+ HAL_IRDA_TxCpltCallback(hirda);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non blocking mode.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhdata;\r
+ uint16_t uhMask = hirda->Mask;\r
+\r
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)\r
+ {\r
+ uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);\r
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) hirda->pRxBuffPtr ;\r
+ *tmp = (uint16_t)(uhdata & uhMask);\r
+ hirda->pRxBuffPtr +=2U;\r
+ }\r
+ else\r
+ {\r
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);\r
+ }\r
+\r
+ if(--hirda->RxXferCount == 0U)\r
+ {\r
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ /* Disable the IRDA Parity Error Interrupt */\r
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Rx process is completed, restore hirda->RxState to Ready */\r
+ hirda->RxState = HAL_IRDA_STATE_READY;\r
+\r
+ HAL_IRDA_RxCpltCallback(hirda);\r
+\r
+ return HAL_OK;\r
+ }\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA Tx transfer completed callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal mode*/\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r
+ {\r
+ hirda->TxXferCount = 0U;\r
+\r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the IRDA CR3 register */\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Enable the IRDA Transmit Complete Interrupt */\r
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r
+ }\r
+ /* DMA Circular mode */\r
+ else\r
+ {\r
+ HAL_IRDA_TxCpltCallback(hirda);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA receive process half complete callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ HAL_IRDA_TxHalfCpltCallback(hirda);\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA Rx Transfer completed callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r
+ {\r
+ hirda->RxXferCount = 0U;\r
+\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the IRDA CR3 register */\r
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* At end of Rx process, restore hirda->RxState to Ready */\r
+ hirda->RxState = HAL_IRDA_STATE_READY;\r
+ }\r
+\r
+ HAL_IRDA_RxCpltCallback(hirda);\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA receive process half complete callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ HAL_IRDA_RxHalfCpltCallback(hirda);\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA communication error callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ hirda->RxXferCount = 0U;\r
+ hirda->TxXferCount = 0U;\r
+\r
+ /* Stop IRDA DMA Tx request if ongoing */\r
+ if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)\r
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )\r
+ {\r
+ IRDA_EndTxTransfer(hirda);\r
+ }\r
+\r
+ /* Stop IRDA DMA Rx request if ongoing */\r
+ if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)\r
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )\r
+ {\r
+ IRDA_EndRxTransfer(hirda);\r
+ }\r
+\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;\r
+\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief IWDG HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Independent Watchdog (IWDG) peripheral:\r
+ * + Initialization and Start functions\r
+ * + IO operation functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### IWDG Generic features #####\r
+ ==============================================================================\r
+ [..]\r
+ (+) The IWDG can be started by either software or hardware (configurable\r
+ through option byte).\r
+\r
+ (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even\r
+ if the main clock fails.\r
+\r
+ (+) Once the IWDG is started, the LSI is forced ON and both can not be \r
+ disabled. The counter starts counting down from the reset value (0xFFF).\r
+ When it reaches the end of count value (0x000) a reset signal is \r
+ generated (IWDG reset).\r
+\r
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, \r
+ the IWDG_RLR value is reloaded in the counter and the watchdog reset is\r
+ prevented.\r
+\r
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional\r
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).\r
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG\r
+ reset occurs.\r
+\r
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),\r
+ the IWDG counter either continues to work normally or stops, depending \r
+ on DBG_IWDG_STOP configuration bit in DBG module, accessible through\r
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros\r
+\r
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s\r
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx\r
+ devices provide the capability to measure the LSI frequency (LSI clock\r
+ connected internally to TIM16 CH1 input capture). The measured value\r
+ can be used to have an IWDG timeout with an acceptable accuracy.\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Use IWDG using HAL_IWDG_Init() function to :\r
+ (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI \r
+ clock is forced ON and IWDG counter starts downcounting.\r
+ (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR & \r
+ IWDG_WINR.\r
+ (+) Configure the IWDG prescaler and counter reload value. This reload \r
+ value will be loaded in the IWDG counter each time the watchdog is \r
+ reloaded, then the IWDG will start counting down from this value.\r
+ (+) wait for status flags to be reset"\r
+ (+) Depending on window parameter:\r
+ (++) If Window Init parameter is same as Window register value, \r
+ nothing more is done but reload counter value in order to exit \r
+ function withy exact time base.\r
+ (++) Else modify Window register. This will automatically reload\r
+ watchdog counter.\r
+\r
+ (#) Then the application program must refresh the IWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset, using\r
+ HAL_IWDG_Refresh() function.\r
+\r
+ *** IWDG HAL driver macros list ***\r
+ ====================================\r
+ [..]\r
+ Below the list of most used macros in IWDG HAL driver:\r
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral\r
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in\r
+ the reload register\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+/** @addtogroup IWDG\r
+ * @brief IWDG HAL module driver.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup IWDG_Private_Defines IWDG Private Defines\r
+ * @{\r
+ */\r
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With \r
+ higher prescaler (256), and according to LSI variation, we need to wait at \r
+ least 6 cycles so 48 ms. */\r
+#define HAL_IWDG_DEFAULT_TIMEOUT 48u\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup IWDG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG_Exported_Functions_Group1\r
+ * @brief Initialization and Start functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Start functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the IWDG according to the specified parameters in the \r
+ IWDG_InitTypeDef of associated handle.\r
+ (+) Manage Window option.\r
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog \r
+ is reloaded in order to exit function with correct time base.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the IWDG according to the specified parameters in the \r
+ * IWDG_InitTypeDef and start watchdog. Before exiting function, \r
+ * watchdog is refreshed in order to have correct time base.\r
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check the IWDG handle allocation */\r
+ if(hiwdg == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));\r
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));\r
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));\r
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));\r
+\r
+ /* Enable IWDG. LSI is turned on automaticaly */\r
+ __HAL_IWDG_START(hiwdg);\r
+\r
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing\r
+ 0x5555 in KR */\r
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);\r
+\r
+ /* Write to IWDG registers the Prescaler & Reload values to work with */\r
+ hiwdg->Instance->PR = hiwdg->Init.Prescaler;\r
+ hiwdg->Instance->RLR = hiwdg->Init.Reload;\r
+\r
+ /* Check pending flag, if previous update not done, return timeout */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for register to be updated */\r
+ while(hiwdg->Instance->SR != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* If window parameter is different than current value, modify window \r
+ register */\r
+ if(hiwdg->Instance->WINR != hiwdg->Init.Window)\r
+ {\r
+ /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,\r
+ even if window feature is disabled, Watchdog will be reloaded by writing \r
+ windows register */\r
+ hiwdg->Instance->WINR = hiwdg->Init.Window;\r
+ }\r
+ else\r
+ {\r
+ /* Reload IWDG counter with value defined in the reload register */\r
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup IWDG_Exported_Functions_Group2\r
+ * @brief IO operation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Refresh the IWDG.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Refresh the IWDG.\r
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)\r
+{\r
+ /* Reload IWDG counter with value defined in the reload register */\r
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_jpeg.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief JPEG HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the JPEG encoder/decoder peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + JPEG processing functions encoding and decoding\r
+ * + JPEG decoding Getting Info and encoding configuration setting\r
+ * + JPEG enable/disable header parsing functions (for decoding)\r
+ * + JPEG Input/Output Buffer configuration.\r
+ * + JPEG callback functions\r
+ * + JPEG Abort/Pause/Resume functions\r
+ * + JPEG custom quantization tables setting functions\r
+ * + IRQ handler management\r
+ * + Peripheral State and Error functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.\r
+ Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.\r
+\r
+ (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set\r
+ the encoding parameters (mandatory before calling the encoding function).\r
+ the application can change the encoding parameter "ImageQuality" from\r
+ 1 to 100 to obtain a more or less quality (visual quality vs the original row image),\r
+ and inversely more or less jpg file size.\r
+\r
+ (#) Note that for decoding operation the JPEG peripheral output data are organized in\r
+ YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification\r
+ ISO/IEC 10918-1 standard. \r
+ It is up to the application to transform these YCbCr blocks to RGB data that can be display.\r
+ \r
+ Respectively, for Encoding operation the JPEG peripheral input should be organized\r
+ in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr\r
+ MCU blocks transformation before feeding the JPEG peripheral with data.\r
+\r
+ (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively\r
+ a JPEG encoding/decoding operation in polling method (blocking).\r
+\r
+ (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively\r
+ a JPEG encoding/decoding operation with Interrupt method (not blocking).\r
+\r
+ (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively\r
+ a JPEG encoding/decoding operation with DMA method (not blocking).\r
+\r
+ (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation \r
+ is a JPEG decoding to provide the application with JPEG image parameters.\r
+ This callback is asserted when the JPEG peripheral successfully parse the\r
+ JPEG header.\r
+\r
+ (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding\r
+ operations to inform the application that the input buffer has been\r
+ consumed by the peripheral and to ask for a new data chunk if the operation\r
+ (encoding/decoding) has not been complete yet.\r
+\r
+ This CallBack should be implemented in the application side. It should \r
+ call the function HAL_JPEG_ConfigInputBuffer if new input data are available, \r
+ or call HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_INPUT" \r
+ to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the\r
+ application to provide a new input data chunk. \r
+ Once the application succeed getting new data and if the input has been paused,\r
+ the application can call the function HAL_JPEG_ConfigInputBuffer to set the new\r
+ input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.\r
+ If the application has ended feeding the HAL JPEG with input data (no more input data), the application \r
+ Should call the function \93HAL_JPEG_ConfigInputBuffer\94 (within the callback HAL_JPEG_GetDataCallback) \r
+ with the parameter \93InDataLength\94 set to zero.\r
+ \r
+ The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows\r
+ to the application to provide the input data (for encoding or decoding) by chunks.\r
+ If the new input data chunk is not available (because data should be read from an input file\r
+ for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)\r
+ Once the new input data chunk is available ( read from a file for example), the application\r
+ can call the function "HAL_JPEG_ConfigInputBuffer" to provide the HAL with the new chunk\r
+ then resume the JPEG HAL input by calling function "HAL_JPEG_Resume".\r
+ \r
+ The application can call functions \93HAL_JPEG_ConfigInputBuffer \93 then "HAL_JPEG_Resume".\r
+ any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available.\r
+ However, to keep data coherency, the function \93HAL_JPEG_Pause\94 must be imperatively called\r
+ (if necessary) within the callback \93HAL_JPEG_GetDataCallback\94, i.e when the HAL JPEG has ended\r
+ Transferring the previous chunk buffer to the JPEG peripheral.\r
+ \r
+ (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver\r
+ has filled the given output buffer with the given size.\r
+ \r
+ This CallBack should be implemented in the application side. It should \r
+ call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver\r
+ with the new output buffer location and size to be used to store next data chunk.\r
+ if the application is not ready to provide the output chunk location then it can\r
+ call the function "HAL_JPEG_Pause" with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT"\r
+ to inform the JPEG HAL driver that it shall pause output data. Once the application\r
+ is ready to receive the new data chunk (output buffer location free or available) it should call\r
+ the function "HAL_JPEG_ConfigOutputBuffer" to provide the HAL JPEG driver\r
+ with the new output chunk buffer location and size, then call "HAL_JPEG_Resume" \r
+ to inform the HAL that it shall resume outputting data in the given output buffer.\r
+\r
+ The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows\r
+ the application to receive data from the JPEG peripheral by chunks. when a chunk\r
+ is received, the application can pause the HAL JPEG output data to be able to process\r
+ these received data (YCbCr to RGB conversion in case of decoding or data storage in case\r
+ of encoding).\r
+\r
+ The application can call functions \93HAL_JPEG_ ConfigOutputBuffer\93 then "HAL_JPEG_Resume".\r
+ any time (outside the HAL_JPEG_ DataReadyCallback) Once the output data buffer is free to use.\r
+ However, to keep data coherency, the function \93HAL_JPEG_Pause\94 must be imperatively called\r
+ (if necessary) within the callback \93HAL_JPEG_ DataReadyCallback\94, i.e when the HAL JPEG has ended\r
+ Transferring the previous chunk buffer from the JPEG peripheral to the application.\r
+\r
+ (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has\r
+ ended the current JPEG encoding operation, and all output data has been transmitted\r
+ to the application.\r
+\r
+ (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has\r
+ ended the current JPEG decoding operation. and all output data has been transmitted\r
+ to the application.\r
+\r
+ (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during \r
+ the current operation. the application can call the function "HAL_JPEG_GetError"\r
+ to retrieve the error codes.\r
+\r
+ (#) By default the HAL JPEG driver uses the default quantization tables\r
+ as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.\r
+ User can change these default tables if necessary using the function "HAL_JPEG_SetUserQuantTables"\r
+ Note that for decoding the quantization tables are automatically extracted from\r
+ the JPEG header.\r
+\r
+ (#) To control JPEG state you can use the following function: HAL_JPEG_GetState() \r
+\r
+ *** JPEG HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in JPEG HAL driver.\r
+ \r
+ (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.\r
+ (+) __HAL_JPEG_ENABLE : Enable the JPEG peripheral.\r
+ (+) __HAL_JPEG_DISABLE : Disable the JPEG peripheral.\r
+ (+) __HAL_JPEG_GET_FLAG : Check the specified JPEG status flag.\r
+ (+) __HAL_JPEG_CLEAR_FLAG : Clear the specified JPEG status flag.\r
+ (+) __HAL_JPEG_ENABLE_IT : Enable the specified JPEG Interrupt.\r
+ (+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt.\r
+ (+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled).\r
+\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup JPEG JPEG \r
+ * @brief JPEG HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_JPEG_MODULE_ENABLED\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup JPEG_Private_Constants\r
+ * @{\r
+ */\r
+#define JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */\r
+#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/\r
+#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/\r
+\r
+#define JPEG_FIFO_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO size in words*/\r
+\r
+#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/\r
+\r
+#define JPEG_DMA_MASK ((uint32_t)0x00001800U) /* JPEG DMA request Mask*/\r
+#define JPEG_DMA_IDMA ((uint32_t)JPEG_CR_IDMAEN) /* DMA request for the input FIFO */\r
+#define JPEG_DMA_ODMA ((uint32_t)JPEG_CR_ODMAEN) /* DMA request for the output FIFO */ \r
+\r
+#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/\r
+#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/\r
+#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */\r
+\r
+#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */\r
+#define JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */\r
+#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */\r
+#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */\r
+\r
+\r
+#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */\r
+\r
+#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */\r
+#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */\r
+ \r
+#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */\r
+\r
+#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */\r
+ \r
+#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */\r
+#define JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/** @addtogroup JPEG_Private_Types\r
+ * @{\r
+ */\r
+\r
+/* \r
+ JPEG Huffman Table Structure definition : \r
+ This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification \r
+ */ \r
+typedef struct \r
+{\r
+ /* These two fields directly represent the contents of a JPEG DHT marker */\r
+ uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */\r
+ \r
+ uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */\r
+ \r
+ \r
+}JPEG_ACHuffTableTypeDef;\r
+\r
+typedef struct \r
+{\r
+ /* These two fields directly represent the contents of a JPEG DHT marker */\r
+ uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */\r
+ \r
+ uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */\r
+ \r
+ \r
+}JPEG_DCHuffTableTypeDef; \r
+ \r
+typedef struct \r
+{\r
+ uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE]; /*!< Code length */\r
+ \r
+ uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */\r
+ \r
+}JPEG_AC_HuffCodeTableTypeDef;\r
+\r
+typedef struct \r
+{\r
+ uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE]; /*!< Code length */\r
+ \r
+ uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */\r
+ \r
+}JPEG_DC_HuffCodeTableTypeDef;\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @addtogroup JPEG_Private_Macros\r
+ * @{\r
+ */\r
+#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK))\r
+/*note : To disable a DMA request we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits \r
+ located in the same DMA request enable register (CR register). */ \r
+#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup JPEG_Private_Variables\r
+ * @{\r
+ */\r
+\r
+static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable =\r
+{\r
+ { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/\r
+ \r
+ { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */\r
+\r
+};\r
+\r
+static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable =\r
+{\r
+ { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, /*Bits*/\r
+ \r
+ { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */\r
+};\r
+\r
+static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable =\r
+{\r
+ { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/\r
+ \r
+ { 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */\r
+ 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,\r
+ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,\r
+ 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,\r
+ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,\r
+ 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,\r
+ 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,\r
+ 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,\r
+ 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,\r
+ 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,\r
+ 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,\r
+ 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,\r
+ 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,\r
+ 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,\r
+ 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,\r
+ 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,\r
+ 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,\r
+ 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,\r
+ 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,\r
+ 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,\r
+ 0xf9, 0xfa }\r
+};\r
+\r
+static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable =\r
+{\r
+ { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/\r
+ \r
+ { 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */\r
+ 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,\r
+ 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,\r
+ 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,\r
+ 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,\r
+ 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,\r
+ 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,\r
+ 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,\r
+ 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,\r
+ 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,\r
+ 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,\r
+ 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,\r
+ 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,\r
+ 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,\r
+ 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,\r
+ 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,\r
+ 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,\r
+ 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,\r
+ 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,\r
+ 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,\r
+ 0xf9, 0xfa }\r
+};\r
+\r
+\r
+/* \r
+ These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1.\r
+*/\r
+static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] = \r
+{\r
+ 16, 11, 10, 16, 24, 40, 51, 61,\r
+ 12, 12, 14, 19, 26, 58, 60, 55,\r
+ 14, 13, 16, 24, 40, 57, 69, 56,\r
+ 14, 17, 22, 29, 51, 87, 80, 62,\r
+ 18, 22, 37, 56, 68, 109, 103, 77,\r
+ 24, 35, 55, 64, 81, 104, 113, 92,\r
+ 49, 64, 78, 87, 103, 121, 120, 101,\r
+ 72, 92, 95, 98, 112, 100, 103, 99\r
+};\r
+static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] = \r
+{\r
+ 17, 18, 24, 47, 99, 99, 99, 99,\r
+ 18, 21, 26, 66, 99, 99, 99, 99,\r
+ 24, 26, 56, 99, 99, 99, 99, 99,\r
+ 47, 66, 99, 99, 99, 99, 99, 99,\r
+ 99, 99, 99, 99, 99, 99, 99, 99,\r
+ 99, 99, 99, 99, 99, 99, 99, 99,\r
+ 99, 99, 99, 99, 99, 99, 99, 99,\r
+ 99, 99, 99, 99, 99, 99, 99, 99\r
+};\r
+\r
+static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =\r
+{\r
+ 0, 1, 8, 16, 9, 2, 3, 10,\r
+ 17, 24, 32, 25, 18, 11, 4, 5,\r
+ 12, 19, 26, 33, 40, 48, 41, 34,\r
+ 27, 20, 13, 6, 7, 14, 21, 28,\r
+ 35, 42, 49, 56, 57, 50, 43, 36,\r
+ 29, 22, 15, 23, 30, 37, 44, 51,\r
+ 58, 59, 52, 45, 38, 31, 39, 46,\r
+ 53, 60, 61, 54, 47, 55, 62, 63\r
+};\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup JPEG_Private_Functions_Prototypes\r
+ * @{\r
+ */\r
+\r
+static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK);\r
+static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);\r
+static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);\r
+static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress);\r
+static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress);\r
+static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);\r
+static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);\r
+static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress);\r
+static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg);\r
+static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg);\r
+static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg);\r
+\r
+static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg);\r
+static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg);\r
+static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords);\r
+static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords);\r
+static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg);\r
+\r
+static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);\r
+static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);\r
+static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);\r
+static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma);\r
+static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma);\r
+static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma);\r
+static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup JPEG_Exported_Functions JPEG Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and de-initialization functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the JPEG peripheral and creates the associated handle\r
+ (+) DeInitialize the JPEG peripheral\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the JPEG according to the specified\r
+ * parameters in the JPEG_InitTypeDef and creates the associated handle.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /*Note : these intermediate variables are used to avoid MISRA warning \r
+ regarding rule 11.5 */\r
+ uint32_t acLum_huffmanTableAddr = (uint32_t)(&JPEG_ACLUM_HuffTable);\r
+ uint32_t dcLum_huffmanTableAddr = (uint32_t)(&JPEG_DCLUM_HuffTable);\r
+ uint32_t acChrom_huffmanTableAddr = (uint32_t)(&JPEG_ACCHROM_HuffTable);\r
+ uint32_t dcChrom_huffmanTableAddr = (uint32_t)(&JPEG_DCCHROM_HuffTable);\r
+ \r
+ /* Check the JPEG handle allocation */\r
+ if(hjpeg == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hjpeg->State == HAL_JPEG_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hjpeg->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_JPEG_MspInit(hjpeg);\r
+ }\r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY;\r
+ \r
+ /* Start the JPEG Core*/\r
+ __HAL_JPEG_ENABLE(hjpeg);\r
+ \r
+ /* Stop the JPEG encoding/decoding process*/\r
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;\r
+ \r
+ /* Disable All Interrupts */\r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ \r
+ /* Disable All DMA requests */\r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);\r
+ \r
+ /* Flush input and output FIFOs*/\r
+ hjpeg->Instance->CR |= JPEG_CR_IFF;\r
+ hjpeg->Instance->CR |= JPEG_CR_OFF; \r
+ \r
+ /* Clear all flags */\r
+ __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r
+ \r
+ hjpeg->QuantTable0 = (uint8_t *)JPEG_LUM_QuantTable;\r
+ hjpeg->QuantTable1 = (uint8_t *)JPEG_CHROM_QuantTable;\r
+ hjpeg->QuantTable2 = NULL;\r
+ hjpeg->QuantTable3 = NULL;\r
+ \r
+ /* init the default Huffman tables*/\r
+ if(JPEG_Set_HuffEnc_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)acLum_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcLum_huffmanTableAddr, (JPEG_ACHuffTableTypeDef *)acChrom_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcChrom_huffmanTableAddr) != HAL_OK)\r
+ {\r
+ hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE;\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Enable header processing*/\r
+ hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;\r
+ \r
+ /* Reset JpegInCount and JpegOutCount */\r
+ hjpeg->JpegInCount = 0;\r
+ hjpeg->JpegOutCount = 0;\r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_READY;\r
+ \r
+ /* Reset the JPEG ErrorCode */\r
+ hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;\r
+ \r
+ /*Clear the context filelds*/\r
+ hjpeg->Context = 0;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the JPEG peripheral. \r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Check the JPEG handle allocation */\r
+ if(hjpeg == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* DeInit the low level hardware: CLOCK, NVIC.*/\r
+ HAL_JPEG_MspDeInit(hjpeg); \r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY;\r
+ \r
+ /* Reset the JPEG ErrorCode */\r
+ hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;\r
+ \r
+ /* Reset JpegInCount and JpegOutCount */\r
+ hjpeg->JpegInCount = 0;\r
+ hjpeg->JpegOutCount = 0;\r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_RESET;\r
+ \r
+ /*Clear the context fields*/\r
+ hjpeg->Context = 0;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hjpeg);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the JPEG MSP.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes JPEG MSP.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions \r
+ * @brief JPEG Configuration functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Configuration functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration\r
+ (+) HAL_JPEG_GetInfo() : Extract the image configuration from the JPEG header during the decoding\r
+ (+) HAL_JPEG_EnableHeaderParsing() : Enable JPEG Header parsing for decoding\r
+ (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding\r
+ (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the JPEG encoding configuration. \r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pConf: pointer to a JPEG_ConfTypeDef structure that contains\r
+ * the encoding configuration \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)\r
+{\r
+ uint32_t error = HAL_OK;\r
+ uint32_t numberMCU, hfactor, vfactor,hMCU, vMCU; \r
+ \r
+ /* Check the JPEG handle allocation */\r
+ if( (hjpeg == NULL) || (pConf == NULL) )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace));\r
+ assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling));\r
+ assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ { \r
+ hjpeg->State = HAL_JPEG_STATE_BUSY;\r
+ \r
+ hjpeg->Conf.ColorSpace = pConf->ColorSpace;\r
+ hjpeg->Conf.ChromaSubsampling = pConf->ChromaSubsampling; \r
+ hjpeg->Conf.ImageHeight = pConf->ImageHeight;\r
+ hjpeg->Conf.ImageWidth = pConf->ImageWidth; \r
+ hjpeg->Conf.ImageQuality = pConf->ImageQuality; \r
+ \r
+ /* Reset the Color Space : by default only one quantization table is used*/ \r
+ hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE;\r
+ \r
+ /* Set Number of color components*/ \r
+ if(hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)\r
+ { \r
+ /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/\r
+ hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING;\r
+ \r
+ JPEG_SetColorGrayScale(hjpeg);\r
+ /* Set quantization table 0*/\r
+ error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0)); \r
+ }\r
+ else if(hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE) \r
+ {\r
+ /* \r
+ Set the Color Space for YCbCr : 2 quantization tables are used \r
+ one for Luminance(Y) and one for both Chrominances (Cb & Cr)\r
+ */\r
+ hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0;\r
+ \r
+ JPEG_SetColorYCBCR(hjpeg);\r
+ \r
+ /* Set quantization table 0*/\r
+ error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));\r
+ /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/\r
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1));\r
+\r
+ if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/\r
+ {\r
+ /* use 3 quantization tables , one for each component*/\r
+ hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE);\r
+ hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1;\r
+ \r
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2));\r
+ \r
+ /*Use Quantization 1 table for component 1*/\r
+ hjpeg->Instance->CONFR5 &= (~JPEG_CONFR6_QT); \r
+ hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; \r
+ \r
+ /*Use Quantization 2 table for component 2*/\r
+ hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT);\r
+ hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; \r
+ }\r
+ }\r
+ else if(hjpeg->Conf.ColorSpace == JPEG_CMYK_COLORSPACE)\r
+ {\r
+ JPEG_SetColorCMYK(hjpeg);\r
+ \r
+ /* Set quantization table 0*/\r
+ error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));\r
+ /*By default quantization table 0 for All components*/ \r
+ \r
+ if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/\r
+ {\r
+ /* use 4 quantization tables , one for each component*/\r
+ hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE;\r
+ \r
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1));\r
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2));\r
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (uint32_t *)(hjpeg->Instance->QMEM3));\r
+ \r
+ /*Use Quantization 1 table for component 1*/\r
+ hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; \r
+ \r
+ /*Use Quantization 2 table for component 2*/\r
+ hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1;\r
+ \r
+ /*Use Quantization 3 table for component 3*/\r
+ hjpeg->Instance->CONFR7 |= JPEG_CONFR7_QT; \r
+ }\r
+ }\r
+\r
+ if(error != HAL_OK)\r
+ {\r
+ hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Set the JPEG State to ready */\r
+ hjpeg->State = HAL_JPEG_STATE_READY;\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ /* Set the image size*/\r
+ hjpeg->Instance->CONFR1 |= ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16); /* set the number of lines*/\r
+ hjpeg->Instance->CONFR3 |= ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16); /* set the number of pixels per line*/\r
+ \r
+ if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/\r
+ {\r
+ hfactor = 16;\r
+ vfactor = 16;\r
+ }\r
+ else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/\r
+ {\r
+ hfactor = 16;\r
+ vfactor = 8; \r
+ } \r
+ else /* Default is 8x8 MCU, 4:4:4*/\r
+ {\r
+ hfactor = 8;\r
+ vfactor = 8; \r
+ } \r
+ \r
+ hMCU = (hjpeg->Conf.ImageWidth / hfactor);\r
+ if((hjpeg->Conf.ImageWidth % hfactor) != 0)\r
+ {\r
+ hMCU++; /*+1 for horizontal incomplete MCU */ \r
+ }\r
+\r
+ vMCU = (hjpeg->Conf.ImageHeight / vfactor);\r
+ if((hjpeg->Conf.ImageHeight % vfactor) != 0)\r
+ {\r
+ vMCU++; /*+1 for vertical incomplete MCU */ \r
+ }\r
+ \r
+ numberMCU = (hMCU * vMCU) - 1; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/\r
+ /* Set the number of MCU*/\r
+ hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU);\r
+ \r
+ hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Set the JPEG State to ready */\r
+ hjpeg->State = HAL_JPEG_STATE_READY; \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Return function status */\r
+ return HAL_BUSY;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Extract the image configuration from the JPEG header during the decoding\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains\r
+ * The JPEG decoded header informations\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)\r
+{\r
+ uint32_t yblockNb, cBblockNb, cRblockNb;\r
+ \r
+ /* Check the JPEG handle allocation */\r
+ if((hjpeg == NULL) || (pInfo == NULL))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /*Read the conf parameters */\r
+ if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)\r
+ {\r
+ pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE; \r
+ } \r
+ else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0)\r
+ {\r
+ pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE;\r
+ }\r
+ else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)\r
+ {\r
+ pInfo->ColorSpace = JPEG_CMYK_COLORSPACE; \r
+ }\r
+ \r
+ pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000U) >> 16;\r
+ pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000U) >> 16;\r
+ \r
+ if((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))\r
+ {\r
+ yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4;\r
+ cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4;\r
+ cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4;\r
+ \r
+ if((yblockNb == 1) && (cBblockNb == 0) && (cRblockNb == 0))\r
+ {\r
+ pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/\r
+ }\r
+ else if((yblockNb == 0) && (cBblockNb == 0) && (cRblockNb == 0))\r
+ {\r
+ pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;\r
+ }\r
+ else if((yblockNb == 3) && (cBblockNb == 0) && (cRblockNb == 0))\r
+ {\r
+ pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING;\r
+ }\r
+ else /*Default is 4:4:4*/\r
+ {\r
+ pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;\r
+ } \r
+ }\r
+ else \r
+ {\r
+ pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;\r
+ }\r
+ \r
+ pInfo->ImageQuality = JPEG_GetQuality(hjpeg);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable JPEG Header parsing for decoding\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for the JPEG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ {\r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY;\r
+ \r
+ /* Enable header processing*/\r
+ hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable JPEG Header parsing for decoding\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for the JPEG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ {\r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY;\r
+ \r
+ /* Disable header processing*/\r
+ hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Modify the default Quantization tables used for JPEG encoding.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param QTable0 : pointer to uint8_t , define the user quantification table for color component 1.\r
+ * If NULL assume no need to update the table and no error return\r
+ * @param QTable1 : pointer to uint8_t , define the user quantification table for color component 2. \r
+ * If NULL assume no need to update the table and no error return.\r
+ * @param QTable2 : pointer to uint8_t , define the user quantification table for color component 3, \r
+ * If NULL assume no need to update the table and no error return. \r
+ * @param QTable3 : pointer to uint8_t , define the user quantification table for color component 4. \r
+ * If NULL assume no need to update the table and no error return.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+\r
+\r
+HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ {\r
+ /* Change the DMA state */\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY;\r
+ \r
+ hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES;\r
+ \r
+ hjpeg->QuantTable0 = QTable0;\r
+ hjpeg->QuantTable1 = QTable1;\r
+ hjpeg->QuantTable2 = QTable2;\r
+ hjpeg->QuantTable3 = QTable3;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Change the DMA state */\r
+ hjpeg->State = HAL_JPEG_STATE_READY; \r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions \r
+ * @brief processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### JPEG processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) HAL_JPEG_Encode() : JPEG encoding with polling process \r
+ (+) HAL_JPEG_Decode() : JPEG decoding with polling process\r
+ (+) HAL_JPEG_Encode_IT() : JPEG encoding with interrupt process\r
+ (+) HAL_JPEG_Decode_IT() : JPEG decoding with interrupt process\r
+ (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process\r
+ (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process\r
+ (+) HAL_JPEG_Pause() : Pause the Input/Output processing \r
+ (+) HAL_JPEG_Resume() : Resume the JPEG Input/Output processing\r
+ (+) HAL_JPEG_ConfigInputBuffer() : Config Encoding/Decoding Input Buffer\r
+ (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer\r
+ (+) HAL_JPEG_Abort() : Aborts the JPEG Encoding/Decoding\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts JPEG encoding with polling processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pDataInMCU: Pointer to the Input buffer\r
+ * @param InDataLength: size in bytes Input buffer\r
+ * @param pDataOut: Pointer to the jpeg output data buffer\r
+ * @param OutDataLength: size in bytes of the Output buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param((InDataLength >= 4));\r
+ assert_param((OutDataLength >= 4));\r
+ \r
+ /* Check In/out buffer allocation and size */\r
+ if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \\r
+ (InDataLength == 0) || (OutDataLength == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State != HAL_JPEG_STATE_READY)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY; \r
+ }\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ { \r
+ if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )\r
+ { \r
+ /*Change JPEG state*/\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;\r
+ \r
+ /*Set the Context to Encode with Polling*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r
+ hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick(); \r
+ /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r
+ InDataLength = InDataLength - (InDataLength % 4);\r
+ OutDataLength = OutDataLength - (OutDataLength % 4);\r
+ \r
+ /*Store In/out buffers pointers and size*/\r
+ hjpeg->pJpegInBuffPtr = pDataInMCU;\r
+ hjpeg->pJpegOutBuffPtr = pDataOut;\r
+ hjpeg->InDataLength = InDataLength;\r
+ hjpeg->OutDataLength = OutDataLength;\r
+ \r
+ /*Reset In/out data counter */\r
+ hjpeg->JpegInCount = 0; \r
+ hjpeg->JpegOutCount = 0;\r
+ \r
+ /*Init decoding process*/\r
+ JPEG_Init_Process(hjpeg);\r
+ \r
+ /*JPEG data processing : In/Out FIFO transfer*/\r
+ while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ \r
+ /* Update error code */\r
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /*Change JPEG state*/\r
+ hjpeg->State= HAL_JPEG_STATE_READY; \r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /*Change JPEG state*/\r
+ hjpeg->State= HAL_JPEG_STATE_READY;\r
+ \r
+ }else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts JPEG decoding with polling processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pDataIn: Pointer to the input data buffer \r
+ * @param InDataLength: size in bytes Input buffer\r
+ * @param pDataOutMCU: Pointer to the Output data buffer\r
+ * @param OutDataLength: size in bytes of the Output buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param((InDataLength >= 4));\r
+ assert_param((OutDataLength >= 4));\r
+ \r
+ /* Check In/out buffer allocation and size */\r
+ if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \\r
+ (InDataLength == 0) || (OutDataLength == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ {\r
+ /*Change JPEG state*/\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;\r
+ \r
+ /*Set the Context to Decode with Polling*/\r
+ /*Set the Context to Encode with Polling*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r
+ hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING); \r
+ \r
+ /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r
+ InDataLength = InDataLength - (InDataLength % 4);\r
+ OutDataLength = OutDataLength - (OutDataLength % 4);\r
+ \r
+ /*Store In/out buffers pointers and size*/\r
+ hjpeg->pJpegInBuffPtr = pDataIn;\r
+ hjpeg->pJpegOutBuffPtr = pDataOutMCU;\r
+ hjpeg->InDataLength = InDataLength;\r
+ hjpeg->OutDataLength = OutDataLength;\r
+ \r
+ /*Reset In/out data counter */\r
+ hjpeg->JpegInCount = 0; \r
+ hjpeg->JpegOutCount = 0;\r
+ \r
+ /*Init decoding process*/\r
+ JPEG_Init_Process(hjpeg);\r
+\r
+ /*JPEG data processing : In/Out FIFO transfer*/\r
+ while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ \r
+ /* Update error code */\r
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+\r
+ /*Change JPEG state*/\r
+ hjpeg->State= HAL_JPEG_STATE_READY; \r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /*Change JPEG state*/\r
+ hjpeg->State= HAL_JPEG_STATE_READY; \r
+ \r
+ }else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts JPEG encoding with interrupt processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pDataInMCU: Pointer to the Input buffer\r
+ * @param InDataLength: size in bytes Input buffer\r
+ * @param pDataOut: Pointer to the jpeg output data buffer\r
+ * @param OutDataLength: size in bytes of the Output buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param((InDataLength >= 4));\r
+ assert_param((OutDataLength >= 4));\r
+ \r
+ /* Check In/out buffer allocation and size */\r
+ if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \\r
+ (InDataLength == 0) || (OutDataLength == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State != HAL_JPEG_STATE_READY)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY; \r
+ } \r
+ else \r
+ {\r
+ if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )\r
+ {\r
+ /*Change JPEG state*/\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;\r
+ \r
+ /*Set the Context to Encode with IT*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r
+ hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT); \r
+ \r
+ /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r
+ InDataLength = InDataLength - (InDataLength % 4);\r
+ OutDataLength = OutDataLength - (OutDataLength % 4);\r
+ \r
+ /*Store In/out buffers pointers and size*/\r
+ hjpeg->pJpegInBuffPtr = pDataInMCU;\r
+ hjpeg->pJpegOutBuffPtr = pDataOut;\r
+ hjpeg->InDataLength = InDataLength;\r
+ hjpeg->OutDataLength = OutDataLength;\r
+ \r
+ /*Reset In/out data counter */\r
+ hjpeg->JpegInCount = 0; \r
+ hjpeg->JpegOutCount = 0;\r
+ \r
+ /*Init decoding process*/\r
+ JPEG_Init_Process(hjpeg); \r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts JPEG decoding with interrupt processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pDataIn: Pointer to the input data buffer \r
+ * @param InDataLength: size in bytes Input buffer\r
+ * @param pDataOutMCU: Pointer to the Output data buffer\r
+ * @param OutDataLength: size in bytes of the Output buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param((InDataLength >= 4));\r
+ assert_param((OutDataLength >= 4));\r
+ \r
+ /* Check In/out buffer allocation and size */\r
+ if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \\r
+ (InDataLength == 0) || (OutDataLength == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ {\r
+ /*Change JPEG state*/\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;\r
+ \r
+ /*Set the Context to Decode with IT*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r
+ hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT); \r
+ \r
+ /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r
+ InDataLength = InDataLength - (InDataLength % 4);\r
+ OutDataLength = OutDataLength - (OutDataLength % 4);\r
+ \r
+ /*Store In/out buffers pointers and size*/\r
+ hjpeg->pJpegInBuffPtr = pDataIn;\r
+ hjpeg->pJpegOutBuffPtr = pDataOutMCU;\r
+ hjpeg->InDataLength = InDataLength;\r
+ hjpeg->OutDataLength = OutDataLength;\r
+ \r
+ /*Reset In/out data counter */\r
+ hjpeg->JpegInCount = 0; \r
+ hjpeg->JpegOutCount = 0; \r
+ \r
+ /*Init decoding process*/\r
+ JPEG_Init_Process(hjpeg); \r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts JPEG encoding with DMA processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pDataInMCU: Pointer to the Input buffer\r
+ * @param InDataLength: size in bytes Input buffer\r
+ * @param pDataOut: Pointer to the jpeg output data buffer\r
+ * @param OutDataLength: size in bytes of the Output buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param((InDataLength >= 4));\r
+ assert_param((OutDataLength >= 4));\r
+ \r
+ /* Check In/out buffer allocation and size */\r
+ if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \\r
+ (InDataLength == 0) || (OutDataLength == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State != HAL_JPEG_STATE_READY)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY; \r
+ } \r
+ else \r
+ {\r
+ if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )\r
+ {\r
+ /*Change JPEG state*/\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;\r
+ \r
+ /*Set the Context to Encode with DMA*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r
+ hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA); \r
+ \r
+ /*Store In/out buffers pointers and size*/\r
+ hjpeg->pJpegInBuffPtr = pDataInMCU;\r
+ hjpeg->pJpegOutBuffPtr = pDataOut;\r
+ hjpeg->InDataLength = InDataLength;\r
+ hjpeg->OutDataLength = OutDataLength;\r
+ \r
+ /*Reset In/out data counter */\r
+ hjpeg->JpegInCount = 0; \r
+ hjpeg->JpegOutCount = 0;\r
+ \r
+ /*Init decoding process*/\r
+ JPEG_Init_Process(hjpeg);\r
+ \r
+ /* JPEG encoding process using DMA */\r
+ JPEG_DMA_StartProcess(hjpeg);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts JPEG decoding with DMA processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pDataIn: Pointer to the input data buffer \r
+ * @param InDataLength: size in bytes Input buffer\r
+ * @param pDataOutMCU: Pointer to the Output data buffer\r
+ * @param OutDataLength: size in bytes of the Output buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param((InDataLength >= 4));\r
+ assert_param((OutDataLength >= 4));\r
+ \r
+ /* Check In/out buffer allocation and size */\r
+ if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \\r
+ (InDataLength == 0) || (OutDataLength == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hjpeg);\r
+ \r
+ if(hjpeg->State == HAL_JPEG_STATE_READY)\r
+ {\r
+ /*Change JPEG state*/\r
+ hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;\r
+ \r
+ /*Set the Context to Decode with DMA*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r
+ hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA); \r
+ \r
+ /*Store In/out buffers pointers and size*/\r
+ hjpeg->pJpegInBuffPtr = pDataIn;\r
+ hjpeg->pJpegOutBuffPtr = pDataOutMCU;\r
+ hjpeg->InDataLength = InDataLength;\r
+ hjpeg->OutDataLength = OutDataLength;\r
+ \r
+ /*Reset In/out data counter */\r
+ hjpeg->JpegInCount = 0; \r
+ hjpeg->JpegOutCount = 0; \r
+ \r
+ /*Init decoding process*/\r
+ JPEG_Init_Process(hjpeg);\r
+ \r
+ /* JPEG decoding process using DMA */\r
+ JPEG_DMA_StartProcess(hjpeg);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_BUSY;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Pause the JPEG Input/Output processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param XferSelection: This parameter can be one of the following values :\r
+ * JPEG_PAUSE_RESUME_INPUT : Pause Input processing\r
+ * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing\r
+ * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)\r
+{\r
+ uint32_t mask = 0;\r
+ \r
+ assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));\r
+ \r
+ if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r
+ { \r
+ if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r
+ {\r
+ hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;\r
+ mask |= JPEG_DMA_IDMA;\r
+ }\r
+ if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r
+ {\r
+ hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;\r
+ mask |= JPEG_DMA_ODMA;\r
+ } \r
+ JPEG_DISABLE_DMA(hjpeg,mask);\r
+\r
+ }\r
+ else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r
+ { \r
+ \r
+ if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r
+ {\r
+ hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;\r
+ mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); \r
+ }\r
+ if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r
+ {\r
+ hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;\r
+ mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); \r
+ } \r
+ __HAL_JPEG_DISABLE_IT(hjpeg,mask);\r
+\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Resume the JPEG Input/Output processing\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param XferSelection: This parameter can be one of the following values :\r
+ * JPEG_PAUSE_RESUME_INPUT : Resume Input processing\r
+ * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing\r
+ * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)\r
+{\r
+ uint32_t mask = 0;\r
+\r
+ assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); \r
+ \r
+ if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r
+ {\r
+ \r
+ if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r
+ {\r
+ hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);\r
+ mask |= JPEG_DMA_IDMA;\r
+ \r
+ /*JPEG Input DMA transfer data number must be multiple of DMA buffer size \r
+ as the destination is a 32 bits register */\r
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);\r
+ \r
+ if(hjpeg->InDataLength > 0)\r
+ { \r
+ /* Start DMA FIFO In transfer */\r
+ HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);\r
+ }\r
+ \r
+ }\r
+ if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r
+ {\r
+ hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);\r
+ mask |= JPEG_DMA_ODMA;\r
+ \r
+ /* Start DMA FIFO Out transfer */\r
+ HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);\r
+ } \r
+ JPEG_ENABLE_DMA(hjpeg,mask);\r
+\r
+ }\r
+ else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r
+ { \r
+ if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r
+ {\r
+ hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);\r
+ mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); \r
+ }\r
+ if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r
+ {\r
+ hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);\r
+ mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); \r
+ } \r
+ __HAL_JPEG_ENABLE_IT(hjpeg,mask);\r
+\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Config Encoding/Decoding Input Buffer.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module.\r
+ * @param pNewInputBuffer: Pointer to the new input data buffer\r
+ * @param InDataLength: Size in bytes of the new Input data buffer \r
+ * @retval HAL status\r
+ */\r
+void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)\r
+{\r
+ hjpeg->pJpegInBuffPtr = pNewInputBuffer;\r
+ hjpeg->InDataLength = InDataLength;\r
+}\r
+\r
+/**\r
+ * @brief Config Encoding/Decoding Output Buffer.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module.\r
+ * @param pNewOutputBuffer: Pointer to the new output data buffer\r
+ * @param OutDataLength: Size in bytes of the new Output data buffer \r
+ * @retval HAL status\r
+ */\r
+void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)\r
+{\r
+ hjpeg->pJpegOutBuffPtr = pNewOutputBuffer;\r
+ hjpeg->OutDataLength = OutDataLength; \r
+}\r
+\r
+/**\r
+ * @brief Aborts the JPEG Encoding/Decoding.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ uint32_t tickstart, tmpContext; \r
+ \r
+ tmpContext = hjpeg->Context;\r
+ \r
+ /*Reset the Context operation and method*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA);\r
+ \r
+ if((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r
+ {\r
+ /* Stop the DMA In/out Xfer*/\r
+ HAL_DMA_Abort(hjpeg->hdmaout);\r
+ HAL_DMA_Abort(hjpeg->hdmain);\r
+ }\r
+ \r
+ /* Stop the JPEG encoding/decoding process*/\r
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check if the JPEG Codec is effectively disabled */\r
+ while(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > JPEG_TIMEOUT_VALUE)\r
+ {\r
+ /* Update error code */\r
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA state */\r
+ hjpeg->State = HAL_JPEG_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ /* Disable All Interrupts */\r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ \r
+ /* Disable All DMA requests */\r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);\r
+ \r
+ /* Flush input and output FIFOs*/\r
+ hjpeg->Instance->CR |= JPEG_CR_IFF;\r
+ hjpeg->Instance->CR |= JPEG_CR_OFF; \r
+ \r
+ /* Clear all flags */\r
+ __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r
+\r
+ /* Reset JpegInCount and JpegOutCount */\r
+ hjpeg->JpegInCount = 0;\r
+ hjpeg->JpegOutCount = 0; \r
+ \r
+ /*Reset the Context Pause*/\r
+ hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT); \r
+ \r
+ /* Change the DMA state*/\r
+ hjpeg->State = HAL_JPEG_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions \r
+ * @brief JPEG process callback functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### JPEG Decode/Encode callback functions #####\r
+ ============================================================================== \r
+ [..] This section provides callback functions:\r
+ (+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback\r
+ (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.\r
+ (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.\r
+ (+) HAL_JPEG_ErrorCallback() : JPEG error callback.\r
+ (+) HAL_JPEG_GetDataCallback() : Get New Data chunk callback. \r
+ (+) HAL_JPEG_DataReadyCallback() : Decoded/Encoded Data ready callback. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Decoding JPEG Info ready callback.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains\r
+ * The JPEG decoded header informations\r
+ * @retval None\r
+ */\r
+__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ UNUSED(pInfo);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Encoding complete callback.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_EncodeCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Decoding complete callback.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_EncodeCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief JPEG error callback.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Get New Data chunk callback.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param NbDecodedData: Number of consummed data in the previous chunk in bytes\r
+ * @retval None\r
+ */\r
+ __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ UNUSED(NbDecodedData);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_GetDataCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Decoded/Encoded Data ready callback.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param pDataOut: pointer to the output data buffer \r
+ * @param OutDataLength: number in bytes of data available in the specified output buffer \r
+ * @retval None\r
+ */\r
+__weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hjpeg);\r
+ UNUSED(pDataOut);\r
+ UNUSED(OutDataLength);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_JPEG_DataReadyCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+\r
+/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management \r
+ * @brief JPEG IRQ handler.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### JPEG IRQ handler management #####\r
+ ============================================================================== \r
+ [..] This section provides JPEG IRQ handler function.\r
+ (+) HAL_JPEG_IRQHandler() : handles JPEG interrupt request\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles JPEG interrupt request.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ switch(hjpeg->State)\r
+ {\r
+ case HAL_JPEG_STATE_BUSY_ENCODING:\r
+ case HAL_JPEG_STATE_BUSY_DECODING: \r
+ /* continue JPEG data encoding/Decoding*/\r
+ /* JPEG data processing : In/Out FIFO transfer*/\r
+ if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r
+ { \r
+ JPEG_Process(hjpeg);\r
+ }\r
+ else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r
+ {\r
+ JPEG_DMA_ContinueProcess(hjpeg);\r
+\r
+ }\r
+ \r
+ break; \r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Error functions #####\r
+ ============================================================================== \r
+ [..] This section provides JPEG State and Errors function.\r
+ (+) HAL_JPEG_GetState() : permits to get in run-time the JPEG state.\r
+ (+) HAL_JPEG_GetError() : Returns the JPEG error code if any.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the JPEG state.\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval JPEG state\r
+ */\r
+HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ return hjpeg->State;\r
+}\r
+\r
+/**\r
+* @brief Return the JPEG error code\r
+* @param hjpeg : pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified JPEG.\r
+* @retval JPEG Error Code\r
+*/\r
+uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ return hjpeg->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @addtogroup JPEG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Generates Huffman sizes/Codes Table from Bits/vals Table\r
+ * @param Bits: pointer to bits table\r
+ * @param Huffsize: pointer to sizes table\r
+ * @param Huffcode: pointer to codes table\r
+ * @param LastK: pointer to last Coeff (table dimmension) \r
+ * @retval HAL status\r
+ */ \r
+static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)\r
+{ \r
+ uint32_t i, p, l, code, si;\r
+ \r
+ /* Figure C.1 \96 Generation of table of Huffman code sizes */\r
+ p = 0;\r
+ for (l = 0; l < 16; l++) \r
+ {\r
+ i = (uint32_t)Bits[l];\r
+ if ( (p + i) > 256)\r
+ { /* check for table overflow */\r
+ return HAL_ERROR;\r
+ }\r
+ while (i != 0)\r
+ {\r
+ Huffsize[p++] = (uint8_t) l+1;\r
+ i--;\r
+ }\r
+ }\r
+ Huffsize[p] = 0;\r
+ *LastK = p; \r
+ \r
+ /* Figure C.2 \96 Generation of table of Huffman codes */ \r
+ code = 0;\r
+ si = Huffsize[0];\r
+ p = 0;\r
+ while (Huffsize[p] != 0) \r
+ {\r
+ while (((uint32_t) Huffsize[p]) == si) \r
+ {\r
+ Huffcode[p++] = code;\r
+ code++;\r
+ }\r
+ /* code must fit in "size" bits (si), no code is allowed to be all ones*/\r
+ if (((uint32_t) code) >= (((uint32_t) 1) << si))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ code <<= 1;\r
+ si++;\r
+ } \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table\r
+ * that can programmed to the JPEG encoder registers\r
+ * @param AC_BitsValsTable: pointer to AC huffman bits/vals table\r
+ * @param AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table \r
+ * @retval HAL status\r
+ */ \r
+static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)\r
+{\r
+ HAL_StatusTypeDef error;\r
+ uint8_t huffsize[257];\r
+ uint32_t huffcode[257];\r
+ uint32_t k;\r
+ uint32_t l,lsb, msb;\r
+ uint32_t lastK;\r
+ \r
+ error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK);\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ }\r
+ \r
+ /* Figure C.3 \96 Ordering procedure for encoding procedure code tables */\r
+ k=0;\r
+ \r
+ while(k < lastK)\r
+ {\r
+ l = AC_BitsValsTable->HuffVal[k];\r
+ if(l == 0)\r
+ {\r
+ l = 160; /*l = 0x00 EOB code*/\r
+ }\r
+ else if(l == 0xF0)/* l = 0xF0 ZRL code*/\r
+ {\r
+ l = 161;\r
+ } \r
+ else\r
+ {\r
+ msb = (l & 0xF0) >> 4;\r
+ lsb = (l & 0x0F);\r
+ l = (msb * 10) + lsb - 1; \r
+ }\r
+ if(l >= JPEG_AC_HUFF_TABLE_SIZE)\r
+ {\r
+ return HAL_ERROR; /* Huffman Table overflow error*/\r
+ }\r
+ else\r
+ {\r
+ AC_SizeCodesTable->HuffmanCode[l] = huffcode[k];\r
+ AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;\r
+ k++;\r
+ } \r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table\r
+ * that can programmed to the JPEG encoder registers\r
+ * @param DC_BitsValsTable: pointer to DC huffman bits/vals table\r
+ * @param DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table \r
+ * @retval HAL status\r
+ */ \r
+static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)\r
+{\r
+ HAL_StatusTypeDef error;\r
+\r
+ uint32_t k;\r
+ uint32_t l;\r
+ uint32_t lastK;\r
+ uint8_t huffsize[257];\r
+ uint32_t huffcode[257]; \r
+ error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK);\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ } \r
+ /* Figure C.3: ordering procedure for encoding procedure code tables */\r
+ k=0;\r
+ \r
+ while(k < lastK)\r
+ {\r
+ l = DC_BitsValsTable->HuffVal[k];\r
+ if(l >= JPEG_DC_HUFF_TABLE_SIZE)\r
+ {\r
+ return HAL_ERROR; /* Huffman Table overflow error*/\r
+ }\r
+ else\r
+ {\r
+ DC_SizeCodesTable->HuffmanCode[l] = huffcode[k];\r
+ DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;\r
+ k++;\r
+ } \r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Set the JPEG register with an DC huffman table at the given DC table address\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param HuffTableDC: pointer to DC huffman table\r
+ * @param DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. \r
+ * @retval HAL status\r
+ */ \r
+static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress)\r
+{\r
+ HAL_StatusTypeDef error = HAL_OK;\r
+ JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;\r
+ uint32_t i, lsb, msb;\r
+ __IO uint32_t *address, *addressDef;\r
+ \r
+ if(DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC0))\r
+ {\r
+ address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE/2));\r
+ }\r
+ else if (DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC1))\r
+ {\r
+ address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE/2));\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(HuffTableDC != NULL)\r
+ {\r
+ error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable);\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ }\r
+ addressDef = address;\r
+ *addressDef = 0x0FFF0FFF;\r
+ addressDef++;\r
+ *addressDef = 0x0FFF0FFF;\r
+ \r
+ i = JPEG_DC_HUFF_TABLE_SIZE;\r
+ while(i>0)\r
+ { \r
+ i--;\r
+ address --;\r
+ msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);\r
+ i--;\r
+ lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);\r
+\r
+ *address = lsb | (msb << 16);\r
+ } \r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Set the JPEG register with an AC huffman table at the given AC table address\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param HuffTableAC: pointer to AC huffman table\r
+ * @param ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. \r
+ * @retval HAL status\r
+ */ \r
+static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress)\r
+{\r
+ HAL_StatusTypeDef error = HAL_OK;\r
+ JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable;\r
+ uint32_t i, lsb, msb;\r
+ __IO uint32_t *address, *addressDef;\r
+ \r
+ if(ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC0))\r
+ {\r
+ address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE/2));\r
+ }\r
+ else if (ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC1))\r
+ {\r
+ address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE/2));\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ if(HuffTableAC != NULL)\r
+ {\r
+ error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable);\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ }\r
+ /* Default values settings : 162\96167 FFFh , 168\96175 FD0h\96FD7h */\r
+ /* Locations 162:175 of each AC table contain information used internally by the core */\r
+\r
+ addressDef = address;\r
+ for(i=0; i<3; i++)\r
+ {\r
+ *addressDef = 0x0FFF0FFF;\r
+ addressDef++;\r
+ }\r
+ *addressDef = 0x0FD10FD0;\r
+ addressDef++;\r
+ *addressDef = 0x0FD30FD2;\r
+ addressDef++;\r
+ *addressDef = 0x0FD50FD4;\r
+ addressDef++;\r
+ *addressDef = 0x0FD70FD6;\r
+ /* end of Locations 162:175 */\r
+\r
+ \r
+ i = JPEG_AC_HUFF_TABLE_SIZE;\r
+ while (i > 0)\r
+ {\r
+ i--;\r
+ address--;\r
+ msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);\r
+ i--;\r
+ lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);\r
+ \r
+ *address = lsb | (msb << 16); \r
+ } \r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the JPEG encoder register huffman tables to used during\r
+ * the encdoing operation\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param HuffTableAC0: AC0 huffman table\r
+ * @param HuffTableDC0: DC0 huffman table\r
+ * @param HuffTableAC1: AC1 huffman table\r
+ * @param HuffTableDC1: DC1 huffman table \r
+ * @retval None\r
+ */ \r
+static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)\r
+{\r
+ HAL_StatusTypeDef error = HAL_OK;\r
+ \r
+ JPEG_Set_Huff_DHTMem(hjpeg, HuffTableAC0, HuffTableDC0, HuffTableAC1, HuffTableDC1);\r
+ \r
+ if(HuffTableAC0 != NULL)\r
+ {\r
+ error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC0, (uint32_t *)(hjpeg->Instance->HUFFENC_AC0));\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ } \r
+ }\r
+ \r
+ if(HuffTableAC1 != NULL)\r
+ {\r
+ error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC1, (uint32_t *)(hjpeg->Instance->HUFFENC_AC1));\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ } \r
+ }\r
+ \r
+ if(HuffTableDC0 != NULL)\r
+ {\r
+ error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC0, (uint32_t *)hjpeg->Instance->HUFFENC_DC0);\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ } \r
+ }\r
+ \r
+ if(HuffTableDC1 != NULL)\r
+ {\r
+ error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC1, (uint32_t *)hjpeg->Instance->HUFFENC_DC1);\r
+ if(error != HAL_OK)\r
+ {\r
+ return error;\r
+ } \r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the JPEG register huffman tables to be included in the JPEG\r
+ * file header (used for encoding only)\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param HuffTableAC0: AC0 huffman table\r
+ * @param HuffTableDC0: DC0 huffman table\r
+ * @param HuffTableAC1: AC1 huffman table\r
+ * @param HuffTableDC1: DC1 huffman table \r
+ * @retval None\r
+ */ \r
+static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)\r
+{\r
+ uint32_t value, index;\r
+ __IO uint32_t *address;\r
+ if(HuffTableDC0 != NULL)\r
+ {\r
+ /* DC0 Huffman Table : BITS*/\r
+ /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/\r
+ address = (hjpeg->Instance->DHTMEM + 3); \r
+ index = 16;\r
+ while(index > 0)\r
+ {\r
+\r
+ *address = (((uint32_t)HuffTableDC0->Bits[index-1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableDC0->Bits[index-2] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableDC0->Bits[index-3] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableDC0->Bits[index-4] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ \r
+ }\r
+ /* DC0 Huffman Table : Val*/\r
+ /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */\r
+ address = (hjpeg->Instance->DHTMEM + 6);\r
+ index = 12;\r
+ while(index > 0)\r
+ {\r
+ *address = (((uint32_t)HuffTableDC0->HuffVal[index-1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableDC0->HuffVal[index-2] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableDC0->HuffVal[index-3] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableDC0->HuffVal[index-4] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ } \r
+ }\r
+\r
+ if(HuffTableAC0 != NULL)\r
+ {\r
+ /* AC0 Huffman Table : BITS*/\r
+ /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/\r
+ address = (hjpeg->Instance->DHTMEM + 10); \r
+ index = 16;\r
+ while(index > 0)\r
+ {\r
+\r
+ *address = (((uint32_t)HuffTableAC0->Bits[index-1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableAC0->Bits[index-2] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableAC0->Bits[index-3] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableAC0->Bits[index-4] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ \r
+ }\r
+ /* AC0 Huffman Table : Val*/\r
+ /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */\r
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */\r
+ address = (hjpeg->Instance->DHTMEM + 51); \r
+ value = *address & 0xFFFF0000U;\r
+ value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFF) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFF);\r
+ *address = value;\r
+ \r
+ /*continue setting 160 AC0 huffman values */\r
+ address--; /* address = hjpeg->Instance->DHTMEM + 50*/\r
+ index = 160;\r
+ while(index > 0)\r
+ {\r
+ *address = (((uint32_t)HuffTableAC0->HuffVal[index-1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableAC0->HuffVal[index-2] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableAC0->HuffVal[index-3] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableAC0->HuffVal[index-4] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ } \r
+ }\r
+\r
+ if(HuffTableDC1 != NULL)\r
+ {\r
+ /* DC1 Huffman Table : BITS*/\r
+ /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/\r
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */\r
+ address = (hjpeg->Instance->DHTMEM + 51);\r
+ value = *address & 0x0000FFFFU;\r
+ value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFF) << 16);\r
+ *address = value;\r
+ \r
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */\r
+ address = (hjpeg->Instance->DHTMEM + 55);\r
+ value = *address & 0xFFFF0000U;\r
+ value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFF); \r
+ *address = value;\r
+ \r
+ /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/\r
+ address--;\r
+ index = 12;\r
+ while(index > 0)\r
+ {\r
+\r
+ *address = (((uint32_t)HuffTableDC1->Bits[index+1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableDC1->Bits[index] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableDC1->Bits[index-1] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableDC1->Bits[index-2] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ \r
+ }\r
+ /* DC1 Huffman Table : Val*/\r
+ /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */\r
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */\r
+ address = (hjpeg->Instance->DHTMEM + 55);\r
+ value = *address & 0x0000FFFF;\r
+ value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFF) << 16);\r
+ *address = value;\r
+ \r
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */\r
+ address = (hjpeg->Instance->DHTMEM + 58);\r
+ value = *address & 0xFFFF0000U;\r
+ value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFF);\r
+ *address = value;\r
+ \r
+ /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/\r
+ address--;\r
+ index = 8;\r
+ while(index > 0)\r
+ {\r
+ *address = (((uint32_t)HuffTableDC1->HuffVal[index+1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableDC1->HuffVal[index-1] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableDC1->HuffVal[index-2] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ } \r
+ }\r
+ \r
+ if(HuffTableAC1 != NULL)\r
+ {\r
+ /* AC1 Huffman Table : BITS*/\r
+ /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/\r
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */\r
+ address = (hjpeg->Instance->DHTMEM + 58);\r
+ value = *address & 0x0000FFFFU;\r
+ value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFF) << 16);\r
+ *address = value;\r
+ \r
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */\r
+ address = (hjpeg->Instance->DHTMEM + 62);\r
+ value = *address & 0xFFFF0000U;\r
+ value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFF);\r
+ *address = value;\r
+ \r
+ /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/\r
+ address--;\r
+ index = 12;\r
+ while(index > 0)\r
+ {\r
+\r
+ *address = (((uint32_t)HuffTableAC1->Bits[index+1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableAC1->Bits[index] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableAC1->Bits[index-1] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableAC1->Bits[index-2] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ \r
+ }\r
+ /* AC1 Huffman Table : Val*/\r
+ /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */\r
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */\r
+ address = (hjpeg->Instance->DHTMEM + 62); \r
+ value = *address & 0x0000FFFF;\r
+ value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFF) << 16);\r
+ *address = value;\r
+ \r
+ /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */\r
+ address = (hjpeg->Instance->DHTMEM + 102);\r
+ index = 160;\r
+ while(index > 0)\r
+ {\r
+ *address = (((uint32_t)HuffTableAC1->HuffVal[index+1] & 0xFF) << 24)|\r
+ (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFF) << 16)|\r
+ (((uint32_t)HuffTableAC1->HuffVal[index-1] & 0xFF) << 8) |\r
+ ((uint32_t)HuffTableAC1->HuffVal[index-2] & 0xFF);\r
+ address--;\r
+ index -=4; \r
+ } \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Configure the JPEG registers with a given quantization table\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param QTable: pointer to an array of 64 bytes giving the quantization table\r
+ * @param QTableAddress: destination quantization address in the JPEG peripheral\r
+ * it could be QMEM0, QMEM1, QMEM2 or QMEM3 \r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress)\r
+{\r
+ uint32_t i, j, *tableAddress, quantRow, quantVal, ScaleFactor;\r
+ \r
+ if((QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM0))) ||\r
+ (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM1))) ||\r
+ (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM2))) ||\r
+ (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM3)))) \r
+ {\r
+ tableAddress = QTableAddress; \r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if ((hjpeg->Conf.ImageQuality >= 50) && (hjpeg->Conf.ImageQuality <= 100)) \r
+ {\r
+ ScaleFactor = 200 - (hjpeg->Conf.ImageQuality * 2);\r
+ }\r
+ else if (hjpeg->Conf.ImageQuality > 0)\r
+ { \r
+ ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality);\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+\r
+ /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/\r
+ i = 0;\r
+ while( i < JPEG_QUANT_TABLE_SIZE)\r
+ {\r
+ quantRow = 0;\r
+ for(j=0; j<4; j++)\r
+ {\r
+ /* Note that the quantization coefficients must be specified in the table in zigzag order */\r
+ quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i+j]]) * ScaleFactor) + 50) / 100;\r
+ \r
+ if(quantVal == 0)\r
+ {\r
+ quantVal = 1; \r
+ }\r
+ else if (quantVal > 255)\r
+ {\r
+ quantVal = 255;\r
+ }\r
+ \r
+ quantRow |= ((quantVal & 0xFF) << (8 * j)); \r
+ }\r
+\r
+ i += 4; \r
+ *tableAddress = quantRow;\r
+ tableAddress ++; \r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Configure the JPEG registers for YCbCr color space\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) \r
+{\r
+ uint32_t ySamplingH;\r
+ uint32_t ySamplingV;\r
+ uint32_t yblockNb;\r
+ \r
+ /*Set Number of color components to 3*/\r
+ hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_NF;\r
+ hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1;\r
+ \r
+ /* compute MCU block size and Y, Cb ,Cr sampling factors*/ \r
+ if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) \r
+ { \r
+ ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ \r
+ ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/\r
+ \r
+ yblockNb = 0x30; /* 4 blocks of 8x8*/\r
+ }\r
+ else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)\r
+ { \r
+ ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ \r
+ ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/\r
+ \r
+ yblockNb = 0x10; /* 2 blocks of 8x8*/ \r
+ } \r
+ else /*JPEG_444_SUBSAMPLING and default*/\r
+ {\r
+ ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ \r
+ ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/\r
+ \r
+ yblockNb = 0; /* 1 block of 8x8*/\r
+ } \r
+ \r
+ hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);\r
+ hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);\r
+ \r
+ /*Reset CONFR4 register*/\r
+ hjpeg->Instance->CONFR4 = 0;\r
+ /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/\r
+ hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );\r
+ \r
+ /*Reset CONFR5 register*/\r
+ hjpeg->Instance->CONFR5 = 0;\r
+ /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/\r
+ hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD);\r
+ \r
+ /*Reset CONFR6 register*/\r
+ hjpeg->Instance->CONFR6 = 0;\r
+ /*Set Horizental and Vertical sampling factor and number of blocks for component 2*/\r
+ /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */\r
+ /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */\r
+ hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Configure the JPEG registers for GrayScale color space\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg)\r
+{ \r
+ /*Set Number of color components to 1*/\r
+ hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);\r
+ \r
+ /*in GrayScale use 1 single Quantization table (Table 0)*/\r
+ /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/\r
+ \r
+ /*Reset CONFR4 register*/\r
+ hjpeg->Instance->CONFR4 = 0;\r
+ /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/\r
+ hjpeg->Instance->CONFR4 |= JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ;\r
+}\r
+\r
+/**\r
+ * @brief Configure the JPEG registers for CMYK color space\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ uint32_t ySamplingH;\r
+ uint32_t ySamplingV;\r
+ uint32_t yblockNb;\r
+ \r
+ /*Set Number of color components to 4*/\r
+ hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS);\r
+ \r
+ /* compute MCU block size and Y, Cb ,Cr sampling factors*/ \r
+ if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) \r
+ { \r
+ ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ \r
+ ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/\r
+ \r
+ yblockNb = 0x30; /* 4 blocks of 8x8*/\r
+ }\r
+ else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)\r
+ { \r
+ ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ \r
+ ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/\r
+ \r
+ yblockNb = 0x10; /* 2 blocks of 8x8*/ \r
+ }\r
+ else /*JPEG_444_SUBSAMPLING and default*/\r
+ { \r
+ ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ \r
+ ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/\r
+ \r
+ yblockNb = 0; /* 1 block of 8x8*/\r
+ } \r
+ \r
+ /*Reset CONFR4 register*/\r
+ hjpeg->Instance->CONFR4 = 0;\r
+ /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/\r
+ hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );\r
+ \r
+ /*Reset CONFR5 register*/\r
+ hjpeg->Instance->CONFR5 = 0;\r
+ /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/\r
+ hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);\r
+ \r
+ /*Reset CONFR6 register*/\r
+ hjpeg->Instance->CONFR6 = 0;\r
+ /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/\r
+ hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);\r
+ \r
+ /*Reset CONFR7 register*/\r
+ hjpeg->Instance->CONFR7 = 0;\r
+ /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/\r
+ hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);\r
+}\r
+\r
+/**\r
+ * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval None\r
+ */\r
+static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /*Reset pause*/\r
+ hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT));\r
+ \r
+ if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)\r
+ {\r
+ /*Set JPEG Codec to Decoding mode */\r
+ hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE;\r
+ } \r
+ else if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)\r
+ {\r
+ /*Set JPEG Codec to Encoding mode */\r
+ hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE;\r
+ }\r
+ \r
+ /*Stop JPEG processing */\r
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;\r
+ \r
+ /* Disable All Interrupts */\r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ \r
+ /* Disable All DMA requests */\r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);\r
+ \r
+ /* Flush input and output FIFOs*/\r
+ hjpeg->Instance->CR |= JPEG_CR_IFF;\r
+ hjpeg->Instance->CR |= JPEG_CR_OFF;\r
+ \r
+ /* Clear all flags */\r
+ __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r
+ \r
+ /*Start Encoding/Decoding*/\r
+ hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START;\r
+ \r
+ if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r
+ { \r
+ /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/\r
+ __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC |JPEG_IT_HPD);\r
+ }\r
+ else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r
+ {\r
+ /*Enable End Of Conversation, and End Of Header parsing interruptions*/\r
+ __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC |JPEG_IT_HPD);\r
+ \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief JPEG encoding/decoding process in case of Polling or Interrupt\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING\r
+ */\r
+static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ uint32_t tmpContext;\r
+ \r
+ /*End of header processing flag rised*/\r
+ if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))\r
+ {\r
+ /*Call Header parsing complet callback */\r
+ HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);\r
+ /* Reset the ImageQuality */\r
+ hjpeg->Conf.ImageQuality = 0;\r
+ /* Note : the image quality is only available at the end of the decoding operation */\r
+ /* at the current stage the calculated image quality is not correct so reset it */ \r
+ \r
+ /*Call Info Ready callback */ \r
+ HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); \r
+ \r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);\r
+ \r
+ /* Clear header processing done flag */\r
+ __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF); \r
+ }\r
+\r
+ /*Input FIFO status handling*/\r
+ if((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0)\r
+ { \r
+ if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != RESET)\r
+ {\r
+ /*Input FIFO threshold flag rised*/\r
+ /*4 words (16 bytes) can be written in */\r
+ JPEG_ReadInputData(hjpeg,4);\r
+ }\r
+ else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != RESET)\r
+ {\r
+ /*Input FIFO Not Full flag rised*/\r
+ /*32-bit value can be written in */\r
+ JPEG_ReadInputData(hjpeg,1);\r
+ }\r
+ }\r
+ \r
+ \r
+ /*Output FIFO flag handling*/\r
+ if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)\r
+ { \r
+ if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != RESET)\r
+ {\r
+ /*Output FIFO threshold flag rised*/\r
+ /*4 words (16 bytes) can be read out */\r
+ JPEG_StoreOutputData(hjpeg, 4); \r
+ }\r
+ else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != RESET)\r
+ {\r
+ /*Output FIFO Not Empty flag rised*/\r
+ /*32-bit value can be read out */\r
+ JPEG_StoreOutputData(hjpeg, 1); \r
+ }\r
+ }\r
+ \r
+ /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/\r
+ if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF)\r
+ { \r
+ /*Stop Encoding/Decoding*/\r
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;\r
+\r
+ if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r
+ {\r
+ /* Disable All Interrupts */\r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ }\r
+ \r
+ /* Clear all flags */\r
+ __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r
+ \r
+ /*Call End of conversion callback */\r
+ if(hjpeg->JpegOutCount > 0)\r
+ {\r
+ /*Output Buffer is not empty, call DecodedDataReadyCallback*/\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ hjpeg->JpegOutCount = 0;\r
+ }\r
+ \r
+ /*Reset Context Operation*/\r
+ tmpContext = hjpeg->Context;\r
+ /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/\r
+ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_READY;\r
+ \r
+ /*Call End of Encoding/Decoding callback */\r
+ if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)\r
+ {\r
+ HAL_JPEG_DecodeCpltCallback(hjpeg);\r
+ }\r
+ else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)\r
+ {\r
+ HAL_JPEG_EncodeCpltCallback(hjpeg); \r
+ }\r
+ \r
+ return JPEG_PROCESS_DONE; \r
+ } \r
+\r
+ \r
+ return JPEG_PROCESS_ONGOING;\r
+}\r
+\r
+/**\r
+ * @brief Store some output data from the JPEG peripheral to the output buffer.\r
+ * This function is used when the JPEG peripheral has new data to output \r
+ * in case of Polling or Interrupt process\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral\r
+ * @retval None \r
+ */\r
+static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)\r
+{\r
+ uint32_t index, nBwords, nbBytes , dataword, *pOutData;\r
+\r
+ pOutData = (uint32_t *)(((uint32_t *)hjpeg->pJpegOutBuffPtr) + (hjpeg->JpegOutCount/4));\r
+ \r
+ if(hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords*4)))\r
+ {\r
+ for(index = 0; index < nbOutputWords; index++) \r
+ {\r
+ /*Transfer 32 bits from the JPEG output FIFO*/\r
+ *pOutData = hjpeg->Instance->DOR;\r
+ pOutData++;\r
+ hjpeg->JpegOutCount += 4;\r
+ }\r
+ if(hjpeg->OutDataLength == hjpeg->JpegOutCount)\r
+ {\r
+ /*Output Buffer is full, call DecodedDataReadyCallback*/\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ hjpeg->JpegOutCount = 0; \r
+ }\r
+ } \r
+ else if(hjpeg->OutDataLength > hjpeg->JpegOutCount)\r
+ {\r
+ nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount)/4;\r
+ for(index = 0; index < nBwords; index++) \r
+ {\r
+ /*Transfer 32 bits from the JPEG output FIFO*/\r
+ *pOutData = hjpeg->Instance->DOR;\r
+ pOutData++;\r
+ hjpeg->JpegOutCount += 4;\r
+ }\r
+ if(hjpeg->OutDataLength == hjpeg->JpegOutCount)\r
+ {\r
+ /*Output Buffer is full, call DecodedDataReadyCallback*/\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ hjpeg->JpegOutCount = 0; \r
+ }\r
+ else\r
+ { \r
+ nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; \r
+ dataword = hjpeg->Instance->DOR;\r
+ for(index = 0; index < nbBytes; index++)\r
+ {\r
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;\r
+ hjpeg->JpegOutCount++;\r
+ } \r
+ /*Output Buffer is full, call DecodedDataReadyCallback*/\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ hjpeg->JpegOutCount = 0;\r
+ \r
+ nbBytes = 4 - nbBytes;\r
+ for(index = nbBytes; index < 4; index++)\r
+ {\r
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;\r
+ hjpeg->JpegOutCount++;\r
+ }\r
+ } \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read some input Data from the input buffer.\r
+ * This function is used when the JPEG peripheral needs new data \r
+ * in case of Polling or Interrupt process\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @param nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request\r
+ * @retval None \r
+ */\r
+static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)\r
+{\r
+ uint32_t nbBytes = 0, nBwords, index, Dataword; \r
+ \r
+ if((hjpeg->InDataLength == 0) || (nbRequestWords == 0))\r
+ {\r
+ /* No more Input data : nothing to do*/\r
+ HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);\r
+ }\r
+ else if(hjpeg->InDataLength > hjpeg->JpegInCount)\r
+ {\r
+ nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;\r
+ }\r
+ else if(hjpeg->InDataLength == hjpeg->JpegInCount)\r
+ {\r
+ /*Call HAL_JPEG_GetDataCallback to get new data */\r
+ HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);\r
+ if(hjpeg->InDataLength > 4)\r
+ { \r
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);\r
+ }\r
+ hjpeg->JpegInCount = 0;\r
+ nbBytes = hjpeg->InDataLength; \r
+ }\r
+ if((nbBytes > 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0))\r
+ { \r
+ nBwords = nbBytes / 4;\r
+ if(nBwords >= nbRequestWords)\r
+ {\r
+ for(index = 0; index < nbRequestWords; index++)\r
+ { \r
+ hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4)));\r
+ \r
+ hjpeg->JpegInCount += 4;\r
+ }\r
+ }\r
+ else /*nBwords < nbRequestWords*/\r
+ {\r
+ if(nBwords > 0)\r
+ {\r
+ for(index = 0; index < nBwords; index++)\r
+ { \r
+ hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4)));\r
+ \r
+ hjpeg->JpegInCount += 4;\r
+ } \r
+ } \r
+ else\r
+ {\r
+ /* end of file*/\r
+ Dataword = 0;\r
+ for(index=0; index< nbBytes; index++)\r
+ {\r
+ Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8 * index);\r
+ hjpeg->JpegInCount++;\r
+ }\r
+ hjpeg->Instance->DIR = Dataword; \r
+ } \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Start the JPEG DMA process (encoding/decoding) \r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING \r
+ */\r
+static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)\r
+{ \r
+ if((hjpeg->InDataLength < 4) || (hjpeg->OutDataLength < 4))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Reset Ending DMA internal context flag*/\r
+ hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA;\r
+ \r
+ /* Disable DMA In/Out Request*/\r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA);\r
+ \r
+ /* Set the JPEG DMA In transfer complete callback */\r
+ hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback; \r
+ /* Set the DMA In error callback */ \r
+ hjpeg->hdmain->XferErrorCallback = JPEG_DMAErrorCallback;\r
+ \r
+ /* Set the JPEG DMA Out transfer complete callback */\r
+ hjpeg->hdmaout->XferCpltCallback = JPEG_DMAOutCpltCallback;\r
+ /* Set the DMA Out error callback */\r
+ hjpeg->hdmaout->XferErrorCallback = JPEG_DMAErrorCallback; \r
+ /* Set the DMA Out Abort callback */ \r
+ hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback;\r
+ \r
+ /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/\r
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);\r
+ \r
+ /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/\r
+ hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4);\r
+ \r
+ /* Start DMA FIFO In transfer */\r
+ HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2); \r
+\r
+ /* Start DMA FIFO Out transfer */\r
+ HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);\r
+\r
+ /* Enable JPEG In/Out DMA requests*/\r
+ JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA | JPEG_DMA_ODMA); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Continue the current JPEG DMA process (encoding/decoding) \r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING \r
+ */\r
+static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ /*End of header processing flag rises*/\r
+ if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))\r
+ {\r
+ /*Call Header parsing complete callback */\r
+ HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);\r
+ \r
+ /* Reset the ImageQuality */\r
+ hjpeg->Conf.ImageQuality = 0;\r
+ /* Note : the image quality is only available at the end of the decoding operation */\r
+ /* at the current stage the calculated image quality is not correct so reset it */ \r
+ \r
+ /*Call Info Ready callback */ \r
+ HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); \r
+ \r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);\r
+ \r
+ /* Clear header processing done flag */\r
+ __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF); \r
+ }\r
+ \r
+ /*End of Conversion handling*/\r
+ if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != RESET)\r
+ { \r
+ /*Disabkle JPEG In/Out DMA Requests*/\r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA); \r
+ \r
+ hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA;\r
+ \r
+ /*Stop Encoding/Decoding*/\r
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;\r
+ \r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ \r
+ /* Clear all flags */\r
+ __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r
+ \r
+ if(hjpeg->hdmain->State == HAL_DMA_STATE_BUSY)\r
+ {\r
+ /* Stop the DMA In Xfer*/\r
+ HAL_DMA_Abort_IT(hjpeg->hdmain);\r
+ }\r
+ \r
+ if(hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY)\r
+ {\r
+ /* Stop the DMA out Xfer*/\r
+ HAL_DMA_Abort_IT(hjpeg->hdmaout);\r
+ }\r
+ else\r
+ {\r
+ return JPEG_DMA_EndProcess(hjpeg);\r
+ } \r
+ }\r
+ \r
+ return JPEG_PROCESS_ONGOING;\r
+}\r
+\r
+/**\r
+ * @brief Finalize the current JPEG DMA process (encoding/decoding) \r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module\r
+ * @retval JPEG_PROCESS_DONE\r
+ */\r
+static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ uint32_t tmpContext, count = JPEG_FIFO_SIZE, *pDataOut;\r
+ \r
+ hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hjpeg->hdmaout->Instance->NDTR & DMA_SxNDT) << 2);\r
+ \r
+ /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/\r
+ if(hjpeg->JpegOutCount == hjpeg->OutDataLength)\r
+ {\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ hjpeg->JpegOutCount = 0;\r
+ }\r
+ \r
+ pDataOut = (uint32_t *)(hjpeg->pJpegOutBuffPtr + hjpeg->JpegOutCount);\r
+ \r
+ while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0))\r
+ {\r
+ count--;\r
+ \r
+ *pDataOut = hjpeg->Instance->DOR;\r
+ pDataOut++;\r
+ hjpeg->JpegOutCount += 4;\r
+ \r
+ if(hjpeg->JpegOutCount == hjpeg->OutDataLength)\r
+ {\r
+ /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ hjpeg->JpegOutCount = 0; \r
+ }\r
+ }\r
+ \r
+ /*Stop Encoding/Decoding*/\r
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;\r
+ \r
+ if(hjpeg->JpegOutCount > 0)\r
+ {\r
+ /*Output Buffer is not empty, call DecodedDataReadyCallback*/\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ hjpeg->JpegOutCount = 0;\r
+ }\r
+ \r
+ tmpContext = hjpeg->Context;\r
+ /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/\r
+ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hjpeg);\r
+ \r
+ /* Change the JPEG state */\r
+ hjpeg->State = HAL_JPEG_STATE_READY;\r
+ \r
+ /*Call End of Encoding/Decoding callback */\r
+ if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)\r
+ {\r
+ HAL_JPEG_DecodeCpltCallback(hjpeg);\r
+ }\r
+ else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)\r
+ {\r
+ HAL_JPEG_EncodeCpltCallback(hjpeg); \r
+ }\r
+ \r
+ \r
+ return JPEG_PROCESS_DONE; \r
+}\r
+\r
+/**\r
+ * @brief DMA input transfer complete callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure. \r
+ * @retval None\r
+ */\r
+static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) \r
+{ \r
+ JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */\r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ \r
+ if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))\r
+ { \r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_IDMA); \r
+ \r
+ hjpeg->JpegInCount = hjpeg->InDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2);\r
+\r
+ /*Call HAL_JPEG_GetDataCallback to get new data */\r
+ HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);\r
+ \r
+ if(hjpeg->InDataLength >= 4)\r
+ {\r
+ /*JPEG Input DMA transfer data number must be multiple of 32 bits word \r
+ as the destination is a 32 bits (4 bytes) register */\r
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); \r
+ }\r
+ else if(hjpeg->InDataLength > 0)\r
+ {\r
+ /*Transfer last data word (i.e last 4 bytes)*/\r
+ hjpeg->InDataLength = 4;\r
+ }\r
+ \r
+ if(((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) && (hjpeg->InDataLength > 0))\r
+ { \r
+ /* Start DMA FIFO In transfer */\r
+ HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);\r
+ JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA);\r
+ } \r
+ \r
+ /* JPEG Conversion still on going : Enable the JPEG IT */\r
+ __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief DMA output transfer complete callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure. \r
+ * @retval None\r
+ */\r
+static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) \r
+{ \r
+ JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; \r
+ \r
+ /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */\r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ \r
+ if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))\r
+ { \r
+ if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0)\r
+ { \r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA); \r
+ hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2);\r
+ \r
+ /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/\r
+ HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r
+ \r
+ if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)\r
+ { \r
+ /* Start DMA FIFO Out transfer */\r
+ HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);\r
+ JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_ODMA);\r
+ }\r
+ }\r
+ \r
+ /* JPEG Conversion still on going : Enable the JPEG IT */\r
+ __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA Transfer error callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure. \r
+ * @retval None\r
+ */\r
+static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* if DMA error is FIFO error ignore it */\r
+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)\r
+ {\r
+ /*Stop Encoding/Decoding*/\r
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;\r
+ \r
+ /* Disable All Interrupts */\r
+ __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r
+ \r
+ /* Disable All DMA requests */\r
+ JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); \r
+ \r
+ hjpeg->State= HAL_JPEG_STATE_READY;\r
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; \r
+ HAL_JPEG_ErrorCallback(hjpeg);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA output Abort callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure. \r
+ * @retval None\r
+ */\r
+static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) \r
+{\r
+ JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)\r
+ {\r
+ JPEG_DMA_EndProcess(hjpeg);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Calculate the decoded image quality (from 1 to 100)\r
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r
+ * the configuration information for JPEG module \r
+ * @retval JPEG image quality from 1 to 100.\r
+ */\r
+static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)\r
+{\r
+ uint32_t quality = 0;\r
+ uint32_t quantRow, quantVal,scale, i, j; \r
+ uint32_t *tableAddress = (uint32_t *)hjpeg->Instance->QMEM0;\r
+ \r
+ i = 0;\r
+ while( i < JPEG_QUANT_TABLE_SIZE)\r
+ {\r
+ quantRow = *tableAddress;\r
+ for(j=0; j<4; j++)\r
+ {\r
+ quantVal = (quantRow >> (8 * j)) & 0xFF;\r
+ if(quantVal == 1)\r
+ {\r
+ /* if Quantization value = 1 then quality is 100%*/\r
+ quality += 100;\r
+ }\r
+ else\r
+ {\r
+ /* Note that the quantization coefficients must be specified in the table in zigzag order */\r
+ scale = (quantVal*100)/((uint32_t) JPEG_LUM_QuantTable[JPEG_ZIGZAG_ORDER[i+j]]);\r
+ \r
+ if(scale <= 100)\r
+ {\r
+ quality += (200 - scale)/2; \r
+ }\r
+ else\r
+ {\r
+ quality += 5000/scale; \r
+ }\r
+ } \r
+ }\r
+\r
+ i += 4;\r
+ tableAddress ++; \r
+ }\r
+\r
+ return (quality/((uint32_t)64)); \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#endif /* HAL_JPEG_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_lptim.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief LPTIM HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Low Power Timer (LPTIM) peripheral:\r
+ * + Initialization and de-initialization functions.\r
+ * + Start/Stop operation functions in polling mode.\r
+ * + Start/Stop operation functions in interrupt mode.\r
+ * + Reading operation functions.\r
+ * + Peripheral State functions.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The LPTIM HAL driver can be used as follows:\r
+\r
+ (#)Initialize the LPTIM low level resources by implementing the\r
+ HAL_LPTIM_MspInit():\r
+ (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().\r
+ (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):\r
+ (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().\r
+ (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().\r
+ (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().\r
+ \r
+ (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function\r
+ configures mainly:\r
+ (##) The instance: LPTIM1.\r
+ (##) Clock: the counter clock.\r
+ - Source : it can be either the ULPTIM input (IN1) or one of\r
+ the internal clock; (APB, LSE, LSI or MSI).\r
+ - Prescaler: select the clock divider.\r
+ (##) UltraLowPowerClock : To be used only if the ULPTIM is selected\r
+ as counter clock source.\r
+ - Polarity: polarity of the active edge for the counter unit\r
+ if the ULPTIM input is selected.\r
+ - SampleTime: clock sampling time to configure the clock glitch\r
+ filter. \r
+ (##) Trigger: How the counter start.\r
+ - Source: trigger can be software or one of the hardware triggers.\r
+ - ActiveEdge : only for hardware trigger.\r
+ - SampleTime : trigger sampling time to configure the trigger\r
+ glitch filter.\r
+ (##) OutputPolarity : 2 opposite polarities are possibles.\r
+ (##) UpdateMode: specifies whether the update of the autoreload and\r
+ the compare values is done immediately or after the end of current\r
+ period. \r
+ \r
+ (#)Six modes are available:\r
+ \r
+ (##) PWM Mode: To generate a PWM signal with specified period and pulse,\r
+ call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption\r
+ mode.\r
+ \r
+ (##) One Pulse Mode: To generate pulse with specified width in response\r
+ to a stimulus, call HAL_LPTIM_OnePulse_Start() or\r
+ HAL_LPTIM_OnePulse_Start_IT() for interruption mode.\r
+ \r
+ (##) Set once Mode: In this mode, the output changes the level (from\r
+ low level to high level if the output polarity is configured high, else\r
+ the opposite) when a compare match occurs. To start this mode, call \r
+ HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for\r
+ interruption mode.\r
+ \r
+ (##) Encoder Mode: To use the encoder interface call\r
+ HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for \r
+ interruption mode.\r
+ \r
+ (##) Time out Mode: an active edge on one selected trigger input rests\r
+ the counter. The first trigger event will start the timer, any\r
+ successive trigger event will reset the counter and the timer will\r
+ restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or \r
+ HAL_LPTIM_TimeOut_Start_IT() for interruption mode.\r
+ \r
+ (##) Counter Mode: counter can be used to count external events on\r
+ the LPTIM Input1 or it can be used to count internal clock cycles.\r
+ To start this mode, call HAL_LPTIM_Counter_Start() or \r
+ HAL_LPTIM_Counter_Start_IT() for interruption mode. \r
+\r
+ \r
+ (#) User can stop any process by calling the corresponding API:\r
+ HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is\r
+ already started in interruption mode.\r
+ \r
+ (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPTIM LPTIM\r
+ * @brief LPTIM HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Types LPTIM Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Defines LPTIM Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPTIM_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the LPTIM according to the specified parameters in the\r
+ LPTIM_InitTypeDef and creates the associated handle.\r
+ (+) DeInitialize the LPTIM peripheral.\r
+ (+) Initialize the LPTIM MSP.\r
+ (+) DeInitialize LPTIM MSP. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the LPTIM according to the specified parameters in the\r
+ * LPTIM_InitTypeDef and creates the associated handle.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ uint32_t tmpcfgr = 0;\r
+\r
+ /* Check the LPTIM handle allocation */\r
+ if(hlptim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));\r
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); \r
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)\r
+ {\r
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));\r
+ } \r
+ assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));\r
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));\r
+ } \r
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); \r
+ assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));\r
+ assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));\r
+ \r
+ if(hlptim->State == HAL_LPTIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hlptim->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_LPTIM_MspInit(hlptim);\r
+ }\r
+ \r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Get the LPTIMx CFGR value */\r
+ tmpcfgr = hlptim->Instance->CFGR;\r
+ \r
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)\r
+ {\r
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));\r
+ }\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));\r
+ }\r
+ \r
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */\r
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |\r
+ LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));\r
+ \r
+ /* Set initialization parameters */\r
+ tmpcfgr |= (hlptim->Init.Clock.Source |\r
+ hlptim->Init.Clock.Prescaler |\r
+ hlptim->Init.OutputPolarity |\r
+ hlptim->Init.UpdateMode |\r
+ hlptim->Init.CounterSource);\r
+ \r
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)\r
+ {\r
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |\r
+ hlptim->Init.UltraLowPowerClock.SampleTime);\r
+ } \r
+ \r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable External trigger and set the trigger source */\r
+ tmpcfgr |= (hlptim->Init.Trigger.Source |\r
+ hlptim->Init.Trigger.ActiveEdge |\r
+ hlptim->Init.Trigger.SampleTime);\r
+ }\r
+ \r
+ /* Write to LPTIMx CFGR */\r
+ hlptim->Instance->CFGR = tmpcfgr;\r
+\r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the LPTIM peripheral. \r
+ * @param hlptim: LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the LPTIM handle allocation */\r
+ if(hlptim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the LPTIM Peripheral Clock */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* DeInit the low level hardware: CLOCK, NVIC.*/\r
+ HAL_LPTIM_MspDeInit(hlptim);\r
+ \r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hlptim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LPTIM MSP.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes LPTIM MSP.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions \r
+ * @brief Start-Stop operation functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### LPTIM Start Stop operation functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start the PWM mode.\r
+ (+) Stop the PWM mode.\r
+ (+) Start the One pulse mode.\r
+ (+) Stop the One pulse mode.\r
+ (+) Start the Set once mode.\r
+ (+) Stop the Set once mode.\r
+ (+) Start the Encoder mode.\r
+ (+) Stop the Encoder mode.\r
+ (+) Start the Timeout mode.\r
+ (+) Stop the Timeout mode. \r
+ (+) Start the Counter mode.\r
+ (+) Stop the Counter mode.\r
+ \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Starts the LPTIM PWM generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set PWM mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM PWM generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM PWM generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set PWM mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Compare write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then enable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable external trigger interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM PWM generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Compare write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then disable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Disable external trigger interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM One pulse generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set one pulse mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM One pulse generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM One pulse generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set one pulse mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Compare write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then enable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable external trigger interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM One pulse generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Compare write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then disable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Disable external trigger interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ }\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM in Set once mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Set WAVE bit to enable the set once mode */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM Set once mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM Set once mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Set WAVE bit to enable the set once mode */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Compare write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then enable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable external trigger interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM Set once mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Compare write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then disable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Disable external trigger interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Encoder interface.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ uint32_t tmpcfgr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r
+\r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+\r
+ /* Get the LPTIMx CFGR value */\r
+ tmpcfgr = hlptim->Instance->CFGR;\r
+\r
+ /* Clear CKPOL bits */\r
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r
+\r
+ /* Set Input polarity */\r
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;\r
+\r
+ /* Write to LPTIMx CFGR */\r
+ hlptim->Instance->CFGR = tmpcfgr;\r
+\r
+ /* Set ENC bit to enable the encoder interface */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+\r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+\r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Encoder interface.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset ENC bit to disable the encoder interface */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Encoder interface in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ uint32_t tmpcfgr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r
+\r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Configure edge sensitivity for encoder mode */\r
+ /* Get the LPTIMx CFGR value */\r
+ tmpcfgr = hlptim->Instance->CFGR;\r
+\r
+ /* Clear CKPOL bits */\r
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r
+\r
+ /* Set Input polarity */\r
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;\r
+\r
+ /* Write to LPTIMx CFGR */\r
+ hlptim->Instance->CFGR = tmpcfgr;\r
+\r
+ /* Set ENC bit to enable the encoder interface */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r
+\r
+ /* Enable "switch to down direction" interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);\r
+\r
+ /* Enable "switch to up direction" interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); \r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+\r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+\r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Encoder interface in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset ENC bit to disable the encoder interface */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r
+ \r
+ /* Disable "switch to down direction" interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);\r
+ \r
+ /* Disable "switch to up direction" interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); \r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Timeout function. The first trigger event will start the\r
+ * timer, any successive trigger event will reset the counter and\r
+ * the timer restarts.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Timeout : Specifies the TimeOut value to rest the counter.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Timeout));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Set TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the Timeout value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Timeout function.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Timeout function in interrupt mode. The first trigger \r
+ * event will start the timer, any successive trigger event will reset\r
+ * the counter and the timer restarts.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Timeout : Specifies the TimeOut value to rest the counter.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Timeout));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */\r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); \r
+ \r
+ /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */\r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\r
+ \r
+ /* Set TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the Timeout value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Timeout function in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ \r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\r
+ \r
+ /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */\r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); \r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Counter mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r
+ {\r
+ /* Check if clock is prescaled */\r
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r
+ /* Set clock prescaler to 0 */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Counter mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Counter mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+\r
+ /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */\r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); \r
+ \r
+ /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */\r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \r
+ \r
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r
+ {\r
+ /* Check if clock is prescaled */\r
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r
+ /* Set clock prescaler to 0 */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r
+ }\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Counter mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ \r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\r
+ \r
+ /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */\r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); \r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Group3 LPTIM Read operation functions \r
+ * @brief Read operation functions.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### LPTIM Read operation functions #####\r
+ ============================================================================== \r
+[..] This section provides LPTIM Reading functions.\r
+ (+) Read the counter value.\r
+ (+) Read the period (Auto-reload) value.\r
+ (+) Read the pulse (Compare)value.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function returns the current counter value.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval Counter value.\r
+ */\r
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ return (hlptim->Instance->CNT);\r
+}\r
+\r
+/**\r
+ * @brief This function return the current Autoreload (Period) value.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval Autoreload value.\r
+ */\r
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ return (hlptim->Instance->ARR);\r
+}\r
+\r
+/**\r
+ * @brief This function return the current Compare (Pulse) value.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval Compare value.\r
+ */\r
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ return (hlptim->Instance->CMP);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup LPTIM_Group4 LPTIM IRQ handler \r
+ * @brief LPTIM IRQ handler.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### LPTIM IRQ handler #####\r
+ ============================================================================== \r
+[..] This section provides LPTIM IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles LPTIM interrupt request.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval None\r
+ */\r
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Compare match interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)\r
+ {\r
+ /* Clear Compare match flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);\r
+ /* Compare match Callback */\r
+ HAL_LPTIM_CompareMatchCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Autoreload match interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)\r
+ {\r
+ /* Clear Autoreload match flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);\r
+ /* Autoreload match Callback */\r
+ HAL_LPTIM_AutoReloadMatchCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Trigger detected interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)\r
+ {\r
+ /* Clear Trigger detected flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);\r
+ /* Trigger detected callback */\r
+ HAL_LPTIM_TriggerCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Compare write interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)\r
+ {\r
+ /* Clear Compare write flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);\r
+ /* Compare write Callback */\r
+ HAL_LPTIM_CompareWriteCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Autoreload write interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)\r
+ {\r
+ /* Clear Autoreload write flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);\r
+ /* Autoreload write Callback */\r
+ HAL_LPTIM_AutoReloadWriteCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Direction counter changed from Down to Up interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)\r
+ {\r
+ /* Clear Direction counter changed from Down to Up flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);\r
+ /* Direction counter changed from Down to Up Callback */\r
+ HAL_LPTIM_DirectionUpCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Direction counter changed from Up to Down interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)\r
+ {\r
+ /* Clear Direction counter changed from Up to Down flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);\r
+ /* Direction counter changed from Up to Down Callback */\r
+ HAL_LPTIM_DirectionDownCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();\r
+}\r
+\r
+/**\r
+ * @brief Compare match callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_CompareMatchCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Autoreload match callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Trigger detected callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_TriggerCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Compare write callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_CompareWriteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Autoreload write callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Direction counter changed from Down to Up callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_DirectionUpCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Direction counter changed from Up to Down callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hlptim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_DirectionDownCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Group5 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the LPTIM state.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ return hlptim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_ltdc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief LTDC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the LTDC peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Program the required configuration through the following parameters: \r
+ the LTDC timing, the horizontal and vertical polarity, \r
+ the pixel clock polarity, Data Enable polarity and the LTDC background color value \r
+ using HAL_LTDC_Init() function\r
+\r
+ (#) Program the required configuration through the following parameters: \r
+ the pixel format, the blending factors, input alpha value, the window size \r
+ and the image size using HAL_LTDC_ConfigLayer() function for foreground\r
+ or/and background layer. \r
+ \r
+ (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and \r
+ HAL_LTDC_EnableCLUT functions.\r
+ \r
+ (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). \r
+\r
+ (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()\r
+ and HAL_LTDC_EnableColorKeying functions.\r
+\r
+ (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()\r
+ function\r
+\r
+ (#) If needed, reconfigure and change the pixel format value, the alpha value\r
+ value, the window size, the window position and the layer start address \r
+ for foreground or/and background layer using respectively the following \r
+ functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),\r
+ HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.\r
+\r
+ (#) Variant functions with \93_NoReload\94 post fix allows to set the LTDC configuration/settings without immediate reload.\r
+ This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) \r
+ then applying(reload) these settings in one shot by calling the function \93HAL_LTDC_Reload\94\r
+\r
+ After calling the \93_NoReload\94 functions to set different color/format/layer settings, \r
+ the program can call the function \93HAL_LTDC_Reload\94 To apply(Reload) these settings. \r
+ Function \93HAL_LTDC_Reload\94 can be called with the parameter \93ReloadType\94 \r
+ set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.\r
+ Function \93HAL_LTDC_Reload\94 can be called with the parameter \93ReloadType\94 \r
+ set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period, \r
+ this option allows to avoid display flicker by applying the new settings during the vertical blanking period.\r
+ \r
+ \r
+ (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() \r
+\r
+ *** LTDC HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in LTDC HAL driver.\r
+ \r
+ (+) __HAL_LTDC_ENABLE: Enable the LTDC.\r
+ (+) __HAL_LTDC_DISABLE: Disable the LTDC.\r
+ (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.\r
+ (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.\r
+ (+) __HAL_LTDC_RELOAD_CONFIG: Reload Layer Configuration.\r
+ (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.\r
+ (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.\r
+ (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. \r
+ (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.\r
+ (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.\r
+ \r
+ [..] \r
+ (@) You can refer to the LTDC HAL driver header file for more useful macros\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+\r
+/** @defgroup LTDC LTDC\r
+ * @brief LTDC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/ \r
+/* Private function prototypes -----------------------------------------------*/\r
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup LTDC_Exported_Functions LTDC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the LTDC\r
+ (+) De-initialize the LTDC \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the LTDC according to the specified\r
+ * parameters in the LTDC_InitTypeDef and create the associated handle.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the LTDC peripheral state */\r
+ if(hltdc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));\r
+ assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));\r
+ assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));\r
+ assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));\r
+ assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));\r
+ assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));\r
+ assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));\r
+ assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));\r
+ assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));\r
+ assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));\r
+ assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));\r
+ assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));\r
+ assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));\r
+\r
+ if(hltdc->State == HAL_LTDC_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hltdc->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware */\r
+ HAL_LTDC_MspInit(hltdc);\r
+ }\r
+ \r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Configures the HS, VS, DE and PC polarity */\r
+ hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);\r
+ hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \\r
+ hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);\r
+\r
+ /* Sets Synchronization size */\r
+ hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);\r
+ tmp = (hltdc->Init.HorizontalSync << 16);\r
+ hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);\r
+\r
+ /* Sets Accumulated Back porch */\r
+ hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);\r
+ tmp = (hltdc->Init.AccumulatedHBP << 16);\r
+ hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);\r
+\r
+ /* Sets Accumulated Active Width */\r
+ hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);\r
+ tmp = (hltdc->Init.AccumulatedActiveW << 16);\r
+ hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);\r
+\r
+ /* Sets Total Width */\r
+ hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);\r
+ tmp = (hltdc->Init.TotalWidth << 16);\r
+ hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);\r
+\r
+ /* Sets the background color value */\r
+ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);\r
+ tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);\r
+ hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);\r
+ hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);\r
+\r
+ /* Enable the transfer Error interrupt */\r
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);\r
+\r
+ /* Enable the FIFO underrun interrupt */\r
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);\r
+\r
+ /* Enable LTDC by setting LTDCEN bit */\r
+ __HAL_LTDC_ENABLE(hltdc);\r
+\r
+ /* Initialize the error code */\r
+ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; \r
+\r
+ /* Initialize the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the LTDC peripheral registers to their default reset\r
+ * values.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* DeInit the low level hardware */\r
+ HAL_LTDC_MspDeInit(hltdc); \r
+\r
+ /* Initialize the error code */\r
+ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;\r
+\r
+ /* Initialize the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LTDC MSP.\r
+ * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hltdc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the LTDC MSP.\r
+ * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hltdc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides function allowing to:\r
+ (+) Handle LTDC interrupt request\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Handles LTDC interrupt request.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC. \r
+ * @retval HAL status\r
+ */\r
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)\r
+ {\r
+ if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)\r
+ {\r
+ /* Disable the transfer Error interrupt */\r
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);\r
+\r
+ /* Clear the transfer error flag */\r
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);\r
+\r
+ /* Update error code */\r
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;\r
+\r
+ /* Change LTDC state */\r
+ hltdc->State = HAL_LTDC_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ /* Transfer error Callback */\r
+ HAL_LTDC_ErrorCallback(hltdc);\r
+ }\r
+ }\r
+ /* FIFO underrun Interrupt management ***************************************/\r
+ if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)\r
+ {\r
+ if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)\r
+ {\r
+ /* Disable the FIFO underrun interrupt */\r
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);\r
+\r
+ /* Clear the FIFO underrun flag */\r
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);\r
+\r
+ /* Update error code */\r
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;\r
+\r
+ /* Change LTDC state */\r
+ hltdc->State = HAL_LTDC_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+ \r
+ /* Transfer error Callback */\r
+ HAL_LTDC_ErrorCallback(hltdc);\r
+ }\r
+ }\r
+ /* Line Interrupt management ************************************************/\r
+ if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)\r
+ {\r
+ if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)\r
+ {\r
+ /* Disable the Line interrupt */\r
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);\r
+\r
+ /* Clear the Line interrupt flag */ \r
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);\r
+\r
+ /* Change LTDC state */\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ /* Line interrupt Callback */\r
+ HAL_LTDC_LineEvenCallback(hltdc);\r
+ }\r
+ }\r
+ /* Register reload Interrupt management ***************************************/\r
+ if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)\r
+ {\r
+ if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)\r
+ {\r
+ /* Disable the register reload interrupt */\r
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);\r
+ \r
+ /* Clear the register reload flag */\r
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);\r
+ \r
+ /* Change LTDC state */\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+ \r
+ /* Register reload interrupt Callback */\r
+ HAL_LTDC_ReloadEventCallback(hltdc);\r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Error LTDC callback.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hltdc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Line Event callback.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hltdc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_LineEvenCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Reload Event callback.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hltdc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_ReloadEvenCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the LTDC foreground or/and background parameters.\r
+ (+) Set the active layer.\r
+ (+) Configure the color keying.\r
+ (+) Configure the C-LUT.\r
+ (+) Enable / Disable the color keying.\r
+ (+) Enable / Disable the C-LUT.\r
+ (+) Update the layer position.\r
+ (+) Update the layer size.\r
+ (+) Update pixel format on the fly. \r
+ (+) Update transparency on the fly.\r
+ (+) Update address on the fly.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the LTDC Layer according to the specified\r
+ * parameters in the LTDC_InitTypeDef and create the associated handle.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains\r
+ * the configuration information for the Layer.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r
+{ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+ \r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));\r
+ assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));\r
+ assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));\r
+ assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));\r
+ assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));\r
+\r
+ /* Copy new layer configuration into handle structure */\r
+ hltdc->LayerCfg[LayerIdx] = *pLayerCfg; \r
+\r
+ /* Configure the LTDC Layer */ \r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Initialize the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the color keying.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param RGBValue: the color key value\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Configures the default color values */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Load the color lookup table.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param pCLUT: pointer to the color lookup table address.\r
+ * @param CLUTSize: the color lookup table size. \r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t counter = 0;\r
+ uint32_t pcounter = 0;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx)); \r
+\r
+ for(counter = 0; (counter < CLUTSize); counter++)\r
+ {\r
+ if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)\r
+ {\r
+ tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r
+ }\r
+ else\r
+ { \r
+ tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r
+ }\r
+ pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);\r
+ pCLUT = (uint32_t *)pcounter;\r
+\r
+ /* Specifies the C-LUT address and RGB value */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;\r
+ }\r
+ \r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc); \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the color keying.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Enable LTDC color keying by setting COLKEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief Disable the color keying.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color keying by setting COLKEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the color lookup table.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color lookup table by setting CLUTEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the color lookup table.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color lookup table by setting CLUTEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables Dither.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Enable Dither by setting DTEN bit */\r
+ LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables Dither.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Disable Dither by setting DTEN bit */\r
+ LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the LTDC window size.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param XSize: LTDC Pixel per line\r
+ * @param YSize: LTDC Line number\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) \r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY; \r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Check the parameters (Layers parameters)*/\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+ assert_param(IS_LTDC_CFBLL(XSize));\r
+ assert_param(IS_LTDC_CFBLNBR(YSize));\r
+\r
+ /* update horizontal start/stop */\r
+ pLayerCfg->WindowX0 = 0;\r
+ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;\r
+\r
+ /* update vertical start/stop */ \r
+ pLayerCfg->WindowY0 = 0;\r
+ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;\r
+\r
+ /* Reconfigures the color frame buffer pitch in byte */\r
+ pLayerCfg->ImageWidth = XSize;\r
+\r
+ /* Reconfigures the frame buffer line number */\r
+ pLayerCfg->ImageHeight = YSize;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the LTDC window position.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param X0: LTDC window X offset\r
+ * @param Y0: LTDC window Y offset\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+\r
+ /* update horizontal start/stop */\r
+ pLayerCfg->WindowX0 = X0;\r
+ pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;\r
+\r
+ /* update vertical start/stop */\r
+ pLayerCfg->WindowY0 = Y0;\r
+ pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reconfigure the pixel format.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Pixelformat: new pixel format value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx]; \r
+\r
+ /* Reconfigure the pixel format */\r
+ pLayerCfg->PixelFormat = Pixelformat;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); \r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reconfigure the layer alpha value.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Alpha: new alpha value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_ALPHA(Alpha));\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Reconfigure the Alpha value */\r
+ pLayerCfg->Alpha = Alpha;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Reconfigure the frame buffer Address.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Address: new address value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Reconfigure the Address */\r
+ pLayerCfg->FBStartAdress = Address;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is\r
+ * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we \r
+ * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels \r
+ * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().\r
+ * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch\r
+ * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.\r
+ * @param LayerIdx: LTDC layer index concerned by the modification of line pitch.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t pitchUpdate = 0;\r
+ uint32_t pixelFormat = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+ \r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ \r
+ /* get LayerIdx used pixel format */\r
+ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;\r
+ \r
+ if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r
+ {\r
+ tmp = 4;\r
+ }\r
+ else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r
+ {\r
+ tmp = 3;\r
+ }\r
+ else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\r
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \\r
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\r
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))\r
+ {\r
+ tmp = 2;\r
+ }\r
+ else\r
+ {\r
+ tmp = 1;\r
+ }\r
+ \r
+ pitchUpdate = ((LinePitchInPixels * tmp) << 16);\r
+ \r
+ /* Clear previously set standard pitch */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;\r
+ \r
+ /* Sets the Reload type as immediate update of LTDC pitch configured above */\r
+ LTDC->SRCR |= LTDC_SRCR_IMR;\r
+ \r
+ /* Set new line pitch value */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;\r
+ \r
+ /* Sets the Reload type as immediate update of LTDC pitch configured above */\r
+ LTDC->SRCR |= LTDC_SRCR_IMR;\r
+ \r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Define the position of the line interrupt.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Line: Line Interrupt Position.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LIPOS(Line));\r
+\r
+ /* Enable the Line interrupt */\r
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);\r
+\r
+ /* Sets the Line Interrupt position */\r
+ LTDC->LIPCR = (uint32_t)Line;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief LTDC configuration reload.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param ReloadType: This parameter can be one of the following values :\r
+ * LTDC_RELOAD_IMMEDIATE : Immediate Reload\r
+ * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)\r
+{\r
+ assert_param(IS_LTDC_RELAOD(ReloadType));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY; \r
+ \r
+ /* Enable the Reload interrupt */ \r
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);\r
+ \r
+ /* Apply Reload type */\r
+ hltdc->Instance->SRCR = ReloadType; \r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the LTDC Layer according to the specified without reloading\r
+ * parameters in the LTDC_InitTypeDef and create the associated handle.\r
+ * Variant of the function HAL_LTDC_ConfigLayer without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains\r
+ * the configuration information for the Layer.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r
+{ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+ \r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));\r
+ assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));\r
+ assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));\r
+ assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));\r
+ assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));\r
+\r
+ /* Copy new layer configuration into handle structure */\r
+ hltdc->LayerCfg[LayerIdx] = *pLayerCfg; \r
+\r
+ /* Configure the LTDC Layer */ \r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Initialize the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the LTDC window size without reloading.\r
+ * Variant of the function HAL_LTDC_SetWindowSize without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param XSize: LTDC Pixel per line\r
+ * @param YSize: LTDC Line number\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) \r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY; \r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Check the parameters (Layers parameters)*/\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+ assert_param(IS_LTDC_CFBLL(XSize));\r
+ assert_param(IS_LTDC_CFBLNBR(YSize));\r
+\r
+ /* update horizontal start/stop */\r
+ pLayerCfg->WindowX0 = 0;\r
+ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;\r
+\r
+ /* update vertical start/stop */ \r
+ pLayerCfg->WindowY0 = 0;\r
+ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;\r
+\r
+ /* Reconfigures the color frame buffer pitch in byte */\r
+ pLayerCfg->ImageWidth = XSize;\r
+\r
+ /* Reconfigures the frame buffer line number */\r
+ pLayerCfg->ImageHeight = YSize;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the LTDC window position without reloading.\r
+ * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param X0: LTDC window X offset\r
+ * @param Y0: LTDC window Y offset\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+\r
+ /* update horizontal start/stop */\r
+ pLayerCfg->WindowX0 = X0;\r
+ pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;\r
+\r
+ /* update vertical start/stop */\r
+ pLayerCfg->WindowY0 = Y0;\r
+ pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reconfigure the pixel format without reloading.\r
+ * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDfef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Pixelformat: new pixel format value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx]; \r
+\r
+ /* Reconfigure the pixel format */\r
+ pLayerCfg->PixelFormat = Pixelformat;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); \r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reconfigure the layer alpha value without reloading.\r
+ * Variant of the function HAL_LTDC_SetAlpha without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Alpha: new alpha value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_ALPHA(Alpha));\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Reconfigure the Alpha value */\r
+ pLayerCfg->Alpha = Alpha;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reconfigure the frame buffer Address without reloading.\r
+ * Variant of the function HAL_LTDC_SetAddress without immediate reload \r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Address: new address value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Reconfigure the Address */\r
+ pLayerCfg->FBStartAdress = Address;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is\r
+ * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we \r
+ * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels \r
+ * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().\r
+ * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch\r
+ * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).\r
+ * Variant of the function HAL_LTDC_SetPitch without immediate reload \r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.\r
+ * @param LayerIdx: LTDC layer index concerned by the modification of line pitch.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t pitchUpdate = 0;\r
+ uint32_t pixelFormat = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+ \r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ \r
+ /* get LayerIdx used pixel format */\r
+ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;\r
+ \r
+ if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r
+ {\r
+ tmp = 4;\r
+ }\r
+ else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r
+ {\r
+ tmp = 3;\r
+ }\r
+ else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\r
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \\r
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\r
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))\r
+ {\r
+ tmp = 2;\r
+ }\r
+ else\r
+ {\r
+ tmp = 1;\r
+ }\r
+ \r
+ pitchUpdate = ((LinePitchInPixels * tmp) << 16);\r
+ \r
+ /* Clear previously set standard pitch */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;\r
+ \r
+ /* Set new line pitch value */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;\r
+ \r
+ /* Do not Sets the Reload */\r
+ \r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the color keying without reloading.\r
+ * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param RGBValue: the color key value\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Configures the default color values */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the color keying without reloading.\r
+ * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Enable LTDC color keying by setting COLKEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disable the color keying without reloading.\r
+ * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color keying by setting COLKEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the color lookup table without reloading.\r
+ * Variant of the function HAL_LTDC_EnableCLUT without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color lookup table by setting CLUTEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the color lookup table without reloading.\r
+ * Variant of the function HAL_LTDC_DisableCLUT without immediate reload\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color lookup table by setting CLUTEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;\r
+\r
+ /* Do not Sets the Reload */\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions\r
+ * @brief Peripheral State and Errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the LTDC state.\r
+ (+) Get error code. \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Return the LTDC state\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL state\r
+ */\r
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ return hltdc->State;\r
+}\r
+\r
+/**\r
+* @brief Return the LTDC error code\r
+* @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+* @retval LTDC Error Code\r
+*/\r
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ return hltdc->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configures the LTDC peripheral \r
+ * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param pLayerCfg: Pointer LTDC Layer Configuration structure\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values: 0 or 1\r
+ * @retval None\r
+ */\r
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t tmp1 = 0;\r
+ uint32_t tmp2 = 0;\r
+\r
+ /* Configures the horizontal start and stop position */\r
+ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);\r
+\r
+ /* Configures the vertical start and stop position */\r
+ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp); \r
+\r
+ /* Specifies the pixel format */\r
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);\r
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);\r
+\r
+ /* Configures the default color values */\r
+ tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);\r
+ tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);\r
+ tmp2 = (pLayerCfg->Alpha0 << 24); \r
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);\r
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); \r
+\r
+ /* Specifies the constant alpha value */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);\r
+\r
+ /* Specifies the blending factors */\r
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);\r
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);\r
+\r
+ /* Configures the color frame buffer start address */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);\r
+\r
+ if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r
+ {\r
+ tmp = 4;\r
+ }\r
+ else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r
+ {\r
+ tmp = 3;\r
+ }\r
+ else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\r
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \\r
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\r
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))\r
+ {\r
+ tmp = 2;\r
+ }\r
+ else\r
+ {\r
+ tmp = 1;\r
+ }\r
+\r
+ /* Configures the color frame buffer pitch in byte */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3));\r
+\r
+ /* Configures the frame buffer line number */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);\r
+\r
+ /* Enable LTDC_Layer by setting LEN bit */ \r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_ltdc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief LTDC Extension HAL module driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @defgroup LTDCEx LTDCEx\r
+ * @brief LTDC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the LTDC\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+/**\r
+ * @brief Retrieve common parameters from DSI Video mode configuration structure\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains\r
+ * the DSI video mode configuration parameters\r
+ * @note The implementation of this function is taking into account the LTDC\r
+ * polarities inversion as described in the current LTDC specification\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)\r
+{\r
+ /* Retrieve signal polarities from DSI */\r
+ \r
+ /* The following polarities are inverted:\r
+ LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH\r
+ LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH\r
+ LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/\r
+ \r
+ /* Note 1 : Code in line w/ Current LTDC specification */\r
+ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;\r
+ hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;\r
+ hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;\r
+\r
+ /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */\r
+ /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;\r
+ hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;\r
+ hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */\r
+ \r
+ /* Retrieve vertical timing parameters from DSI */\r
+ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1;\r
+ hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1;\r
+ hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1;\r
+ hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Retrieve common parameters from DSI Adapted command mode configuration structure\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains\r
+ * the DSI command mode configuration parameters\r
+ * @note The implementation of this function is taking into account the LTDC\r
+ * polarities inversion as described in the current LTDC specification\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)\r
+{\r
+ /* Retrieve signal polarities from DSI */\r
+ \r
+ /* The following polarities are inverted:\r
+ LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH\r
+ LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH\r
+ LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/\r
+ \r
+ /* Note 1 : Code in line w/ Current LTDC specification */\r
+ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;\r
+ hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;\r
+ hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;\r
+ \r
+ /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */\r
+ /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;\r
+ hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;\r
+ hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */\r
+ \r
+ return HAL_OK;\r
+}\r
+#endif /*STM32F769xx | STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_LTCD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_mdios.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief MDIOS HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the MDIOS Peripheral.\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ *\r
+ * \r
+ @verbatim \r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The MDIOS HAL driver can be used as follow:\r
+\r
+ (#) Declare a MDIOS_HandleTypeDef handle structure.\r
+\r
+ (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:\r
+ (##) Enable the MDIOS interface clock.\r
+ (##) MDIOS pins configuration:\r
+ (+++) Enable clocks for the MDIOS GPIOs.\r
+ (+++) Configure the MDIOS pins as alternate function.\r
+ (##) NVIC configuration if you need to use interrupt process:\r
+ (+++) Configure the MDIOS interrupt priority.\r
+ (+++) Enable the NVIC MDIOS IRQ handle.\r
+\r
+ (#) Program the Port Address and the Preamble Check in the Init structure.\r
+\r
+ (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.\r
+\r
+ (#) Perform direct slave read/write operations using the following APIs:\r
+ (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()\r
+ (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()\r
+\r
+ (#) Get the Master read/write operations flags using the following APIs:\r
+ (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()\r
+ (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()\r
+\r
+ (#) Clear the read/write flags using the following APIs:\r
+ (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()\r
+ (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()\r
+\r
+ (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called\r
+ the MDIOS will generate an interrupt in the following cases: \r
+ (##) a DINn register written by the Master\r
+ (##) a DOUTn register read by the Master\r
+ (##) an error occur\r
+\r
+ (@) A callback is executed for each genereted interrupt, so the driver provide the following \r
+ HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()\r
+ (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt\r
+ and execute the previous callbacks\r
+ \r
+ (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.\r
+ (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources \r
+ (GPIO, Clocks, NVIC configuration ...)\r
+\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MDIOS MDIOS\r
+ * @brief HAL MDIOS module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_MDIOS_MODULE_ENABLED\r
+ \r
+#if defined (MDIOS)\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)\r
+#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)\r
+#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))\r
+\r
+#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)\r
+#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)\r
+\r
+/* Private macro -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the MDIOS\r
+ (+) The following parameters can be configured: \r
+ (++) Port Address\r
+ (++) Preamble Check\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the MDIOS according to the specified parameters in \r
+ * the MDIOS_InitTypeDef and creates the associated handle .\r
+ * @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains\r
+ * the configuration information for MDIOS module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ uint32_t tmpcr = 0;\r
+\r
+ /* Check the MDIOS handle allocation */\r
+ if(hmdios == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));\r
+ assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));\r
+ assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hmdios);\r
+ \r
+ if(hmdios->State == HAL_MDIOS_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_MDIOS_MspInit(hmdios);\r
+ }\r
+ \r
+ /* Change the MDIOS state */\r
+ hmdios->State = HAL_MDIOS_STATE_BUSY;\r
+ \r
+ /* Get the MDIOS CR value */\r
+ tmpcr = hmdios->Instance->CR;\r
+ \r
+ /* Clear PORT_ADDRESS, DPC and EN bits */\r
+ tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));\r
+ \r
+ /* Set MDIOS control parametrs and enable the peripheral */\r
+ tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\\r
+ (hmdios->Init.PreambleCheck) | \\r
+ (MDIOS_CR_EN));\r
+ \r
+ /* Write the MDIOS CR */\r
+ hmdios->Instance->CR = tmpcr;\r
+ \r
+ /* Change the MDIOS state */\r
+ hmdios->State = HAL_MDIOS_STATE_READY;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hmdios);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the MDIOS peripheral.\r
+ * @param hmdios: MDIOS handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Check the MDIOS handle allocation */\r
+ if(hmdios == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));\r
+ \r
+ /* Change the MDIOS state */\r
+ hmdios->State = HAL_MDIOS_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_MDIOS_DISABLE(hmdios);\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_MDIOS_MspDeInit(hmdios);\r
+ \r
+ /* Change the MDIOS state */\r
+ hmdios->State = HAL_MDIOS_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hmdios);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief MDIOS MSP Init\r
+ * @param hmdios: mdios handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hmdios);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MDIOS_MspInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief MDIOS MSP DeInit\r
+ * @param hmdios: mdios handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hmdios);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MDIOS_MspDeInit can be implemented in the user file\r
+ */ \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions \r
+ * @brief MDIOS Read/Write functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the MDIOS \r
+ read and write operations.\r
+\r
+ (#) APIs that allow to the MDIOS to read/write from/to the \r
+ values of one of the DINn/DOUTn registers:\r
+ (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()\r
+ (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()\r
+\r
+ (#) APIs that provide if there are some Slave registres have been \r
+ read or written by the Master:\r
+ (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()\r
+ (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()\r
+\r
+ (#) APIs that Clear the read/write flags:\r
+ (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()\r
+ (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()\r
+\r
+ (#) A set of Callbacks are provided:\r
+ (+) HAL_MDIOS_WriteCpltCallback()\r
+ (+) HAL_MDIOS_ReadCpltCallback()\r
+ (+) HAL_MDIOS_ErrorCallback() \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes to an MDIOS output register\r
+ * @param hmdios: mdios handle\r
+ * @param RegNum: MDIOS input register number \r
+ * @param Data: Data to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)\r
+{\r
+ uint32_t tmpreg;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_MDIOS_REGISTER(RegNum));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hmdios);\r
+ \r
+ /* Get the addr of output register to be written by the MDIOS */\r
+ tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum);\r
+ \r
+ /* Write to DOUTn register */\r
+ *((uint32_t *)tmpreg) = Data; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hmdios);\r
+ \r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief Reads an MDIOS input register\r
+ * @param hmdios: mdios handle\r
+ * @param RegNum: MDIOS input register number\r
+ * @param pData: pointer to Data\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)\r
+{\r
+ uint32_t tmpreg;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_MDIOS_REGISTER(RegNum));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hmdios);\r
+ \r
+ /* Get the addr of input register to be read by the MDIOS */\r
+ tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum);\r
+\r
+ /* Read DINn register */\r
+ *pData = (uint16_t)(*((uint32_t *)tmpreg));\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hmdios);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets Written registers by MDIO master\r
+ * @param hmdios: mdios handle\r
+ * @retval bit map of written registers addresses\r
+ */\r
+uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)\r
+{ \r
+ return hmdios->Instance->WRFR; \r
+}\r
+\r
+/**\r
+ * @brief Gets Read registers by MDIO master\r
+ * @param hmdios: mdios handle\r
+ * @retval bit map of read registers addresses\r
+ */\r
+uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)\r
+{ \r
+ return hmdios->Instance->RDFR; \r
+}\r
+\r
+/**\r
+ * @brief Clears Write registers flag\r
+ * @param hmdios: mdios handle\r
+ * @param RegNum: registers addresses to be cleared\r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_MDIOS_REGISTER(RegNum));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hmdios);\r
+ \r
+ /* Clear write registers flags */\r
+ hmdios->Instance->CWRFR |= (RegNum);\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hmdios);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Clears Read register flag\r
+ * @param hmdios: mdios handle\r
+ * @param RegNum: registers addresses to be cleared\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_MDIOS_REGISTER(RegNum));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hmdios);\r
+ \r
+ /* Clear read registers flags */\r
+ hmdios->Instance->CRDFR |= (RegNum); \r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hmdios);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Enables Events for MDIOS peripheral \r
+ * @param hmdios: mdios handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hmdios);\r
+ \r
+ /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */\r
+ __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hmdios);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief This function handles MDIOS interrupt request.\r
+ * @param hmdios: MDIOS handle\r
+ * @retval None\r
+ */\r
+void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Write Register Interrupt enabled ? */\r
+ if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET)\r
+ {\r
+ /* Write register flag */\r
+ if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET)\r
+ {\r
+ /* Write callback function */\r
+ HAL_MDIOS_WriteCpltCallback(hmdios);\r
+ \r
+ /* Clear write register flag */\r
+ HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);\r
+ }\r
+ }\r
+ \r
+ /* Read Register Interrupt enabled ? */\r
+ if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET)\r
+ {\r
+ /* Read register flag */\r
+ if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET)\r
+ {\r
+ /* Read callback function */\r
+ HAL_MDIOS_ReadCpltCallback(hmdios);\r
+ \r
+ /* Clear read register flag */\r
+ HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);\r
+ }\r
+ }\r
+ \r
+ /* Error Interrupt enabled ? */\r
+ if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET)\r
+ {\r
+ /* All Errors Flag */\r
+ if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET)\r
+ {\r
+ /* Error Callback */\r
+ HAL_MDIOS_ErrorCallback(hmdios);\r
+ \r
+ /* Clear errors flag */\r
+ __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);\r
+ }\r
+ }\r
+ \r
+ /* check MDIOS WAKEUP exti flag */\r
+ if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* MDIOS WAKEUP interrupt user callback */\r
+ HAL_MDIOS_WakeUpCallback(hmdios);\r
+ \r
+ /* Clear MDIOS WAKEUP Exti pending bit */\r
+ __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Write Complete Callback\r
+ * @param hmdios: mdios handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hmdios);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MDIOS_WriteCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Read Complete Callback\r
+ * @param hmdios: mdios handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hmdios);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MDIOS_ReadCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Error Callback\r
+ * @param hmdios: mdios handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hmdios);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MDIOS_ErrorCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief MDIOS WAKEUP interrupt callback\r
+ * @param hmdios: mdios handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hmdios);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_MDIOS_WakeUpCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions \r
+ * @brief MDIOS control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the MDIOS.\r
+ (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. \r
+ (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Gets MDIOS error flags \r
+ * @param hmdios: mdios handle\r
+ * @retval bit map of occured errors \r
+ */\r
+uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* return errors flags on status register */\r
+ return hmdios->Instance->SR;\r
+}\r
+\r
+/**\r
+ * @brief Return the MDIOS HAL state\r
+ * @param hmdios: mdios handle\r
+ * @retval MDIOS state\r
+ */\r
+HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)\r
+{\r
+ /* Return MDIOS state */\r
+ return hmdios->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+#endif /* MDIOS */\r
+#endif /* HAL_MDIOS_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_nand.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief NAND HAL module driver.\r
+ * This file provides a generic firmware to drive NAND memories mounted \r
+ * as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control NAND flash memories. It uses the FMC/FSMC layer functions to interface \r
+ with NAND devices. This driver is used as follows:\r
+ \r
+ (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() \r
+ with control and timing parameters for both common and attribute spaces.\r
+ \r
+ (+) Read NAND flash memory maker and device IDs using the function\r
+ HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef \r
+ structure declared by the function caller. \r
+ \r
+ (+) Access NAND flash memory by read/write operations using the functions\r
+ HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()\r
+ to read/write page(s)/spare area(s). These functions use specific device \r
+ information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef \r
+ structure. The read/write address information is contained by the Nand_Address_Typedef\r
+ structure passed as parameter.\r
+ \r
+ (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().\r
+ \r
+ (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().\r
+ The erase block address information is contained in the Nand_Address_Typedef \r
+ structure passed as parameter.\r
+ \r
+ (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().\r
+ \r
+ (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/\r
+ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction\r
+ feature or the function HAL_NAND_GetECC() to get the ECC correction code. \r
+ \r
+ (+) You can monitor the NAND device HAL state by calling the function\r
+ HAL_NAND_GetState() \r
+\r
+ [..]\r
+ (@) This driver is a set of generic APIs which handle standard NAND flash operations.\r
+ If a NAND flash device contains different operations and/or implementations, \r
+ it should be implemented separately.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+\r
+/** @defgroup NAND NAND \r
+ * @brief NAND HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private Constants ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup NAND_Exported_Functions NAND Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NAND Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize\r
+ the NAND memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Perform NAND memory Initialization sequence\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param ComSpace_Timing: pointer to Common space timing structure\r
+ * @param AttSpace_Timing: pointer to Attribute space timing structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)\r
+{\r
+ /* Check the NAND handle state */\r
+ if(hnand == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hnand->State == HAL_NAND_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hnand->Lock = HAL_UNLOCKED;\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_NAND_MspInit(hnand);\r
+ } \r
+\r
+ /* Initialize NAND control Interface */\r
+ FMC_NAND_Init(hnand->Instance, &(hnand->Init));\r
+ \r
+ /* Initialize NAND common space timing Interface */ \r
+ FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);\r
+ \r
+ /* Initialize NAND attribute space timing Interface */ \r
+ FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);\r
+ \r
+ /* Enable the NAND device */\r
+ __FMC_NAND_ENABLE(hnand->Instance);\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Perform NAND memory De-Initialization sequence\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) \r
+{\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_NAND_MspDeInit(hnand);\r
+\r
+ /* Configure the NAND registers with their reset values */\r
+ FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);\r
+\r
+ /* Reset the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hnand);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief NAND MSP Init\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hnand);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NAND_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief NAND MSP DeInit\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hnand);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NAND_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+\r
+/**\r
+ * @brief This function handles NAND device interrupt request.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+*/\r
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* Check NAND interrupt Rising edge flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt Rising edge pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);\r
+ }\r
+ \r
+ /* Check NAND interrupt Level flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt Level pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);\r
+ }\r
+\r
+ /* Check NAND interrupt Falling edge flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt Falling edge pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);\r
+ }\r
+ \r
+ /* Check NAND interrupt FIFO empty flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt FIFO empty pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);\r
+ } \r
+\r
+}\r
+\r
+/**\r
+ * @brief NAND interrupt feature callback\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hnand);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NAND_ITCallback could be implemented in the user file\r
+ */\r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NAND Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the NAND \r
+ memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Read the NAND memory electronic signature\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pNAND_ID: NAND ID structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)\r
+{\r
+ __IO uint32_t data = 0;\r
+ __IO uint32_t data1 = 0;\r
+ uint32_t deviceAddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* Send Read ID command sequence */ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+\r
+ /* Read the electronic signature from NAND flash */\r
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)\r
+ {\r
+ data = *(__IO uint32_t *)deviceAddress;\r
+\r
+ /* Return the data read */\r
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);\r
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);\r
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);\r
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);\r
+ }\r
+ else\r
+ {\r
+ data = *(__IO uint32_t *)deviceAddress;\r
+ data1 = *((__IO uint32_t *)deviceAddress + 4);\r
+ \r
+ /* Return the data read */\r
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);\r
+ pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);\r
+ pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);\r
+ pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);\r
+ }\r
+\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief NAND memory reset\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)\r
+{\r
+ uint32_t deviceAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand);\r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Identify the device address */ \r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* Send NAND reset command */ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;\r
+ \r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+ \r
+}\r
+ \r
+/**\r
+ * @brief Read Page(s) from NAND memory block (8-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to destination read buffer\r
+ * @param NumPageToRead : number of pages to read from block \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)\r
+{\r
+ __IO uint32_t index = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+\r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r
+ \r
+ /* Page(s) read loop */ \r
+ while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r
+ { \r
+ /* update the buffer size */\r
+ size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);\r
+ \r
+ /* Send read page command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; \r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;\r
+ __DSB();\r
+ \r
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)\r
+ {\r
+ /* Get Data into Buffer */ \r
+ for(; index < size; index++)\r
+ {\r
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Data into Buffer */ \r
+ for(; index < size; index++)\r
+ {\r
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;\r
+ }\r
+ }\r
+ \r
+ /* Increment read pages number */\r
+ numPagesRead++;\r
+ \r
+ /* Decrement pages to read */\r
+ NumPageToRead--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r
+ }\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Read Page(s) from NAND memory block (16-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to destination read buffer\r
+ * @param NumPageToRead : number of pages to read from block \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)\r
+{ \r
+ __IO uint32_t index = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+\r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r
+ \r
+ /* Page(s) read loop */ \r
+ while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r
+ { \r
+ /* update the buffer size */\r
+ size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);\r
+ \r
+ /* Send read page command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; \r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Get Data into Buffer */ \r
+ for(; index < size; index++)\r
+ {\r
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;\r
+ }\r
+ \r
+ /* Increment read pages number */\r
+ numPagesRead++;\r
+ \r
+ /* Decrement pages to read */\r
+ NumPageToRead--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r
+ }\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Write Page(s) to NAND memory block (8-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to source buffer to write \r
+ * @param NumPageToWrite : number of pages to write to block \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)\r
+{\r
+ __IO uint32_t index = 0;\r
+ uint32_t tickstart = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+\r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r
+ \r
+ /* Page(s) write loop */\r
+ while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r
+ { \r
+ /* update the buffer size */\r
+ size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);\r
+ \r
+ /* Send write page command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r
+ __DSB();\r
+\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)\r
+ {\r
+ /* Write data to memory */\r
+ for(; index < size; index++)\r
+ {\r
+ *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;\r
+ __DSB();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Write data to memory */\r
+ for(; index < size; index++)\r
+ {\r
+ *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;\r
+ __DSB();\r
+ }\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Read status until NAND is ready */\r
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT; \r
+ } \r
+ } \r
+ \r
+ /* Increment written pages number */\r
+ numPagesWritten++;\r
+ \r
+ /* Decrement pages to write */\r
+ NumPageToWrite--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r
+ }\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Write Page(s) to NAND memory block (16-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to source buffer to write \r
+ * @param NumPageToWrite : number of pages to write to block \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)\r
+{\r
+ __IO uint32_t index = 0;\r
+ uint32_t tickstart = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+\r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r
+ \r
+ /* Page(s) write loop */\r
+ while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r
+ {\r
+ /* update the buffer size */\r
+ size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);\r
+ \r
+ /* Send write page command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r
+ __DSB();\r
+\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; index < size; index++)\r
+ {\r
+ *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;\r
+ __DSB();\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Read status until NAND is ready */\r
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT; \r
+ } \r
+ } \r
+ \r
+ /* Increment written pages number */\r
+ numPagesWritten++;\r
+ \r
+ /* Decrement pages to write */\r
+ NumPageToWrite--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r
+ }\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read Spare area(s) from NAND memory (8-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer: pointer to source buffer to write \r
+ * @param NumSpareAreaToRead: Number of spare area to read \r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)\r
+{\r
+ __IO uint32_t index = 0; \r
+ uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand); \r
+ \r
+ /* Spare area(s) read loop */ \r
+ while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r
+ {\r
+ /* update the buffer size */\r
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); \r
+\r
+ /* Send read spare area command sequence */ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ } \r
+\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Get Data into Buffer */\r
+ for(; index < size; index++)\r
+ {\r
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;\r
+ }\r
+ \r
+ /* Increment read spare areas number */\r
+ numSpareAreaRead++;\r
+ \r
+ /* Decrement spare areas to read */\r
+ NumSpareAreaToRead--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));\r
+ }\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Read Spare area(s) from NAND memory (16-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer: pointer to source buffer to write \r
+ * @param NumSpareAreaToRead: Number of spare area to read \r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)\r
+{\r
+ __IO uint32_t index = 0; \r
+ uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand); \r
+ \r
+ /* Spare area(s) read loop */ \r
+ while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r
+ {\r
+ /* update the buffer size */\r
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); \r
+\r
+ /* Send read spare area command sequence */ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ } \r
+\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Get Data into Buffer */\r
+ for(; index < size; index++)\r
+ {\r
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;\r
+ }\r
+ \r
+ /* Increment read spare areas number */\r
+ numSpareAreaRead++;\r
+ \r
+ /* Decrement spare areas to read */\r
+ NumSpareAreaToRead--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));\r
+ }\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Write Spare area(s) to NAND memory (8-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to source buffer to write \r
+ * @param NumSpareAreaTowrite : number of spare areas to write to block\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)\r
+{\r
+ __IO uint32_t index = 0;\r
+ uint32_t tickstart = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the FMC_NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand); \r
+ \r
+ /* Spare area(s) write loop */\r
+ while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r
+ {\r
+ /* update the buffer size */\r
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);\r
+\r
+ /* Send write Spare area command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); \r
+ __DSB();\r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; index < size; index++)\r
+ {\r
+ *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;\r
+ __DSB();\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Read status until NAND is ready */\r
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT; \r
+ }\r
+ }\r
+\r
+ /* Increment written spare areas number */\r
+ numSpareAreaWritten++;\r
+ \r
+ /* Decrement spare areas to write */\r
+ NumSpareAreaTowrite--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));\r
+ }\r
+\r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Write Spare area(s) to NAND memory (16-bits addressing)\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to source buffer to write \r
+ * @param NumSpareAreaTowrite : number of spare areas to write to block\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)\r
+{\r
+ __IO uint32_t index = 0;\r
+ uint32_t tickstart = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the FMC_NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand); \r
+ \r
+ /* Spare area(s) write loop */\r
+ while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r
+ {\r
+ /* update the buffer size */\r
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);\r
+\r
+ /* Send write Spare area command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); \r
+ __DSB();\r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; index < size; index++)\r
+ {\r
+ *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;\r
+ __DSB();\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Read status until NAND is ready */\r
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT; \r
+ }\r
+ }\r
+\r
+ /* Increment written spare areas number */\r
+ numSpareAreaWritten++;\r
+ \r
+ /* Decrement spare areas to write */\r
+ NumSpareAreaTowrite--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));\r
+ }\r
+\r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief NAND memory Block erase \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)\r
+{\r
+ uint32_t DeviceAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand);\r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ DeviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* Send Erase block command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ __DSB();\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ __DSB();\r
+ } \r
+ \r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; \r
+ __DSB();\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief NAND memory read status \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval NAND status\r
+ */\r
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)\r
+{\r
+ uint32_t data = 0;\r
+ uint32_t DeviceAddress = 0;\r
+ \r
+ /* Identify the device address */\r
+ DeviceAddress = NAND_DEVICE;\r
+\r
+ /* Send Read status operation command */\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;\r
+ \r
+ /* Read status register data */\r
+ data = *(__IO uint8_t *)DeviceAddress;\r
+\r
+ /* Return the status */\r
+ if((data & NAND_ERROR) == NAND_ERROR)\r
+ {\r
+ return NAND_ERROR;\r
+ } \r
+ else if((data & NAND_READY) == NAND_READY)\r
+ {\r
+ return NAND_READY;\r
+ }\r
+\r
+ return NAND_BUSY; \r
+}\r
+\r
+/**\r
+ * @brief Increment the NAND memory address\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress: pointer to NAND address structure\r
+ * @retval The new status of the increment address operation. It can be:\r
+ * - NAND_VALID_ADDRESS: When the new address is valid address\r
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address\r
+ */\r
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)\r
+{\r
+ uint32_t status = NAND_VALID_ADDRESS;\r
+ \r
+ /* Increment page address */\r
+ pAddress->Page++;\r
+\r
+ /* Check NAND address is valid */\r
+ if(pAddress->Page == hnand->Info.BlockSize)\r
+ {\r
+ pAddress->Page = 0;\r
+ pAddress->Block++;\r
+ \r
+ if(pAddress->Block == hnand->Info.ZoneSize)\r
+ {\r
+ pAddress->Block = 0;\r
+ pAddress->Zone++;\r
+\r
+ if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))\r
+ {\r
+ status = NAND_INVALID_ADDRESS;\r
+ }\r
+ }\r
+ } \r
+ \r
+ return (status);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NAND Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the NAND interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ \r
+/**\r
+ * @brief Enables dynamically NAND ECC feature.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* Enable ECC feature */\r
+ FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) \r
+{\r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* Disable ECC feature */\r
+ FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically NAND ECC feature.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param ECCval: pointer to ECC value \r
+ * @param Timeout: maximum timeout to wait \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* Get NAND ECC value */\r
+ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+\r
+ return status; \r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NAND State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the NAND controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief return the NAND state\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL state\r
+ */\r
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)\r
+{\r
+ return hnand->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_nor.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief NOR HAL module driver.\r
+ * This file provides a generic firmware to drive NOR memories mounted \r
+ * as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control NOR flash memories. It uses the FMC layer functions to interface \r
+ with NOR devices. This driver is used as follows:\r
+ \r
+ (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() \r
+ with control and timing parameters for both normal and extended mode.\r
+ \r
+ (+) Read NOR flash memory manufacturer code and device IDs using the function\r
+ HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef \r
+ structure declared by the function caller. \r
+ \r
+ (+) Access NOR flash memory by read/write data unit operations using the functions\r
+ HAL_NOR_Read(), HAL_NOR_Program().\r
+ \r
+ (+) Perform NOR flash erase block/chip operations using the functions \r
+ HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().\r
+ \r
+ (+) Read the NOR flash CFI (common flash interface) IDs using the function\r
+ HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef\r
+ structure declared by the function caller.\r
+ \r
+ (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/\r
+ HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation \r
+ \r
+ (+) You can monitor the NOR device HAL state by calling the function\r
+ HAL_NOR_GetState() \r
+ [..]\r
+ (@) This driver is a set of generic APIs which handle standard NOR flash operations.\r
+ If a NOR flash device contains different operations and/or implementations, \r
+ it should be implemented separately.\r
+\r
+ *** NOR HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in NOR HAL driver.\r
+ \r
+ (+) NOR_WRITE : NOR memory write data to specified address\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup NOR NOR\r
+ * @brief NOR driver modules\r
+ * @{\r
+ */\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+ \r
+/** @defgroup NOR_Private_Defines NOR Private Defines\r
+ * @{\r
+ */\r
+\r
+/* Constants to define address to set to write a command */\r
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555\r
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055\r
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA\r
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555\r
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555\r
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA\r
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555\r
+\r
+/* Constants to define data to program a command */\r
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0\r
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA\r
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055\r
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090\r
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0\r
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080\r
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA\r
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055\r
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010\r
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098\r
+\r
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25\r
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29\r
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30\r
+\r
+/* Mask on NOR STATUS REGISTER */\r
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020\r
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup NOR_Private_Variables NOR Private Variables\r
+ * @{\r
+ */\r
+\r
+static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup NOR_Exported_Functions NOR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NOR Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize\r
+ the NOR memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Perform the NOR memory Initialization sequence\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param Timing: pointer to NOR control timing structure \r
+ * @param ExtTiming: pointer to NOR extended mode timing structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)\r
+{\r
+ /* Check the NOR handle parameter */\r
+ if(hnor == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hnor->State == HAL_NOR_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hnor->Lock = HAL_UNLOCKED;\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_NOR_MspInit(hnor);\r
+ }\r
+ \r
+ /* Initialize NOR control Interface */\r
+ FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));\r
+\r
+ /* Initialize NOR timing Interface */\r
+ FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); \r
+\r
+ /* Initialize NOR extended mode timing Interface */\r
+ FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);\r
+\r
+ /* Enable the NORSRAM device */\r
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);\r
+\r
+ /* Initialize NOR Memory Data Width*/\r
+ if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)\r
+ {\r
+ uwNORMemoryDataWidth = NOR_MEMORY_8B;\r
+ }\r
+ else\r
+ {\r
+ uwNORMemoryDataWidth = NOR_MEMORY_16B;\r
+ }\r
+\r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Perform NOR memory De-Initialization sequence\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) \r
+{\r
+ /* De-Initialize the low level hardware (MSP) */\r
+ HAL_NOR_MspDeInit(hnor);\r
+ \r
+ /* Configure the NOR registers with their reset values */\r
+ FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);\r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hnor);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief NOR MSP Init\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hnor);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NOR_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief NOR MSP DeInit\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hnor);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NOR_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief NOR MSP Wait for Ready/Busy signal\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param Timeout: Maximum timeout value\r
+ * @retval None\r
+ */\r
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hnor);\r
+ UNUSED(Timeout);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NOR_MspWait could be implemented in the user file\r
+ */ \r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NOR Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the NOR memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Read NOR flash IDs\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pNOR_ID : pointer to NOR ID structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read ID command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);\r
+\r
+ /* Read the NOR IDs */\r
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);\r
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);\r
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);\r
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the NOR memory to Read mode.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)\r
+{\r
+ uint32_t deviceaddress = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);\r
+\r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read data from NOR memory \r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pAddress: pointer to Device address\r
+ * @param pData : pointer to read data \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read data command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);\r
+\r
+ /* Read the data */\r
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Program data to NOR memory \r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pAddress: Device address\r
+ * @param pData : pointer to the data to write \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send program data command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);\r
+\r
+ /* Write the data */\r
+ NOR_WRITE(pAddress, *pData);\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads a half-word buffer from the NOR memory.\r
+ * @param hnor: pointer to the NOR handle\r
+ * @param uwAddress: NOR memory internal address to read from.\r
+ * @param pData: pointer to the buffer that receives the data read from the \r
+ * NOR memory.\r
+ * @param uwBufferSize : number of Half word to read.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read data command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);\r
+ \r
+ /* Read buffer */\r
+ while( uwBufferSize > 0) \r
+ {\r
+ *pData++ = *(__IO uint16_t *)uwAddress;\r
+ uwAddress += 2;\r
+ uwBufferSize--;\r
+ } \r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes a half-word buffer to the NOR memory. This function must be used \r
+ only with S29GL128P NOR memory. \r
+ * @param hnor: pointer to the NOR handle\r
+ * @param uwAddress: NOR memory internal start write address \r
+ * @param pData: pointer to source data buffer. \r
+ * @param uwBufferSize: Size of the buffer to write\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)\r
+{\r
+ uint16_t * p_currentaddress = (uint16_t *)NULL;\r
+ uint16_t * p_endaddress = (uint16_t *)NULL;\r
+ uint32_t lastloadedaddress = 0, deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Initialize variables */\r
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));\r
+ p_endaddress = p_currentaddress + (uwBufferSize-1);\r
+ lastloadedaddress = (uint32_t)(uwAddress);\r
+\r
+ /* Issue unlock command sequence */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); \r
+\r
+ /* Write Buffer Load Command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1)); \r
+\r
+ /* Load Data into NOR Buffer */\r
+ while(p_currentaddress <= p_endaddress)\r
+ {\r
+ /* Store last loaded address & data value (for polling) */\r
+ lastloadedaddress = (uint32_t)p_currentaddress;\r
+ \r
+ NOR_WRITE(p_currentaddress, *pData++);\r
+ \r
+ p_currentaddress ++; \r
+ }\r
+\r
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+ \r
+}\r
+\r
+/**\r
+ * @brief Erase the specified block of the NOR memory \r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param BlockAddress : Block to erase address \r
+ * @param Address: Device address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ }\r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send block erase command sequence */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);\r
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);\r
+\r
+ /* Check the NOR memory status and update the controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Erase the entire NOR chip.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param Address : Device address \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ }\r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY; \r
+ \r
+ /* Send NOR chip erase command sequence */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);\r
+ \r
+ /* Check the NOR memory status and update the controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Read NOR flash CFI IDs\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pNOR_CFI : pointer to NOR CFI IDs structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read CFI query command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);\r
+\r
+ /* read the NOR CFI information */\r
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);\r
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);\r
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);\r
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);\r
+\r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NOR Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the NOR interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables dynamically NOR write operation.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+\r
+ /* Enable write operation */\r
+ FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically NOR write operation.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+\r
+ /* Update the SRAM controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Disable write operation */\r
+ FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_PROTECTED;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup NOR_Exported_Functions_Group4 NOR State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NOR State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the NOR controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief return the NOR controller state\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval NOR controller state\r
+ */\r
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)\r
+{\r
+ return hnor->State;\r
+}\r
+\r
+/**\r
+ * @brief Returns the NOR operation status.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module. \r
+ * @param Address: Device address\r
+ * @param Timeout: NOR programming Timeout\r
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR\r
+ * or HAL_NOR_STATUS_TIMEOUT\r
+ */\r
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)\r
+{ \r
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;\r
+ uint16_t tmpSR1 = 0, tmpSR2 = 0;\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/\r
+ HAL_NOR_MspWait(hnor, Timeout);\r
+ \r
+ /* Get the NOR memory operation status -------------------------------------*/\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ status = HAL_NOR_STATUS_TIMEOUT; \r
+ } \r
+ } \r
+\r
+ /* Read NOR status register (DQ6 and DQ5) */\r
+ tmpSR1 = *(__IO uint16_t *)Address;\r
+ tmpSR2 = *(__IO uint16_t *)Address;\r
+\r
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */\r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) \r
+ {\r
+ return HAL_NOR_STATUS_SUCCESS ;\r
+ }\r
+ \r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)\r
+ {\r
+ status = HAL_NOR_STATUS_ONGOING;\r
+ }\r
+ \r
+ tmpSR1 = *(__IO uint16_t *)Address;\r
+ tmpSR2 = *(__IO uint16_t *)Address;\r
+\r
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */\r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) \r
+ {\r
+ return HAL_NOR_STATUS_SUCCESS;\r
+ }\r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)\r
+ {\r
+ return HAL_NOR_STATUS_ERROR;\r
+ } \r
+ }\r
+\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pcd.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief PCD HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The PCD HAL driver can be used as follows:\r
+\r
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:\r
+ PCD_HandleTypeDef hpcd;\r
+ \r
+ (#) Fill parameters of Init structure in HCD handle\r
+ \r
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) \r
+\r
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:\r
+ (##) Enable the PCD/USB Low Level interface clock using \r
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)\r
+ \r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure PCD pin-out\r
+ (##) Configure PCD NVIC interrupt\r
+ \r
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:\r
+ (##) hpcd.pData = pdev;\r
+\r
+ (#)Enable PCD transmission and reception:\r
+ (##) HAL_PCD_Start();\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCD PCD\r
+ * @brief PCD HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PCD_Private_Macros PCD Private Macros\r
+ * @{\r
+ */ \r
+#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup PCD_Private_Functions PCD Private Functions\r
+ * @{\r
+ */\r
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Functions PCD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the PCD according to the specified\r
+ * parameters in the PCD_InitTypeDef and create the associated handle.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)\r
+{ \r
+ uint32_t i = 0;\r
+ \r
+ /* Check the PCD handle allocation */\r
+ if(hpcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));\r
+\r
+ hpcd->State = HAL_PCD_STATE_BUSY;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+ HAL_PCD_MspInit(hpcd);\r
+\r
+ /* Disable the Interrupts */\r
+ __HAL_PCD_DISABLE(hpcd);\r
+ \r
+ /*Init the Core (common init.) */\r
+ USB_CoreInit(hpcd->Instance, hpcd->Init);\r
+ \r
+ /* Force Device Mode*/\r
+ USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);\r
+ \r
+ /* Init endpoints structures */\r
+ for (i = 0; i < 15 ; i++)\r
+ {\r
+ /* Init ep structure */\r
+ hpcd->IN_ep[i].is_in = 1;\r
+ hpcd->IN_ep[i].num = i;\r
+ hpcd->IN_ep[i].tx_fifo_num = i;\r
+ /* Control until ep is activated */\r
+ hpcd->IN_ep[i].type = EP_TYPE_CTRL;\r
+ hpcd->IN_ep[i].maxpacket = 0;\r
+ hpcd->IN_ep[i].xfer_buff = 0;\r
+ hpcd->IN_ep[i].xfer_len = 0;\r
+ }\r
+ \r
+ for (i = 0; i < 15 ; i++)\r
+ {\r
+ hpcd->OUT_ep[i].is_in = 0;\r
+ hpcd->OUT_ep[i].num = i;\r
+ hpcd->IN_ep[i].tx_fifo_num = i;\r
+ /* Control until ep is activated */\r
+ hpcd->OUT_ep[i].type = EP_TYPE_CTRL;\r
+ hpcd->OUT_ep[i].maxpacket = 0;\r
+ hpcd->OUT_ep[i].xfer_buff = 0;\r
+ hpcd->OUT_ep[i].xfer_len = 0;\r
+ \r
+ hpcd->Instance->DIEPTXF[i] = 0;\r
+ }\r
+ \r
+ /* Init Device */\r
+ USB_DevInit(hpcd->Instance, hpcd->Init);\r
+ \r
+ hpcd->State= HAL_PCD_STATE_READY;\r
+ \r
+ /* Activate LPM */\r
+ if (hpcd->Init.lpm_enable == 1)\r
+ {\r
+ HAL_PCDEx_ActivateLPM(hpcd);\r
+ }\r
+ \r
+ USB_DevDisconnect (hpcd->Instance); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the PCD peripheral. \r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Check the PCD handle allocation */\r
+ if(hpcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hpcd->State = HAL_PCD_STATE_BUSY;\r
+ \r
+ /* Stop Device */\r
+ HAL_PCD_Stop(hpcd);\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_PCD_MspDeInit(hpcd);\r
+ \r
+ hpcd->State = HAL_PCD_STATE_RESET; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the PCD MSP.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes PCD MSP.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the PCD data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Start The USB OTG Device.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)\r
+{ \r
+ __HAL_LOCK(hpcd); \r
+ USB_DevConnect (hpcd->Instance); \r
+ __HAL_PCD_ENABLE(hpcd);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop The USB OTG Device.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)\r
+{ \r
+ __HAL_LOCK(hpcd); \r
+ __HAL_PCD_DISABLE(hpcd);\r
+ USB_StopDevice(hpcd->Instance);\r
+ USB_DevDisconnect (hpcd->Instance);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle PCD interrupt request.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+ uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;\r
+ uint32_t fifoemptymsk = 0, temp = 0;\r
+ USB_OTG_EPTypeDef *ep = NULL;\r
+ uint32_t hclk = 200000000;\r
+ \r
+ /* ensure that we are in device mode */\r
+ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)\r
+ {\r
+ /* avoid spurious interrupt */\r
+ if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) \r
+ {\r
+ return;\r
+ }\r
+ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);\r
+ }\r
+ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))\r
+ {\r
+ epnum = 0;\r
+ \r
+ /* Read in the device interrupt bits */\r
+ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);\r
+ \r
+ while ( ep_intr )\r
+ {\r
+ if (ep_intr & 0x1)\r
+ {\r
+ epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);\r
+ \r
+ if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)\r
+ {\r
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);\r
+ \r
+ if(hpcd->Init.dma_enable == 1)\r
+ {\r
+ hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; \r
+ }\r
+ \r
+ HAL_PCD_DataOutStageCallback(hpcd, epnum);\r
+ if(hpcd->Init.dma_enable == 1)\r
+ {\r
+ if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))\r
+ {\r
+ /* this is ZLP, so prepare EP0 for next setup */\r
+ USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);\r
+ } \r
+ }\r
+ }\r
+ \r
+ if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)\r
+ {\r
+ /* Inform the upper layer that a setup packet is available */\r
+ HAL_PCD_SetupStageCallback(hpcd);\r
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);\r
+ }\r
+ \r
+ if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)\r
+ {\r
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);\r
+ }\r
+ /* Clear Status Phase Received interrupt */\r
+ if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\r
+ {\r
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\r
+ }\r
+ }\r
+ epnum++;\r
+ ep_intr >>= 1;\r
+ }\r
+ }\r
+ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))\r
+ {\r
+ /* Read in the device interrupt bits */\r
+ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);\r
+ \r
+ epnum = 0;\r
+ \r
+ while ( ep_intr )\r
+ {\r
+ if (ep_intr & 0x1) /* In ITR */\r
+ {\r
+ epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);\r
+\r
+ if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)\r
+ {\r
+ fifoemptymsk = 0x1 << epnum;\r
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
+ \r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);\r
+ \r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; \r
+ }\r
+ \r
+ HAL_PCD_DataInStageCallback(hpcd, epnum);\r
+\r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ /* this is ZLP, so prepare EP0 for next setup */\r
+ if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))\r
+ {\r
+ /* prepare to rx more setup packets */\r
+ USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);\r
+ }\r
+ } \r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);\r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);\r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);\r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);\r
+ } \r
+ if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)\r
+ {\r
+ PCD_WriteEmptyTxFifo(hpcd , epnum);\r
+ }\r
+ }\r
+ epnum++;\r
+ ep_intr >>= 1;\r
+ }\r
+ }\r
+ \r
+ /* Handle Resume Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))\r
+ {\r
+ /* Clear the Remote Wake-up Signaling */\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r
+ \r
+ if(hpcd->LPM_State == LPM_L1)\r
+ {\r
+ hpcd->LPM_State = LPM_L0;\r
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r
+ }\r
+ else\r
+ {\r
+ HAL_PCD_ResumeCallback(hpcd);\r
+ }\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);\r
+ }\r
+ \r
+ /* Handle Suspend Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))\r
+ {\r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
+ {\r
+ \r
+ HAL_PCD_SuspendCallback(hpcd);\r
+ }\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);\r
+ }\r
+ \r
+ /* Handle LPM Interrupt */ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))\r
+ {\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); \r
+ if( hpcd->LPM_State == LPM_L0)\r
+ {\r
+ hpcd->LPM_State = LPM_L1;\r
+ hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;\r
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r
+ }\r
+ else\r
+ {\r
+ HAL_PCD_SuspendCallback(hpcd);\r
+ }\r
+ }\r
+ \r
+ /* Handle Reset Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))\r
+ {\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; \r
+ USB_FlushTxFifo(hpcd->Instance , 0 );\r
+ \r
+ for (i = 0; i < hpcd->Init.dev_endpoints ; i++)\r
+ {\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ USBx_DEVICE->DAINTMSK |= 0x10001;\r
+ \r
+ if(hpcd->Init.use_dedicated_ep1)\r
+ {\r
+ USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); \r
+ USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); \r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);\r
+ USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);\r
+ }\r
+ \r
+ /* Set Default Address to 0 */\r
+ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\r
+ \r
+ /* setup EP0 to receive SETUP packets */\r
+ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r
+ \r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);\r
+ }\r
+ \r
+ /* Handle Enumeration done Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))\r
+ {\r
+ USB_ActivateSetup(hpcd->Instance);\r
+ hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\r
+ \r
+ if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)\r
+ {\r
+ hpcd->Init.speed = USB_OTG_SPEED_HIGH;\r
+ hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ else\r
+ {\r
+ hpcd->Init.speed = USB_OTG_SPEED_FULL;\r
+ hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; \r
+ \r
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency \r
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response \r
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access \r
+ latency to the Data FIFO */\r
+ \r
+ /* Get hclk frequency value */\r
+ hclk = HAL_RCC_GetHCLKFreq();\r
+ \r
+ if((hclk >= 14200000)&&(hclk < 15000000))\r
+ {\r
+ /* hclk Clock Range between 14.2-15 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 15000000)&&(hclk < 16000000))\r
+ {\r
+ /* hclk Clock Range between 15-16 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 16000000)&&(hclk < 17200000))\r
+ {\r
+ /* hclk Clock Range between 16-17.2 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 17200000)&&(hclk < 18500000))\r
+ {\r
+ /* hclk Clock Range between 17.2-18.5 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 18500000)&&(hclk < 20000000))\r
+ {\r
+ /* hclk Clock Range between 18.5-20 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 20000000)&&(hclk < 21800000))\r
+ {\r
+ /* hclk Clock Range between 20-21.8 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 21800000)&&(hclk < 24000000))\r
+ {\r
+ /* hclk Clock Range between 21.8-24 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 24000000)&&(hclk < 27700000))\r
+ {\r
+ /* hclk Clock Range between 24-27.7 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else if((hclk >= 27700000)&&(hclk < 32000000))\r
+ {\r
+ /* hclk Clock Range between 27.7-32 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ }\r
+ \r
+ else /* if(hclk >= 32000000) */\r
+ {\r
+ /* hclk Clock Range between 32-200 MHz */\r
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);\r
+ } \r
+ }\r
+ \r
+ HAL_PCD_ResetCallback(hpcd);\r
+ \r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);\r
+ }\r
+ \r
+ /* Handle RxQLevel Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))\r
+ {\r
+ USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ temp = USBx->GRXSTSP;\r
+ ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];\r
+ \r
+ if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)\r
+ {\r
+ if((temp & USB_OTG_GRXSTSP_BCNT) != 0)\r
+ {\r
+ USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);\r
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ }\r
+ }\r
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)\r
+ {\r
+ USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);\r
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ }\r
+ USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ }\r
+ \r
+ /* Handle SOF Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))\r
+ {\r
+ HAL_PCD_SOFCallback(hpcd);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);\r
+ }\r
+ \r
+ /* Handle Incomplete ISO IN Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))\r
+ {\r
+ HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);\r
+ } \r
+ \r
+ /* Handle Incomplete ISO OUT Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r
+ {\r
+ HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r
+ } \r
+ \r
+ /* Handle Connection event Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))\r
+ {\r
+ HAL_PCD_ConnectCallback(hpcd);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);\r
+ } \r
+ \r
+ /* Handle Disconnection event Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))\r
+ {\r
+ temp = hpcd->Instance->GOTGINT;\r
+ \r
+ if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)\r
+ {\r
+ HAL_PCD_DisconnectCallback(hpcd);\r
+ }\r
+ hpcd->Instance->GOTGINT |= temp;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Data OUT stage callback.\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number \r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ UNUSED(epnum); \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Data IN stage callback.\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number \r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ UNUSED(epnum); \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_DataInStageCallback could be implemented in the user file\r
+ */ \r
+}\r
+/**\r
+ * @brief Setup stage callback.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_SetupStageCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief USB Start Of Frame callback.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_SOFCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief USB Reset callback.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ResetCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Suspend event callback.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_SuspendCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Resume event callback.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ResumeCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Incomplete ISO OUT callback.\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ UNUSED(epnum); \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Incomplete ISO IN callback.\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number \r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ UNUSED(epnum); \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Connection event callback.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ConnectCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Disconnection event callback.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_DisconnectCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the PCD data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Connect the USB device.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ USB_DevConnect(hpcd->Instance);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disconnect the USB device.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ USB_DevDisconnect(hpcd->Instance);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the USB Device address. \r
+ * @param hpcd: PCD handle\r
+ * @param address: new device address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ USB_SetDevAddress(hpcd->Instance, address);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Open and configure an endpoint.\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @param ep_mps: endpoint max packet size\r
+ * @param ep_type: endpoint type \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)\r
+{\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((ep_addr & 0x80) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r
+ }\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ ep->is_in = (0x80 & ep_addr) != 0;\r
+ ep->maxpacket = ep_mps;\r
+ ep->type = ep_type;\r
+ if (ep->is_in)\r
+ {\r
+ /* Assign a Tx FIFO */\r
+ ep->tx_fifo_num = ep->num;\r
+ }\r
+ /* Set initial data PID. */\r
+ if (ep_type == EP_TYPE_BULK )\r
+ {\r
+ ep->data_pid_start = 0;\r
+ }\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_ActivateEndpoint(hpcd->Instance , ep);\r
+ __HAL_UNLOCK(hpcd); \r
+ return ret;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Deactivate an endpoint.\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{ \r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((ep_addr & 0x80) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r
+ }\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ ep->is_in = (0x80 & ep_addr) != 0;\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_DeactivateEndpoint(hpcd->Instance , ep);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Receive an amount of data. \r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @param pBuf: pointer to the reception buffer \r
+ * @param len: amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r
+ \r
+ /*setup and start the Xfer */\r
+ ep->xfer_buff = pBuf; \r
+ ep->xfer_len = len;\r
+ ep->xfer_count = 0;\r
+ ep->is_in = 0;\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ ep->dma_addr = (uint32_t)pBuf; \r
+ }\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ \r
+ if ((ep_addr & 0x7F) == 0 )\r
+ {\r
+ USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ else\r
+ {\r
+ USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get Received Data Size.\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval Data Size\r
+ */\r
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;\r
+}\r
+/**\r
+ * @brief Send an amount of data. \r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @param pBuf: pointer to the transmission buffer \r
+ * @param len: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ \r
+ /*setup and start the Xfer */\r
+ ep->xfer_buff = pBuf; \r
+ ep->xfer_len = len;\r
+ ep->xfer_count = 0;\r
+ ep->is_in = 1;\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ ep->dma_addr = (uint32_t)pBuf; \r
+ }\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ \r
+ if ((ep_addr & 0x7F) == 0 )\r
+ {\r
+ USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ else\r
+ {\r
+ USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ \r
+ __HAL_UNLOCK(hpcd);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set a STALL condition over an endpoint.\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((0x80 & ep_addr) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr];\r
+ }\r
+ \r
+ ep->is_stall = 1;\r
+ ep->num = ep_addr & 0x7F;\r
+ ep->is_in = ((ep_addr & 0x80) == 0x80);\r
+ \r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_EPSetStall(hpcd->Instance , ep);\r
+ if((ep_addr & 0x7F) == 0)\r
+ {\r
+ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r
+ }\r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Clear a STALL condition over in an endpoint.\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((0x80 & ep_addr) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr];\r
+ }\r
+ \r
+ ep->is_stall = 0;\r
+ ep->num = ep_addr & 0x7F;\r
+ ep->is_in = ((ep_addr & 0x80) == 0x80);\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_EPClearStall(hpcd->Instance , ep);\r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Flush an endpoint.\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ \r
+ if ((ep_addr & 0x80) == 0x80)\r
+ {\r
+ USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);\r
+ }\r
+ else\r
+ {\r
+ USB_FlushRxFifo(hpcd->Instance);\r
+ }\r
+ \r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Activate remote wakeup signalling.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
+ {\r
+ /* Activate Remote wakeup signaling */\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief De-activate remote wakeup signalling.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ /* De-activate Remote wakeup signaling */\r
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the PCD handle state.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL state\r
+ */\r
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)\r
+{\r
+ return hpcd->State;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup PCD_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Check FIFO for the next packet to be loaded.\r
+ * @param hpcd: PCD handle\r
+ * @param epnum : endpoint number \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ USB_OTG_EPTypeDef *ep;\r
+ int32_t len = 0;\r
+ uint32_t len32b;\r
+ uint32_t fifoemptymsk = 0;\r
+\r
+ ep = &hpcd->IN_ep[epnum];\r
+ len = ep->xfer_len - ep->xfer_count;\r
+ \r
+ if (len > ep->maxpacket)\r
+ {\r
+ len = ep->maxpacket;\r
+ }\r
+ \r
+ \r
+ len32b = (len + 3) / 4;\r
+ \r
+ while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&\r
+ ep->xfer_count < ep->xfer_len &&\r
+ ep->xfer_len != 0)\r
+ {\r
+ /* Write the FIFO */\r
+ len = ep->xfer_len - ep->xfer_count;\r
+ \r
+ if (len > ep->maxpacket)\r
+ {\r
+ len = ep->maxpacket;\r
+ }\r
+ len32b = (len + 3) / 4;\r
+ \r
+ USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); \r
+ \r
+ ep->xfer_buff += len;\r
+ ep->xfer_count += len;\r
+ }\r
+ \r
+ if(len <= 0)\r
+ {\r
+ fifoemptymsk = 0x1 << epnum;\r
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
+ \r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pcd_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief PCD HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Extended features functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCDEx PCDEx\r
+ * @brief PCD Extended HAL module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r
+ * @brief PCDEx control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Update FIFO configuration\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set Tx FIFO\r
+ * @param hpcd: PCD handle\r
+ * @param fifo: The number of Tx fifo\r
+ * @param size: Fifo size\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)\r
+{\r
+ uint8_t i = 0;\r
+ uint32_t Tx_Offset = 0;\r
+\r
+ /* TXn min size = 16 words. (n : Transmit FIFO index)\r
+ When a TxFIFO is not used, the Configuration should be as follows: \r
+ case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)\r
+ --> Txm can use the space allocated for Txn.\r
+ case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)\r
+ --> Txn should be configured with the minimum space of 16 words\r
+ The FIFO is used optimally when used TxFIFOs are allocated in the top \r
+ of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.\r
+ When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */\r
+ \r
+ Tx_Offset = hpcd->Instance->GRXFSIZ;\r
+ \r
+ if(fifo == 0)\r
+ {\r
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);\r
+ }\r
+ else\r
+ {\r
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;\r
+ for (i = 0; i < (fifo - 1); i++)\r
+ {\r
+ Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);\r
+ }\r
+ \r
+ /* Multiply Tx_Size by 2 to get higher performance */\r
+ hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set Rx FIFO\r
+ * @param hpcd: PCD handle\r
+ * @param size: Size of Rx fifo\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)\r
+{\r
+ hpcd->Instance->GRXFSIZ = size;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Activate LPM Feature\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ hpcd->lpm_active = ENABLE;\r
+ hpcd->LPM_State = LPM_L0;\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;\r
+ USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief DeActivate LPM feature.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ hpcd->lpm_active = DISABLE;\r
+ USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;\r
+ USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Send LPM message to user layer callback.\r
+ * @param hpcd: PCD handle\r
+ * @param msg: LPM message\r
+ * @retval HAL status\r
+ */\r
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hpcd);\r
+ UNUSED(msg);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCDEx_LPM_Callback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR PWR\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWR_Private_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
+ * @{\r
+ */ \r
+#define PVD_MODE_IT ((uint32_t)0x00010000U)\r
+#define PVD_MODE_EVT ((uint32_t)0x00020000U)\r
+#define PVD_RISING_EDGE ((uint32_t)0x00000001U)\r
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask\r
+ * @{\r
+ */ \r
+#define PWR_EWUP_MASK ((uint32_t)0x00003F00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ After reset, the backup domain (RTC registers, RTC backup data \r
+ registers and backup SRAM) is protected against possible unwanted \r
+ write accesses. \r
+ To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __HAL_RCC_PWR_CLK_ENABLE() macro.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+ __HAL_RCC_PWR_FORCE_RESET();\r
+ __HAL_RCC_PWR_RELEASE_RESET();\r
+}\r
+\r
+/**\r
+ * @brief Enables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+ /* Enable access to RTC and backup registers */\r
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @brief Disables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+ /* Disable access to RTC and backup registers */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ \r
+ *** PVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a \r
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower \r
+ than the PVD threshold. This event is internally connected to the EXTI \r
+ line16 and can generate an interrupt if enabled. This is done through\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+ *** Wake-up pin configuration ***\r
+ ================================\r
+ [..]\r
+ (+) Wake-up pin is used to wake up the system from Standby mode. This pin is \r
+ forced in input pull-down configuration and is active on rising edges.\r
+ (+) There are to 6 Wake-up pin in the STM32F7 devices family\r
+\r
+ *** Low Power modes configuration ***\r
+ =====================================\r
+ [..]\r
+ The devices feature 3 low-power modes:\r
+ (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.\r
+ (+) Stop mode: all clocks are stopped, regulator running, regulator \r
+ in low power mode\r
+ (+) Standby mode: 1.2V domain powered off.\r
+ \r
+ *** Sleep mode ***\r
+ ==================\r
+ [..]\r
+ (+) Entry:\r
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)\r
+ functions with\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ \r
+ -@@- The Regulator parameter is not used for the STM32F7 family \r
+ and is kept as parameter just to maintain compatibility with the \r
+ lower power families (STM32L).\r
+ (+) Exit:\r
+ Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** Stop mode ***\r
+ =================\r
+ [..]\r
+ In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents \r
+ are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, FLASH can be powered off before \r
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\r
+ It can be switched on again by software after exiting the Stop mode using\r
+ the HAL_PWREx_DisableFlashPowerDown() function. \r
+\r
+ (+) Entry:\r
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) \r
+ function with:\r
+ (++) Main regulator ON.\r
+ (++) Low Power regulator ON.\r
+ (+) Exit:\r
+ Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+\r
+ *** Standby mode ***\r
+ ====================\r
+ [..]\r
+ (+)\r
+ The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. \r
+ The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \r
+ the HSE oscillator are also switched off. SRAM and register contents are lost \r
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby \r
+ circuitry.\r
+ \r
+ The voltage regulator is OFF.\r
+ \r
+ (++) Entry:\r
+ (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r
+ (++) Exit:\r
+ (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r
+ wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode ***\r
+ =============================================\r
+ [..]\r
+ \r
+ (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
+ Wakeup event, a tamper event or a time-stamp event, without depending on \r
+ an external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes\r
+ \r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \r
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
+\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to configure the RTC to detect the tamper or time stamp event using the\r
+ HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
+ \r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration\r
+ * information for the PVD.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage threshold corresponding to each \r
+ * detection level.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+ \r
+ /* Set PLS[7:5] bits according to PVDLevel value */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);\r
+ \r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+ }\r
+ \r
+ /* Configure event mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+ }\r
+ \r
+ /* Configure the edge */\r
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+ \r
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+ /* Enable the power voltage detector */\r
+ SET_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+ /* Disable the power voltage detector */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Enable the WakeUp PINx functionality.\r
+ * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r
+ * This parameter can be one of the following legacy values, which sets the default polarity: \r
+ * detection on high level (rising edge):\r
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 \r
+ * or one of the following value where the user can explicitly states the enabled pin and\r
+ * the chosen polarity \r
+ * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW \r
+ * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW \r
+ * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW \r
+ * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
+ * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW \r
+ * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW \r
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
+ \r
+ /* Enable wake-up pin */\r
+ SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));\r
+ \r
+ /* Specifies the Wake-Up pin polarity for the event detection\r
+ (rising or falling edge) */\r
+ MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));\r
+}\r
+\r
+/**\r
+ * @brief Disables the WakeUp PINx functionality.\r
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1\r
+ * @arg PWR_WAKEUP_PIN2\r
+ * @arg PWR_WAKEUP_PIN3\r
+ * @arg PWR_WAKEUP_PIN4\r
+ * @arg PWR_WAKEUP_PIN5\r
+ * @arg PWR_WAKEUP_PIN6 \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+\r
+ CLEAR_BIT(PWR->CSR2, WakeUpPinx);\r
+}\r
+ \r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * \r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r
+ * \r
+ * @note In Sleep mode, the systick is stopped to avoid exit from this mode with\r
+ * systick interrupt when used as time base for Timeout \r
+ * \r
+ * @param Regulator: Specifies the regulator state in SLEEP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r
+ * @note This parameter is not used for the STM32F7 family and is kept as parameter\r
+ * just to maintain compatibility with the lower power families.\r
+ * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters Stop mode. \r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced. \r
+ * @param Regulator: Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+ \r
+ /* Select the regulator state in Stop mode ---------------------------------*/\r
+ tmpreg = PWR->CR1;\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);\r
+ \r
+ /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */\r
+ tmpreg |= Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR1 = tmpreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); \r
+}\r
+\r
+/**\r
+ * @brief Enters Standby mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * - Reset pad (still available) \r
+ * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \r
+ * Alarm out, or RTC clock calibration out.\r
+ * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. \r
+ * - WKUP pins if enabled. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Select Standby mode */\r
+ PWR->CR1 |= PWR_CR1_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD interrupt request.\r
+ * @note This API should be called under the PVD_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWR_PVD_IRQHandler(void)\r
+{\r
+ /* Check PWR Exti flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+ \r
+ /* Clear PWR Exti pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief PWR PVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWR_PVDCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \r
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * Setting this bit is useful when the processor is expected to run only on\r
+ * interruptions handling. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \r
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Enables CORTEX M4 SEVONPEND bit. \r
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+ /* Set SEVONPEND bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables CORTEX M4 SEVONPEND bit. \r
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+ /* Clear SEVONPEND bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Extended PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of PWR extension peripheral: \r
+ * + Peripheral Extended features functions\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx PWREx\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWREx_Private_Constants\r
+ * @{\r
+ */ \r
+#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000\r
+#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000\r
+#define PWR_BKPREG_TIMEOUT_VALUE 1000\r
+#define PWR_VOSRDY_TIMEOUT_VALUE 1000\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions \r
+ * @brief Peripheral Extended features functions \r
+ *\r
+@verbatim \r
+\r
+ ===============================================================================\r
+ ##### Peripheral extended features functions #####\r
+ ===============================================================================\r
+\r
+ *** Main and Backup Regulators configuration ***\r
+ ================================================\r
+ [..] \r
+ (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from \r
+ the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is \r
+ retained even in Standby or VBAT mode when the low power backup regulator\r
+ is enabled. It can be considered as an internal EEPROM when VBAT is \r
+ always present. You can use the HAL_PWREx_EnableBkUpReg() function to \r
+ enable the low power backup regulator. \r
+\r
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD) \r
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to \r
+ save battery life.\r
+\r
+ (+) The backup SRAM is not mass erased by a tamper event. It is read \r
+ protected to prevent confidential data, such as cryptographic private \r
+ key, from being accessed. The backup SRAM can be erased only through \r
+ the Flash interface when a protection level change from level 1 to \r
+ level 0 is requested. \r
+ -@- Refer to the description of Read protection (RDP) in the Flash \r
+ programming manual.\r
+\r
+ (+) The main internal regulator can be configured to have a tradeoff between \r
+ performance and power consumption when the device does not operate at \r
+ the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() \r
+ macro which configure VOS bit in PWR_CR register\r
+ \r
+ Refer to the product datasheets for more details.\r
+\r
+ *** FLASH Power Down configuration ****\r
+ =======================================\r
+ [..] \r
+ (+) By setting the FPDS bit in the PWR_CR register by using the \r
+ HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power \r
+ down mode when the device enters Stop mode. When the Flash memory \r
+ is in power down mode, an additional startup delay is incurred when \r
+ waking up from Stop mode.\r
+\r
+ *** Over-Drive and Under-Drive configuration ****\r
+ =================================================\r
+ [..] \r
+ (+) In Run mode: the main regulator has 2 operating modes available:\r
+ (++) Normal mode: The CPU and core logic operate at maximum frequency at a given \r
+ voltage scaling (scale 1, scale 2 or scale 3)\r
+ (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a \r
+ higher frequency than the normal mode for a given voltage scaling (scale 1, \r
+ scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and\r
+ disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow \r
+ the sequence described in Reference manual.\r
+ \r
+ (+) In Stop mode: the main regulator or low power regulator supplies a low power \r
+ voltage to the 1.2V domain, thus preserving the content of registers \r
+ and internal SRAM. 2 operating modes are available:\r
+ (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only \r
+ available when the main regulator or the low power regulator is used in Scale 3 or \r
+ low voltage mode.\r
+ (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only\r
+ available when the main regulator or the low power regulator is in low voltage mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Enable Backup regulator */\r
+ PWR->CSR1 |= PWR_CSR1_BRE;\r
+ \r
+ /* Workaround for the following hardware bug: */\r
+ /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r
+ PWR->CSR1 |= PWR_CSR1_EIWUP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is set */ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Disable Backup regulator */\r
+ PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);\r
+ \r
+ /* Workaround for the following hardware bug: */\r
+ /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r
+ PWR->CSR1 |= PWR_CSR1_EIWUP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is set */ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableFlashPowerDown(void)\r
+{\r
+ /* Enable the Flash Power Down */\r
+ PWR->CR1 |= PWR_CR1_FPDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableFlashPowerDown(void)\r
+{\r
+ /* Disable the Flash Power Down */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);\r
+}\r
+\r
+/**\r
+ * @brief Enables Main Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void)\r
+{\r
+ /* Enable Main regulator low voltage */\r
+ PWR->CR1 |= PWR_CR1_MRUDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables Main Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void)\r
+{ \r
+ /* Disable Main regulator low voltage */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);\r
+}\r
+\r
+/**\r
+ * @brief Enables Low Power Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void)\r
+{\r
+ /* Enable low power regulator */\r
+ PWR->CR1 |= PWR_CR1_LPUDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables Low Power Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void)\r
+{\r
+ /* Disable low power regulator */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);\r
+}\r
+\r
+/**\r
+ * @brief Activates the Over-Drive mode.\r
+ * @note This mode allows the CPU and the core logic to operate at a higher frequency\r
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
+ * critical tasks and when the system clock source is either HSI or HSE. \r
+ * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
+ * The peripheral clocks must be enabled once the Over-drive mode is activated. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable the Over-drive to extend the clock frequency to 216 MHz */\r
+ __HAL_PWR_OVERDRIVE_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Enable the Over-drive switch */\r
+ __HAL_PWR_OVERDRIVESWITCHING_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates the Over-Drive mode.\r
+ * @note This mode allows the CPU and the core logic to operate at a higher frequency\r
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
+ * critical tasks and when the system clock source is either HSI or HSE. \r
+ * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
+ * The peripheral clocks must be enabled once the Over-drive mode is activated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Disable the Over-drive switch */\r
+ __HAL_PWR_OVERDRIVESWITCHING_DISABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ /* Disable the Over-drive */\r
+ __HAL_PWR_OVERDRIVE_DISABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enters in Under-Drive STOP mode.\r
+ * \r
+ * @note This mode can be selected only when the Under-Drive is already active \r
+ * \r
+ * @note This mode is enabled only with STOP low power mode.\r
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r
+ * mode is only available when the main regulator or the low power regulator \r
+ * is in low voltage mode\r
+ * \r
+ * @note If the Under-drive mode was enabled, it is automatically disabled after \r
+ * exiting Stop mode. \r
+ * When the voltage regulator operates in Under-drive mode, an additional \r
+ * startup delay is induced when waking up from Stop mode.\r
+ * \r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * \r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * \r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced.\r
+ * \r
+ * @param Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode \r
+ * and Flash memory in power-down when the device is in Stop under-drive mode\r
+ * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode \r
+ * and Flash memory in power-down when the device is in Stop under-drive mode\r
+ * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tempreg = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+ \r
+ /* Enable Power ctrl clock */\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ /* Enable the Under-drive Mode ---------------------------------------------*/\r
+ /* Clear Under-drive flag */\r
+ __HAL_PWR_CLEAR_ODRUDR_FLAG();\r
+ \r
+ /* Enable the Under-drive */ \r
+ __HAL_PWR_UNDERDRIVE_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for UnderDrive mode is ready */\r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tempreg = PWR->CR1;\r
+ /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */\r
+ tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);\r
+ \r
+ /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */\r
+ tempreg |= Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR1 = tempreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_SLEEPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Returns Voltage Scaling Range.\r
+ * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or \r
+ * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1\r
+ */ \r
+uint32_t HAL_PWREx_GetVoltageRange(void)\r
+{\r
+ return (PWR->CR1 & PWR_CR1_VOS);\r
+}\r
+\r
+/**\r
+ * @brief Configures the main internal regulator output voltage.\r
+ * @param VoltageScaling: specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\r
+ * typical output voltage at 1.4 V, \r
+ * system frequency up to 216 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\r
+ * typical output voltage at 1.2 V, \r
+ * system frequency up to 180 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,\r
+ * typical output voltage at 1.00 V, \r
+ * system frequency up to 151 MHz.\r
+ * @note To update the system clock frequency(SYSCLK):\r
+ * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().\r
+ * - Call the HAL_RCC_OscConfig() to configure the PLL.\r
+ * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.\r
+ * - Set the new system clock frequency using the HAL_RCC_ClockConfig().\r
+ * @note The scale can be modified only when the HSI or HSE clock source is selected \r
+ * as system clock source, otherwise the API returns HAL_ERROR. \r
+ * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits\r
+ * value in the PWR_CR1 register are not taken in account.\r
+ * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.\r
+ * @note The new voltage scale is active only when the PLL is ON. \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));\r
+\r
+ /* Enable Power ctrl clock */\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\r
+ {\r
+ /* Disable the main PLL */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick(); \r
+ /* Wait till PLL is disabled */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set Range */\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);\r
+ \r
+ /* Enable the main PLL */\r
+ __HAL_RCC_PLL_ENABLE();\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_qspi.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief QSPI HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the QuadSPI interface (QSPI).\r
+ * + Initialization and de-initialization functions\r
+ * + Indirect functional mode management\r
+ * + Memory-mapped functional mode management\r
+ * + Auto-polling functional mode management\r
+ * + Interrupts and flags management\r
+ * + DMA channel configuration for indirect functional mode\r
+ * + Errors management and abort functionality\r
+ *\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ *** Initialization ***\r
+ ======================\r
+ [..]\r
+ (#) As prerequisite, fill in the HAL_QSPI_MspInit() :\r
+ (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().\r
+ (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().\r
+ (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
+ (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().\r
+ (++) If interrupt mode is used, enable and configure QuadSPI global\r
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+ (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel \r
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), \r
+ link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure \r
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+ (#) Configure the flash size, the clock prescaler, the fifo threshold, the\r
+ clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.\r
+\r
+ *** Indirect functional mode ***\r
+ ================================\r
+ [..]\r
+ (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() \r
+ functions :\r
+ (++) Instruction phase : the mode used and if present the instruction opcode.\r
+ (++) Address phase : the mode used and if present the size and the address value.\r
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate \r
+ bytes values.\r
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+ (++) Data phase : the mode used and if present the number of bytes.\r
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
+ if activated.\r
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+ (#) If no data is required for the command, it is sent directly to the memory :\r
+ (++) In polling mode, the output of the function is done when the transfer is complete.\r
+ (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.\r
+ (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or \r
+ HAL_QSPI_Transmit_IT() after the command configuration :\r
+ (++) In polling mode, the output of the function is done when the transfer is complete.\r
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r
+ is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
+ (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and \r
+ HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
+ (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or \r
+ HAL_QSPI_Receive_IT() after the command configuration :\r
+ (++) In polling mode, the output of the function is done when the transfer is complete.\r
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r
+ is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
+ (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and \r
+ HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
+\r
+ *** Auto-polling functional mode ***\r
+ ====================================\r
+ [..]\r
+ (#) Configure the command sequence and the auto-polling functional mode using the \r
+ HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :\r
+ (++) Instruction phase : the mode used and if present the instruction opcode.\r
+ (++) Address phase : the mode used and if present the size and the address value.\r
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate \r
+ bytes values.\r
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+ (++) Data phase : the mode used.\r
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
+ if activated.\r
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+ (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),\r
+ the polling interval and the automatic stop activation.\r
+ (#) After the configuration :\r
+ (++) In polling mode, the output of the function is done when the status match is reached. The\r
+ automatic stop is activated to avoid an infinite loop.\r
+ (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.\r
+\r
+ *** Memory-mapped functional mode ***\r
+ =====================================\r
+ [..]\r
+ (#) Configure the command sequence and the memory-mapped functional mode using the \r
+ HAL_QSPI_MemoryMapped() functions :\r
+ (++) Instruction phase : the mode used and if present the instruction opcode.\r
+ (++) Address phase : the mode used and the size.\r
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate \r
+ bytes values.\r
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+ (++) Data phase : the mode used.\r
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
+ if activated.\r
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+ (++) The timeout activation and the timeout period.\r
+ (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on \r
+ the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.\r
+\r
+ *** Errors management and abort functionality ***\r
+ ==================================================\r
+ [..]\r
+ (#) HAL_QSPI_GetError() function gives the error raised during the last operation.\r
+ (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and \r
+ flushes the fifo :\r
+ (++) In polling mode, the output of the function is done when the transfer \r
+ complete bit is set and the busy bit cleared.\r
+ (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when \r
+ the transfer complete bi is set.\r
+\r
+ *** Control functions ***\r
+ =========================\r
+ [..]\r
+ (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.\r
+ (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.\r
+ (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.\r
+ (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold \r
+\r
+ *** Workarounds linked to Silicon Limitation ***\r
+ ====================================================\r
+ [..]\r
+ (#) Workarounds Implemented inside HAL Driver\r
+ (++) Extra data written in the FIFO at the end of a read transfer\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup QSPI QSPI\r
+ * @brief HAL QSPI module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup QSPI_Private_Constants \r
+ * @{\r
+ */\r
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U) /*!<Indirect write mode*/\r
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/\r
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/\r
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/** @addtogroup QSPI_Private_Macros QSPI Private Macros\r
+ * @{\r
+ */\r
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \\r
+ ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \\r
+ ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \\r
+ ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup QSPI_Private_Functions QSPI Private Functions\r
+ * @{\r
+ */\r
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma); \r
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);\r
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to :\r
+ (+) Initialize the QuadSPI.\r
+ (+) De-initialize the QuadSPI.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the QSPI mode according to the specified parameters\r
+ * in the QSPI_InitTypeDef and creates the associated handle.\r
+ * @param hqspi: qspi handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Check the QSPI handle allocation */\r
+ if(hqspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));\r
+ assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));\r
+ assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));\r
+ assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));\r
+ assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));\r
+ assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));\r
+ assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));\r
+ assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));\r
+\r
+ if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )\r
+ {\r
+ assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r
+ }\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hqspi->Lock = HAL_UNLOCKED;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_QSPI_MspInit(hqspi);\r
+ \r
+ /* Configure the default timeout for the QSPI memory access */\r
+ HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);\r
+ }\r
+ \r
+ /* Configure QSPI FIFO Threshold */\r
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));\r
+\r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ \r
+ /* Configure QSPI Clock Prescaler and Sample Shift */\r
+ MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));\r
+ \r
+ /* Configure QSPI Flash Size, CS High Time and Clock Mode */\r
+ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), \r
+ ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));\r
+ \r
+ /* Enable the QSPI peripheral */\r
+ __HAL_QSPI_ENABLE(hqspi);\r
+ \r
+ /* Set QSPI error code to none */\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; \r
+\r
+ /* Initialize the QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the QSPI peripheral \r
+ * @param hqspi: qspi handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Check the QSPI handle allocation */\r
+ if(hqspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ /* Disable the QSPI Peripheral Clock */\r
+ __HAL_QSPI_DISABLE(hqspi);\r
+\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_QSPI_MspDeInit(hqspi);\r
+\r
+ /* Set QSPI error code to none */\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+ /* Initialize the QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief QSPI MSP Init\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_QSPI_MspInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief QSPI MSP DeInit\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_QSPI_MspDeInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions \r
+ * @brief QSPI Transmit/Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to :\r
+ (+) Handle the interrupts.\r
+ (+) Handle the command sequence.\r
+ (+) Transmit data in blocking, interrupt or DMA mode.\r
+ (+) Receive data in blocking, interrupt or DMA mode.\r
+ (+) Manage the auto-polling functional mode.\r
+ (+) Manage the memory-mapped functional mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles QSPI interrupt request.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None.\r
+ */\r
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ __IO uint32_t *data_reg;\r
+ uint32_t flag = READ_REG(hqspi->Instance->SR);\r
+ uint32_t itsource = READ_REG(hqspi->Instance->CR);\r
+\r
+ /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/\r
+ if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))\r
+ {\r
+ data_reg = &hqspi->Instance->DR;\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
+ {\r
+ /* Transmission process */\r
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r
+ {\r
+ if (hqspi->TxXferCount > 0)\r
+ {\r
+ /* Fill the FIFO until it is full */\r
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r
+ hqspi->TxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* No more data available for the transfer */\r
+ /* Disable the QSPI FIFO Threshold Interrupt */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
+ {\r
+ /* Receiving Process */\r
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r
+ {\r
+ if (hqspi->RxXferCount > 0)\r
+ {\r
+ /* Read the FIFO until it is empty */\r
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
+ hqspi->RxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* All data have been received for the transfer */\r
+ /* Disable the QSPI FIFO Threshold Interrupt */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* FIFO Threshold callback */\r
+ HAL_QSPI_FifoThresholdCallback(hqspi);\r
+ }\r
+\r
+ /* QSPI Transfer Complete interrupt occurred -------------------------------*/\r
+ else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);\r
+\r
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
+ \r
+ /* Transfer complete callback */\r
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
+ {\r
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r
+ {\r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ \r
+ /* Disable the DMA channel */\r
+ __HAL_DMA_DISABLE(hqspi->hdma);\r
+ }\r
+\r
+#if defined(QSPI1_V1_0)\r
+/* Clear Busy bit */\r
+ HAL_QSPI_Abort_IT(hqspi);\r
+#endif\r
+ \r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+ /* TX Complete callback */\r
+ HAL_QSPI_TxCpltCallback(hqspi);\r
+ }\r
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
+ {\r
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r
+ {\r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ \r
+ /* Disable the DMA channel */\r
+ __HAL_DMA_DISABLE(hqspi->hdma);\r
+ }\r
+ else\r
+ {\r
+ data_reg = &hqspi->Instance->DR;\r
+ while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)\r
+ {\r
+ if (hqspi->RxXferCount > 0)\r
+ {\r
+ /* Read the last data received in the FIFO until it is empty */\r
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
+ hqspi->RxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* All data have been received for the transfer */\r
+ break;\r
+ }\r
+ }\r
+ }\r
+#if defined(QSPI1_V1_0)\r
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
+ HAL_QSPI_Abort_IT(hqspi);\r
+#endif /* QSPI_V1_0*/ \r
+ \r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+ /* RX Complete callback */\r
+ HAL_QSPI_RxCpltCallback(hqspi);\r
+ }\r
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY)\r
+ {\r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+ /* Command Complete callback */\r
+ HAL_QSPI_CmdCpltCallback(hqspi);\r
+ }\r
+ else if(hqspi->State == HAL_QSPI_STATE_ABORT)\r
+ {\r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+ if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)\r
+ {\r
+ /* Abort called by the user */\r
+\r
+ /* Abort Complete callback */\r
+ HAL_QSPI_AbortCpltCallback(hqspi);\r
+ }\r
+ else \r
+ {\r
+ /* Abort due to an error (eg : DMA error) */\r
+\r
+ /* Error callback */\r
+ HAL_QSPI_ErrorCallback(hqspi);\r
+ }\r
+ }\r
+ }\r
+\r
+ /* QSPI Status Match interrupt occurred ------------------------------------*/\r
+ else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);\r
+ \r
+ /* Check if the automatic poll mode stop is activated */\r
+ if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)\r
+ {\r
+ /* Disable the QSPI Transfer Error and Status Match Interrupts */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r
+\r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+\r
+ /* Status match callback */\r
+ HAL_QSPI_StatusMatchCallback(hqspi);\r
+ }\r
+\r
+ /* QSPI Transfer Error interrupt occurred ----------------------------------*/\r
+ else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);\r
+ \r
+ /* Disable all the QSPI Interrupts */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
+\r
+ /* Set error code */\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;\r
+ \r
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r
+ {\r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ \r
+ /* Disable the DMA channel */\r
+ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r
+ HAL_DMA_Abort_IT(hqspi->hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ \r
+ /* Error callback */\r
+ HAL_QSPI_ErrorCallback(hqspi);\r
+ }\r
+ }\r
+\r
+ /* QSPI Timeout interrupt occurred -----------------------------------------*/\r
+ else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);\r
+ \r
+ /* Time out callback */\r
+ HAL_QSPI_TimeOutCallback(hqspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the command configuration. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd : structure that contains the command configuration information\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Indirect Read or Write Modes\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY; \r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Call the configuration function */\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ if (cmd->DataMode == QSPI_DATA_NONE)\r
+ {\r
+ /* When there is no data phase, the transfer start as soon as the configuration is done \r
+ so wait until TC flag is set to go back in idle state */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Sets the command configuration in interrupt mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd : structure that contains the command configuration information\r
+ * @note This function is used only in Indirect Read or Write Modes\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY; \r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ if (cmd->DataMode == QSPI_DATA_NONE)\r
+ {\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
+ }\r
+ \r
+ /* Call the configuration function */\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ if (cmd->DataMode == QSPI_DATA_NONE)\r
+ {\r
+ /* When there is no data phase, the transfer start as soon as the configuration is done \r
+ so activate TC and TE interrupts */\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Enable the QSPI Transfer Error Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);\r
+ }\r
+ else\r
+ {\r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in blocking mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Indirect Write Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+ if(pData != NULL )\r
+ {\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+ \r
+ /* Configure counters and size of the handle */\r
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pTxBuffPtr = pData;\r
+ \r
+ /* Configure QSPI: CCR register with functional as indirect write */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+\r
+ while(hqspi->TxXferCount > 0)\r
+ {\r
+ /* Wait until FT flag is set to send data */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);\r
+\r
+ if (status != HAL_OK)\r
+ { \r
+ break;\r
+ }\r
+\r
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r
+ hqspi->TxXferCount--;\r
+ }\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Wait until TC flag is set to go back in idle state */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ /* Clear Transfer Complete bit */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+#if defined(QSPI1_V1_0)\r
+ /* Clear Busy bit */\r
+ status = HAL_QSPI_Abort(hqspi);\r
+#endif /* QSPI_V1_0 */ \r
+ }\r
+ }\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ else\r
+ {\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY;\r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Indirect Read Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ if(pData != NULL )\r
+ {\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+ \r
+ /* Configure counters and size of the handle */\r
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pRxBuffPtr = pData;\r
+\r
+ /* Configure QSPI: CCR register with functional as indirect read */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+ /* Start the transfer by re-writing the address in AR register */\r
+ WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+ \r
+ while(hqspi->RxXferCount > 0)\r
+ {\r
+ /* Wait until FT or TC flag is set to read received data */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);\r
+\r
+ if (status != HAL_OK)\r
+ { \r
+ break;\r
+ }\r
+\r
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
+ hqspi->RxXferCount--;\r
+ }\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Wait until TC flag is set to go back in idle state */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ /* Clear Transfer Complete bit */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+#if defined(QSPI1_V1_0)\r
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
+ status = HAL_QSPI_Abort(hqspi);\r
+#endif /* QSPI_V1_0 */ \r
+ }\r
+ }\r
+\r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ else\r
+ {\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @note This function is used only in Indirect Write Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{ \r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ if(pData != NULL )\r
+ {\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+\r
+ /* Configure counters and size of the handle */\r
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pTxBuffPtr = pData;\r
+ \r
+ /* Configure QSPI: CCR register with functional as indirect write */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
+ \r
+ }\r
+ else\r
+ {\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in no-blocking mode with Interrupt\r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @note This function is used only in Indirect Read Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ if(pData != NULL )\r
+ {\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+ \r
+ /* Configure counters and size of the handle */\r
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pRxBuffPtr = pData;\r
+\r
+ /* Configure QSPI: CCR register with functional as indirect read */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+ /* Start the transfer by re-writing the address in AR register */\r
+ WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
+ }\r
+ else\r
+ {\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Sends an amount of data in non blocking mode with DMA. \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @note This function is used only in Indirect Write Mode\r
+ * @note If DMA peripheral access is configured as halfword, the number \r
+ * of data and the fifo threshold should be aligned on halfword\r
+ * @note If DMA peripheral access is configured as word, the number \r
+ * of data and the fifo threshold should be aligned on word\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t *tmp;\r
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ /* Clear the error code */ \r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ if(pData != NULL ) \r
+ {\r
+ /* Configure counters of the handle */\r
+ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r
+ {\r
+ hqspi->TxXferCount = data_size;\r
+ }\r
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r
+ {\r
+ if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))\r
+ {\r
+ /* The number of data or the fifo threshold is not aligned on halfword \r
+ => no transfer possible with DMA peripheral access configured as halfword */\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ else\r
+ {\r
+ hqspi->TxXferCount = (data_size >> 1);\r
+ }\r
+ }\r
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r
+ {\r
+ if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))\r
+ {\r
+ /* The number of data or the fifo threshold is not aligned on word \r
+ => no transfer possible with DMA peripheral access configured as word */\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ else\r
+ {\r
+ hqspi->TxXferCount = (data_size >> 2);\r
+ }\r
+ }\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r
+\r
+ /* Configure size and pointer of the handle */\r
+ hqspi->TxXferSize = hqspi->TxXferCount;\r
+ hqspi->pTxBuffPtr = pData;\r
+ \r
+ /* Configure QSPI: CCR register with functional mode as indirect write */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ /* Set the QSPI DMA transfer complete callback */\r
+ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;\r
+ \r
+ /* Set the QSPI DMA Half transfer complete callback */\r
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
+ \r
+ /* Clear the DMA abort callback */ \r
+ hqspi->hdma->XferAbortCallback = NULL;\r
+\r
+ /* Configure the direction of the DMA */\r
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;\r
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r
+\r
+ /* Enable the QSPI transmit DMA Channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Enable the QSPI transfer error Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r
+\r
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ \r
+ status = HAL_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+\r
+ return status;\r
+}\r
+ \r
+/**\r
+ * @brief Receives an amount of data in non blocking mode with DMA. \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer.\r
+ * @note This function is used only in Indirect Read Mode\r
+ * @note If DMA peripheral access is configured as halfword, the number \r
+ * of data and the fifo threshold should be aligned on halfword\r
+ * @note If DMA peripheral access is configured as word, the number \r
+ * of data and the fifo threshold should be aligned on word\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t *tmp;\r
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ if(pData != NULL ) \r
+ {\r
+ /* Configure counters of the handle */\r
+ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r
+ {\r
+ hqspi->RxXferCount = data_size;\r
+ }\r
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r
+ {\r
+ if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))\r
+ {\r
+ /* The number of data or the fifo threshold is not aligned on halfword \r
+ => no transfer possible with DMA peripheral access configured as halfword */\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ else\r
+ {\r
+ hqspi->RxXferCount = (data_size >> 1);\r
+ }\r
+ }\r
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r
+ {\r
+ if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))\r
+ {\r
+ /* The number of data or the fifo threshold is not aligned on word \r
+ => no transfer possible with DMA peripheral access configured as word */\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ else\r
+ {\r
+ hqspi->RxXferCount = (data_size >> 2);\r
+ }\r
+ }\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+ \r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r
+ \r
+ /* Configure size and pointer of the handle */\r
+ hqspi->RxXferSize = hqspi->RxXferCount;\r
+ hqspi->pRxBuffPtr = pData;\r
+ \r
+ /* Set the QSPI DMA transfer complete callback */\r
+ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;\r
+ \r
+ /* Set the QSPI DMA Half transfer complete callback */\r
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
+ \r
+ /* Clear the DMA abort callback */ \r
+ hqspi->hdma->XferAbortCallback = NULL;\r
+ \r
+ /* Configure the direction of the DMA */\r
+ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;\r
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r
+ \r
+ /* Enable the DMA Channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);\r
+ \r
+ /* Configure QSPI: CCR register with functional as indirect read */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+ \r
+ /* Start the transfer by re-writing the address in AR register */\r
+ WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Enable the QSPI transfer error Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r
+ \r
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+ status = HAL_ERROR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configure the QSPI Automatic Polling Mode in blocking mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information.\r
+ * @param cfg: structure that contains the polling configuration information.\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Automatic Polling Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+ \r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+ \r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+ \r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+ \r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+ \r
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ \r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Configure QSPI: PSMAR register with the status match value */\r
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
+ \r
+ /* Configure QSPI: PSMKR register with the status mask value */\r
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
+ \r
+ /* Configure QSPI: PIR register with the interval value */\r
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
+ \r
+ /* Configure QSPI: CR register with Match mode and Automatic stop enabled \r
+ (otherwise there will be an infinite loop in blocking mode) */\r
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r
+ (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));\r
+ \r
+ /* Call the configuration function */\r
+ cmd->NbData = cfg->StatusBytesSize;\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
+ \r
+ /* Wait until SM flag is set to go back in idle state */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Return function status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information.\r
+ * @param cfg: structure that contains the polling configuration information.\r
+ * @note This function is used only in Automatic Polling Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+ \r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+ \r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+ \r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+ \r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+ \r
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
+ assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Configure QSPI: PSMAR register with the status match value */\r
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
+ \r
+ /* Configure QSPI: PSMKR register with the status mask value */\r
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
+ \r
+ /* Configure QSPI: PIR register with the interval value */\r
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
+ \r
+ /* Configure QSPI: CR register with Match mode and Automatic stop mode */\r
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r
+ (cfg->MatchMode | cfg->AutomaticStop));\r
+ \r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);\r
+ \r
+ /* Call the configuration function */\r
+ cmd->NbData = cfg->StatusBytesSize;\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Enable the QSPI Transfer Error and status match Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Configure the Memory Mapped mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information.\r
+ * @param cfg: structure that contains the memory mapped configuration information.\r
+ * @note This function is used only in Memory mapped Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+ assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;\r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Configure QSPI: CR register with timeout counter enable */\r
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);\r
+\r
+ if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)\r
+ {\r
+ assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));\r
+ \r
+ /* Configure QSPI: LPTR register with the low-power timeout value */\r
+ WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);\r
+ \r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);\r
+\r
+ /* Enable the QSPI TimeOut Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);\r
+ }\r
+ \r
+ /* Call the configuration function */\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Return function status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Transfer Error callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Abort completed callback.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_QSPI_AbortCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Command completed callback.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_CmdCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief FIFO Threshold callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Status Match callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_StatusMatchCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Timeout callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hqspi);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_TimeOutCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions \r
+ * @brief QSPI control and State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control and State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to :\r
+ (+) Check in run-time the state of the driver. \r
+ (+) Check the error code set during last operation.\r
+ (+) Abort any operation.\r
+..... \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the QSPI handle state.\r
+ * @param hqspi: QSPI handle\r
+ * @retval HAL state\r
+ */\r
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Return QSPI handle state */\r
+ return hqspi->State;\r
+}\r
+\r
+/**\r
+* @brief Return the QSPI error code\r
+* @param hqspi: QSPI handle\r
+* @retval QSPI Error Code\r
+*/\r
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ return hqspi->ErrorCode;\r
+}\r
+\r
+/**\r
+* @brief Abort the current transmission\r
+* @param hqspi: QSPI handle\r
+* @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Check if the state is in one of the busy states */\r
+ if ((hqspi->State & 0x2) != 0)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r
+ {\r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ \r
+ /* Abort DMA channel */\r
+ status = HAL_DMA_Abort(hqspi->hdma);\r
+ if(status != HAL_OK)\r
+ {\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
+ }\r
+ } \r
+ \r
+ /* Configure QSPI: CR register with Abort request */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
+ \r
+ /* Wait until TC flag is set to go back in idle state */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Wait until BUSY flag is reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+ }\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+* @brief Abort the current transmission (non-blocking function)\r
+* @param hqspi: QSPI handle\r
+* @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check if the state is in one of the busy states */\r
+ if ((hqspi->State & 0x2) != 0)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_ABORT; \r
+ \r
+ /* Disable all interrupts */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));\r
+ \r
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r
+ {\r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ \r
+ /* Abort DMA channel */\r
+ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r
+ HAL_DMA_Abort_IT(hqspi->hdma);\r
+ } \r
+ else\r
+ {\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Enable the QSPI Transfer Complete Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+ \r
+ /* Configure QSPI: CR register with Abort request */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
+ }\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/** @brief Set QSPI timeout\r
+ * @param hqspi: QSPI handle.\r
+ * @param Timeout: Timeout for the QSPI memory access.\r
+ * @retval None\r
+ */\r
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)\r
+{\r
+ hqspi->Timeout = Timeout;\r
+}\r
+\r
+/** @brief Set QSPI Fifo threshold.\r
+ * @param hqspi: QSPI handle.\r
+ * @param Threshold: Threshold of the Fifo (value between 1 and 16).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ /* Synchronize init structure with new FIFO threshold value */\r
+ hqspi->Init.FifoThreshold = Threshold;\r
+ \r
+ /* Configure QSPI FIFO Threshold */\r
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, \r
+ ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/** @brief Get QSPI Fifo threshold.\r
+ * @param hqspi: QSPI handle.\r
+ * @retval Fifo threshold (value between 1 and 16)\r
+ */\r
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/**\r
+ * @brief DMA QSPI receive process complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hqspi->RxXferCount = 0;\r
+ \r
+ /* Enable the QSPI transfer complete Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI transmit process complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hqspi->TxXferCount = 0;\r
+ \r
+ /* Enable the QSPI transfer complete Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI receive process half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_QSPI_RxHalfCpltCallback(hqspi); \r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI transmit process half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_QSPI_TxHalfCpltCallback(hqspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI communication error callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* if DMA error is FIFO error ignore it */\r
+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)\r
+ {\r
+ hqspi->RxXferCount = 0;\r
+ hqspi->TxXferCount = 0;\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
+ \r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ \r
+ /* Abort the QSPI */\r
+ HAL_QSPI_Abort_IT(hqspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI abort complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ hqspi->RxXferCount = 0;\r
+ hqspi->TxXferCount = 0;\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_ABORT)\r
+ {\r
+ /* DMA Abort called by QSPI abort */\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Enable the QSPI Transfer Complete Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+ \r
+ /* Configure QSPI: CR register with Abort request */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
+ }\r
+ else\r
+ {\r
+ /* DMA Abort called due to a transfer error interrupt */\r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ \r
+ /* Error callback */\r
+ HAL_QSPI_ErrorCallback(hqspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Wait for a flag state until timeout.\r
+ * @param hqspi: QSPI handle\r
+ * @param Flag: Flag checked\r
+ * @param State: Value of the flag expected\r
+ * @param tickstart: Start tick value\r
+ * @param Timeout: Duration of the time out\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, \r
+ FlagStatus State, uint32_t tickstart, uint32_t Timeout)\r
+{\r
+ /* Wait until flag is in expected state */ \r
+ while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)\r
+ {\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))\r
+ {\r
+ hqspi->State = HAL_QSPI_STATE_ERROR;\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the communication registers.\r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information\r
+ * @param FunctionalMode: functional mode to configured\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode\r
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode\r
+ * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode\r
+ * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode\r
+ * @retval None\r
+ */\r
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)\r
+{\r
+ assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));\r
+\r
+ if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
+ {\r
+ /* Configure QSPI: DLR register with the number of data to read or write */\r
+ WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));\r
+ }\r
+ \r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ /* Configure QSPI: ABR register with alternate bytes value */\r
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
+\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with instruction, address and alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with instruction and alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r
+ cmd->Instruction | FunctionalMode));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with instruction and address ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r
+ cmd->Instruction | FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with only instruction ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | \r
+ FunctionalMode));\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ /* Configure QSPI: ABR register with alternate bytes value */\r
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
+\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with address and alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
+ cmd->InstructionMode | FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with only alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r
+ FunctionalMode));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with only address ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r
+ FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with only data phase ----*/\r
+ if (cmd->DataMode != QSPI_DATA_NONE)\r
+ {\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Reset and Clock Control (RCC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### RCC specific features #####\r
+ ==============================================================================\r
+ [..] \r
+ After reset the device is running from Internal High Speed oscillator \r
+ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache \r
+ and I-Cache are disabled, and all peripherals are off except internal\r
+ SRAM, Flash and JTAG.\r
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ all peripherals mapped on these busses are running at HSI speed.\r
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ (+) All GPIOs are in input floating state, except the JTAG pins which\r
+ are assigned to be used for debug purpose.\r
+ \r
+ [..] \r
+ Once the device started from reset, the user application has to: \r
+ (+) Configure the clock source to be used to drive the System clock\r
+ (if the application needs higher frequency/performance)\r
+ (+) Configure the System clock frequency and Flash settings \r
+ (+) Configure the AHB and APB busses prescalers\r
+ (+) Enable the clock for the peripheral(s) to be used\r
+ (+) Configure the clock source(s) for peripherals which clocks are not\r
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)\r
+\r
+ ##### RCC Limitations #####\r
+ ==============================================================================\r
+ [..] \r
+ A delay between an RCC peripheral clock enable and the effective peripheral \r
+ enabling should be taken into account in order to manage the peripheral read/write \r
+ from/to registers.\r
+ (+) This delay depends on the peripheral mapping.\r
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle \r
+ after the clock enable bit is set on the hardware register\r
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle \r
+ after the clock enable bit is set on the hardware register\r
+\r
+ [..] \r
+ Implemented Workaround:\r
+ (+) For AHB & APB peripherals, a dummy read to the peripheral register has been\r
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC RCC\r
+ * @brief RCC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+\r
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()\r
+#define MCO1_GPIO_PORT GPIOA\r
+#define MCO1_PIN GPIO_PIN_8\r
+\r
+#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()\r
+#define MCO2_GPIO_PORT GPIOC\r
+#define MCO2_PIN GPIO_PIN_9\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Variables RCC Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to configure the internal/external oscillators\r
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 \r
+ and APB2).\r
+\r
+ [..] Internal/external clock and PLL configuration\r
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+\r
+ (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
+\r
+ (#) PLL (clocked by HSI or HSE), featuring two different output clocks:\r
+ (++) The first output is used to generate the high speed system clock (up to 216 MHz)\r
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
+ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
+\r
+ (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()\r
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System \r
+ clock source), the System clock is automatically switched to HSI and an interrupt\r
+ is generated if enabled. The interrupt is linked to the Cortex-M7 NMI \r
+ (Non-Maskable Interrupt) exception vector. \r
+\r
+ (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\r
+ clock (through a configurable prescaler) on PA8 pin.\r
+\r
+ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\r
+ clock (through a configurable prescaler) on PC9 pin.\r
+\r
+ [..] System, AHB and APB busses clocks configuration \r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable \r
+ prescaler and used to clock the CPU, memory and peripherals mapped \r
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived \r
+ from AHB clock through configurable prescalers and used to clock \r
+ the peripherals mapped on these busses. You can use \r
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. \r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+ (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or\r
+ from an external clock mapped on the I2S_CKIN pin. \r
+ You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.\r
+ (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or\r
+ from an external clock mapped on the I2S_CKIN pin. \r
+ You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. \r
+ (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r
+ divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()\r
+ macros to configure this clock. \r
+ (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz\r
+ to work correctly, while the SDIO require a frequency equal or lower than\r
+ to 48. This clock is derived of the main PLL through PLLQ divider.\r
+ (+@) IWDG clock which is always the LSI clock.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * - HSI ON and used as system clock source\r
+ * - HSE, PLL and PLLI2S OFF\r
+ * - AHB, APB1 and APB2 prescaler set to 1.\r
+ * - CSS, MCO1 and MCO2 OFF\r
+ * - All interrupts disabled\r
+ * @note This function doesn't modify the configuration of the\r
+ * - Peripheral clocks \r
+ * - LSI, LSE and RTC clocks \r
+ * @retval None\r
+ */\r
+void HAL_RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); \r
+ \r
+ /* Reset CFGR register */\r
+ CLEAR_REG(RCC->CFGR);\r
+ \r
+ /* Reset HSEON, CSSON, PLLON, PLLI2S */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); \r
+ \r
+ /* Reset PLLCFGR register */\r
+ CLEAR_REG(RCC->PLLCFGR);\r
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U)); \r
+ \r
+ /* Reset PLLI2SCFGR register */\r
+ CLEAR_REG(RCC->PLLI2SCFGR);\r
+ SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);\r
+ \r
+ /* Reset HSEBYP bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
+ \r
+ /* Disable all interrupts */\r
+ CLEAR_REG(RCC->CIR);\r
+ \r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HSI_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the\r
+ * RCC_OscInitTypeDef.\r
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC Oscillators.\r
+ * @note The PLL is not disabled when used as system clock.\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
+ * supported by this function. User should request a transition to LSE Off\r
+ * first and then LSE On or LSE Bypass.\r
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this function. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
+ \r
+ /*------------------------------- HSE Configuration ------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
+ /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */\r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) \r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\r
+ {\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the new HSE configuration ---------------------------------------*/\r
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
+ \r
+ /* Check the HSE State */\r
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSE is bypassed or disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- HSI Configuration --------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
+ \r
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ \r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) \r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\r
+ {\r
+ /* When HSI is used as system clock it will not disabled */\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration is allowed */\r
+ else\r
+ {\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check the HSI State */\r
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r
+ {\r
+ /* Enable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ } \r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSI Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
+\r
+ /* Check the LSI State */\r
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r
+ {\r
+ /* Enable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_ENABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSE Configuration -------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
+ \r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+ \r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Set the new LSE configuration -----------------------------------------*/\r
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
+ /* Check the LSE State */\r
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ }\r
+ /*-------------------------------- PLL Configuration -----------------------*/\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r
+ {\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ { \r
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
+ \r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Configure the main PLL clock source, multiplication and division factors. */\r
+ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \\r
+ RCC_OscInitStruct->PLL.PLLM | \\r
+ (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \\r
+ (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \\r
+ (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));\r
+ /* Enable the main PLL. */\r
+ __HAL_RCC_PLL_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified \r
+ * parameters in the RCC_ClkInitStruct.\r
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC peripheral.\r
+ * @param FLatency: FLASH Latency, this parameter depend on device selected\r
+ * \r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency \r
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function\r
+ *\r
+ * @note The HSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * \r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready. \r
+ * You can use HAL_RCC_GetClockConfig() function to know which clock is\r
+ * currently used as system clock source.\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r
+ * (for more details refer to section above "Initialization/de-initialization functions")\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
+ assert_param(IS_FLASH_LATENCY(FLatency));\r
+\r
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY) \r
+ must be correctly programmed according to the frequency of the CPU clock \r
+ (HCLK) and the supply voltage of the device. */\r
+ \r
+ /* Increasing the CPU frequency */\r
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))\r
+ { \r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+ \r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /*-------------------------- HCLK Configuration --------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+ {\r
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+ }\r
+ \r
+ /*------------------------- SYSCLK Configuration ---------------------------*/ \r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
+ { \r
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
+ \r
+ /* HSE is selected as System Clock Source */\r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ /* Check the HSE ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* PLL is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ /* Check the PLL ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* HSI is selected as System Clock Source */\r
+ else\r
+ {\r
+ /* Check the HSI ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Decreasing the number of wait states because of lower CPU frequency */\r
+ if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))\r
+ {\r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+ \r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK1 Configuration ---------------------------*/ \r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
+ }\r
+ \r
+ /*-------------------------- PCLK2 Configuration ---------------------------*/ \r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));\r
+ }\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];\r
+ \r
+ /* Configure the source of time base considering new system clocks settings*/\r
+ HAL_InitTick (TICK_INT_PRIORITY);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief RCC clocks control functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks \r
+ frequencies.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).\r
+ * @note PA8/PC9 should be configured in alternate function mode.\r
+ * @param RCC_MCOx: specifies the output direction for the clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).\r
+ * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).\r
+ * @param RCC_MCOSource: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r
+ * @param RCC_MCODiv: specifies the MCOx prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock\r
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r
+ * @retval None\r
+ */\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCOx));\r
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
+ /* RCC_MCO1 */\r
+ if(RCC_MCOx == RCC_MCO1)\r
+ {\r
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
+ \r
+ /* MCO1 Clock Enable */\r
+ MCO1_CLK_ENABLE();\r
+ \r
+ /* Configure the MCO1 pin in alternate function mode */ \r
+ GPIO_InitStruct.Pin = MCO1_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r
+ \r
+ /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));\r
+ \r
+ /* MCO2 Clock Enable */\r
+ MCO2_CLK_ENABLE();\r
+ \r
+ /* Configure the MCO2 pin in alternate function mode */\r
+ GPIO_InitStruct.Pin = MCO2_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);\r
+ \r
+ /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to \r
+ * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. \r
+ * @retval None\r
+ */\r
+void HAL_RCC_EnableCSS(void)\r
+{\r
+ SET_BIT(RCC->CR, RCC_CR_CSSON);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Clock Security System.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_DisableCSS(void)\r
+{\r
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON);\r
+}\r
+\r
+/**\r
+ * @brief Returns the SYSCLK frequency\r
+ * \r
+ * @note The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors. \r
+ * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * @note The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @note This function can be used by the user application to compute the \r
+ * baudrate for the communication peripherals or configure other parameters.\r
+ * \r
+ * @note Each time SYSCLK changes, this function must be called to update the\r
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ * \r
+ * \r
+ * @retval SYSCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetSysClockFreq(void)\r
+{\r
+ uint32_t pllm = 0, pllvco = 0, pllp = 0;\r
+ uint32_t sysclockfreq = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ switch (RCC->CFGR & RCC_CFGR_SWS)\r
+ {\r
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */\r
+ {\r
+ sysclockfreq = HSI_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */\r
+ {\r
+ sysclockfreq = HSE_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */\r
+ {\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\r
+ SYSCLK = PLL_VCO / PLLP */\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); \r
+ }\r
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);\r
+ \r
+ sysclockfreq = pllvco/pllp;\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ sysclockfreq = HSI_VALUE;\r
+ break;\r
+ }\r
+ }\r
+ return sysclockfreq;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HCLK frequency \r
+ * @note Each time HCLK changes, this function must be called to update the\r
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect. \r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.\r
+ * @retval HCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetHCLKFreq(void)\r
+{\r
+ return SystemCoreClock;\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK1 frequency \r
+ * @note Each time PCLK1 changes, this function must be called to update the\r
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK1Freq(void)\r
+{ \r
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK2 frequency \r
+ * @note Each time PCLK2 changes, this function must be called to update the\r
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK2 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK2Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);\r
+} \r
+\r
+/**\r
+ * @brief Configures the RCC_OscInitStruct according to the internal \r
+ * RCC configuration registers.\r
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that \r
+ * will be configured.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ /* Set all possible values for the Oscillator type parameter ---------------*/\r
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r
+ \r
+ /* Get the HSE configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
+ }\r
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
+ }\r
+ \r
+ /* Get the HSI configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
+ }\r
+ \r
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));\r
+ \r
+ /* Get the LSE configuration -----------------------------------------------*/\r
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
+ }\r
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
+ }\r
+ \r
+ /* Get the LSI configuration -----------------------------------------------*/\r
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
+ }\r
+ \r
+ /* Get the PLL configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
+ }\r
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);\r
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));\r
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));\r
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));\r
+}\r
+\r
+/**\r
+ * @brief Configures the RCC_ClkInitStruct according to the internal \r
+ * RCC configuration registers.\r
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that \r
+ * will be configured.\r
+ * @param pFLatency: Pointer on the Flash Latency.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)\r
+{\r
+ /* Set all possible values for the Clock type parameter --------------------*/\r
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
+ \r
+ /* Get the SYSCLK configuration --------------------------------------------*/ \r
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r
+ \r
+ /* Get the HCLK configuration ----------------------------------------------*/ \r
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); \r
+ \r
+ /* Get the APB1 configuration ----------------------------------------------*/ \r
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); \r
+ \r
+ /* Get the APB2 configuration ----------------------------------------------*/ \r
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);\r
+ \r
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/ \r
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); \r
+}\r
+\r
+/**\r
+ * @brief This function handles the RCC CSS interrupt request.\r
+ * @note This API should be called under the NMI_Handler().\r
+ * @retval None\r
+ */\r
+void HAL_RCC_NMI_IRQHandler(void)\r
+{\r
+ /* Check RCC CSSF flag */\r
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
+ {\r
+ /* RCC Clock Security System interrupt user callback */\r
+ HAL_RCC_CSSCallback();\r
+\r
+ /* Clear RCC CSS pending bit */\r
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RCC Clock Security System interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_RCC_CSSCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RCC_CSSCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Extension RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities RCC extension peripheral:\r
+ * + Extended Peripheral Control functions\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx RCCEx\r
+ * @brief RCCEx HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Defines RCCEx Private Defines\r
+ * @{\r
+ */\r
+ \r
+#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */\r
+#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions \r
+ * @brief Extended Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks \r
+ frequencies.\r
+ [..] \r
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
+ select the RTC clock source; in this case the Backup domain will be reset in \r
+ order to modify the RTC Clock source, as consequence RTC registers (including \r
+ the backup registers) and RCC_BDCR register will be set to their reset values.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the RCC extended peripherals clocks according to the specified\r
+ * parameters in the RCC_PeriphCLKInitTypeDef.\r
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+ * contains the configuration information for the Extended Peripherals\r
+ * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).\r
+ * \r
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select \r
+ * the RTC clock source; in this case the Backup domain will be reset in \r
+ * order to modify the RTC Clock source, as consequence RTC registers (including \r
+ * the backup registers) are set to their reset values.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg0 = 0;\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t plli2sused = 0;\r
+ uint32_t pllsaiused = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
+ \r
+ /*----------------------------------- I2S configuration ----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));\r
+ \r
+ /* Configure I2S Clock source */\r
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);\r
+ \r
+ /* Enable the PLLI2S when it's used as clock source for I2S */\r
+ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1; \r
+ }\r
+ }\r
+ \r
+ /*------------------------------------ SAI1 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\r
+ \r
+ /* Configure SAI1 Clock source */\r
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1; \r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+ }\r
+ \r
+ /*------------------------------------ SAI2 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\r
+ \r
+ /* Configure SAI2 Clock source */\r
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r
+ \r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1; \r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+ }\r
+ \r
+ /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r
+ { \r
+ plli2sused = 1; \r
+ } \r
+ \r
+ /*------------------------------------ RTC configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\r
+ {\r
+ /* Check for RTC Parameters used to output RTCCLK */\r
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
+ \r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait for Backup domain Write protection disable */\r
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */\r
+ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);\r
+\r
+ if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\r
+ {\r
+ /* Store the content of BDCR register before the reset of Backup Domain */\r
+ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r
+\r
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
+ __HAL_RCC_BACKUPRESET_FORCE();\r
+ __HAL_RCC_BACKUPRESET_RELEASE();\r
+\r
+ /* Restore the Content of BDCR register */\r
+ RCC->BDCR = tmpreg0;\r
+\r
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r
+ }\r
+\r
+ /*------------------------------------ TIM configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r
+ \r
+ /* Configure Timer Prescaler */\r
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r
+ \r
+ /* Configure the I2C1 clock source */\r
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r
+ \r
+ /* Configure the I2C2 clock source */\r
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r
+ \r
+ /* Configure the I2C3 clock source */\r
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C4 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r
+ \r
+ /* Configure the I2C4 clock source */\r
+ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r
+ \r
+ /* Configure the USART1 clock source */\r
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r
+ \r
+ /* Configure the USART2 clock source */\r
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r
+ \r
+ /* Configure the USART3 clock source */\r
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART4 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r
+ \r
+ /* Configure the UART4 clock source */\r
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART5 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r
+ \r
+ /* Configure the UART5 clock source */\r
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART6 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));\r
+ \r
+ /* Configure the USART6 clock source */\r
+ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART7 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));\r
+ \r
+ /* Configure the UART7 clock source */\r
+ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART8 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));\r
+ \r
+ /* Configure the UART8 clock source */\r
+ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);\r
+ }\r
+ \r
+ /*--------------------------------------- CEC Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));\r
+ \r
+ /* Configure the CEC clock source */\r
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- CK48 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));\r
+ \r
+ /* Configure the CLK48 source */\r
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\r
+\r
+ /* Enable the PLLSAI when it's used as clock source for CK48 */\r
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+ }\r
+\r
+ /*-------------------------------------- LTDC Configuration -----------------------------------*/\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r
+ \r
+ /* Configure the LTPIM1 clock source */\r
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r
+ }\r
+ \r
+ /*------------------------------------- SDMMC1 Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r
+ \r
+ /* Configure the SDMMC1 clock source */\r
+ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r
+ }\r
+ \r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+ /*------------------------------------- SDMMC2 Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));\r
+ \r
+ /* Configure the SDMMC2 clock source */\r
+ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);\r
+ }\r
+ \r
+ /*------------------------------------- DFSDM1 Configuration -------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\r
+\r
+ /* Configure the DFSDM1 interface clock source */\r
+ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\r
+ }\r
+ \r
+ /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));\r
+\r
+ /* Configure the DFSDM interface clock source */\r
+ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);\r
+ } \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */\r
+ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\r
+ {\r
+ /* Disable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_DISABLE(); \r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLLI2S is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* check for common PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r
+ \r
+ /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ \r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+ \r
+ /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ }\r
+ \r
+ /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ \r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) \r
+ {\r
+ /* Check for PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+ /* Check for PLLI2S/DIVQ parameters */\r
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\r
+ \r
+ /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r
+ /* Configure the PLLI2S division factors */ \r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ \r
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); \r
+ } \r
+\r
+ /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ \r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r
+ \r
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r
+ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);\r
+ } \r
+ \r
+ /*----------------- In Case of PLLI2S is just selected -----------------*/ \r
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\r
+ {\r
+ /* Check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */\r
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ } \r
+ \r
+ /* Enable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_ENABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLI2S is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ } \r
+ \r
+ /*-------------------------------------- PLLSAI Configuration ---------------------------------*/\r
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */\r
+ if(pllsaiused == 1)\r
+ {\r
+ /* Disable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_DISABLE(); \r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is disabled */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ { \r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ /* Check the PLLSAI division factors */\r
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\r
+ \r
+ /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ \r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\r
+ {\r
+ /* check for PLLSAIQ Parameter */\r
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\r
+ /* check for PLLSAI/DIVQ Parameter */\r
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\r
+ \r
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ \r
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\r
+ } \r
+\r
+ /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ \r
+ /* In Case of PLLI2S is selected as source clock for CK48 */ \r
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\r
+ /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));\r
+ \r
+ /* Configure the PLLSAI division factors */\r
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */\r
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);\r
+ } \r
+\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+ /*---------------------------- LTDC configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\r
+ {\r
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));\r
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));\r
+ \r
+ /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r
+ \r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);\r
+ \r
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ \r
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\r
+ } \r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+ /* Enable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_ENABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is ready */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ { \r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal\r
+ * RCC configuration registers.\r
+ * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tempreg = 0;\r
+ \r
+ /* Set all possible values for the extended clock type parameter------------*/\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\\r
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\\r
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\\r
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\\r
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\\r
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\\r
+ RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\\r
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\\r
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\\r
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\\r
+ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\\r
+ RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO;\r
+#else \r
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\\r
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\\r
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\\r
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\\r
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\\r
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\\r
+ RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\\r
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\\r
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\\r
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\\r
+ RCC_PERIPHCLK_CLK48;\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+ \r
+ /* Get the PLLI2S Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));\r
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r
+ \r
+ /* Get the PLLSAI Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));\r
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); \r
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); \r
+ \r
+ /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/\r
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));\r
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));\r
+ PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));\r
+\r
+ /* Get the SAI1 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r
+ \r
+ /* Get the SAI2 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\r
+ \r
+ /* Get the I2S clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();\r
+ \r
+ /* Get the I2C1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r
+ \r
+ /* Get the I2C2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();\r
+ \r
+ /* Get the I2C3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();\r
+ \r
+ /* Get the I2C4 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();\r
+ \r
+ /* Get the USART1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();\r
+ \r
+ /* Get the USART2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();\r
+ \r
+ /* Get the USART3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();\r
+ \r
+ /* Get the UART4 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();\r
+ \r
+ /* Get the UART5 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();\r
+ \r
+ /* Get the USART6 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();\r
+ \r
+ /* Get the UART7 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();\r
+ \r
+ /* Get the UART8 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();\r
+ \r
+ /* Get the LPTIM1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r
+ \r
+ /* Get the CEC clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();\r
+ \r
+ /* Get the CK48 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\r
+\r
+ /* Get the SDMMC1 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();\r
+ \r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+ /* Get the SDMMC2 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();\r
+ \r
+ /* Get the DFSDM clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();\r
+ \r
+ /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+ /* Get the RTC Clock configuration -----------------------------------------------*/\r
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\r
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\r
+ \r
+ /* Get the TIM Prescaler configuration --------------------------------------------*/\r
+ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r
+ }\r
+ else\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..) \r
+ * @note Return 0 if peripheral clock identifier not managed by this API\r
+ * @param PeriphClk: Peripheral clock identifier\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock\r
+ * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock\r
+ * @retval Frequency in KHz\r
+ */\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* This variable is used to store the SAI clock frequency (value in Hz) */\r
+ uint32_t frequency = 0;\r
+ /* This variable is used to store the VCO Input (value in Hz) */\r
+ uint32_t vcoinput = 0;\r
+ /* This variable is used to store the SAI clock source */\r
+ uint32_t saiclocksource = 0;\r
+ \r
+ if (PeriphClk == RCC_PERIPHCLK_SAI1)\r
+ {\r
+ saiclocksource = RCC->DCKCFGR1; \r
+ saiclocksource &= RCC_DCKCFGR1_SAI1SEL;\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLLSAI is the clock source for SAI1 */ \r
+ {\r
+ /* Configure the PLLSAI division factor */\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ } \r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r
+ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r
+ frequency = frequency/(tmpreg); \r
+ break; \r
+ }\r
+ case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */\r
+ { \r
+ /* Configure the PLLI2S division factor */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+ \r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r
+ tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); \r
+ frequency = frequency/(tmpreg);\r
+ break;\r
+ }\r
+ case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break; \r
+ }\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+ case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/\r
+ {\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the main PLL Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* In Case the main PLL Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+ break; \r
+ }\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+ default :\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ \r
+ if (PeriphClk == RCC_PERIPHCLK_SAI2)\r
+ {\r
+ saiclocksource = RCC->DCKCFGR1; \r
+ saiclocksource &= RCC_DCKCFGR1_SAI2SEL;\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLLSAI is the clock source for SAI*/ \r
+ {\r
+ /* Configure the PLLSAI division factor */\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ } \r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r
+ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r
+ frequency = frequency/(tmpreg); \r
+ break; \r
+ }\r
+ case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */\r
+ { \r
+ /* Configure the PLLI2S division factor */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+ \r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r
+ tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); \r
+ frequency = frequency/(tmpreg);\r
+ break;\r
+ }\r
+ case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break; \r
+ }\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */\r
+ {\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the main PLL Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* In Case the main PLL Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+ break; \r
+ }\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+ default :\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ \r
+ return frequency;\r
+}\r
+\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+/**\r
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the\r
+ * RCC_OscInitTypeDef.\r
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC Oscillators.\r
+ * @note The PLL is not disabled when used as system clock.\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
+ * supported by this function. User should request a transition to LSE Off\r
+ * first and then LSE On or LSE Bypass.\r
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this function. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
+ \r
+ /*------------------------------- HSE Configuration ------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
+ /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */\r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) \r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\r
+ {\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the new HSE configuration ---------------------------------------*/\r
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
+ \r
+ /* Check the HSE State */\r
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSE is bypassed or disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- HSI Configuration --------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
+ \r
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ \r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) \r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\r
+ {\r
+ /* When HSI is used as system clock it will not disabled */\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration is allowed */\r
+ else\r
+ {\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check the HSI State */\r
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r
+ {\r
+ /* Enable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ } \r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSI Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
+\r
+ /* Check the LSI State */\r
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r
+ {\r
+ /* Enable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_ENABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSE Configuration -------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
+ \r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+ \r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+\r
+ /* Set the new LSE configuration -----------------------------------------*/\r
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
+ /* Check the LSE State */\r
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ }\r
+ /*-------------------------------- PLL Configuration -----------------------*/\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r
+ {\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ { \r
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r
+ \r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Configure the main PLL clock source, multiplication and division factors. */\r
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
+ RCC_OscInitStruct->PLL.PLLM,\r
+ RCC_OscInitStruct->PLL.PLLN,\r
+ RCC_OscInitStruct->PLL.PLLP,\r
+ RCC_OscInitStruct->PLL.PLLQ,\r
+ RCC_OscInitStruct->PLL.PLLR);\r
+ \r
+ /* Enable the main PLL. */\r
+ __HAL_RCC_PLL_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rng.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief RNG HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Random Number Generator (RNG) peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The RNG HAL driver can be used as follows:\r
+\r
+ (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro \r
+ in HAL_RNG_MspInit().\r
+ (#) Activate the RNG peripheral using HAL_RNG_Init() function.\r
+ (#) Wait until the 32 bit Random Number Generator contains a valid \r
+ random data using (polling/interrupt) mode. \r
+ (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RNG \r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup RNG_Private_Constants\r
+ * @{\r
+ */\r
+#define RNG_TIMEOUT_VALUE 2\r
+/**\r
+ * @}\r
+ */ \r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup RNG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RNG_Exported_Functions_Group1\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the RNG according to the specified parameters \r
+ in the RNG_InitTypeDef and create the associated handle\r
+ (+) DeInitialize the RNG peripheral\r
+ (+) Initialize the RNG MSP\r
+ (+) DeInitialize RNG MSP \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the RNG peripheral and creates the associated handle.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)\r
+{ \r
+ /* Check the RNG handle allocation */\r
+ if(hrng == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ __HAL_LOCK(hrng);\r
+ \r
+ if(hrng->State == HAL_RNG_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hrng->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware */\r
+ HAL_RNG_MspInit(hrng);\r
+ }\r
+ \r
+ /* Change RNG peripheral state */\r
+ hrng->State = HAL_RNG_STATE_BUSY;\r
+\r
+ /* Enable the RNG Peripheral */\r
+ __HAL_RNG_ENABLE(hrng);\r
+\r
+ /* Initialize the RNG state */\r
+ hrng->State = HAL_RNG_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RNG peripheral. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)\r
+{ \r
+ /* Check the RNG handle allocation */\r
+ if(hrng == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Disable the RNG Peripheral */\r
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);\r
+ \r
+ /* Clear RNG interrupt status flags */\r
+ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_RNG_MspDeInit(hrng);\r
+ \r
+ /* Update the RNG state */\r
+ hrng->State = HAL_RNG_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ /* Return the function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RNG MSP.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrng);\r
+ \r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_MspInit must be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RNG MSP.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrng);\r
+ \r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_MspDeInit must be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RNG_Exported_Functions_Group2\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Get the 32 bit Random number\r
+ (+) Get the 32 bit Random number with interrupt enabled\r
+ (+) Handle RNG interrupt request \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Generates a 32-bit random number.\r
+ * @note Each time the random number data is read the RNG_FLAG_DRDY flag \r
+ * is automatically cleared.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @param random32bit: pointer to generated random number variable if successful.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)\r
+{\r
+ uint32_t tickstart = 0; \r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hrng); \r
+ \r
+ /* Check RNG peripheral state */\r
+ if(hrng->State == HAL_RNG_STATE_READY)\r
+ {\r
+ /* Change RNG peripheral state */ \r
+ hrng->State = HAL_RNG_STATE_BUSY; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check if data register contains valid random data */\r
+ while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)\r
+ { \r
+ hrng->State = HAL_RNG_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Get a 32bit Random number */\r
+ hrng->RandomNumber = hrng->Instance->DR;\r
+ *random32bit = hrng->RandomNumber;\r
+ \r
+ hrng->State = HAL_RNG_STATE_READY;\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Generates a 32-bit random number in interrupt mode.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hrng);\r
+ \r
+ /* Check RNG peripheral state */\r
+ if(hrng->State == HAL_RNG_STATE_READY)\r
+ {\r
+ /* Change RNG peripheral state */ \r
+ hrng->State = HAL_RNG_STATE_BUSY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r
+ __HAL_RNG_ENABLE_IT(hrng);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ status = HAL_ERROR;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Handles RNG interrupt request.\r
+ * @note In the case of a clock error, the RNG is no more able to generate \r
+ * random numbers because the PLL48CLK clock is not correct. User has \r
+ * to check that the clock controller is correctly configured to provide\r
+ * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). \r
+ * The clock error has no impact on the previously generated \r
+ * random numbers, and the RNG_DR register contents can be used.\r
+ * @note In the case of a seed error, the generation of random numbers is \r
+ * interrupted as long as the SECS bit is '1'. If a number is \r
+ * available in the RNG_DR register, it must not be used because it may \r
+ * not have enough entropy. In this case, it is recommended to clear the \r
+ * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable \r
+ * the RNG peripheral to reinitialize and restart the RNG.\r
+ * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS\r
+ * or CEIS are set. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+\r
+ */\r
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* RNG clock error interrupt occurred */\r
+ if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))\r
+ { \r
+ /* Change RNG peripheral state */\r
+ hrng->State = HAL_RNG_STATE_ERROR;\r
+ \r
+ HAL_RNG_ErrorCallback(hrng);\r
+ \r
+ /* Clear the clock error flag */\r
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);\r
+ \r
+ }\r
+ \r
+ /* Check RNG data ready interrupt occurred */ \r
+ if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)\r
+ {\r
+ /* Generate random number once, so disable the IT */\r
+ __HAL_RNG_DISABLE_IT(hrng);\r
+ \r
+ /* Get the 32bit Random number (DRDY flag automatically cleared) */ \r
+ hrng->RandomNumber = hrng->Instance->DR;\r
+ \r
+ if(hrng->State != HAL_RNG_STATE_ERROR)\r
+ {\r
+ /* Change RNG peripheral state */\r
+ hrng->State = HAL_RNG_STATE_READY; \r
+ \r
+ /* Data Ready callback */ \r
+ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);\r
+ } \r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Returns generated random number in polling mode (Obsolete)\r
+ * Use HAL_RNG_GenerateRandomNumber() API instead.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval Random value\r
+ */\r
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)\r
+{\r
+ if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)\r
+ {\r
+ return hrng->RandomNumber; \r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),\r
+ * Use HAL_RNG_GenerateRandomNumber_IT() API instead.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval 32-bit random number\r
+ */\r
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)\r
+{\r
+ uint32_t random32bit = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hrng);\r
+ \r
+ /* Change RNG peripheral state */ \r
+ hrng->State = HAL_RNG_STATE_BUSY; \r
+ \r
+ /* Get a 32bit Random number */ \r
+ random32bit = hrng->Instance->DR;\r
+ \r
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r
+ __HAL_RNG_ENABLE_IT(hrng); \r
+ \r
+ /* Return the 32 bit random number */ \r
+ return random32bit;\r
+}\r
+\r
+/**\r
+ * @brief Read latest generated random number. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval random value\r
+ */\r
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)\r
+{\r
+ return(hrng->RandomNumber);\r
+}\r
+\r
+/**\r
+ * @brief Data Ready callback in non-blocking mode. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @param random32bit: generated random number.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrng);\r
+ \r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_ReadyDataCallback must be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief RNG error callbacks.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrng);\r
+ \r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_ErrorCallback must be implemented in the user file.\r
+ */\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ \r
+/** @addtogroup RNG_Exported_Functions_Group3\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Returns the RNG state.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL state\r
+ */\r
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)\r
+{\r
+ return hrng->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief RTC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Real Time Clock (RTC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + RTC Time and Date functions\r
+ * + RTC Alarm functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Backup Domain Operating Condition #####\r
+ ==============================================================================\r
+ [..] The real-time clock (RTC), the RTC backup registers, and the backup \r
+ SRAM (BKP SRAM) can be powered from the VBAT voltage when the main \r
+ VDD supply is powered off.\r
+ To retain the content of the RTC backup registers, backup SRAM, and supply \r
+ the RTC when VDD is turned off, VBAT pin can be connected to an optional \r
+ standby voltage supplied by a battery or by another source.\r
+\r
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned\r
+ off, the VBAT pin powers the following blocks:\r
+ (#) The RTC\r
+ (#) The LSE oscillator\r
+ (#) The backup SRAM when the low power backup regulator is enabled\r
+ (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)\r
+ \r
+ [..] When the backup domain is supplied by VDD (analog switch connected to VDD),\r
+ the following pins are available:\r
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins\r
+ (#) PC13 can be used as a GPIO or as the RTC_AF1 pin\r
+ (#) PI8 can be used as a GPIO or as the RTC_AF2 pin\r
+ \r
+ [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT \r
+ because VDD is not present), the following pins are available:\r
+ (#) PC14 and PC15 can be used as LSE pins only\r
+ (#) PC13 can be used as the RTC_AF1 pin \r
+ (#) PI8 can be used as the RTC_AF2 pin\r
+ (#) PC1 can be used as the RTC_AF3 pin\r
+ \r
+ ##### Backup Domain Reset #####\r
+ ==================================================================\r
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register \r
+ to their reset values. The BKPSRAM is not affected by this reset. The only\r
+ way to reset the BKPSRAM is through the Flash interface by requesting \r
+ a protection level change from 1 to 0.\r
+ [..] A backup domain reset is generated when one of the following events occurs:\r
+ (#) Software reset, triggered by setting the BDRST bit in the \r
+ RCC Backup domain control register (RCC_BDCR). \r
+ (#) VDD or VBAT power on, if both supplies have previously been powered off. \r
+\r
+ ##### Backup Domain Access #####\r
+ ==================================================================\r
+ [..] After reset, the backup domain (RTC registers, RTC backup data \r
+ registers and backup SRAM) is protected against possible unwanted write \r
+ accesses. \r
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __HAL_RCC_PWR_CLK_ENABLE() function.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+ (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.\r
+ (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.\r
+ \r
+ \r
+ ##### How to use this driver #####\r
+ ==================================================================\r
+ [..] \r
+ (+) Enable the RTC domain access (see description in the section above).\r
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r
+ format using the HAL_RTC_Init() function.\r
+ \r
+ *** Time and Date configuration ***\r
+ ===================================\r
+ [..] \r
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() \r
+ and HAL_RTC_SetDate() functions.\r
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. \r
+ \r
+ *** Alarm configuration ***\r
+ ===========================\r
+ [..]\r
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. \r
+ You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.\r
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.\r
+ \r
+ ##### RTC and low power modes #####\r
+ ==================================================================\r
+ [..] The MCU can be woken up from a low power mode by an RTC alternate \r
+ function.\r
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r
+ RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r
+ These RTC alternate functions can wake up the system from the Stop and \r
+ Standby low power modes.\r
+ [..] The system can also wake up from low power modes without depending \r
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r
+ or the RTC wakeup events.\r
+ [..] The RTC provides a programmable time base for waking up from the \r
+ Stop or Standby mode at regular intervals.\r
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock source\r
+ is LSE or LSI.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC RTC\r
+ * @brief RTC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Exported_Functions RTC Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RTC_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to initialize and configure the \r
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable \r
+ RTC registers Write protection, enter and exit the RTC initialization mode, \r
+ RTC registers synchronization check and reference clock detection enable.\r
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. \r
+ It is split into 2 programmable prescalers to minimize power consumption.\r
+ (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.\r
+ (++) When both prescalers are used, it is recommended to configure the \r
+ asynchronous prescaler to a high value to minimize power consumption.\r
+ (#) All RTC registers are Write protected. Writing to the RTC registers\r
+ is enabled by writing a key into the Write Protection register, RTC_WPR.\r
+ (#) To configure the RTC Calendar, user application should enter \r
+ initialization mode. In this mode, the calendar counter is stopped \r
+ and its value can be updated. When the initialization sequence is \r
+ complete, the calendar restarts counting after 4 RTCCLK cycles.\r
+ (#) To read the calendar through the shadow registers after Calendar \r
+ initialization, calendar update or after wakeup from low power modes \r
+ the software must first clear the RSF flag. The software must then \r
+ wait until it is set again before reading the calendar, which means \r
+ that the calendar registers have been correctly copied into the \r
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function \r
+ implements the above software sequence (RSF clear and RSF check).\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the RTC peripheral \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Check the RTC peripheral state */\r
+ if(hrtc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));\r
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));\r
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));\r
+ assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));\r
+ assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));\r
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));\r
+ \r
+ if(hrtc->State == HAL_RTC_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hrtc->Lock = HAL_UNLOCKED;\r
+ /* Initialize RTC MSP */\r
+ HAL_RTC_MspInit(hrtc);\r
+ }\r
+ \r
+ /* Set RTC state */ \r
+ hrtc->State = HAL_RTC_STATE_BUSY; \r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ { \r
+ /* Clear RTC_CR FMT, OSEL and POL Bits */\r
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));\r
+ /* Set RTC_CR register */\r
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);\r
+ \r
+ /* Configure the RTC PRER */\r
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);\r
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ \r
+ hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;\r
+ hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); \r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RTC peripheral \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @note This function doesn't reset the RTC Backup Data registers. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r
+\r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_BUSY; \r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Reset TR, DR and CR registers */\r
+ hrtc->Instance->TR = (uint32_t)0x00000000;\r
+ hrtc->Instance->DR = (uint32_t)0x00002101;\r
+ /* Reset All CR bits except CR[2:0] */\r
+ hrtc->Instance->CR &= (uint32_t)0x00000007;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till WUTWF flag is set and if Time out is reached exit */\r
+ while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Reset all RTC CR register bits */\r
+ hrtc->Instance->CR &= (uint32_t)0x00000000;\r
+ hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;\r
+ hrtc->Instance->PRER = (uint32_t)0x007F00FF;\r
+ hrtc->Instance->ALRMAR = (uint32_t)0x00000000;\r
+ hrtc->Instance->ALRMBR = (uint32_t)0x00000000;\r
+ hrtc->Instance->SHIFTR = (uint32_t)0x00000000;\r
+ hrtc->Instance->CALR = (uint32_t)0x00000000;\r
+ hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;\r
+ hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset ISR register and exit initialization mode */\r
+ hrtc->Instance->ISR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset Tamper and alternate functions configuration register */\r
+ hrtc->Instance->TAMPCR = 0x00000000;\r
+ \r
+ /* Reset Option register */\r
+ hrtc->Instance->OR = 0x00000000;\r
+ \r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* De-Initialize RTC MSP */\r
+ HAL_RTC_MspDeInit(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hrtc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RTC MSP.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RTC MSP.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group2 RTC Time and Date functions\r
+ * @brief RTC Time and Date functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC Time and Date functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure Time and Date features\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets RTC current time.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTime: Pointer to Time structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));\r
+ assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(sTime->Hours));\r
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sTime->TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(sTime->Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));\r
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));\r
+ \r
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \\r
+ (((uint32_t)sTime->TimeFormat) << 16)); \r
+ }\r
+ else\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sTime->Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); \r
+ } \r
+ else\r
+ {\r
+ sTime->TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));\r
+ tmpreg = (((uint32_t)(sTime->Hours) << 16) | \\r
+ ((uint32_t)(sTime->Minutes) << 8) | \\r
+ ((uint32_t)sTime->Seconds) | \\r
+ ((uint32_t)(sTime->TimeFormat) << 16)); \r
+ }\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_TR register */\r
+ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r
+ \r
+ /* Clear the bits to be configured */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;\r
+ \r
+ /* Configure the RTC_CR register */\r
+ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ \r
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(hrtc); \r
+ \r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets RTC current time.\r
+ * @param hrtc: RTC handle\r
+ * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned \r
+ * with input format (BIN or BCD), also SubSeconds field returning the\r
+ * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler\r
+ * factor to be used for second fraction ratio computation.\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FORMAT_BIN: Binary data format \r
+ * @arg RTC_FORMAT_BCD: BCD data format\r
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds\r
+ * value in second fraction ratio with time unit following generic formula:\r
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit\r
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS\r
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values \r
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.\r
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read\r
+ * to ensure consistency between the time and date values.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ \r
+ /* Get subseconds values from the correspondent registers*/\r
+ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);\r
+ \r
+ /* Get SecondFraction structure field from the corresponding register field*/\r
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);\r
+\r
+ /* Get the TR register */\r
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); \r
+ \r
+ /* Fill the structure fields with the read parameters */\r
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r
+ sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r
+ \r
+ /* Check the input parameters format */\r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ /* Convert the time structure parameters to Binary format */\r
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);\r
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);\r
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets RTC current date.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sDate: Pointer to date structure\r
+ * @param Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FORMAT_BIN: Binary data format \r
+ * @arg RTC_FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r
+{\r
+ uint32_t datetmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY; \r
+ \r
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))\r
+ {\r
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);\r
+ }\r
+ \r
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ { \r
+ assert_param(IS_RTC_YEAR(sDate->Year));\r
+ assert_param(IS_RTC_MONTH(sDate->Month));\r
+ assert_param(IS_RTC_DATE(sDate->Date)); \r
+ \r
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \\r
+ ((uint32_t)sDate->WeekDay << 13)); \r
+ }\r
+ else\r
+ { \r
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));\r
+ datetmpreg = RTC_Bcd2ToByte(sDate->Month);\r
+ assert_param(IS_RTC_MONTH(datetmpreg));\r
+ datetmpreg = RTC_Bcd2ToByte(sDate->Date);\r
+ assert_param(IS_RTC_DATE(datetmpreg));\r
+ \r
+ datetmpreg = ((((uint32_t)sDate->Year) << 16) | \\r
+ (((uint32_t)sDate->Month) << 8) | \\r
+ ((uint32_t)sDate->Date) | \\r
+ (((uint32_t)sDate->WeekDay) << 13)); \r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state*/\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_DR register */\r
+ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ \r
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY ;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets RTC current date.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sDate: Pointer to Date structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FORMAT_BIN: Binary data format \r
+ * @arg RTC_FORMAT_BCD: BCD data format\r
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values \r
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.\r
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r
+{\r
+ uint32_t datetmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ \r
+ /* Get the DR register */\r
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); \r
+\r
+ /* Fill the structure fields with the read parameters */\r
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));\r
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); \r
+\r
+ /* Check the input parameters format */\r
+ if(Format == RTC_FORMAT_BIN)\r
+ { \r
+ /* Convert the date structure parameters to Binary format */\r
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);\r
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);\r
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group3 RTC Alarm functions\r
+ * @brief RTC Alarm functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC Alarm functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure Alarm feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Sets the specified RTC Alarm.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sAlarm: Pointer to Alarm structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ \r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ else\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ } \r
+ \r
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ \r
+ /* Configure the Alarm A or Alarm B Sub Second registers */\r
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Configure the Alarm register */\r
+ if(sAlarm->Alarm == RTC_ALARM_A)\r
+ {\r
+ /* Disable the Alarm A interrupt */\r
+ __HAL_RTC_ALARMA_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm A Sub Second register */\r
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMA_ENABLE(hrtc);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Alarm B interrupt */\r
+ __HAL_RTC_ALARMB_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ } \r
+ \r
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm B Sub Second register */\r
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMB_ENABLE(hrtc); \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified RTC Alarm with Interrupt \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sAlarm: Pointer to Alarm structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @note The Alarm register can only be written when the corresponding Alarm\r
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()). \r
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ else\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ }\r
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ /* Configure the Alarm A or Alarm B Sub Second registers */\r
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Configure the Alarm register */\r
+ if(sAlarm->Alarm == RTC_ALARM_A)\r
+ {\r
+ /* Disable the Alarm A interrupt */\r
+ __HAL_RTC_ALARMA_DISABLE(hrtc);\r
+\r
+ /* Clear flag alarm A */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm A Sub Second register */\r
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMA_ENABLE(hrtc);\r
+ /* Configure the Alarm interrupt */\r
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Alarm B interrupt */\r
+ __HAL_RTC_ALARMB_DISABLE(hrtc);\r
+\r
+ /* Clear flag alarm B */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+\r
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm B Sub Second register */\r
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMB_ENABLE(hrtc);\r
+ /* Configure the Alarm interrupt */\r
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);\r
+ }\r
+\r
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();\r
+ \r
+ EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactive the specified RTC Alarm \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Alarm: Specifies the Alarm.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_ALARM_A: AlarmA\r
+ * @arg RTC_ALARM_B: AlarmB\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALARM(Alarm));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ if(Alarm == RTC_ALARM_A)\r
+ {\r
+ /* AlarmA */\r
+ __HAL_RTC_ALARMA_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* AlarmB */\r
+ __HAL_RTC_ALARMB_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc); \r
+ \r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief Gets the RTC Alarm value and masks.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sAlarm: Pointer to Date structure\r
+ * @param Alarm: Specifies the Alarm.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_ALARM_A: AlarmA\r
+ * @arg RTC_ALARM_B: AlarmB \r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FORMAT_BIN: Binary data format \r
+ * @arg RTC_FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)\r
+{\r
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_ALARM(Alarm));\r
+ \r
+ if(Alarm == RTC_ALARM_A)\r
+ {\r
+ /* AlarmA */\r
+ sAlarm->Alarm = RTC_ALARM_A;\r
+ \r
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);\r
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);\r
+ }\r
+ else\r
+ {\r
+ sAlarm->Alarm = RTC_ALARM_B;\r
+ \r
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);\r
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);\r
+ }\r
+ \r
+ /* Fill the structure with the read parameters */\r
+ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);\r
+ sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);\r
+ sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));\r
+ sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;\r
+ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);\r
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);\r
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ } \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles Alarm interrupt request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)\r
+{ \r
+ if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)\r
+ {\r
+ /* AlarmA callback */ \r
+ HAL_RTC_AlarmAEventCallback(hrtc);\r
+ \r
+ /* Clear the Alarm interrupt pending bit */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);\r
+ }\r
+ }\r
+ \r
+ if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)\r
+ {\r
+ /* AlarmB callback */ \r
+ HAL_RTCEx_AlarmBEventCallback(hrtc);\r
+ \r
+ /* Clear the Alarm interrupt pending bit */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);\r
+ }\r
+ }\r
+ \r
+ /* Clear the EXTI's line Flag for RTC Alarm */\r
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief Alarm A callback.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles AlarmA Polling request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Alarm interrupt pending bit */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group4 Peripheral Control functions \r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Wait for RTC Time and Date Synchronization\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r
+ * synchronized with RTC APB clock.\r
+ * @note The RTC Resynchronization mode is write protected, use the \r
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. \r
+ * @note To read the calendar through the shadow registers after Calendar \r
+ * initialization, calendar update or after wakeup from low power modes \r
+ * the software must first clear the RSF flag. \r
+ * The software must then wait until it is set again before reading \r
+ * the calendar, which means that the calendar registers have been \r
+ * correctly copied into the RTC_TR and RTC_DR shadow registers. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Clear RSF flag */\r
+ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the registers to be synchronised */\r
+ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTC_Group5 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Get RTC state\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Returns the RTC state.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL state\r
+ */\r
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)\r
+{\r
+ return hrtc->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Enters the RTC Initialization mode.\r
+ * @note The RTC Initialization mode is write protected, use the\r
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Check if the Initialization mode is set */\r
+ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ /* Set the Initialization mode */\r
+ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC is in INIT state and if Time out is reached exit */\r
+ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Converts a 2 digit decimal to BCD format.\r
+ * @param Value: Byte to be converted\r
+ * @retval Converted byte\r
+ */\r
+uint8_t RTC_ByteToBcd2(uint8_t Value)\r
+{\r
+ uint32_t bcdhigh = 0;\r
+ \r
+ while(Value >= 10)\r
+ {\r
+ bcdhigh++;\r
+ Value -= 10;\r
+ }\r
+ \r
+ return ((uint8_t)(bcdhigh << 4) | Value);\r
+}\r
+\r
+/**\r
+ * @brief Converts from 2 digit BCD to Binary.\r
+ * @param Value: BCD value to be converted\r
+ * @retval Converted word\r
+ */\r
+uint8_t RTC_Bcd2ToByte(uint8_t Value)\r
+{\r
+ uint32_t tmp = 0;\r
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r
+ return (tmp + (Value & (uint8_t)0x0F));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rtc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief RTC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Real Time Clock (RTC) Extension peripheral:\r
+ * + RTC Time Stamp functions\r
+ * + RTC Tamper functions \r
+ * + RTC Wake-up functions\r
+ * + Extension Control functions\r
+ * + Extension RTC features functions \r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (+) Enable the RTC domain access.\r
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r
+ format using the HAL_RTC_Init() function.\r
+ \r
+ *** RTC Wakeup configuration ***\r
+ ================================\r
+ [..] \r
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()\r
+ function. You can also configure the RTC Wakeup timer in interrupt mode \r
+ using the HAL_RTC_SetWakeUpTimer_IT() function.\r
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() \r
+ function.\r
+ \r
+ *** TimeStamp configuration ***\r
+ ===============================\r
+ [..]\r
+ (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.\r
+ You can also configure the RTC TimeStamp with interrupt mode using the\r
+ HAL_RTC_SetTimeStamp_IT() function.\r
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r
+ function.\r
+\r
+ *** Internal TimeStamp configuration ***\r
+ ===============================\r
+ [..]\r
+ (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function.\r
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r
+ function.\r
+ \r
+ *** Tamper configuration ***\r
+ ============================\r
+ [..]\r
+ (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge \r
+ or Level according to the Tamper filter (if equal to 0 Edge else Level) \r
+ value, sampling frequency, NoErase, MaskFlag, precharge or discharge and\r
+ Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper\r
+ with interrupt mode using HAL_RTC_SetTamper_IT() function.\r
+ (+) The default configuration of the Tamper erases the backup registers. To avoid\r
+ erase, enable the NoErase field on the RTC_TAMPCR register.\r
+ \r
+ *** Backup Data Registers configuration ***\r
+ ===========================================\r
+ [..]\r
+ (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()\r
+ function. \r
+ (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()\r
+ function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTCEx RTCEx \r
+ * @brief RTC Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions\r
+ * @{\r
+ */\r
+ \r
+\r
+/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions\r
+ * @brief RTC TimeStamp and Tamper functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC TimeStamp and Tamper functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure TimeStamp feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets TimeStamp.\r
+ * @note This API must be called before enabling the TimeStamp feature. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the \r
+ * rising edge of the related pin.\r
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. \r
+ * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+ \r
+ tmpreg|= TimeStampEdge;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r
+ hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); \r
+ \r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ hrtc->Instance->CR = (uint32_t)tmpreg;\r
+ \r
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets TimeStamp with Interrupt. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @note This API must be called before enabling the TimeStamp feature.\r
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the \r
+ * rising edge of the related pin.\r
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. \r
+ * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+ \r
+ tmpreg |= TimeStampEdge;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ hrtc->Instance->CR = (uint32_t)tmpreg;\r
+ \r
+ hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r
+ hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); \r
+ \r
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r
+ \r
+ /* Enable IT timestamp */ \r
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);\r
+ \r
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r
+ \r
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates TimeStamp. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);\r
+ \r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+ \r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ hrtc->Instance->CR = (uint32_t)tmpreg;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets Internal TimeStamp.\r
+ * @note This API must be called before enabling the internal TimeStamp feature.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hrtc);\r
+\r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Configure the internal Time Stamp Enable bits */\r
+ __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+\r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+\r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates internal TimeStamp.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hrtc);\r
+\r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Configure the internal Time Stamp Enable bits */\r
+ __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrtc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC TimeStamp value.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTimeStamp: Pointer to Time structure\r
+ * @param sTimeStampDate: Pointer to Date structure \r
+ * @param Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * FORMAT_BIN: Binary data format \r
+ * FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)\r
+{\r
+ uint32_t tmptime = 0, tmpdate = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+\r
+ /* Get the TimeStamp time and date registers values */\r
+ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);\r
+ tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Fill the Time structure fields with the read parameters */\r
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r
+ sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r
+ sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;\r
+ \r
+ /* Fill the Date structure fields with the read parameters */\r
+ sTimeStampDate->Year = 0;\r
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r
+\r
+ /* Check the input parameters format */\r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ /* Convert the TimeStamp structure parameters to Binary format */\r
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);\r
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);\r
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);\r
+ \r
+ /* Convert the DateTimeStamp structure parameters to Binary format */\r
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);\r
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);\r
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);\r
+ }\r
+ \r
+ /* Clear the TIMESTAMP Flag */\r
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets Tamper\r
+ * @note By calling this API we disable the tamper interrupt for all tampers. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTamper: Pointer to Tamper Structure.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r
+ assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); \r
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r
+ { \r
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); \r
+ } \r
+ \r
+ if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r
+ { \r
+ sTamper->NoErase = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r
+ }\r
+ }\r
+\r
+ if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r
+ {\r
+ sTamper->MaskFlag = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r
+ }\r
+ }\r
+ \r
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\\r
+ (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\r
+ (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r
+\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\r
+ (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\r
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r
+\r
+ hrtc->Instance->TAMPCR |= tmpreg; \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+\r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets Tamper with interrupt.\r
+ * @note By calling this API we force the tamper interrupt for all tampers.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTamper: Pointer to RTC Tamper.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r
+ assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));\r
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r
+ assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); \r
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Configure the tamper trigger */\r
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r
+ { \r
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); \r
+ } \r
+ \r
+ if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r
+ { \r
+ sTamper->NoErase = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r
+ }\r
+ }\r
+\r
+ if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r
+ {\r
+ sTamper->MaskFlag = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r
+ }\r
+ }\r
+ \r
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\\r
+ (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\r
+ (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r
+ \r
+ hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\r
+ (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\r
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r
+\r
+ hrtc->Instance->TAMPCR |= tmpreg;\r
+\r
+ /* RTC Tamper Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r
+\r
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates Tamper.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Tamper: Selected tamper pin.\r
+ * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)\r
+{\r
+ assert_param(IS_RTC_TAMPER(Tamper)); \r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+/* Disable the selected Tamper pin */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~Tamper;\r
+\r
+ if ((Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ /* Disable the Tamper1 interrupt */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1);\r
+ }\r
+ if ((Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ /* Disable the Tamper2 interrupt */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2);\r
+ }\r
+ if ((Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ /* Disable the Tamper2 interrupt */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3);\r
+ } \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief This function handles TimeStamp interrupt request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)\r
+{ \r
+ if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)\r
+ {\r
+ /* TIMESTAMP callback */ \r
+ HAL_RTCEx_TimeStampEventCallback(hrtc);\r
+\r
+ /* Clear the TIMESTAMP interrupt pending bit */\r
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);\r
+ }\r
+ }\r
+\r
+ /* Get the status of the Interrupt */\r
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)\r
+ {\r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\r
+ (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))\r
+ {\r
+ /* Tamper callback */\r
+ HAL_RTCEx_Tamper1EventCallback(hrtc);\r
+\r
+ /* Clear the Tamper interrupt pending bit */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r
+ }\r
+ }\r
+\r
+ /* Get the status of the Interrupt */\r
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)\r
+ {\r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\r
+ (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))\r
+ {\r
+ /* Tamper callback */\r
+ HAL_RTCEx_Tamper2EventCallback(hrtc);\r
+\r
+ /* Clear the Tamper interrupt pending bit */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);\r
+ }\r
+ }\r
+\r
+ /* Get the status of the Interrupt */\r
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)\r
+ {\r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\r
+ (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))\r
+ {\r
+ /* Tamper callback */\r
+ HAL_RTCEx_Tamper3EventCallback(hrtc);\r
+\r
+ /* Clear the Tamper interrupt pending bit */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);\r
+ }\r
+ }\r
+ \r
+ /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();\r
+\r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief TimeStamp callback. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_TimeStampEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tamper 1 callback. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_Tamper1EventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tamper 2 callback. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_Tamper2EventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tamper 3 callback. \r
+ * @param hrtc: RTC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles TimeStamp polling request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)\r
+ { \r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)\r
+ {\r
+ /* Clear the TIMESTAMP OverRun Flag */\r
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);\r
+ \r
+ /* Change TIMESTAMP state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR; \r
+ \r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief This function handles Tamper1 Polling.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Get the status of the Interrupt */\r
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Tamper Flag */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief This function handles Tamper2 Polling.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Get the status of the Interrupt */\r
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Tamper Flag */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles Tamper3 Polling.\r
+ * @param hrtc: RTC handle\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ /* Get the status of the Interrupt */\r
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Clear the Tamper Flag */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);\r
+\r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTCEx_Group2 RTC Wake-up functions\r
+ * @brief RTC Wake-up functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC Wake-up functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure Wake-up feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets wake up timer. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param WakeUpCounter: Wake up counter\r
+ * @param WakeUpClock: Wake up clock \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/\r
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)\r
+ {\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ \r
+ /* Clear the Wakeup Timer clock source bits in CR register */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
+ \r
+ /* Configure the clock source */\r
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r
+ \r
+ /* Configure the Wakeup Timer counter */\r
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r
+ \r
+ /* Enable the Wakeup Timer */\r
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); \r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets wake up timer with interrupt\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param WakeUpCounter: Wake up counter\r
+ * @param WakeUpClock: Wake up clock \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/\r
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)\r
+ {\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ \r
+ /* Configure the Wakeup Timer counter */\r
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r
+\r
+ /* Clear the Wakeup Timer clock source bits in CR register */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
+\r
+ /* Configure the clock source */\r
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r
+ \r
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();\r
+ \r
+ EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;\r
+ \r
+ /* Configure the Interrupt in the RTC_CR register */\r
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);\r
+ \r
+ /* Enable the Wakeup Timer */\r
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates wake up timer counter.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Disable the Wakeup Timer */\r
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets wake up timer counter.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval Counter value\r
+ */\r
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Get the counter value */\r
+ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); \r
+}\r
+\r
+/**\r
+ * @brief This function handles Wake Up Timer interrupt request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)\r
+{ \r
+ if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)\r
+ {\r
+ /* WAKEUPTIMER callback */ \r
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);\r
+ \r
+ /* Clear the WAKEUPTIMER interrupt pending bit */\r
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r
+ }\r
+ }\r
+ \r
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */\r
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief Wake Up Timer callback.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles Wake Up Timer Polling.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the WAKEUPTIMER Flag */\r
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RTCEx_Group3 Extension Peripheral Control functions \r
+ * @brief Extension Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extension Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Write a data in a specified RTC Backup data register\r
+ (+) Read a data in a specified RTC Backup data register\r
+ (+) Set the Coarse calibration parameters.\r
+ (+) Deactivate the Coarse calibration parameters\r
+ (+) Set the Smooth calibration parameters.\r
+ (+) Configure the Synchronization Shift Control Settings.\r
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ (+) Enable the RTC reference clock detection.\r
+ (+) Disable the RTC reference clock detection.\r
+ (+) Enable the Bypass Shadow feature.\r
+ (+) Disable the Bypass Shadow feature.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a data in a specified RTC Backup data register.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param BackupRegister: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register.\r
+ * @param Data: Data to be written in the specified RTC Backup data register. \r
+ * @retval None\r
+ */\r
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(BackupRegister));\r
+ \r
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r
+ tmp += (BackupRegister * 4);\r
+ \r
+ /* Write the specified register */\r
+ *(__IO uint32_t *)tmp = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified RTC Backup data Register.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param BackupRegister: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register. \r
+ * @retval Read value\r
+ */\r
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(BackupRegister));\r
+\r
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r
+ tmp += (BackupRegister * 4);\r
+ \r
+ /* Read the specified register */\r
+ return (*(__IO uint32_t *)tmp);\r
+}\r
+\r
+/**\r
+ * @brief Sets the Smooth calibration parameters.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param SmoothCalibPeriod: Select the Smooth Calibration Period.\r
+ * This parameter can be can be one of the following values :\r
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.\r
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.\r
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.\r
+ * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.\r
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.\r
+ * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.\r
+ * This parameter can be one any value from 0 to 0x000001FF.\r
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses \r
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field \r
+ * SmouthCalibMinusPulsesValue must be equal to 0. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* check if a calibration is pending*/\r
+ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* check if a calibration is pending*/\r
+ while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Configure the Smooth calibration settings */\r
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Synchronization Shift Control Settings.\r
+ * @note When REFCKON is set, firmware must not write to Shift control register. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.\r
+ * This parameter can be one of the following values :\r
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. \r
+ * @arg RTC_SHIFTADD1S_RESET: No effect.\r
+ * @param ShiftSubFS: Select the number of Second Fractions to substitute.\r
+ * This parameter can be one any value from 0 to 0x7FFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));\r
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));\r
+\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until the shift is completed*/\r
+ while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Check if the reference clock detection is disabled */\r
+ if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)\r
+ {\r
+ /* Configure the Shift settings */\r
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);\r
+ \r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param CalibOutput: Select the Calibration output Selection .\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. \r
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Clear flags before config */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;\r
+ \r
+ /* Configure the RTC_CR register */\r
+ hrtc->Instance->CR |= (uint32_t)CalibOutput;\r
+ \r
+ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the RTC reference clock detection.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state*/\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);\r
+\r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the RTC reference clock detection.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)\r
+{ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state*/\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Bypass Shadow feature.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @note When the Bypass Shadow is enabled the calendar value are taken \r
+ * directly from the Calendar counter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set the BYPSHAD bit */\r
+ hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Bypass Shadow feature.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @note When the Bypass Shadow is enabled the calendar value are taken \r
+ * directly from the Calendar counter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Reset the BYPSHAD bit */\r
+ hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup RTCEx_Group4 Extended features functions \r
+ * @brief Extended features functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) RTC Alram B callback\r
+ (+) RTC Poll for Alarm B request\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Alarm B callback.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hrtc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_AlarmBEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles AlarmB Polling request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Alarm Flag */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sai.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SAI HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Serial Audio Interface (SAI) peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+\r
+ [..]\r
+ The SAI HAL driver can be used as follows:\r
+\r
+ (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).\r
+ (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:\r
+ (##) Enable the SAI interface clock.\r
+ (##) SAI pins configuration:\r
+ (+++) Enable the clock for the SAI GPIOs.\r
+ (+++) Configure these SAI pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()\r
+ and HAL_SAI_Receive_IT() APIs):\r
+ (+++) Configure the SAI interrupt priority.\r
+ (+++) Enable the NVIC SAI IRQ handle.\r
+\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()\r
+ and HAL_SAI_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the\r
+ DMA Tx/Rx Stream.\r
+\r
+ (#) The initialization can be done by two ways\r
+ (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().\r
+ (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().\r
+\r
+ [..]\r
+ (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)\r
+ will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()\r
+ inside the transmit and receive process.\r
+ [..]\r
+ (@) Make sure that either:\r
+ (+@) I2S PLL is configured or\r
+ (+@) SAI PLL is configured or\r
+ (+@) External clock source is configured after setting correctly\r
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file.\r
+ [..]\r
+ (@) In master Tx mode: enabling the audio block immediately generates the bit clock\r
+ for the external slaves even if there is no data in the FIFO, However FS signal\r
+ generation is conditioned by the presence of data in the FIFO.\r
+\r
+ [..]\r
+ (@) In master Rx mode: enabling the audio block immediately generates the bit clock\r
+ and FS signal for the external slaves.\r
+\r
+ [..]\r
+ (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:\r
+ (+@) First bit Offset <= (SLOT size - Data size)\r
+ (+@) Data size <= SLOT size\r
+ (+@) Number of SLOT x SLOT size = Frame length\r
+ (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.\r
+\r
+ [..]\r
+ Three operation modes are available within this driver :\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()\r
+ (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()\r
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback()\r
+ (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()\r
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback()\r
+ (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback()\r
+\r
+ *** DMA mode IO operation ***\r
+ =============================\r
+ [..]\r
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()\r
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback()\r
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()\r
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback()\r
+ (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback()\r
+ (+) Pause the DMA Transfer using HAL_SAI_DMAPause()\r
+ (+) Resume the DMA Transfer using HAL_SAI_DMAResume()\r
+ (+) Stop the DMA Transfer using HAL_SAI_DMAStop()\r
+\r
+ *** SAI HAL driver additional function list ***\r
+ ===============================================\r
+ [..]\r
+ Below the list the others API available SAI HAL driver :\r
+\r
+ (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode\r
+ (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode\r
+ (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode\r
+ (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode\r
+ (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.\r
+ (+) HAL_SAI_Abort(): Abort the current transfer\r
+\r
+ *** SAI HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in SAI HAL driver :\r
+\r
+ (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral\r
+ (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral\r
+ (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts\r
+ (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts\r
+ (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is\r
+ enabled or disabled\r
+ (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SAI SAI\r
+ * @brief SAI HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+\r
+/** @defgroup SAI_Private_Typedefs SAI Private Typedefs\r
+ * @{\r
+ */\r
+typedef enum {\r
+ SAI_MODE_DMA,\r
+ SAI_MODE_IT\r
+}SAI_ModeTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @defgroup SAI_Private_Constants SAI Private Constants\r
+ * @{\r
+ */\r
+#define SAI_FIFO_SIZE 8\r
+#define SAI_DEFAULT_TIMEOUT 4 /* 4ms */\r
+#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/** @defgroup SAI_Private_Functions SAI Private Functions\r
+ * @{\r
+ */\r
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);\r
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);\r
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r
+\r
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);\r
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);\r
+\r
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SAI_Exported_Functions SAI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and\r
+ de-initialize the SAIx peripheral:\r
+\r
+ (+) User must implement HAL_SAI_MspInit() function in which he configures\r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_SAI_Init() to configure the selected device with\r
+ the selected configuration:\r
+ (++) Mode (Master/slave TX/RX)\r
+ (++) Protocol\r
+ (++) Data Size\r
+ (++) MCLK Output\r
+ (++) Audio frequency\r
+ (++) FIFO Threshold\r
+ (++) Frame Config\r
+ (++) Slot Config\r
+\r
+ (+) Call the function HAL_SAI_DeInit() to restore the default configuration\r
+ of the selected SAI peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the structure FrameInit, SlotInit and the low part of\r
+ * Init according to the specified parameters and call the function\r
+ * HAL_SAI_Init to initialize the SAI block.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param protocol: one of the supported protocol @ref SAI_Protocol\r
+ * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize\r
+ * the configuration information for SAI module.\r
+ * @param nbslot: Number of slot.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));\r
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));\r
+\r
+ switch(protocol)\r
+ {\r
+ case SAI_I2S_STANDARD :\r
+ case SAI_I2S_MSBJUSTIFIED :\r
+ case SAI_I2S_LSBJUSTIFIED :\r
+ status = SAI_InitI2S(hsai, protocol, datasize, nbslot);\r
+ break;\r
+ case SAI_PCM_LONG :\r
+ case SAI_PCM_SHORT :\r
+ status = SAI_InitPCM(hsai, protocol, datasize, nbslot);\r
+ break;\r
+ default :\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ status = HAL_SAI_Init(hsai);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the SAI according to the specified parameters.\r
+ * in the SAI_InitTypeDef structure and initialize the associated handle.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)\r
+{\r
+ uint32_t tmpregisterGCR = 0;\r
+ uint32_t ckstr_bits = 0;\r
+ uint32_t syncen_bits = 0;\r
+\r
+ /* Check the SAI handle allocation */\r
+ if(hsai == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* check the instance */\r
+ assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));\r
+ \r
+ /* Check the SAI Block parameters */\r
+ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));\r
+ assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));\r
+ assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));\r
+ assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));\r
+ assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));\r
+ assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));\r
+ assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));\r
+ assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));\r
+ assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));\r
+ assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));\r
+ assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));\r
+ assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));\r
+ assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));\r
+ assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));\r
+ \r
+ /* Check the SAI Block Frame parameters */\r
+ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));\r
+ assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));\r
+ assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));\r
+ assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));\r
+ assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));\r
+ \r
+ /* Check the SAI Block Slot parameters */\r
+ assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));\r
+ assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));\r
+ assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));\r
+ assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));\r
+ \r
+ if(hsai->State == HAL_SAI_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hsai->Lock = HAL_UNLOCKED;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_SAI_MspInit(hsai);\r
+ }\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY;\r
+ \r
+ /* Disable the selected SAI peripheral */\r
+ SAI_Disable(hsai);\r
+ \r
+ /* SAI Block Synchro Configuration -----------------------------------------*/\r
+ /* This setting must be done with both audio block (A & B) disabled */\r
+ switch(hsai->Init.SynchroExt)\r
+ {\r
+ case SAI_SYNCEXT_DISABLE :\r
+ tmpregisterGCR = 0;\r
+ break;\r
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :\r
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;\r
+ break;\r
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :\r
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ switch(hsai->Init.Synchro)\r
+ {\r
+ case SAI_ASYNCHRONOUS :\r
+ {\r
+ syncen_bits = 0;\r
+ }\r
+ break;\r
+ case SAI_SYNCHRONOUS :\r
+ {\r
+ syncen_bits = SAI_xCR1_SYNCEN_0;\r
+ }\r
+ break;\r
+ case SAI_SYNCHRONOUS_EXT_SAI1 :\r
+ {\r
+ syncen_bits = SAI_xCR1_SYNCEN_1;\r
+ }\r
+ break;\r
+ case SAI_SYNCHRONOUS_EXT_SAI2 :\r
+ {\r
+ syncen_bits = SAI_xCR1_SYNCEN_1;\r
+ tmpregisterGCR |= SAI_GCR_SYNCIN_0;\r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+\r
+ if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))\r
+ {\r
+ SAI1->GCR = tmpregisterGCR;\r
+ }\r
+ else \r
+ {\r
+ SAI2->GCR = tmpregisterGCR;\r
+ }\r
+\r
+ if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)\r
+ {\r
+ uint32_t freq = 0;\r
+ uint32_t tmpval;\r
+\r
+ if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B ))\r
+ {\r
+ freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);\r
+ }\r
+ if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B ))\r
+ {\r
+ freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);\r
+ }\r
+ \r
+ /* Configure Master Clock using the following formula :\r
+ MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS\r
+ FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256\r
+ MCKDIV[3:0] = SAI_CK_x / FS * 512 */\r
+ /* (freq x 10) to keep Significant digits */\r
+ tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256);\r
+ hsai->Init.Mckdiv = tmpval / 10;\r
+ \r
+ /* Round result to the nearest integer */\r
+ if((tmpval % 10) > 8)\r
+ {\r
+ hsai->Init.Mckdiv+= 1;\r
+ }\r
+ }\r
+ \r
+ /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */\r
+ if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r
+ { /* Transmit */\r
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR;\r
+ }\r
+ else\r
+ { /* Receive */\r
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0;\r
+ }\r
+ \r
+ /* SAI Block Configuration -------------------------------------------------*/\r
+ /* SAI CR1 Configuration */\r
+ hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \\r
+ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\\r
+ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \\r
+ SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);\r
+ \r
+ hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \\r
+ hsai->Init.DataSize | hsai->Init.FirstBit | \\r
+ ckstr_bits | syncen_bits | \\r
+ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \\r
+ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20));\r
+ \r
+ /* SAI CR2 Configuration */\r
+ hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);\r
+ hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);\r
+ \r
+ /* SAI Frame Configuration -----------------------------------------*/\r
+ hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \\r
+ SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));\r
+ hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) |\r
+ hsai->FrameInit.FSOffset |\r
+ hsai->FrameInit.FSDefinition |\r
+ hsai->FrameInit.FSPolarity |\r
+ ((hsai->FrameInit.ActiveFrameLength - 1) << 8));\r
+ \r
+ /* SAI Block_x SLOT Configuration ------------------------------------------*/\r
+ /* This register has no meaning in AC 97 and SPDIF audio protocol */\r
+ hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \\r
+ SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));\r
+ \r
+ hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize\r
+ | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8);\r
+ \r
+ /* Initialize the error code */\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ \r
+ /* Initialize the SAI state */\r
+ hsai->State= HAL_SAI_STATE_READY;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the SAI peripheral.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Check the SAI handle allocation */\r
+ if(hsai == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hsai->State = HAL_SAI_STATE_BUSY;\r
+\r
+ /* Disabled All interrupt and clear all the flag */\r
+ hsai->Instance->IMR = 0;\r
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;\r
+ \r
+ /* Disable the SAI */\r
+ SAI_Disable(hsai);\r
+\r
+ /* Flush the fifo */\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_SAI_MspDeInit(hsai);\r
+\r
+ /* Initialize the error code */\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+\r
+ /* Initialize the SAI state */\r
+ hsai->State = HAL_SAI_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the SAI MSP.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsai);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SAI_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the SAI MSP.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsai);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SAI_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the SAI data\r
+ transfers.\r
+\r
+ (+) There are two modes of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode.\r
+ The status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (++) No-Blocking mode : The communication is performed using Interrupts\r
+ or DMA. These functions return the status of the transfer startup.\r
+ The end of the data processing will be indicated through the\r
+ dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+\r
+ (+) Blocking mode functions are :\r
+ (++) HAL_SAI_Transmit()\r
+ (++) HAL_SAI_Receive()\r
+ (++) HAL_SAI_TransmitReceive()\r
+\r
+ (+) Non Blocking mode functions with Interrupt are :\r
+ (++) HAL_SAI_Transmit_IT()\r
+ (++) HAL_SAI_Receive_IT()\r
+ (++) HAL_SAI_TransmitReceive_IT()\r
+\r
+ (+) Non Blocking mode functions with DMA are :\r
+ (++) HAL_SAI_Transmit_DMA()\r
+ (++) HAL_SAI_Receive_DMA()\r
+ (++) HAL_SAI_TransmitReceive_DMA()\r
+\r
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+ (++) HAL_SAI_TxCpltCallback()\r
+ (++) HAL_SAI_RxCpltCallback()\r
+ (++) HAL_SAI_ErrorCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmit an amount of data in blocking mode.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ hsai->pBuffPtr = pData;\r
+ hsai->State = HAL_SAI_STATE_BUSY_TX;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+\r
+ /* Check if the SAI is already enabled */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* fill the fifo with data before to enabled the SAI */\r
+ SAI_FillFifo(hsai);\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+\r
+ while(hsai->XferCount > 0)\r
+ {\r
+ /* Write data if the FIFO is not full */\r
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)\r
+ {\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ hsai->Instance->DR = (*hsai->pBuffPtr++);\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 2;\r
+ }\r
+ else\r
+ {\r
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 4;\r
+ }\r
+ hsai->XferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Check for the Timeout */\r
+ if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout)))\r
+ {\r
+ /* Update error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r
+\r
+ /* Clear all the flags */\r
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;\r
+\r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+\r
+ /* Flush the fifo */\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r
+\r
+ /* Change the SAI state */\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ hsai->State = HAL_SAI_STATE_BUSY_RX;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+\r
+ /* Check if the SAI is already enabled */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+\r
+ /* Receive data */\r
+ while(hsai->XferCount > 0)\r
+ {\r
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)\r
+ {\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;\r
+ hsai->pBuffPtr+= 2;\r
+ }\r
+ else\r
+ {\r
+ *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;\r
+ hsai->pBuffPtr+= 4;\r
+ }\r
+ hsai->XferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Check for the Timeout */\r
+ if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout)))\r
+ {\r
+ /* Update error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r
+\r
+ /* Clear all the flags */\r
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;\r
+\r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+\r
+ /* Flush the fifo */\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r
+\r
+ /* Change the SAI state */\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ hsai->State = HAL_SAI_STATE_BUSY_TX;\r
+\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;\r
+ }\r
+ else\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;\r
+ }\r
+\r
+ /* Fill the fifo before starting the communication */\r
+ SAI_FillFifo(hsai);\r
+\r
+ /* Enable FRQ and OVRUDR interrupts */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+\r
+ /* Check if the SAI is already enabled */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ hsai->State = HAL_SAI_STATE_BUSY_RX;\r
+\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;\r
+ }\r
+ else\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;\r
+ }\r
+\r
+ /* Enable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+\r
+ /* Check if the SAI is already enabled */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pause the audio stream playing from the Media.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ /* Pause the audio file playing by disabling the SAI DMA requests */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the audio stream playing from the Media.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ /* Enable the SAI DMA requests */\r
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r
+\r
+ /* If the SAI peripheral is still not enabled, enable it */\r
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the audio stream playing from the Media.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ /* Disable the SAI DMA request */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+\r
+ /* Abort the SAI DMA Streams */\r
+ if(hsai->hdmatx != NULL)\r
+ {\r
+ if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ if(hsai->hdmarx != NULL)\r
+ {\r
+ if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort the current transfer and disable the SAI.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ /* Check SAI DMA is enabled or not */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)\r
+ {\r
+ /* Disable the SAI DMA request */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+ \r
+ /* Abort the SAI DMA Streams */\r
+ if(hsai->hdmatx != NULL)\r
+ {\r
+ if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ if(hsai->hdmarx != NULL)\r
+ {\r
+ if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+ /* Disabled All interrupt and clear all the flag */\r
+ hsai->Instance->IMR = 0;\r
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;\r
+\r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+\r
+ /* Flush the fifo */\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r
+\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with DMA.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ hsai->State = HAL_SAI_STATE_BUSY_TX;\r
+\r
+ /* Set the SAI Tx DMA Half transfer complete callback */\r
+ hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;\r
+\r
+ /* Set the SAI TxDMA transfer complete callback */\r
+ hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hsai->hdmatx->XferErrorCallback = SAI_DMAError;\r
+\r
+ /* Set the DMA Tx abort callback */\r
+ hsai->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the Tx DMA Stream */\r
+ if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)\r
+ {\r
+ __HAL_UNLOCK(hsai);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check if the SAI is already enabled */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+\r
+ /* Enable the interrupts for error handling */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+\r
+ /* Enable SAI Tx DMA Request */\r
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with DMA.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{\r
+\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+\r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ hsai->State = HAL_SAI_STATE_BUSY_RX;\r
+\r
+ /* Set the SAI Rx DMA Half transfer complete callback */\r
+ hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;\r
+\r
+ /* Set the SAI Rx DMA transfer complete callback */\r
+ hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hsai->hdmarx->XferErrorCallback = SAI_DMAError;\r
+\r
+ /* Set the DMA Rx abort callback */\r
+ hsai->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the Rx DMA Stream */\r
+ if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)\r
+ {\r
+ __HAL_UNLOCK(hsai);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check if the SAI is already enabled */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+\r
+ /* Enable the interrupts for error handling */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+\r
+ /* Enable SAI Rx DMA Request */\r
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the Tx mute mode.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param val: value sent during the mute @ref SAI_Block_Mute_Value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)\r
+{\r
+ assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));\r
+\r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Disable the Tx mute mode.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Enable the Rx mute detection.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param callback: function called when the mute is detected.\r
+ * @param counter: number a data before mute detection max 63.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)\r
+{\r
+ assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));\r
+\r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ /* set the mute counter */\r
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);\r
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));\r
+ hsai->mutecallback = callback;\r
+ /* enable the IT interrupt */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Disable the Rx mute detection.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ /* set the mutecallback to NULL */\r
+ hsai->mutecallback = (SAIcallback)NULL;\r
+ /* enable the IT interrupt */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Handle SAI interrupt request.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ uint32_t itflags = hsai->Instance->SR;\r
+ uint32_t itsources = hsai->Instance->IMR;\r
+ uint32_t cr1config = hsai->Instance->CR1; \r
+ uint32_t tmperror;\r
+\r
+ /* SAI Fifo request interrupt occured ------------------------------------*/\r
+ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))\r
+ {\r
+ hsai->InterruptServiceRoutine(hsai);\r
+ }\r
+ /* SAI Overrun error interrupt occurred ----------------------------------*/\r
+ else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))\r
+ {\r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+ /* Get the SAI error code */\r
+ tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR); \r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode |= tmperror;\r
+ /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ /* SAI mutedet interrupt occurred ----------------------------------*/\r
+ else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))\r
+ {\r
+ /* Clear the SAI mutedet flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);\r
+ /* call the call back function */\r
+ if(hsai->mutecallback != (SAIcallback)NULL)\r
+ {\r
+ /* inform the user that an RX mute event has been detected */\r
+ hsai->mutecallback();\r
+ }\r
+ }\r
+ /* SAI AFSDET interrupt occurred ----------------------------------*/\r
+ else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))\r
+ {\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;\r
+ /* Check SAI DMA is enabled or not */\r
+ if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)\r
+ {\r
+ /* Abort the SAI DMA Streams */\r
+ if(hsai->hdmatx != NULL)\r
+ {\r
+ /* Set the DMA Tx abort callback */\r
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;\r
+\r
+ /* Abort DMA in IT mode */\r
+ HAL_DMA_Abort_IT(hsai->hdmatx);\r
+ }\r
+ else if(hsai->hdmarx != NULL)\r
+ {\r
+ /* Set the DMA Rx abort callback */\r
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;\r
+ /* Abort DMA in IT mode */\r
+ HAL_DMA_Abort_IT(hsai->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Abort SAI */ \r
+ HAL_SAI_Abort(hsai);\r
+ \r
+ /* Set error callback */\r
+ HAL_SAI_ErrorCallback(hsai); \r
+ }\r
+ }\r
+ /* SAI LFSDET interrupt occurred ----------------------------------*/\r
+ else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))\r
+ {\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;\r
+\r
+ /* Check SAI DMA is enabled or not */\r
+ if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)\r
+ {\r
+ /* Abort the SAI DMA Streams */\r
+ if(hsai->hdmatx != NULL)\r
+ {\r
+ /* Set the DMA Tx abort callback */\r
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; \r
+ /* Abort DMA in IT mode */\r
+ HAL_DMA_Abort_IT(hsai->hdmatx);\r
+ }\r
+ else if(hsai->hdmarx != NULL)\r
+ {\r
+ /* Set the DMA Rx abort callback */\r
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; \r
+ /* Abort DMA in IT mode */ \r
+ HAL_DMA_Abort_IT(hsai->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Abort SAI */ \r
+ HAL_SAI_Abort(hsai);\r
+ \r
+ /* Set error callback */\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ }\r
+ /* SAI WCKCFG interrupt occurred ----------------------------------*/\r
+ else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))\r
+ {\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;\r
+\r
+ /* Abort the SAI DMA Streams */\r
+ if(hsai->hdmatx != NULL)\r
+ {\r
+ /* Set the DMA Tx abort callback */\r
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; \r
+ /* Abort DMA in IT mode */\r
+ HAL_DMA_Abort_IT(hsai->hdmatx);\r
+ }\r
+ else if(hsai->hdmarx != NULL)\r
+ {\r
+ /* Set the DMA Rx abort callback */\r
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; \r
+ /* Abort DMA in IT mode */ \r
+ HAL_DMA_Abort_IT(hsai->hdmarx);\r
+ }\r
+ else\r
+ {\r
+ /* If WCKCFG occurs, SAI audio block is automatically disabled */\r
+ /* Disable all interrupts and clear all flags */\r
+ hsai->Instance->IMR = 0U;\r
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;\r
+ /* Set the SAI state to ready to be able to start again the process */\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Initialize XferCount */\r
+ hsai->XferCount = 0U;\r
+\r
+ /* SAI error Callback */\r
+ HAL_SAI_ErrorCallback(hsai); \r
+ }\r
+ }\r
+ /* SAI CNRDY interrupt occurred ----------------------------------*/\r
+ else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))\r
+ {\r
+ /* Clear the SAI CNRDY flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;\r
+ /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callback.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsai);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SAI_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer Half completed callback.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsai);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SAI_TxHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callback.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsai);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SAI_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer half completed callback.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsai);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SAI_RxHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SAI error callback.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsai);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SAI_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the SAI handle state.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL state\r
+ */\r
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)\r
+{\r
+ return hsai->State;\r
+}\r
+\r
+/**\r
+* @brief Return the SAI error code.\r
+* @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SAI Block.\r
+* @retval SAI Error Code\r
+*/\r
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)\r
+{\r
+ return hsai->ErrorCode;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SAI_Private_Functions\r
+ * @brief Private functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the SAI I2S protocol according to the specified parameters\r
+ * in the SAI_InitTypeDef and create the associated handle.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param protocol: one of the supported protocol.\r
+ * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize\r
+ * the configuration information for SAI module.\r
+ * @param nbslot: number of slot minimum value is 2 and max is 16. \r
+ * the value must be a multiple of 2.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r
+{\r
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;\r
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;\r
+ /* Compute ClockStrobing according AudioMode */\r
+ if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r
+ { /* Transmit */\r
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;\r
+ }\r
+ else\r
+ { /* Receive */\r
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;\r
+ }\r
+ hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;\r
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;\r
+ hsai->SlotInit.FirstBitOffset = 0;\r
+ hsai->SlotInit.SlotNumber = nbslot;\r
+\r
+ /* in IS2 the number of slot must be even */\r
+ if((nbslot & 0x1) != 0 )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ switch(protocol)\r
+ {\r
+ case SAI_I2S_STANDARD :\r
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;\r
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;\r
+ break;\r
+ case SAI_I2S_MSBJUSTIFIED :\r
+ case SAI_I2S_LSBJUSTIFIED :\r
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;\r
+ hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Frame definition */\r
+ switch(datasize)\r
+ {\r
+ case SAI_PROTOCOL_DATASIZE_16BIT:\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ hsai->FrameInit.FrameLength = 32*(nbslot/2);\r
+ hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;\r
+ break;\r
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ hsai->FrameInit.FrameLength = 64*(nbslot/2);\r
+ hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ case SAI_PROTOCOL_DATASIZE_24BIT:\r
+ hsai->Init.DataSize = SAI_DATASIZE_24;\r
+ hsai->FrameInit.FrameLength = 64*(nbslot/2);\r
+ hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ case SAI_PROTOCOL_DATASIZE_32BIT:\r
+ hsai->Init.DataSize = SAI_DATASIZE_32;\r
+ hsai->FrameInit.FrameLength = 64*(nbslot/2);\r
+ hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+ if(protocol == SAI_I2S_LSBJUSTIFIED)\r
+ {\r
+ if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)\r
+ {\r
+ hsai->SlotInit.FirstBitOffset = 16;\r
+ }\r
+ if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)\r
+ {\r
+ hsai->SlotInit.FirstBitOffset = 8;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the SAI PCM protocol according to the specified parameters\r
+ * in the SAI_InitTypeDef and create the associated handle.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param protocol: one of the supported protocol\r
+ * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize\r
+ * @param nbslot: number of slot minimum value is 1 and the max is 16.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r
+{\r
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;\r
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;\r
+ /* Compute ClockStrobing according AudioMode */\r
+ if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r
+ { /* Transmit */\r
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;\r
+ }\r
+ else\r
+ { /* Receive */\r
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;\r
+ }\r
+ hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME;\r
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;\r
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;\r
+ hsai->SlotInit.FirstBitOffset = 0;\r
+ hsai->SlotInit.SlotNumber = nbslot;\r
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;\r
+\r
+ switch(protocol)\r
+ {\r
+ case SAI_PCM_SHORT :\r
+ hsai->FrameInit.ActiveFrameLength = 1;\r
+ break;\r
+ case SAI_PCM_LONG :\r
+ hsai->FrameInit.ActiveFrameLength = 13;\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ switch(datasize)\r
+ {\r
+ case SAI_PROTOCOL_DATASIZE_16BIT:\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ hsai->FrameInit.FrameLength = 16 * nbslot;\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;\r
+ break;\r
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ hsai->FrameInit.FrameLength = 32 * nbslot;\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ case SAI_PROTOCOL_DATASIZE_24BIT :\r
+ hsai->Init.DataSize = SAI_DATASIZE_24;\r
+ hsai->FrameInit.FrameLength = 32 * nbslot;\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ case SAI_PROTOCOL_DATASIZE_32BIT:\r
+ hsai->Init.DataSize = SAI_DATASIZE_32;\r
+ hsai->FrameInit.FrameLength = 32 * nbslot;\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Fill the fifo.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* fill the fifo with data before to enabled the SAI */\r
+ while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))\r
+ {\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ hsai->Instance->DR = (*hsai->pBuffPtr++);\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 2;\r
+ }\r
+ else\r
+ {\r
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 4;\r
+ }\r
+ hsai->XferCount--;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the interrupt flag to set according the SAI setup.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param mode: SAI_MODE_DMA or SAI_MODE_IT\r
+ * @retval the list of the IT flag to enable\r
+ */\r
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)\r
+{\r
+ uint32_t tmpIT = SAI_IT_OVRUDR;\r
+ \r
+ if(mode == SAI_MODE_IT)\r
+ {\r
+ tmpIT|= SAI_IT_FREQ;\r
+ }\r
+\r
+ if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&\r
+ ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))\r
+ {\r
+ tmpIT|= SAI_IT_CNRDY;\r
+ }\r
+\r
+ if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r
+ {\r
+ tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;\r
+ }\r
+ else\r
+ {\r
+ /* hsai has been configured in master mode */\r
+ tmpIT|= SAI_IT_WCKCFG;\r
+ }\r
+ return tmpIT;\r
+}\r
+\r
+/**\r
+ * @brief Disable the SAI and wait for the disabling.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)\r
+{\r
+ register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000);\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Disable the SAI instance */\r
+ __HAL_SAI_DISABLE(hsai);\r
+\r
+ do \r
+ {\r
+ /* Check for the Timeout */\r
+ if (count-- == 0)\r
+ { \r
+ /* Update error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r
+ status = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Handle the end of the transmission */\r
+ /* Disable FREQ and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+ }\r
+ else\r
+ {\r
+ /* Write data on DR register */\r
+ hsai->Instance->DR = (*hsai->pBuffPtr++);\r
+ hsai->XferCount--;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Handle the end of the transmission */\r
+ /* Disable FREQ and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+ }\r
+ else\r
+ {\r
+ /* Write data on DR register */\r
+ hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;\r
+ hsai->pBuffPtr+=2;\r
+ hsai->XferCount--;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Handle the end of the transmission */\r
+ /* Disable FREQ and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+ }\r
+ else\r
+ {\r
+ /* Write data on DR register */\r
+ hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;\r
+ hsai->pBuffPtr+=4;\r
+ hsai->XferCount--;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Receive data */\r
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;\r
+ hsai->XferCount--;\r
+\r
+ /* Check end of the transfer */\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Disable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+\r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_RxCpltCallback(hsai);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Receive data */\r
+ *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;\r
+ hsai->pBuffPtr+=2;\r
+ hsai->XferCount--;\r
+\r
+ /* Check end of the transfer */\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Disable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+\r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_RxCpltCallback(hsai);\r
+ }\r
+}\r
+/**\r
+ * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Receive data */\r
+ *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;\r
+ hsai->pBuffPtr+=4;\r
+ hsai->XferCount--;\r
+\r
+ /* Check end of the transfer */\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Disable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ \r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_RxCpltCallback(hsai);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI transmit process complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ hsai->XferCount = 0;\r
+ \r
+ /* Disable SAI Tx DMA Request */\r
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);\r
+\r
+ /* Stop the interrupts error handling */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+ \r
+ hsai->State= HAL_SAI_STATE_READY;\r
+ }\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI transmit process half complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_SAI_TxHalfCpltCallback(hsai);\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI receive process complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable Rx DMA Request */\r
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);\r
+ hsai->XferCount = 0;\r
+\r
+ /* Stop the interrupts error handling */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ }\r
+ HAL_SAI_RxCpltCallback(hsai);\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI receive process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_SAI_RxHalfCpltCallback(hsai);\r
+}\r
+/**\r
+ * @brief DMA SAI communication error callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* Set SAI error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;\r
+\r
+ if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE))\r
+ {\r
+ /* Disable the SAI DMA request */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+\r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+ \r
+ /* Set the SAI state ready to be able to start again the process */\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+\r
+ /* Initialize XferCount */\r
+ hsai->XferCount = 0U;\r
+ }\r
+ /* SAI error Callback */ \r
+ HAL_SAI_ErrorCallback(hsai);\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI Abort callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) \r
+{\r
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable DMA request */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+\r
+ /* Disable all interrupts and clear all flags */\r
+ hsai->Instance->IMR = 0U;\r
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;\r
+ \r
+ if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)\r
+ {\r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+\r
+ /* Flush the fifo */\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r
+ }\r
+ /* Set the SAI state to ready to be able to start again the process */\r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ \r
+ /* Initialize XferCount */\r
+ hsai->XferCount = 0U; \r
+\r
+ /* SAI error Callback */ \r
+ HAL_SAI_ErrorCallback(hsai);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sai_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief Empty file; This file is no longer used to set synchronization and\r
+ * to get SAI block frequency. Its content is now moved to common files\r
+ * (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7\r
+ * family. It's just kept for compatibility reasons.\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sd.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SD card HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Secure Digital (SD) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ This driver implements a high level communication layer for read and write from/to \r
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by \r
+ the user in HAL_SD_MspInit() function (MSP layer). \r
+ Basically, the MSP layer configuration should be the same as we provide in the \r
+ examples.\r
+ You can easily tailor this configuration according to hardware resources.\r
+\r
+ [..]\r
+ This driver is a generic layered driver for SDMMC memories which uses the HAL \r
+ SDMMC driver functions to interface with SD and uSD cards devices. \r
+ It is used as follows:\r
+ \r
+ (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:\r
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); \r
+ (##) SDMMC pins configuration for SD card\r
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); \r
+ (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()\r
+ and according to your pin assignment;\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()\r
+ and HAL_SD_WriteBlocks_DMA() APIs).\r
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); \r
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. \r
+ (##) NVIC configuration if you need to use interrupt process when using DMA transfer.\r
+ (+++) Configure the SDMMC and DMA interrupt priorities using functions\r
+ HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority\r
+ (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()\r
+ (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT() \r
+ and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.\r
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()\r
+ and __HAL_SD_SDMMC_CLEAR_IT()\r
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization \r
+\r
+ \r
+ *** SD Card Initialization and configuration ***\r
+ ================================================ \r
+ [..]\r
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes \r
+ the SD Card and put it into StandBy State (Ready for data transfer). \r
+ This function provide the following operations:\r
+ \r
+ (#) Apply the SD Card initialization process at 400KHz and check the SD Card \r
+ type (Standard Capacity or High Capacity). You can change or adapt this \r
+ frequency by adjusting the "ClockDiv" field. \r
+ The SD Card frequency (SDMMC_CK) is computed as follows:\r
+ \r
+ SDMMC_CK = SDMMCCLK / (ClockDiv + 2)\r
+ \r
+ In initialization mode and according to the SD Card standard, \r
+ make sure that the SDMMC_CK frequency doesn't exceed 400KHz.\r
+ \r
+ (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo \r
+ structure. This structure provide also ready computed SD Card capacity \r
+ and Block size.\r
+ \r
+ -@- These information are stored in SD handle structure in case of future use. \r
+ \r
+ (#) Configure the SD Card Data transfer frequency. By Default, the card transfer \r
+ frequency is set to 24MHz. You can change or adapt this frequency by adjusting \r
+ the "ClockDiv" field.\r
+ In transfer mode and according to the SD Card standard, make sure that the \r
+ SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.\r
+ To be able to use a frequency higher than 24MHz, you should use the SDMMC \r
+ peripheral in bypass mode. Refer to the corresponding reference manual \r
+ for more details.\r
+ \r
+ (#) Select the corresponding SD Card according to the address read with the step 2.\r
+ \r
+ (#) Configure the SD Card in wide bus mode: 4-bits data.\r
+ \r
+ *** SD Card Read operation ***\r
+ ==============================\r
+ [..] \r
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). \r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 bytes).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+\r
+ (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().\r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 bytes).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+ After this, you have to call the function HAL_SD_CheckReadOperation(), to insure\r
+ that the read transfer is done correctly in both DMA and SD sides.\r
+ \r
+ *** SD Card Write operation ***\r
+ =============================== \r
+ [..] \r
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). \r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 bytes).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+\r
+ (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().\r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 byte).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+ After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure\r
+ that the write transfer is done correctly in both DMA and SD sides. \r
+ \r
+ *** SD card status ***\r
+ ====================== \r
+ [..]\r
+ (+) At any time, you can check the SD Card status and get the SD card state \r
+ by using the HAL_SD_GetStatus() function. This function checks first if the \r
+ SD card is still connected and then get the internal SD Card transfer state. \r
+ (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() \r
+ function. \r
+\r
+ *** SD HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in SD HAL driver.\r
+ \r
+ (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device\r
+ (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device\r
+ (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer\r
+ (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer\r
+ (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt\r
+ (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt\r
+ (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not\r
+ (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags\r
+ \r
+ (@) You can refer to the SD HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SD \r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup SD_Private_Defines\r
+ * @{\r
+ */\r
+/** \r
+ * @brief SDMMC Data block size \r
+ */ \r
+#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))\r
+/** \r
+ * @brief SDMMC Static flags, Timeout, FIFO Address \r
+ */\r
+#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\\r
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\\r
+ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\\r
+ SDMMC_FLAG_DBCKEND)) \r
+\r
+#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000U)\r
+\r
+/** \r
+ * @brief Mask for errors Card Status R1 (OCR Register) \r
+ */\r
+#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)\r
+#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)\r
+#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)\r
+#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)\r
+#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)\r
+#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)\r
+#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)\r
+#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)\r
+#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)\r
+#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)\r
+#define SD_OCR_CC_ERROR ((uint32_t)0x00100000U)\r
+#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)\r
+#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)\r
+#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)\r
+#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)\r
+#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)\r
+#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)\r
+#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000U)\r
+#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)\r
+#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)\r
+\r
+/** \r
+ * @brief Masks for R6 Response \r
+ */\r
+#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)\r
+#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)\r
+#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)\r
+\r
+#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)\r
+#define SD_HIGH_CAPACITY ((uint32_t)0x40000000U)\r
+#define SD_STD_CAPACITY ((uint32_t)0x00000000U)\r
+#define SD_CHECK_PATTERN ((uint32_t)0x000001AAU)\r
+\r
+#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)\r
+#define SD_ALLZERO ((uint32_t)0x00000000U)\r
+\r
+#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)\r
+#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)\r
+#define SD_CARD_LOCKED ((uint32_t)0x02000000U)\r
+\r
+#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)\r
+#define SD_0TO7BITS ((uint32_t)0x000000FFU)\r
+#define SD_8TO15BITS ((uint32_t)0x0000FF00U)\r
+#define SD_16TO23BITS ((uint32_t)0x00FF0000U)\r
+#define SD_24TO31BITS ((uint32_t)0xFF000000U)\r
+#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)\r
+\r
+#define SD_HALFFIFO ((uint32_t)0x00000008U)\r
+#define SD_HALFFIFOBYTES ((uint32_t)0x00000020U)\r
+\r
+/** \r
+ * @brief Command Class Supported \r
+ */\r
+#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080U)\r
+#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040U)\r
+#define SD_CCCC_ERASE ((uint32_t)0x00000020U)\r
+\r
+/** \r
+ * @brief Following commands are SD Card Specific commands.\r
+ * SDMMC_APP_CMD should be sent before sending these commands. \r
+ */\r
+#define SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Functions SD Private Functions\r
+ * @{\r
+ */\r
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);\r
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); \r
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);\r
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);\r
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);\r
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);\r
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); \r
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);\r
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);\r
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);\r
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SD_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group1\r
+ * @brief Initialization and de-initialization functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize the SD\r
+ card device to be ready for use.\r
+ \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SD card according to the specified parameters in the \r
+ SD_HandleTypeDef and create the associated handle.\r
+ * @param hsd: SD handle\r
+ * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information \r
+ * @retval HAL SD error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)\r
+{ \r
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SD_InitTypeDef tmpinit;\r
+ \r
+ /* Allocate lock resource and initialize it */\r
+ hsd->Lock = HAL_UNLOCKED;\r
+ \r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SD_MspInit(hsd);\r
+ \r
+ /* Default SDMMC peripheral configuration for SD card initialization */\r
+ tmpinit.ClockEdge = SDMMC_CLOCK_EDGE_RISING;\r
+ tmpinit.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE;\r
+ tmpinit.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;\r
+ tmpinit.BusWide = SDMMC_BUS_WIDE_1B;\r
+ tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;\r
+ tmpinit.ClockDiv = SDMMC_INIT_CLK_DIV;\r
+ \r
+ /* Initialize SDMMC peripheral interface with default configuration */\r
+ SDMMC_Init(hsd->Instance, tmpinit);\r
+ \r
+ /* Identify card operating voltage */\r
+ errorstate = SD_PowerON(hsd); \r
+ \r
+ if(errorstate != SD_OK) \r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Initialize the present SDMMC card(s) and put them in idle state */\r
+ errorstate = SD_Initialize_Cards(hsd);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Read CSD/CID MSD registers */\r
+ errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);\r
+ \r
+ if (errorstate == SD_OK)\r
+ {\r
+ /* Select the Card */\r
+ errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));\r
+ }\r
+ \r
+ /* Configure SDMMC peripheral interface */\r
+ SDMMC_Init(hsd->Instance, hsd->Init); \r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the SD card.\r
+ * @param hsd: SD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)\r
+{\r
+ \r
+ /* Set SD power state to off */ \r
+ SD_PowerOFF(hsd);\r
+ \r
+ /* De-Initialize the MSP layer */\r
+ HAL_SD_MspDeInit(hsd);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the SD MSP.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief De-Initialize SD MSP.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group2\r
+ * @brief Data transfer functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the data \r
+ transfer from/to SD card.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads block(s) from a specified address in a card. The Data transfer \r
+ * is managed by polling mode. \r
+ * @param hsd: SD handle\r
+ * @param pReadBuffer: pointer to the buffer that will contain the received data\r
+ * @param ReadAddr: Address from where data is to be read \r
+ * @param BlockSize: SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of SD blocks to read \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ ReadAddr /= 512;\r
+ }\r
+ \r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t) BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */\r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize;\r
+ sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Send CMD18 READ_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD17 READ_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; \r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Read block(s) in polling mode */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Poll on SDMMC flags */\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ /* Read data from SDMMC Rx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ }\r
+ } \r
+ }\r
+ else\r
+ {\r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); \r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ } \r
+ \r
+ /* In case of single block transfer, no need of stop transfer at all */\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ /* Read data from SDMMC Rx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Send stop transmission command in case of multiblock read */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))\r
+ { \r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\\r
+ (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send stop transmission command */\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ }\r
+ \r
+ /* Get error state */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ count = SD_DATATIMEOUT;\r
+ \r
+ /* Empty FIFO if there is still any data */\r
+ while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r
+ {\r
+ *tempbuff = SDMMC_ReadFIFO(hsd->Instance);\r
+ tempbuff++;\r
+ count--;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Allows to write block(s) to a specified address in a card. The Data\r
+ * transfer is managed by polling mode. \r
+ * @param hsd: SD handle\r
+ * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit\r
+ * @param WriteAddr: Address from where data is to be written \r
+ * @param BlockSize: SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of SD blocks to write \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;\r
+ uint32_t *tempbuff = (uint32_t *)pWriteBuffer;\r
+ uint8_t cardstate = 0;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ WriteAddr /= 512;\r
+ }\r
+ \r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Send CMD25 WRITE_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD24 WRITE_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;\r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);\r
+ } \r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Set total number of bytes to write */\r
+ totalnumberofbytes = NumberOfBlocks * BlockSize;\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Write block(s) in polling mode */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))\r
+ {\r
+ if ((totalnumberofbytes - bytestransferred) < 32)\r
+ {\r
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);\r
+ \r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < restwords; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, tempbuff);\r
+ tempbuff++;\r
+ bytestransferred += 4;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ bytestransferred += 32;\r
+ }\r
+ }\r
+ } \r
+ }\r
+ else\r
+ {\r
+ /* In case of single data block transfer no need of stop command at all */ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))\r
+ {\r
+ if ((totalnumberofbytes - bytestransferred) < 32)\r
+ {\r
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);\r
+ \r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < restwords; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, tempbuff);\r
+ tempbuff++; \r
+ bytestransferred += 4;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ bytestransferred += 32;\r
+ }\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Send stop transmission command in case of multiblock write */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))\r
+ { \r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send stop transmission command */\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ }\r
+ \r
+ /* Get error state */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);\r
+ \r
+ errorstate = SD_TX_UNDERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Wait till the card is in programming state */\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ \r
+ while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))\r
+ {\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Reads block(s) from a specified address in a card. The Data transfer \r
+ * is managed by DMA mode. \r
+ * @note This API should be followed by the function HAL_SD_CheckReadOperation()\r
+ * to check the completion of the read process \r
+ * @param hsd: SD handle \r
+ * @param pReadBuffer: Pointer to the buffer that will contain the received data\r
+ * @param ReadAddr: Address from where data is to be read \r
+ * @param BlockSize: SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of blocks to read.\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ /* Initialize handle flags */\r
+ hsd->SdTransferCplt = 0;\r
+ hsd->DmaTransferCplt = 0;\r
+ hsd->SdTransferErr = SD_OK; \r
+ \r
+ /* Initialize SD Read operation */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ hsd->SdOperation = SD_READ_SINGLE_BLOCK;\r
+ }\r
+ \r
+ /* Enable transfer interrupts */\r
+ __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\\r
+ SDMMC_IT_DTIMEOUT |\\r
+ SDMMC_IT_DATAEND |\\r
+ SDMMC_IT_RXOVERR));\r
+ \r
+ /* Enable SDMMC DMA transfer */\r
+ __HAL_SD_SDMMC_DMA_ENABLE(hsd);\r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt;\r
+ hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;\r
+ \r
+ /* Enable the DMA Channel */\r
+ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ ReadAddr /= 512;\r
+ }\r
+ \r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Check number of blocks command */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Send CMD18 READ_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD17 READ_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;\r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);\r
+ }\r
+ \r
+ /* Update the SD transfer error in SD handle */\r
+ hsd->SdTransferErr = errorstate;\r
+ \r
+ return errorstate;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Writes block(s) to a specified address in a card. The Data transfer \r
+ * is managed by DMA mode. \r
+ * @note This API should be followed by the function HAL_SD_CheckWriteOperation()\r
+ * to check the completion of the write process (by SD current status polling). \r
+ * @param hsd: SD handle\r
+ * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit\r
+ * @param WriteAddr: Address from where data is to be read \r
+ * @param BlockSize: the SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of blocks to write\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ /* Initialize handle flags */\r
+ hsd->SdTransferCplt = 0;\r
+ hsd->DmaTransferCplt = 0;\r
+ hsd->SdTransferErr = SD_OK;\r
+ \r
+ /* Initialize SD Write operation */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;\r
+ } \r
+ \r
+ /* Enable transfer interrupts */\r
+ __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\\r
+ SDMMC_IT_DTIMEOUT |\\r
+ SDMMC_IT_DATAEND |\\r
+ SDMMC_IT_TXUNDERR)); \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;\r
+ hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;\r
+ \r
+ /* Enable the DMA Channel */\r
+ HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);\r
+\r
+ /* Enable SDMMC DMA transfer */\r
+ __HAL_SD_SDMMC_DMA_ENABLE(hsd);\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ WriteAddr /= 512;\r
+ }\r
+\r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+\r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+\r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Check number of blocks command */\r
+ if(NumberOfBlocks <= 1)\r
+ {\r
+ /* Send CMD24 WRITE_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD25 WRITE_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;\r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+\r
+ /* Check for error conditions */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);\r
+ }\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ hsd->SdTransferErr = errorstate;\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief This function waits until the SD DMA data read transfer is finished. \r
+ * This API should be called after HAL_SD_ReadBlocks_DMA() function\r
+ * to insure that all data sent by the card is already transferred by the \r
+ * DMA controller.\r
+ * @param hsd: SD handle\r
+ * @param Timeout: Timeout duration \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t timeout = Timeout;\r
+ uint32_t tmp1, tmp2;\r
+ HAL_SD_ErrorTypedef tmp3;\r
+ \r
+ /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r
+ \r
+ while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))\r
+ {\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; \r
+ timeout--;\r
+ }\r
+\r
+ timeout = Timeout;\r
+ \r
+ /* Wait until the Rx transfer is no longer active */\r
+ while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0))\r
+ {\r
+ timeout--; \r
+ }\r
+ \r
+ /* Send stop command in multiblock read */\r
+ if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)\r
+ {\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ \r
+ if ((timeout == 0) && (errorstate == SD_OK))\r
+ {\r
+ errorstate = SD_DATA_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Return error state */\r
+ if (hsd->SdTransferErr != SD_OK)\r
+ {\r
+ return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief This function waits until the SD DMA data write transfer is finished. \r
+ * This API should be called after HAL_SD_WriteBlocks_DMA() function\r
+ * to insure that all data sent by the card is already transferred by the \r
+ * DMA controller.\r
+ * @param hsd: SD handle\r
+ * @param Timeout: Timeout duration \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t timeout = Timeout;\r
+ uint32_t tmp1, tmp2;\r
+ HAL_SD_ErrorTypedef tmp3;\r
+\r
+ /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r
+ \r
+ while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))\r
+ {\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r
+ timeout--;\r
+ }\r
+ \r
+ timeout = Timeout;\r
+ \r
+ /* Wait until the Tx transfer is no longer active */\r
+ while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT)) && (timeout > 0))\r
+ {\r
+ timeout--; \r
+ }\r
+\r
+ /* Send stop command in multiblock write */\r
+ if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)\r
+ {\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ \r
+ if ((timeout == 0) && (errorstate == SD_OK))\r
+ {\r
+ errorstate = SD_DATA_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Return error state */\r
+ if (hsd->SdTransferErr != SD_OK)\r
+ {\r
+ return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);\r
+ }\r
+ \r
+ /* Wait until write is complete */\r
+ while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)\r
+ { \r
+ }\r
+\r
+ return errorstate; \r
+}\r
+\r
+/**\r
+ * @brief Erases the specified memory area of the given SD card.\r
+ * @param hsd: SD handle \r
+ * @param startaddr: Start byte address\r
+ * @param endaddr: End byte address\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ \r
+ uint32_t delay = 0;\r
+ __IO uint32_t maxdelay = 0;\r
+ uint8_t cardstate = 0;\r
+ \r
+ /* Check if the card command class supports erase command */\r
+ if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get max delay value */\r
+ maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);\r
+ \r
+ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get start and end block for high capacity cards */\r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ startaddr /= 512;\r
+ endaddr /= 512;\r
+ }\r
+ \r
+ /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */\r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send CMD32 SD_ERASE_GRP_START with argument as addr */\r
+ sdmmc_cmdinitstructure.Argument =(uint32_t)startaddr;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD33 SD_ERASE_GRP_END with argument as addr */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)endaddr;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ }\r
+ \r
+ /* Send CMD38 ERASE */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ERASE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ for (; delay < maxdelay; delay++)\r
+ {\r
+ }\r
+ \r
+ /* Wait until the card is in programming state */\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ \r
+ delay = SD_DATATIMEOUT;\r
+ \r
+ while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))\r
+ {\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ delay--;\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief This function handles SD card interrupt request.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)\r
+{ \r
+ /* Check for SDMMC interrupt flags */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND); \r
+ \r
+ /* SD transfer is complete */\r
+ hsd->SdTransferCplt = 1;\r
+\r
+ /* No transfer error */ \r
+ hsd->SdTransferErr = SD_OK;\r
+\r
+ HAL_SD_XferCpltCallback(hsd); \r
+ } \r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ hsd->SdTransferErr = SD_DATA_CRC_FAIL;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ \r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ hsd->SdTransferErr = SD_DATA_TIMEOUT;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ hsd->SdTransferErr = SD_RX_OVERRUN;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);\r
+ \r
+ hsd->SdTransferErr = SD_TX_UNDERRUN;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+\r
+ /* Disable all SDMMC peripheral interrupt sources */\r
+ __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND |\\r
+ SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\\r
+ SDMMC_IT_RXOVERR); \r
+}\r
+\r
+\r
+/**\r
+ * @brief SD end of transfer callback.\r
+ * @param hsd: SD handle \r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_XferCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SD Transfer Error callback.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsd);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_XferErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SD Transfer complete Rx callback in non blocking mode.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_RxCpltCallback could be implemented in the user file\r
+ */ \r
+} \r
+\r
+/**\r
+ * @brief SD DMA transfer complete Rx error callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_RxErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SD Transfer complete Tx callback in non blocking mode.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_TxCpltCallback could be implemented in the user file\r
+ */ \r
+} \r
+\r
+/**\r
+ * @brief SD DMA transfer complete error Tx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_TxErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group3\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the SD card \r
+ operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns information about specific card.\r
+ * @param hsd: SD handle\r
+ * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that \r
+ * contains all SD cardinformation \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t tmp = 0;\r
+ \r
+ pCardInfo->CardType = (uint8_t)(hsd->CardType);\r
+ pCardInfo->RCA = (uint16_t)(hsd->RCA);\r
+ \r
+ /* Byte 0 */\r
+ tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;\r
+ pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);\r
+ pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);\r
+ pCardInfo->SD_csd.Reserved1 = tmp & 0x03;\r
+ \r
+ /* Byte 1 */\r
+ tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;\r
+ pCardInfo->SD_csd.TAAC = (uint8_t)tmp;\r
+ \r
+ /* Byte 2 */\r
+ tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;\r
+ pCardInfo->SD_csd.NSAC = (uint8_t)tmp;\r
+ \r
+ /* Byte 3 */\r
+ tmp = hsd->CSD[0] & 0x000000FF;\r
+ pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;\r
+ \r
+ /* Byte 4 */\r
+ tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;\r
+ pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);\r
+ \r
+ /* Byte 5 */\r
+ tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;\r
+ pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);\r
+ pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F);\r
+ \r
+ /* Byte 6 */\r
+ tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;\r
+ pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);\r
+ pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);\r
+ pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);\r
+ pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4);\r
+ pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */\r
+ \r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))\r
+ {\r
+ pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;\r
+ \r
+ /* Byte 7 */\r
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);\r
+ pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);\r
+ pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;\r
+ \r
+ pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;\r
+ pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);\r
+ \r
+ /* Byte 9 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);\r
+ pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;\r
+ pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;\r
+ pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;\r
+ /* Byte 10 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);\r
+ pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;\r
+ \r
+ pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ;\r
+ pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));\r
+ pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);\r
+ pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;\r
+ }\r
+ else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ /* Byte 7 */\r
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);\r
+ pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);\r
+ \r
+ pCardInfo->SD_csd.DeviceSize |= (tmp << 8);\r
+ \r
+ /* Byte 9 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);\r
+ \r
+ pCardInfo->SD_csd.DeviceSize |= (tmp);\r
+ \r
+ /* Byte 10 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);\r
+ \r
+ pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024);\r
+ pCardInfo->CardBlockSize = 512;\r
+ }\r
+ else\r
+ {\r
+ /* Not supported card type */\r
+ errorstate = SD_ERROR;\r
+ }\r
+ \r
+ pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;\r
+ pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;\r
+ \r
+ /* Byte 11 */\r
+ tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);\r
+ pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;\r
+ pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);\r
+ \r
+ /* Byte 12 */\r
+ tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);\r
+ pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;\r
+ pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;\r
+ pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;\r
+ pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;\r
+ pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;\r
+ pCardInfo->SD_csd.Reserved3 = 0;\r
+ pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);\r
+ \r
+ /* Byte 14 */\r
+ tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;\r
+ pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;\r
+ pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;\r
+ pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;\r
+ pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;\r
+ pCardInfo->SD_csd.ECC = (tmp & 0x03);\r
+ \r
+ /* Byte 15 */\r
+ tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);\r
+ pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;\r
+ pCardInfo->SD_csd.Reserved4 = 1;\r
+ \r
+ /* Byte 0 */\r
+ tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);\r
+ pCardInfo->SD_cid.ManufacturerID = tmp;\r
+ \r
+ /* Byte 1 */\r
+ tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.OEM_AppliID = tmp << 8;\r
+ \r
+ /* Byte 2 */\r
+ tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);\r
+ pCardInfo->SD_cid.OEM_AppliID |= tmp;\r
+ \r
+ /* Byte 3 */\r
+ tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);\r
+ pCardInfo->SD_cid.ProdName1 = tmp << 24;\r
+ \r
+ /* Byte 4 */\r
+ tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);\r
+ pCardInfo->SD_cid.ProdName1 |= tmp << 16;\r
+ \r
+ /* Byte 5 */\r
+ tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.ProdName1 |= tmp << 8;\r
+ \r
+ /* Byte 6 */\r
+ tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_cid.ProdName1 |= tmp;\r
+ \r
+ /* Byte 7 */\r
+ tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);\r
+ pCardInfo->SD_cid.ProdName2 = tmp;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);\r
+ pCardInfo->SD_cid.ProdRev = tmp;\r
+ \r
+ /* Byte 9 */\r
+ tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.ProdSN = tmp << 24;\r
+ \r
+ /* Byte 10 */\r
+ tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_cid.ProdSN |= tmp << 16;\r
+ \r
+ /* Byte 11 */\r
+ tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);\r
+ pCardInfo->SD_cid.ProdSN |= tmp << 8;\r
+ \r
+ /* Byte 12 */\r
+ tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);\r
+ pCardInfo->SD_cid.ProdSN |= tmp;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;\r
+ pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;\r
+ \r
+ /* Byte 14 */\r
+ tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_cid.ManufactDate |= tmp;\r
+ \r
+ /* Byte 15 */\r
+ tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);\r
+ pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;\r
+ pCardInfo->SD_cid.Reserved2 = 1;\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Enables wide bus operation for the requested card if supported by \r
+ * card.\r
+ * @param hsd: SD handle \r
+ * @param WideMode: Specifies the SD card wide bus mode \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)\r
+ * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer\r
+ * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SDMMC_InitTypeDef tmpinit;\r
+ \r
+ /* MMC Card does not support this feature */\r
+ if (hsd->CardType == MULTIMEDIA_CARD)\r
+ {\r
+ errorstate = SD_UNSUPPORTED_FEATURE;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ if (WideMode == SDMMC_BUS_WIDE_8B)\r
+ {\r
+ errorstate = SD_UNSUPPORTED_FEATURE;\r
+ }\r
+ else if (WideMode == SDMMC_BUS_WIDE_4B)\r
+ {\r
+ errorstate = SD_WideBus_Enable(hsd);\r
+ }\r
+ else if (WideMode == SDMMC_BUS_WIDE_1B)\r
+ {\r
+ errorstate = SD_WideBus_Disable(hsd);\r
+ }\r
+ else\r
+ {\r
+ /* WideMode is not a valid argument*/\r
+ errorstate = SD_INVALID_PARAMETER;\r
+ }\r
+ \r
+ if (errorstate == SD_OK)\r
+ {\r
+ /* Configure the SDMMC peripheral */\r
+ tmpinit.ClockEdge = hsd->Init.ClockEdge;\r
+ tmpinit.ClockBypass = hsd->Init.ClockBypass;\r
+ tmpinit.ClockPowerSave = hsd->Init.ClockPowerSave;\r
+ tmpinit.BusWide = WideMode;\r
+ tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;\r
+ tmpinit.ClockDiv = hsd->Init.ClockDiv;\r
+ SDMMC_Init(hsd->Instance, tmpinit);\r
+ }\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Aborts an ongoing data transfer.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Send CMD12 STOP_TRANSMISSION */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Switches the SD card to High Speed mode.\r
+ * This API must be used after "Transfer State"\r
+ * @note This operation should be followed by the configuration \r
+ * of PLL to have SDMMCCK clock between 67 and 75 MHz\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ \r
+ uint8_t SD_hs[64] = {0};\r
+ uint32_t SD_scr[2] = {0, 0};\r
+ uint32_t SD_SPEC = 0 ;\r
+ uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;\r
+ \r
+ /* Initialize the Data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ /* Get SCR Register */\r
+ errorstate = SD_FindSCR(hsd, SD_scr);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Test the Version supported by the card*/ \r
+ SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000);\r
+ \r
+ if (SD_SPEC != SD_ALLZERO)\r
+ {\r
+ /* Set Block Size for Card */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)64;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */\r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = 64;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Send CMD6 switch mode */\r
+ sdmmc_cmdinitstructure.Argument = 0x80FFFF01U;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); \r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ }\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ count = SD_DATATIMEOUT;\r
+ \r
+ while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r
+ {\r
+ *tempbuff = SDMMC_ReadFIFO(hsd->Instance);\r
+ tempbuff++;\r
+ count--;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Test if the switch mode HS is ok */\r
+ if ((SD_hs[13]& 2) != 2)\r
+ {\r
+ errorstate = SD_UNSUPPORTED_FEATURE;\r
+ } \r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group4\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in runtime the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the current SD card's status.\r
+ * @param hsd: SD handle\r
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status \r
+ * SD Status register)\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t count = 0;\r
+ \r
+ /* Check SD response */\r
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Set block size for card if it is not equal to current block size for card */\r
+ sdmmc_cmdinitstructure.Argument = 64;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD55 */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = 64;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get status data */\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ pSDstatus += 8;\r
+ }\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+ \r
+ count = SD_DATATIMEOUT;\r
+ while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r
+ {\r
+ *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);\r
+ pSDstatus++;\r
+ count--;\r
+ }\r
+ \r
+ /* Clear all the static status flags*/\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Gets the current sd card data status.\r
+ * @param hsd: SD handle\r
+ * @retval Data Transfer state\r
+ */\r
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER;\r
+\r
+ /* Get SD card state */\r
+ cardstate = SD_GetState(hsd);\r
+ \r
+ /* Find SD status according to card state*/\r
+ if (cardstate == SD_CARD_TRANSFER)\r
+ {\r
+ return SD_TRANSFER_OK;\r
+ }\r
+ else if(cardstate == SD_CARD_ERROR)\r
+ {\r
+ return SD_TRANSFER_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return SD_TRANSFER_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the SD card status.\r
+ * @param hsd: SD handle \r
+ * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that \r
+ * will contain the SD card status information \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t tmp = 0;\r
+ uint32_t sd_status[16];\r
+ \r
+ errorstate = HAL_SD_SendSDStatus(hsd, sd_status);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Byte 0 */\r
+ tmp = (sd_status[0] & 0xC0) >> 6;\r
+ pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;\r
+ \r
+ /* Byte 0 */\r
+ tmp = (sd_status[0] & 0x20) >> 5;\r
+ pCardStatus->SECURED_MODE = (uint8_t)tmp;\r
+ \r
+ /* Byte 2 */\r
+ tmp = (sd_status[0] & 0x00FF0000) >> 16;\r
+ pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8);\r
+ \r
+ /* Byte 3 */\r
+ tmp = (sd_status[0] & 0xFF000000) >> 24;\r
+ pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp;\r
+ \r
+ /* Byte 4 */\r
+ tmp = (sd_status[1] & 0xFF);\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24);\r
+ \r
+ /* Byte 5 */\r
+ tmp = (sd_status[1] & 0xFF00) >> 8;\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16);\r
+ \r
+ /* Byte 6 */\r
+ tmp = (sd_status[1] & 0xFF0000) >> 16;\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8);\r
+ \r
+ /* Byte 7 */\r
+ tmp = (sd_status[1] & 0xFF000000) >> 24;\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (sd_status[2] & 0xFF);\r
+ pCardStatus->SPEED_CLASS = (uint8_t)tmp;\r
+ \r
+ /* Byte 9 */\r
+ tmp = (sd_status[2] & 0xFF00) >> 8;\r
+ pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;\r
+ \r
+ /* Byte 10 */\r
+ tmp = (sd_status[2] & 0xF00000) >> 20;\r
+ pCardStatus->AU_SIZE = (uint8_t)tmp;\r
+ \r
+ /* Byte 11 */\r
+ tmp = (sd_status[2] & 0xFF000000) >> 24;\r
+ pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8);\r
+ \r
+ /* Byte 12 */\r
+ tmp = (sd_status[3] & 0xFF);\r
+ pCardStatus->ERASE_SIZE |= (uint16_t)tmp;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (sd_status[3] & 0xFC00) >> 10;\r
+ pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (sd_status[3] & 0x0300) >> 8;\r
+ pCardStatus->ERASE_OFFSET = (uint8_t)tmp;\r
+ \r
+ return errorstate;\r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private function ----------------------------------------------------------*/ \r
+/** @addtogroup SD_Private_Functions\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief SD DMA transfer complete Rx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* DMA transfer is complete */\r
+ hsd->DmaTransferCplt = 1;\r
+ \r
+ /* Wait until SD transfer is complete */\r
+ while(hsd->SdTransferCplt == 0)\r
+ {\r
+ }\r
+ \r
+ /* Disable the DMA channel */\r
+ HAL_DMA_Abort(hdma);\r
+\r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); \r
+}\r
+\r
+/**\r
+ * @brief SD DMA transfer Error Rx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);\r
+}\r
+\r
+/**\r
+ * @brief SD DMA transfer complete Tx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* DMA transfer is complete */\r
+ hsd->DmaTransferCplt = 1;\r
+ \r
+ /* Wait until SD transfer is complete */\r
+ while(hsd->SdTransferCplt == 0)\r
+ {\r
+ }\r
+ \r
+ /* Disable the DMA channel */\r
+ HAL_DMA_Abort(hdma);\r
+\r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); \r
+}\r
+\r
+/**\r
+ * @brief SD DMA transfer Error Tx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);\r
+}\r
+\r
+/**\r
+ * @brief Returns the SD current state.\r
+ * @param hsd: SD handle\r
+ * @retval SD card current state\r
+ */\r
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)\r
+{\r
+ uint32_t resp1 = 0;\r
+ \r
+ if (SD_SendStatus(hsd, &resp1) != SD_OK)\r
+ {\r
+ return SD_CARD_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes all cards or single card as the case may be Card(s) come \r
+ * into standby state.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; \r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint16_t sd_rca = 1;\r
+ \r
+ if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if(hsd->CardType != SECURE_DIGITAL_IO_CARD)\r
+ {\r
+ /* Send CMD2 ALL_SEND_CID */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp2Error(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get Card identification number data */\r
+ hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r
+ hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r
+ hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r
+ }\r
+ \r
+ if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send CMD3 SET_REL_ADDR with argument 0 */\r
+ /* SD Card publishes its RCA. */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ }\r
+ \r
+ if (hsd->CardType != SECURE_DIGITAL_IO_CARD)\r
+ {\r
+ /* Get the SD card RCA */\r
+ hsd->RCA = sd_rca;\r
+ \r
+ /* Send CMD9 SEND_CSD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp2Error(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get Card Specific Data */\r
+ hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r
+ hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r
+ hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r
+ }\r
+ \r
+ /* All cards are initialized */\r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Selects od Deselects the corresponding card.\r
+ * @param hsd: SD handle\r
+ * @param addr: Address of the card to be selected \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Send CMD7 SDMMC_SEL_DESEL_CARD */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)addr;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Enquires cards about their operating voltage and configures clock\r
+ * controls and stores SD information that will be needed in future\r
+ * in the SD handle.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; \r
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK; \r
+ uint32_t response = 0, count = 0, validvoltage = 0;\r
+ uint32_t sdtype = SD_STD_CAPACITY;\r
+ \r
+ /* Power ON Sequence -------------------------------------------------------*/\r
+ /* Disable SDMMC Clock */\r
+ __HAL_SD_SDMMC_DISABLE(hsd); \r
+ \r
+ /* Set Power State to ON */\r
+ SDMMC_PowerState_ON(hsd->Instance);\r
+\r
+ /* 1ms: required power up waiting time before starting the SD initialization \r
+ sequence */\r
+ HAL_Delay(1);\r
+ \r
+ /* Enable SDMMC Clock */\r
+ __HAL_SD_SDMMC_ENABLE(hsd);\r
+ \r
+ /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/\r
+ /* No CMD response required */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_NO;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdError(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ /* CMD Response Timeout (wait for CMDSENT flag) */\r
+ return errorstate;\r
+ }\r
+ \r
+ /* CMD8: SEND_IF_COND ------------------------------------------------------*/\r
+ /* Send CMD8 to verify SD card interface operating condition */\r
+ /* Argument: - [31:12]: Reserved (shall be set to '0')\r
+ - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)\r
+ - [7:0]: Check Pattern (recommended 0xAA) */\r
+ /* CMD Response: R7 */\r
+ sdmmc_cmdinitstructure.Argument = SD_CHECK_PATTERN;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_SDMMC_SEND_IF_COND;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */ \r
+ errorstate = SD_CmdResp7Error(hsd);\r
+ \r
+ if (errorstate == SD_OK)\r
+ {\r
+ /* SD Card 2.0 */\r
+ hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; \r
+ sdtype = SD_HIGH_CAPACITY;\r
+ }\r
+ \r
+ /* Send CMD55 */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ /* If errorstate is Command Timeout, it is a MMC card */\r
+ /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)\r
+ or SD card 1.x */\r
+ if(errorstate == SD_OK)\r
+ {\r
+ /* SD CARD */\r
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */\r
+ while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))\r
+ {\r
+ \r
+ /* SEND CMD55 APP_CMD with RCA as 0 */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD41 */\r
+ sdmmc_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp3Error(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get command response */\r
+ response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ /* Get operating voltage*/\r
+ validvoltage = (((response >> 31) == 1) ? 1 : 0);\r
+ \r
+ count++;\r
+ }\r
+ \r
+ if(count >= SD_MAX_VOLT_TRIAL)\r
+ {\r
+ errorstate = SD_INVALID_VOLTRANGE;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */\r
+ {\r
+ hsd->CardType = HIGH_CAPACITY_SD_CARD;\r
+ }\r
+ \r
+ } /* else MMC Card */\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Turns the SDMMC output signals off.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Set Power State to OFF */\r
+ SDMMC_PowerState_OFF(hsd->Instance);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Returns the current card's status.\r
+ * @param hsd: SD handle\r
+ * @param pCardStatus: pointer to the buffer that will contain the SD card \r
+ * status (Card Status register) \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ if(pCardStatus == NULL)\r
+ {\r
+ errorstate = SD_INVALID_PARAMETER;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send Status command */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get SD card status */\r
+ *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for CMD0.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t timeout, tmp;\r
+ \r
+ timeout = SDMMC_CMD0TIMEOUT;\r
+ \r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);\r
+ \r
+ while((timeout > 0) && (!tmp))\r
+ {\r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);\r
+ timeout--;\r
+ }\r
+ \r
+ if(timeout == 0)\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R7 response.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_ERROR;\r
+ uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp;\r
+ \r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); \r
+ \r
+ while((!tmp) && (timeout > 0))\r
+ {\r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);\r
+ timeout--;\r
+ }\r
+ \r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); \r
+ \r
+ if((timeout == 0) || tmp)\r
+ {\r
+ /* Card is not V2.0 compliant or card does not support the set voltage range */\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND))\r
+ {\r
+ /* Card is SD V2.0 compliant */\r
+ errorstate = SD_OK;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R1 response.\r
+ * @param hsd: SD handle\r
+ * @param SD_CMD: The sent command index \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t response_r1;\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Check response received is of desired command */\r
+ if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)\r
+ {\r
+ errorstate = SD_ILLEGAL_CMD;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* We have received response, retrieve it for analysis */\r
+ response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)\r
+ {\r
+ return(SD_ADDR_OUT_OF_RANGE);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)\r
+ {\r
+ return(SD_ADDR_MISALIGNED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)\r
+ {\r
+ return(SD_BLOCK_LEN_ERR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)\r
+ {\r
+ return(SD_ERASE_SEQ_ERR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)\r
+ {\r
+ return(SD_BAD_ERASE_PARAM);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)\r
+ {\r
+ return(SD_WRITE_PROT_VIOLATION);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)\r
+ {\r
+ return(SD_LOCK_UNLOCK_FAILED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)\r
+ {\r
+ return(SD_COM_CRC_FAILED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)\r
+ {\r
+ return(SD_ILLEGAL_CMD);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)\r
+ {\r
+ return(SD_CARD_ECC_FAILED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)\r
+ {\r
+ return(SD_CC_ERROR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)\r
+ {\r
+ return(SD_GENERAL_UNKNOWN_ERROR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)\r
+ {\r
+ return(SD_STREAM_READ_UNDERRUN);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)\r
+ {\r
+ return(SD_STREAM_WRITE_OVERRUN);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)\r
+ {\r
+ return(SD_CID_CSD_OVERWRITE);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)\r
+ {\r
+ return(SD_WP_ERASE_SKIP);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)\r
+ {\r
+ return(SD_CARD_ECC_DISABLED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)\r
+ {\r
+ return(SD_ERASE_RESET);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)\r
+ {\r
+ return(SD_AKE_SEQ_ERROR);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R3 (OCR) response.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R2 (CID or CSD) response.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R6 (RCA) response.\r
+ * @param hsd: SD handle\r
+ * @param SD_CMD: The sent command index\r
+ * @param pRCA: Pointer to the variable that will contain the SD card relative \r
+ * address RCA \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t response_r1;\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+ \r
+ /* Check response received is of desired command */\r
+ if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)\r
+ {\r
+ errorstate = SD_ILLEGAL_CMD;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* We have received response, retrieve it. */\r
+ response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)\r
+ {\r
+ *pRCA = (uint16_t) (response_r1 >> 16);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)\r
+ {\r
+ return(SD_GENERAL_UNKNOWN_ERROR);\r
+ }\r
+ \r
+ if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)\r
+ {\r
+ return(SD_ILLEGAL_CMD);\r
+ }\r
+ \r
+ if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)\r
+ {\r
+ return(SD_COM_CRC_FAILED);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Enables the SDMMC wide bus mode.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ uint32_t scr[2] = {0, 0};\r
+ \r
+ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get SCR Register */\r
+ errorstate = SD_FindSCR(hsd, scr);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* If requested card supports wide bus operation */\r
+ if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)\r
+ {\r
+ /* Send CMD55 APP_CMD with argument as card's RCA.*/\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */\r
+ sdmmc_cmdinitstructure.Argument = 2;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Disables the SDMMC wide bus mode.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ uint32_t scr[2] = {0, 0};\r
+ \r
+ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get SCR Register */\r
+ errorstate = SD_FindSCR(hsd, scr);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* If requested card supports 1 bit mode operation */\r
+ if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)\r
+ {\r
+ /* Send CMD55 APP_CMD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+}\r
+ \r
+ \r
+/**\r
+ * @brief Finds the SD card SCR register value.\r
+ * @param hsd: SD handle\r
+ * @param pSCR: pointer to the buffer that will contain the SCR value \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t index = 0;\r
+ uint32_t tempscr[2] = {0, 0};\r
+ \r
+ /* Set Block Size To 8 Bytes */\r
+ /* Send CMD55 APP_CMD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)8;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD55 APP_CMD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = 8;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))\r
+ {\r
+ *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);\r
+ index++;\r
+ }\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\\r
+ ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);\r
+ \r
+ *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\\r
+ ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks if the SD card is in programming state.\r
+ * @param hsd: SD handle\r
+ * @param pStatus: pointer to the variable that will contain the SD card state \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ __IO uint32_t responseR1 = 0;\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ /* Check response received is of desired command */\r
+ if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)\r
+ {\r
+ errorstate = SD_ILLEGAL_CMD;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ \r
+ /* We have received response, retrieve it for analysis */\r
+ responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ /* Find out card status */\r
+ *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);\r
+ \r
+ if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)\r
+ {\r
+ return(SD_ADDR_OUT_OF_RANGE);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)\r
+ {\r
+ return(SD_ADDR_MISALIGNED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)\r
+ {\r
+ return(SD_BLOCK_LEN_ERR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)\r
+ {\r
+ return(SD_ERASE_SEQ_ERR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)\r
+ {\r
+ return(SD_BAD_ERASE_PARAM);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)\r
+ {\r
+ return(SD_WRITE_PROT_VIOLATION);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)\r
+ {\r
+ return(SD_LOCK_UNLOCK_FAILED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)\r
+ {\r
+ return(SD_COM_CRC_FAILED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)\r
+ {\r
+ return(SD_ILLEGAL_CMD);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)\r
+ {\r
+ return(SD_CARD_ECC_FAILED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)\r
+ {\r
+ return(SD_CC_ERROR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)\r
+ {\r
+ return(SD_GENERAL_UNKNOWN_ERROR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)\r
+ {\r
+ return(SD_STREAM_READ_UNDERRUN);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)\r
+ {\r
+ return(SD_STREAM_WRITE_OVERRUN);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)\r
+ {\r
+ return(SD_CID_CSD_OVERWRITE);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)\r
+ {\r
+ return(SD_WP_ERASE_SKIP);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)\r
+ {\r
+ return(SD_CARD_ECC_DISABLED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)\r
+ {\r
+ return(SD_ERASE_RESET);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)\r
+ {\r
+ return(SD_AKE_SEQ_ERROR);\r
+ }\r
+ \r
+ return errorstate;\r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sdram.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SDRAM HAL module driver.\r
+ * This file provides a generic firmware to drive SDRAM memories mounted \r
+ * as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control SDRAM memories. It uses the FMC layer functions to interface \r
+ with SDRAM devices. \r
+ The following sequence should be followed to configure the FMC to interface\r
+ with SDRAM memories: \r
+ \r
+ (#) Declare a SDRAM_HandleTypeDef handle structure, for example:\r
+ SDRAM_HandleTypeDef hdsram \r
+ \r
+ (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed \r
+ values of the structure member.\r
+ \r
+ (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined \r
+ base register instance for NOR or SDRAM device \r
+ \r
+ (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:\r
+ FMC_SDRAM_TimingTypeDef Timing;\r
+ and fill its fields with the allowed values of the structure member.\r
+ \r
+ (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function\r
+ performs the following sequence:\r
+ \r
+ (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()\r
+ (##) Control register configuration using the FMC SDRAM interface function \r
+ FMC_SDRAM_Init()\r
+ (##) Timing register configuration using the FMC SDRAM interface function \r
+ FMC_SDRAM_Timing_Init()\r
+ (##) Program the SDRAM external device by applying its initialization sequence\r
+ according to the device plugged in your hardware. This step is mandatory\r
+ for accessing the SDRAM device. \r
+\r
+ (#) At this stage you can perform read/write accesses from/to the memory connected \r
+ to the SDRAM Bank. You can perform either polling or DMA transfer using the\r
+ following APIs:\r
+ (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access\r
+ (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer\r
+ \r
+ (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/\r
+ HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or \r
+ the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM\r
+ device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef \r
+ structure. \r
+ \r
+ (#) You can continuously monitor the SDRAM device HAL state by calling the function\r
+ HAL_SDRAM_GetState() \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDRAM SDRAM\r
+ * @brief SDRAM driver modules\r
+ * @{\r
+ */\r
+#ifdef HAL_SDRAM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SDRAM Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize\r
+ the SDRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Performs the SDRAM device initialization sequence.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param Timing: Pointer to SDRAM control timing structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)\r
+{ \r
+ /* Check the SDRAM handle parameter */\r
+ if(hsdram == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hsdram->State == HAL_SDRAM_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hsdram->Lock = HAL_UNLOCKED;\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SDRAM_MspInit(hsdram);\r
+ }\r
+ \r
+ /* Initialize the SDRAM controller state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Initialize SDRAM control Interface */\r
+ FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));\r
+ \r
+ /* Initialize SDRAM timing Interface */\r
+ FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); \r
+ \r
+ /* Update the SDRAM controller state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Perform the SDRAM device initialization sequence.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SDRAM_MspDeInit(hsdram);\r
+\r
+ /* Configure the SDRAM registers with their reset values */\r
+ FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);\r
+\r
+ /* Reset the SDRAM controller state */\r
+ hsdram->State = HAL_SDRAM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsdram);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SDRAM MSP Init.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsdram);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SDRAM MSP DeInit.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsdram);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief This function handles SDRAM refresh error interrupt request.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+*/\r
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Check SDRAM interrupt Rising edge flag */\r
+ if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))\r
+ {\r
+ /* SDRAM refresh error interrupt callback */\r
+ HAL_SDRAM_RefreshErrorCallback(hsdram);\r
+ \r
+ /* Clear SDRAM refresh error interrupt pending bit */\r
+ __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief SDRAM Refresh error callback.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module. \r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsdram);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete error callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SDRAM Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the SDRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads 8-bit data buffer from the SDRAM memory.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Read data from source */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint8_t *)pSdramAddress; \r
+ pDstBuffer++;\r
+ pSdramAddress++;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Writes 8-bit data buffer to SDRAM memory.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;\r
+ pSrcBuffer++;\r
+ pSdramAddress++;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Reads 16-bit data buffer from the SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Read data from source */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint16_t *)pSdramAddress; \r
+ pDstBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 16-bit data buffer to SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;\r
+ pSrcBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads 32-bit data buffer from the SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Read data from source */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint32_t *)pSdramAddress; \r
+ pDstBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 32-bit data buffer to SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;\r
+ pSrcBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads a Words data from the SDRAM memory using DMA transfer. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */ \r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(tmp == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;\r
+ hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */ \r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;\r
+ hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SDRAM_Exported_Functions_Group3 Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SDRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the SDRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically SDRAM write protection.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)\r
+{ \r
+ /* Check the SDRAM controller state */ \r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Enable write protection */\r
+ FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically SDRAM write protection.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Disable write protection */\r
+ FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sends Command to the SDRAM bank.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param Command: SDRAM command structure\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Send SDRAM command */\r
+ FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);\r
+ \r
+ /* Update the SDRAM controller state state */\r
+ if(Command->CommandMode == FMC_SDRAM_CMD_PALL)\r
+ {\r
+ hsdram->State = HAL_SDRAM_STATE_PRECHARGED;\r
+ }\r
+ else\r
+ {\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Programs the SDRAM Memory Refresh rate.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module. \r
+ * @param RefreshRate: The SDRAM refresh rate value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ } \r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Program the refresh rate */\r
+ FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module. \r
+ * @param AutoRefreshNumber: The SDRAM auto Refresh number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ } \r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Set the Auto-Refresh number */\r
+ FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the SDRAM memory current mode.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval The SDRAM memory mode. \r
+ */\r
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Return the SDRAM memory current mode */\r
+ return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SDRAM_Exported_Functions_Group4 State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SDRAM State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the SDRAM controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the SDRAM state.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ return hsdram->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_SDRAM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_smartcard.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SMARTCARD HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the SMARTCARD peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and Errors functions \r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The SMARTCARD HAL driver can be used as follow:\r
+ \r
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure.\r
+ (#) Associate a USART to the SMARTCARD handle hsc.\r
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) SMARTCARD pins configuration:\r
+ (+++) Enable the clock for the SMARTCARD GPIOs.\r
+ (+++) Configure these SMARTCARD pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()\r
+ and HAL_SMARTCARD_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (+++) The specific USART interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()\r
+ and HAL_SMARTCARD_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,\r
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission\r
+ error enabling or disabling in the hsc Init structure.\r
+ \r
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)\r
+ in the hsc AdvancedInit structure.\r
+\r
+ (#) Initialize the SMARTCARD associated USART registers by calling\r
+ the HAL_SMARTCARD_Init() API. \r
+ \r
+ [..]\r
+ (@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by \r
+ calling the customized HAL_SMARTCARD_MspInit() API.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARD SMARTCARD\r
+ * @brief HAL USART SMARTCARD module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants\r
+ * @{\r
+ */\r
+#define TEACK_REACK_TIMEOUT 1000U\r
+#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000U\r
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) \r
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))\r
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) \r
+/**\r
+ * @}\r
+ */\r
+/* Private macros -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup SMARTCARD_Private_Functions\r
+ * @{\r
+ */\r
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);\r
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc);\r
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc);\r
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);\r
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);\r
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);\r
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);\r
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USART\r
+ associated to the SmartCard.\r
+ (+) These parameters can be configured: \r
+ (++) Baud Rate\r
+ (++) Parity: parity should be enabled,\r
+ Frame Length is fixed to 8 bits plus parity.\r
+ (++) Receiver/transmitter modes\r
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)\r
+ (++) Prescaler value\r
+ (++) Guard bit time \r
+ (++) NACK enabling or disabling on transmission error \r
+\r
+ (+) The following advanced features can be configured as well:\r
+ (++) TX and/or RX pin level inversion\r
+ (++) data logical level inversion\r
+ (++) RX and TX pins swap\r
+ (++) RX overrun detection disabling\r
+ (++) DMA disabling on RX error\r
+ (++) MSB first on communication line\r
+ (++) Time out enabling (and if activated, timeout value)\r
+ (++) Block length\r
+ (++) Auto-retry counter \r
+ \r
+ [..] \r
+ The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures \r
+ (details for the procedures are available in reference manual).\r
+\r
+@endverbatim\r
+\r
+ The USART frame format is given in the following table:\r
+\r
+ +---------------------------------------------------------------+\r
+ | M1M0 bits | PCE bit | USART frame |\r
+ |-----------------------|---------------------------------------|\r
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |\r
+ +---------------------------------------------------------------+\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SMARTCARD mode according to the specified\r
+ * parameters in the SMARTCARD_InitTypeDef and create the associated handle .\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Check the SMARTCARD handle allocation */\r
+ if(hsc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r
+ \r
+ if(hsc->gState == HAL_SMARTCARD_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hsc->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
+ HAL_SMARTCARD_MspInit(hsc);\r
+ }\r
+ \r
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_SMARTCARD_DISABLE(hsc);\r
+\r
+ /* Set the SMARTCARD Communication parameters */\r
+ SMARTCARD_SetConfig(hsc);\r
+\r
+ if(hsc->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)\r
+ {\r
+ SMARTCARD_AdvFeatureConfig(hsc);\r
+ }\r
+\r
+ /* In SmartCard mode, the following bits must be kept cleared: \r
+ - LINEN in the USART_CR2 register,\r
+ - HDSEL and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);\r
+ CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));\r
+\r
+ /* set the USART in SMARTCARD mode */\r
+ SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_SMARTCARD_ENABLE(hsc);\r
+ \r
+ /* TEACK and/or REACK to check before moving hsc->State to Ready */\r
+ return (SMARTCARD_CheckIdleState(hsc));\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SMARTCARD peripheral \r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Check the SMARTCARD handle allocation */\r
+ if(hsc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r
+\r
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_SMARTCARD_MspDeInit(hsc);\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ hsc->gState = HAL_SMARTCARD_STATE_RESET;\r
+ hsc->RxState = HAL_SMARTCARD_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SMARTCARD MSP Init\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SMARTCARD MSP DeInit\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions \r
+ * @brief SMARTCARD Transmit and Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode. \r
+ The HAL status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (+) No-Blocking mode: The communication is performed using Interrupts \r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the \r
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+ The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks \r
+ will be executed respectively at the end of the Transmit or Receive process\r
+ The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_SMARTCARD_Transmit()\r
+ (+) HAL_SMARTCARD_Receive() \r
+ \r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_SMARTCARD_Transmit_IT()\r
+ (+) HAL_SMARTCARD_Receive_IT()\r
+ (+) HAL_SMARTCARD_IRQHandler()\r
+ (+) SMARTCARD_Transmit_IT()\r
+ (+) SMARTCARD_Receive_IT() \r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (+) HAL_SMARTCARD_Transmit_DMA()\r
+ (+) HAL_SMARTCARD_Receive_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (+) HAL_SMARTCARD_TxCpltCallback()\r
+ (+) HAL_SMARTCARD_RxCpltCallback()\r
+ (+) HAL_SMARTCARD_ErrorCallback()\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Send an amount of data in blocking mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; \r
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ \r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ hsc->TxXferSize = Size;\r
+ hsc->TxXferCount = Size;\r
+ while(hsc->TxXferCount > 0U)\r
+ {\r
+ hsc->TxXferCount--;\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ hsc->Instance->TDR = (*pData++ & (uint8_t)0xFFU);\r
+ }\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* At end of Tx process, restore hsc->gState to Ready */\r
+ hsc->gState = HAL_SMARTCARD_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+ \r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ \r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hsc->RxXferSize = Size;\r
+ hsc->RxXferCount = Size;\r
+ /* Check the remain data to be received */\r
+ while(hsc->RxXferCount > 0U)\r
+ {\r
+ hsc->RxXferCount--;\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FFU);\r
+ }\r
+\r
+ /* At end of Rx process, restore hsc->RxState to Ready */\r
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Tx process is not already ongoing */\r
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pTxBuffPtr = pData;\r
+ hsc->TxXferSize = Size;\r
+ hsc->TxXferCount = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the SMARTCARD Transmit Complete Interrupt */\r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Rx process is not already ongoing */ \r
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY) \r
+ {\r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pRxBuffPtr = pData;\r
+ hsc->RxXferSize = Size;\r
+ hsc->RxXferCount = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+ \r
+ /* Enable the SMARTCARD Parity Error Interrupt */\r
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the SMARTCARD Data Register not empty Interrupt */\r
+ SET_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ /* Check that a Tx process is not already ongoing */\r
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pTxBuffPtr = pData;\r
+ hsc->TxXferSize = Size;\r
+ hsc->TxXferCount = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;\r
+\r
+ /* Set the SMARTCARD DMA transfer complete callback */\r
+ hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;\r
+\r
+ /* Set the SMARTCARD error callback */\r
+ hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;\r
+ \r
+ /* Set the DMA abort callback */\r
+ hsc->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the SMARTCARD transmit DMA Stream */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size);\r
+ \r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the SMARTCARD associated USART CR3 register */\r
+ SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), \r
+ * the received data contain the parity bit (MSB position) \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ /* Check that a Rx process is not already ongoing */\r
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pRxBuffPtr = pData;\r
+ hsc->RxXferSize = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;\r
+\r
+ /* Set the SMARTCARD DMA transfer complete callback */\r
+ hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;\r
+\r
+ /* Set the SMARTCARD DMA error callback */\r
+ hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;\r
+ \r
+ /* Set the DMA abort callback */\r
+ hsc->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA Stream */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+ \r
+ /* Enable the SMARTCARD Parity Error Interrupt */\r
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the SMARTCARD associated USART CR3 register */\r
+ SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+ \r
+/**\r
+ * @brief SMARTCARD interrupt requests handling.\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ uint32_t isrflags = READ_REG(hsc->Instance->ISR);\r
+ uint32_t cr1its = READ_REG(hsc->Instance->CR1);\r
+ uint32_t cr3its = READ_REG(hsc->Instance->CR3);\r
+ uint32_t dmarequest = 0x00U;\r
+ uint32_t errorflags = 0x00U;\r
+\r
+ /* If no error occurs */\r
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r
+ if(errorflags == RESET)\r
+ {\r
+ /* SMARTCARD in mode Receiver -------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ SMARTCARD_Receive_IT(hsc);\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* If some errors occur */\r
+ if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r
+ {\r
+ /* SMARTCARD parity error interrupt occurred ---------------------------*/\r
+ if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r
+ { \r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;\r
+ }\r
+\r
+ /* SMARTCARD frame error interrupt occurred ----------------------------*/\r
+ if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ { \r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;\r
+ }\r
+\r
+ /* SMARTCARD noise error interrupt occurred ----------------------------*/\r
+ if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ { \r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;\r
+ }\r
+\r
+ /* SMARTCARD Over-Run interrupt occurred -------------------------------*/\r
+ if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ { \r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;\r
+ }\r
+ /* Call the Error call Back in case of Errors */\r
+ if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)\r
+ {\r
+ /* SMARTCARD in mode Receiver -----------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ SMARTCARD_Receive_IT(hsc);\r
+ }\r
+\r
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+ consider error as blocking */\r
+ dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);\r
+ if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)\r
+ {\r
+ /* Blocking error : transfer is aborted\r
+ Set the SMARTCARD state ready to be able to start again the process,\r
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
+ SMARTCARD_EndRxTransfer(hsc);\r
+ /* Disable the SMARTCARD DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the SMARTCARD DMA Rx channel */\r
+ if(hsc->hdmarx != NULL)\r
+ {\r
+ /* Set the SMARTCARD DMA Abort callback : \r
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */\r
+ hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;\r
+\r
+ if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hsc->hdmarx->XferAbortCallback(hsc->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ }\r
+ }\r
+ return;\r
+ } /* End if some error occurs */\r
+ \r
+ /* SMARTCARD in mode Transmitter -------------------------------------------*/\r
+ if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r
+ {\r
+ SMARTCARD_Transmit_IT(hsc);\r
+ return;\r
+ }\r
+ \r
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/\r
+ if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r
+ {\r
+ /* Disable the SMARTCARD Transmit Complete Interrupt */ \r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Tx process is ended, restore hsmartcard->gState to Ready */\r
+ hsc->gState = HAL_SMARTCARD_STATE_READY;\r
+\r
+ HAL_SMARTCARD_TxCpltCallback(hsc);\r
+ \r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SMARTCARD error callbacks\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsc);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State functions \r
+ * @brief SMARTCARD State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.\r
+ (+) HAL_SMARTCARD_GetState() API is helpful to check in run-time the state of the SMARTCARD peripheral \r
+ (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral \r
+ (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief return the SMARTCARD state\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL state\r
+ */\r
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ uint32_t temp1= 0x00U, temp2 = 0x00U;\r
+ temp1 = hsc->gState;\r
+ temp2 = hsc->RxState;\r
+ \r
+ return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+ * @brief Return the SMARTCARD error code\r
+ * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SMARTCARD.\r
+ * @retval SMARTCARD Error Code\r
+ */\r
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ return hsc->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Send an amount of data in non blocking mode \r
+ * @param hsc: SMARTCARD handle.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)\r
+ {\r
+ if(hsc->TxXferCount == 0)\r
+ {\r
+ /* Disable the SMARTCARD Transmit Complete Interrupt */\r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);\r
+ \r
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+ \r
+ /* Tx process is ended, restore hsmartcard->gState to Ready */\r
+ hsc->gState = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ HAL_SMARTCARD_TxCpltCallback(hsc);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ { \r
+ hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFFU);\r
+ hsc->TxXferCount--;\r
+ \r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non blocking mode \r
+ * @param hsc: SMARTCARD handle.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Check that a Rx process is ongoing */\r
+ if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) \r
+ {\r
+ *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFFU);\r
+ \r
+ if(--hsc->RxXferCount == 0)\r
+ {\r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);\r
+ \r
+ /* Disable the SMARTCARD Parity Error Interrupt */\r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r
+ \r
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+ \r
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;\r
+ \r
+ HAL_SMARTCARD_RxCpltCallback(hsc);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the SMARTCARD associated USART peripheral \r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ uint32_t tmpreg = 0x00000000U;\r
+ uint32_t clocksource = 0x00000000U;\r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r
+ assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate)); \r
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)); \r
+ assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)); \r
+ assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));\r
+ assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));\r
+ assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));\r
+ assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));\r
+ assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); \r
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling));\r
+ assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState));\r
+ assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable));\r
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount)); \r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).\r
+ * Oversampling is forced to 16 (OVER8 = 0).\r
+ * Configure the Parity and Mode: \r
+ * set PS bit according to hsc->Init.Parity value\r
+ * set TE and RE bits according to hsc->Init.Mode value */\r
+ tmpreg = (uint32_t) hsc->Init.Parity | hsc->Init.Mode;\r
+ /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor \r
+ the bidirectional line to detect a NACK signal in case of parity error. \r
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */\r
+ if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE))\r
+ {\r
+ tmpreg |= USART_CR1_RE; \r
+ }\r
+ tmpreg |= (uint32_t) hsc->Init.WordLength;\r
+ MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR2 Configuration -----------------------*/\r
+ /* Stop bits are forced to 1.5 (STOP = 11) */\r
+ tmpreg = hsc->Init.StopBits;\r
+ /* Synchronous mode is activated by default */\r
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity; \r
+ tmpreg |= (uint32_t) hsc->Init.CLKPhase | hsc->Init.CLKLastBit;\r
+ tmpreg |= (uint32_t) hsc->Init.TimeOutEnable;\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_FIELDS, tmpreg); \r
+ \r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* Configure \r
+ * - one-bit sampling method versus three samples' majority rule \r
+ * according to hsc->Init.OneBitSampling \r
+ * - NACK transmission in case of parity error according \r
+ * to hsc->Init.NACKEnable \r
+ * - autoretry counter according to hsc->Init.AutoRetryCount */\r
+ tmpreg = (uint32_t) hsc->Init.OneBitSampling | hsc->Init.NACKState;\r
+ tmpreg |= (uint32_t) (hsc->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);\r
+ MODIFY_REG(hsc->Instance-> CR3,USART_CR3_FIELDS, tmpreg);\r
+ \r
+ /*-------------------------- USART GTPR Configuration ----------------------*/\r
+ tmpreg = (uint32_t) (hsc->Init.Prescaler | (hsc->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));\r
+ MODIFY_REG(hsc->Instance->GTPR, (uint32_t)(USART_GTPR_GT|USART_GTPR_PSC), tmpreg); \r
+ \r
+ /*-------------------------- USART RTOR Configuration ----------------------*/ \r
+ tmpreg = (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);\r
+ if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)\r
+ {\r
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));\r
+ tmpreg |= (uint32_t) hsc->Init.TimeOutValue;\r
+ }\r
+ MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);\r
+ \r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ SMARTCARD_GETCLOCKSOURCE(hsc, clocksource);\r
+ switch (clocksource)\r
+ {\r
+ case SMARTCARD_CLOCKSOURCE_PCLK1: \r
+ hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);\r
+ break;\r
+ case SMARTCARD_CLOCKSOURCE_PCLK2: \r
+ hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);\r
+ break;\r
+ case SMARTCARD_CLOCKSOURCE_HSI: \r
+ hsc->Instance->BRR = (uint16_t)((HSI_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); \r
+ break; \r
+ case SMARTCARD_CLOCKSOURCE_SYSCLK: \r
+ hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);\r
+ break; \r
+ case SMARTCARD_CLOCKSOURCE_LSE: \r
+ hsc->Instance->BRR = (uint16_t)((LSE_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); \r
+ break;\r
+ default:\r
+ break;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Check the SMARTCARD Idle State\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ /* Initialize the SMARTCARD ErrorCode */\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ \r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the Transmitter is enabled */\r
+ if((hsc->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((hsc->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+ \r
+ /* Initialize the SMARTCARD state*/\r
+ hsc->gState= HAL_SMARTCARD_STATE_READY;\r
+ hsc->RxState= HAL_SMARTCARD_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features \r
+ * @param hsc: SMARTCARD handle \r
+ * @retval None\r
+ */\r
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc)\r
+{ \r
+ /* Check whether the set of advanced features to configure is properly set */ \r
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsc->AdvancedInit.AdvFeatureInit));\r
+ \r
+ /* if required, configure TX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsc->AdvancedInit.TxPinLevelInvert));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_TXINV, hsc->AdvancedInit.TxPinLevelInvert);\r
+ }\r
+ \r
+ /* if required, configure RX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsc->AdvancedInit.RxPinLevelInvert));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_RXINV, hsc->AdvancedInit.RxPinLevelInvert);\r
+ }\r
+ \r
+ /* if required, configure data inversion */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsc->AdvancedInit.DataInvert));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_DATAINV, hsc->AdvancedInit.DataInvert);\r
+ }\r
+ \r
+ /* if required, configure RX/TX pins swap */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsc->AdvancedInit.Swap));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_SWAP, hsc->AdvancedInit.Swap);\r
+ }\r
+ \r
+ /* if required, configure RX overrun detection disabling */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_OVERRUN(hsc->AdvancedInit.OverrunDisable)); \r
+ MODIFY_REG(hsc->Instance->CR3, USART_CR3_OVRDIS, hsc->AdvancedInit.OverrunDisable);\r
+ }\r
+ \r
+ /* if required, configure DMA disabling on reception error */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsc->AdvancedInit.DMADisableonRxError)); \r
+ MODIFY_REG(hsc->Instance->CR3, USART_CR3_DDRE, hsc->AdvancedInit.DMADisableonRxError);\r
+ }\r
+ \r
+ /* if required, configure MSB first on communication line */ \r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsc->AdvancedInit.MSBFirst)); \r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_MSBFIRST, hsc->AdvancedInit.MSBFirst);\r
+ }\r
+}\r
+ \r
+/**\r
+ * @brief This function handles SMARTCARD Communication Timeout.\r
+ * @param hsc SMARTCARD handle\r
+ * @param Flag specifies the SMARTCARD flag to check.\r
+ * @param Status The new Flag status (SET or RESET).\r
+ * @param Tickstart Tick start value\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+ /* Wait until flag is set */\r
+ while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);\r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);\r
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+ \r
+ hsc->gState= HAL_SMARTCARD_STATE_READY;\r
+ hsc->RxState= HAL_SMARTCARD_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/*\r
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).\r
+ * @param hsc: SMARTCARD handle.\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Disable TXEIE and TCIE interrupts */\r
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+ \r
+ /* At end of Tx process, restore hsc->gState to Ready */\r
+ hsc->gState = HAL_SMARTCARD_STATE_READY;\r
+}\r
+\r
+\r
+/**\r
+ * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).\r
+ * @param hsc: SMARTCARD handle.\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+ \r
+ /* At end of Rx process, restore hsc->RxState to Ready */\r
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief DMA SMARTCARD transmit process complete callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) \r
+{ \r
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hsc->TxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);\r
+ \r
+ /* Enable the SMARTCARD Transmit Complete Interrupt */ \r
+ SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);\r
+}\r
+\r
+/**\r
+ * @brief DMA SMARTCARD receive process complete callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hsc->RxXferCount = 0;\r
+ \r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r
+ \r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the SMARTCARD associated USART CR3 register */\r
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);\r
+ \r
+ /* At end of Rx process, restore hsc->RxState to Ready */\r
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;\r
+ \r
+ HAL_SMARTCARD_RxCpltCallback(hsc);\r
+}\r
+\r
+/**\r
+ * @brief DMA SMARTCARD communication error callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hsc->RxXferCount = 0U;\r
+ hsc->TxXferCount = 0U;\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;\r
+ \r
+ /* Stop SMARTCARD DMA Tx request if ongoing */\r
+ if ( (hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)\r
+ &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) )\r
+ {\r
+ SMARTCARD_EndTxTransfer(hsc);\r
+ }\r
+ \r
+ /* Stop SMARTCARD DMA Rx request if ongoing */\r
+ if ( (hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)\r
+ &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) )\r
+ {\r
+ SMARTCARD_EndRxTransfer(hsc);\r
+ }\r
+ \r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+}\r
+\r
+/**\r
+ * @brief DMA SMARTCARD communication abort callback, when call by HAL services on Error\r
+ * (To be called at end of DMA Abort procedure following error occurrence).\r
+ * @param hdma: DMA handle.\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hsc->RxXferCount = 0U;\r
+ hsc->TxXferCount = 0U;\r
+\r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_smartcard_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SMARTCARD HAL module driver.\r
+ *\r
+ * This file provides extended firmware functions to manage the following \r
+ * functionalities of the SmartCard.\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The Extended SMARTCARD HAL driver can be used as follow:\r
+\r
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), \r
+ then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, \r
+ auto-retry counter,...) in the hsc AdvancedInit structure.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARDEx SMARTCARDEx\r
+ * @brief SMARTCARD Extended HAL module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions\r
+ * @brief Extended control functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.\r
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly \r
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly \r
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature\r
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Update on the fly the SMARTCARD block length in RTOR register\r
+ * @param hsc: SMARTCARD handle\r
+ * @param BlockLength: SMARTCARD block length (8-bit long at most) \r
+ * @retval None\r
+ */\r
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)\r
+{\r
+ MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));\r
+}\r
+\r
+/**\r
+ * @brief Update on the fly the receiver timeout value in RTOR register\r
+ * @param hsc: SMARTCARD handle\r
+ * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout\r
+ * value must be less or equal to 0x0FFFFFFFF. \r
+ * @retval None\r
+ */\r
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)\r
+{\r
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));\r
+ MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); \r
+}\r
+\r
+/**\r
+ * @brief Enable the SMARTCARD receiver timeout feature\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* Set the USART RTOEN bit */\r
+ hsc->Instance->CR2 |= USART_CR2_RTOEN;\r
+\r
+ hsc->gState = HAL_SMARTCARD_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the SMARTCARD receiver timeout feature\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* Clear the USART RTOEN bit */\r
+ hsc->Instance->CR2 &= ~(USART_CR2_RTOEN);\r
+\r
+ hsc->gState = HAL_SMARTCARD_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_spdifrx.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the SPDIFRX audio interface:\r
+ * + Initialization and Configuration\r
+ * + Data transfers functions\r
+ * + DMA transfers management\r
+ * + Interrupts and flags management \r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The SPDIFRX HAL driver can be used as follow:\r
+ \r
+ (#) Declare SPDIFRX_HandleTypeDef handle structure.\r
+ (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:\r
+ (##) Enable the SPDIFRX interface clock. \r
+ (##) SPDIFRX pins configuration:\r
+ (+++) Enable the clock for the SPDIFRX GPIOs.\r
+ (+++) Configure these SPDIFRX pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).\r
+ (+++) Configure the SPDIFRX interrupt priority.\r
+ (+++) Enable the NVIC SPDIFRX IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).\r
+ (+++) Declare a DMA handle structure for the reception of the Data Flow channel.\r
+ (+++) Declare a DMA handle structure for the reception of the Control Flow channel.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.\r
+ (+++) Configure the DMA Channel.\r
+ (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r
+ DMA CtrlRx/DataRx channel.\r
+ \r
+ (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits\r
+ using HAL_SPDIFRX_Init() function.\r
+\r
+ -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros\r
+ __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.\r
+ -@- Make sure that ck_spdif clock is configured. \r
+ \r
+ (#) Three operation modes are available within this driver :\r
+ \r
+ *** Polling mode for reception operation (for debug purpose) ***\r
+ ================================================================\r
+ [..] \r
+ (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()\r
+ (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()\r
+ \r
+ *** Interrupt mode for reception operation ***\r
+ =========================================\r
+ [..] \r
+ (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() \r
+ (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() \r
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback\r
+\r
+ *** DMA mode for reception operation ***\r
+ ========================================\r
+ [..] \r
+ (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() \r
+ (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA() \r
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback\r
+ (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()\r
+\r
+ *** SPDIFRX HAL driver macros list ***\r
+ =============================================\r
+ [..]\r
+ Below the list of most used macros in USART HAL driver.\r
+ (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)\r
+ (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) \r
+ (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)\r
+ (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts\r
+ (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts\r
+ (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.\r
+\r
+ [..]\r
+ (@) You can refer to the SPDIFRX HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @defgroup SPDIFRX SPDIFRX\r
+* @brief SPDIFRX HAL module driver\r
+* @{\r
+*/\r
+\r
+#ifdef HAL_SPDIFRX_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define SPDIFRX_TIMEOUT_VALUE 0xFFFF\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup SPDIFRX_Private_Functions\r
+ * @{\r
+ */\r
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);\r
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);\r
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and \r
+ de-initialize the SPDIFRX peripheral:\r
+ \r
+ (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures \r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+ \r
+ (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with \r
+ the selected configuration:\r
+ (++) Input Selection (IN0, IN1,...)\r
+ (++) Maximum allowed re-tries during synchronization phase\r
+ (++) Wait for activity on SPDIF selected input\r
+ (++) Channel status selection (from channel A or B)\r
+ (++) Data format (LSB, MSB, ...)\r
+ (++) Stereo mode\r
+ (++) User bits masking (PT,C,U,V,...)\r
+ \r
+ (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration \r
+ of the selected SPDIFRXx peripheral. \r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SPDIFRX according to the specified parameters \r
+ * in the SPDIFRX_InitTypeDef and create the associated handle.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the SPDIFRX handle allocation */\r
+ if(hspdif == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the SPDIFRX parameters */\r
+ assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));\r
+ assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));\r
+ assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));\r
+ assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));\r
+ assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));\r
+ assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));\r
+ assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));\r
+ assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));\r
+ assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));\r
+ assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));\r
+ \r
+ if(hspdif->State == HAL_SPDIFRX_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hspdif->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_SPDIFRX_MspInit(hspdif);\r
+ }\r
+ \r
+ /* SPDIFRX peripheral state is BUSY*/\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY; \r
+ \r
+ /* Disable SPDIFRX interface (IDLE State) */\r
+ __HAL_SPDIFRX_IDLE(hspdif);\r
+ \r
+ /* Reset the old SPDIFRX CR configuration */\r
+ tmpreg = hspdif->Instance->CR;\r
+ \r
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |\r
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |\r
+ SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL); \r
+ \r
+ /* Sets the new configuration of the SPDIFRX peripheral */\r
+ tmpreg |= ((uint16_t) hspdif->Init.StereoMode |\r
+ hspdif->Init.InputSelection |\r
+ hspdif->Init.Retries |\r
+ hspdif->Init.WaitForActivity |\r
+ hspdif->Init.ChannelSelection |\r
+ hspdif->Init.DataFormat |\r
+ hspdif->Init.PreambleTypeMask |\r
+ hspdif->Init.ChannelStatusMask |\r
+ hspdif->Init.ValidityBitMask |\r
+ hspdif->Init.ParityErrorMask);\r
+ \r
+ hspdif->Instance->CR = tmpreg; \r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* SPDIFRX peripheral state is READY*/\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SPDIFRX peripheral \r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Check the SPDIFRX handle allocation */\r
+ if(hspdif == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r
+ \r
+ /* Disable SPDIFRX interface (IDLE state) */\r
+ __HAL_SPDIFRX_IDLE(hspdif);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_SPDIFRX_MspDeInit(hspdif);\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* SPDIFRX peripheral state is RESET*/\r
+ hspdif->State = HAL_SPDIFRX_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SPDIFRX MSP Init\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspdif);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SPDIFRX MSP DeInit\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspdif);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Sets the SPDIFRX dtat format according to the specified parameters \r
+ * in the SPDIFRX_InitTypeDef.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param sDataFormat: SPDIFRX data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the SPDIFRX handle allocation */\r
+ if(hspdif == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the SPDIFRX parameters */\r
+ assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));\r
+ assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));\r
+ assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));\r
+ assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));\r
+ assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));\r
+ assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));\r
+ \r
+ /* Reset the old SPDIFRX CR configuration */\r
+ tmpreg = hspdif->Instance->CR;\r
+ \r
+ if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&\r
+ (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||\r
+ ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |\r
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); \r
+ \r
+ /* Sets the new configuration of the SPDIFRX peripheral */\r
+ tmpreg |= ((uint16_t) sDataFormat.StereoMode |\r
+ sDataFormat.DataFormat |\r
+ sDataFormat.PreambleTypeMask |\r
+ sDataFormat.ChannelStatusMask |\r
+ sDataFormat.ValidityBitMask |\r
+ sDataFormat.ParityErrorMask);\r
+ \r
+ hspdif->Instance->CR = tmpreg; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### IO operation functions #####\r
+=============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the SPDIFRX data \r
+ transfers.\r
+\r
+ (#) There is two mode of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode. \r
+ The status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (++) No-Blocking mode : The communication is performed using Interrupts \r
+ or DMA. These functions return the status of the transfer start-up.\r
+ The end of the data processing will be indicated through the \r
+ dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+\r
+ (#) Blocking mode functions are :\r
+ (++) HAL_SPDIFRX_ReceiveDataFlow()\r
+ (++) HAL_SPDIFRX_ReceiveControlFlow()\r
+ (+@) Do not use blocking mode to receive both control and data flow at the same time.\r
+\r
+ (#) No-Blocking mode functions with Interrupt are :\r
+ (++) HAL_SPDIFRX_ReceiveControlFlow_IT()\r
+ (++) HAL_SPDIFRX_ReceiveDataFlow_IT()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()\r
+ (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (++) HAL_SPDIFRX_RxCpltCallback()\r
+ (++) HAL_SPDIFRX_ErrorCallback()\r
+\r
+@endverbatim\r
+* @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Receives an amount of data (Data Flow) in blocking mode. \r
+ * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains\r
+ * the configuration information for SPDIFRX module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if((pData == NULL ) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r
+ \r
+ /* Start synchronisation */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ \r
+ /* Receive data flow */\r
+ while(Size > 0U)\r
+ { \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until RXNE flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ (*pData++) = hspdif->Instance->DR;\r
+ Size--; \r
+ } \r
+ \r
+ /* SPDIFRX ready */\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data (Control Flow) in blocking mode. \r
+ * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains\r
+ * the configuration information for SPDIFRX module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if((pData == NULL ) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r
+ \r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ \r
+ /* Receive control flow */\r
+ while(Size > 0U)\r
+ { \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until CSRNE flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ (*pData++) = hspdif->Instance->CSR;\r
+ Size--; \r
+ } \r
+ \r
+ /* SPDIFRX ready */\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be received .\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))\r
+ {\r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->pRxBuffPtr = pData;\r
+ hspdif->RxXferSize = Size;\r
+ hspdif->RxXferCount = Size;\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* Check if a receive process is ongoing or not */\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;\r
+ \r
+ \r
+ /* Enable the SPDIFRX PE Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+ \r
+ /* Enable the SPDIFRX OVR Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ /* Enable the SPDIFRX RXNE interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Control Flow) with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample (Control Flow) to be received :\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->pCsBuffPtr = pData;\r
+ hspdif->CsXferSize = Size;\r
+ hspdif->CsXferCount = Size;\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* Check if a receive process is ongoing or not */\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;\r
+ \r
+ \r
+ /* Enable the SPDIFRX PE Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+ \r
+ /* Enable the SPDIFRX OVR Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ /* Enable the SPDIFRX CSRNE interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Data Flow) mode with DMA \r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be received :\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))\r
+ { \r
+ hspdif->pRxBuffPtr = pData;\r
+ hspdif->RxXferSize = Size;\r
+ hspdif->RxXferCount = Size;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;\r
+ \r
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */\r
+ hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;\r
+ \r
+ /* Set the SPDIFRX Rx DMA transfer complete callback */\r
+ hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;\r
+ \r
+ /* Enable the DMA request */\r
+ HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);\r
+ \r
+ /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/\r
+ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Control Flow) with DMA \r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data (Control Flow) sample to be received :\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ if((pData == NULL) || (Size == 0U)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))\r
+ { \r
+ hspdif->pCsBuffPtr = pData;\r
+ hspdif->CsXferSize = Size;\r
+ hspdif->CsXferCount = Size;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;\r
+ \r
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */\r
+ hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;\r
+ \r
+ /* Set the SPDIFRX Rx DMA transfer complete callback */\r
+ hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;\r
+ \r
+ /* Enable the DMA request */\r
+ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);\r
+ \r
+ /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/\r
+ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief stop the audio stream receive from the Media.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ /* Disable the SPDIFRX DMA requests */\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);\r
+ \r
+ /* Disable the SPDIFRX DMA channel */\r
+ __HAL_DMA_DISABLE(hspdif->hdmaDrRx);\r
+ __HAL_DMA_DISABLE(hspdif->hdmaCsRx);\r
+ \r
+ /* Disable SPDIFRX peripheral */\r
+ __HAL_SPDIFRX_IDLE(hspdif);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles SPDIFRX interrupt request.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval HAL status\r
+ */\r
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)\r
+{ \r
+ /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ SPDIFRX_ReceiveDataFlow_IT(hspdif);\r
+ }\r
+ \r
+ /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ SPDIFRX_ReceiveControlFlow_IT(hspdif);\r
+ }\r
+ \r
+ /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);\r
+ \r
+ /* Change the SPDIFRX error code */\r
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;\r
+ \r
+ /* the transfer is not stopped */\r
+ HAL_SPDIFRX_ErrorCallback(hspdif);\r
+ } \r
+ \r
+ /* SPDIFRX Parity error interrupt occurred ---------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);\r
+ \r
+ /* Change the SPDIFRX error code */\r
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;\r
+ \r
+ /* the transfer is not stopped */\r
+ HAL_SPDIFRX_ErrorCallback(hspdif);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer (Data flow) half completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspdif);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer (Data flow) completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspdif);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx (Control flow) Transfer half completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspdif);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer (Control flow) completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspdif);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SPDIFRX error callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspdif);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+##### Peripheral State and Errors functions #####\r
+=============================================================================== \r
+[..]\r
+This subsection permit to get in run-time the status of the peripheral \r
+and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the SPDIFRX state\r
+ * @param hspdif : SPDIFRX handle\r
+ * @retval HAL state\r
+ */\r
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ return hspdif->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the SPDIFRX error code\r
+ * @param hspdif : SPDIFRX handle\r
+ * @retval SPDIFRX Error Code\r
+ */\r
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ return hspdif->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Data flow) complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Rx DMA Request */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);\r
+ hspdif->RxXferCount = 0;\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY; \r
+ }\r
+ HAL_SPDIFRX_RxCpltCallback(hspdif); \r
+}\r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Data flow) half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ HAL_SPDIFRX_RxHalfCpltCallback(hspdif); \r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Control flow) complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Cb DMA Request */\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);\r
+ hspdif->CsXferCount = 0;\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_READY; \r
+ HAL_SPDIFRX_CxCpltCallback(hspdif); \r
+}\r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Control flow) half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ HAL_SPDIFRX_CxHalfCpltCallback(hspdif); \r
+}\r
+\r
+/**\r
+ * @brief DMA SPDIFRX communication error callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Rx and Cb DMA Request */\r
+ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));\r
+ hspdif->RxXferCount = 0;\r
+ \r
+ hspdif->State= HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Set the error code and execute error callback*/\r
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;\r
+ HAL_SPDIFRX_ErrorCallback(hspdif);\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Data Flow) with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Receive data */\r
+ (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;\r
+ hspdif->RxXferCount--;\r
+ \r
+ if(hspdif->RxXferCount == 0)\r
+ { \r
+ /* Disable RXNE/PE and OVR interrupts */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ HAL_SPDIFRX_RxCpltCallback(hspdif);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Control Flow) with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Receive data */\r
+ (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;\r
+ hspdif->CsXferCount--;\r
+ \r
+ if(hspdif->CsXferCount == 0)\r
+ { \r
+ /* Disable CSRNE interrupt */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ HAL_SPDIFRX_CxCpltCallback(hspdif);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SPDIFRX Communication Timeout.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param Flag: Flag checked\r
+ * @param Status: Value of the flag expected\r
+ * @param Timeout: Duration of the timeout\r
+ * @param tickstart: Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)\r
+{\r
+ /* Wait until flag is set */\r
+ if(Status == RESET)\r
+ {\r
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);\r
+ \r
+ hspdif->State= HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);\r
+ \r
+ hspdif->State= HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+* @}\r
+*/\r
+\r
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_spi.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SPI HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The SPI HAL driver can be used as follows:\r
+\r
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:\r
+ SPI_HandleTypeDef hspi;\r
+\r
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\r
+ (##) Enable the SPIx interface clock\r
+ (##) SPI pins configuration\r
+ (+++) Enable the clock for the SPI GPIOs\r
+ (+++) Configure these SPI pins as alternate function push-pull\r
+ (##) NVIC configuration if you need to use interrupt process\r
+ (+++) Configure the SPIx interrupt priority\r
+ (+++) Enable the NVIC SPI IRQ handle\r
+ (##) DMA Configuration if you need to use DMA process\r
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel\r
+ (+++) Enable the DMAx clock\r
+ (+++) Configure the DMA handle parameters\r
+ (+++) Configure the DMA Tx or Rx channel\r
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel\r
+\r
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\r
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\r
+\r
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customized HAL_SPI_MspInit() API.\r
+ [..]\r
+ Circular mode restriction:\r
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r
+ (##) Master 2Lines RxOnly\r
+ (##) Master 1Line Rx\r
+ (#) The CRC feature is not managed when the DMA circular mode is enabled\r
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\r
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI SPI\r
+ * @brief SPI HAL module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup SPI_Private_Constants SPI Private Constants\r
+ * @{\r
+ */\r
+#define SPI_DEFAULT_TIMEOUT 50\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup SPI_Private_Functions SPI Private Functions\r
+ * @{\r
+ */\r
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);\r
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);\r
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+#if (USE_SPI_CRC != 0U)\r
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+#endif\r
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\r
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);\r
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Functions SPI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and\r
+ de-initialize the SPIx peripheral:\r
+\r
+ (+) User must implement HAL_SPI_MspInit() function in which he configures\r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_SPI_Init() to configure the selected device with\r
+ the selected configuration:\r
+ (++) Mode\r
+ (++) Direction\r
+ (++) Data Size\r
+ (++) Clock Polarity and Phase\r
+ (++) NSS Management\r
+ (++) BaudRate Prescaler\r
+ (++) FirstBit\r
+ (++) TIMode\r
+ (++) CRC Calculation\r
+ (++) CRC Polynomial if CRC enabled\r
+ (++) CRC Length, used only with Data8 and Data16\r
+ (++) FIFO reception threshold\r
+\r
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration\r
+ of the selected SPIx peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the SPI according to the specified parameters\r
+ * in the SPI_InitTypeDef and initialize the associated handle.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\r
+{\r
+ uint32_t frxth;\r
+\r
+ /* Check the SPI handle allocation */\r
+ if(hspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));\r
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\r
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\r
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\r
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\r
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));\r
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\r
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\r
+#if (USE_SPI_CRC != 0U)\r
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\r
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));\r
+ }\r
+ /* Align the CRC Length on the data size */\r
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)\r
+ {\r
+ /* CRC Length aligned on the data size : value set by default */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;\r
+ }\r
+ else\r
+ {\r
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;\r
+ }\r
+ }\r
+#endif\r
+\r
+ if(hspi->State == HAL_SPI_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hspi->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+ HAL_SPI_MspInit(hspi);\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY;\r
+\r
+ /* Disable the selected SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+\r
+ /* Align by default the rs fifo threshold on the data size */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ frxth = SPI_RXFIFO_THRESHOLD_HF;\r
+ }\r
+ else\r
+ {\r
+ frxth = SPI_RXFIFO_THRESHOLD_QF;\r
+ }\r
+\r
+ /* CRC calculation is valid only for 16Bit and 8 Bit */\r
+ if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))\r
+ {\r
+ /* CRC must be disabled */\r
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
+ }\r
+\r
+ /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/\r
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,\r
+ Communication speed, First bit, CRC calculation state, CRC Length */\r
+ hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |\r
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\r
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);\r
+\r
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ {\r
+ hspi->Instance->CR1|= SPI_CR1_CRCL;\r
+ }\r
+\r
+ /* Configure : NSS management */\r
+ /* Configure : Rx Fifo Threshold */\r
+ hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |\r
+ hspi->Init.DataSize ) | frxth;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Configure : CRC Polynomial */\r
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);\r
+#endif\r
+\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->State= HAL_SPI_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the SPI peripheral.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Check the SPI handle allocation */\r
+ if(hspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY;\r
+\r
+ /* Disable the SPI Peripheral Clock */\r
+ __HAL_SPI_DISABLE(hspi);\r
+\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_SPI_MspDeInit(hspi);\r
+\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->State = HAL_SPI_STATE_RESET;\r
+\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SPI MSP Init\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_MspInit should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SPI MSP DeInit\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_MspDeInit should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the SPI\r
+ data transfers.\r
+\r
+ [..] The SPI supports master and slave mode :\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (++) No-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, These APIs return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\r
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmit an amount of data in blocking mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ /* Set the transaction information */\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = (uint8_t *)NULL;\r
+ hspi->RxXferSize = 0;\r
+ hspi->RxXferCount = 0;\r
+\r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_TX(hspi);\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Transmit data in 16 Bit mode */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* Transmit data in 16 Bit mode */\r
+ while (hspi->TxXferCount > 0)\r
+ {\r
+ /* Wait until TXE flag is set to send data */\r
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)\r
+ {\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Timeout management */\r
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))\r
+ {\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Transmit data in 8 Bit mode */\r
+ else\r
+ {\r
+ while (hspi->TxXferCount > 0)\r
+ {\r
+ /* Wait until TXE flag is set to send data */\r
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)\r
+ {\r
+ if(hspi->TxXferCount > 1)\r
+ {\r
+ /* write on the data register in packing mode */\r
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount -= 2;\r
+ }\r
+ else\r
+ {\r
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Timeout management */\r
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))\r
+ {\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Enable CRC Transmission */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;\r
+ }\r
+#endif\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+ {\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ }\r
+\r
+error:\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+#if (USE_SPI_CRC != 0U)\r
+ __IO uint16_t tmpreg;\r
+#endif\r
+ uint32_t tickstart = HAL_GetTick();\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
+ {\r
+ /* the receive process is not supported in 2Lines direction master mode */\r
+ /* in this case we call the TransmitReceive process */\r
+ /* Process Locked */\r
+ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ hspi->pTxBuffPtr = (uint8_t *)NULL;\r
+ hspi->TxXferSize = 0;\r
+ hspi->TxXferCount = 0;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ /* this is done to handle the CRCNEXT before the latest data */\r
+ hspi->RxXferCount--;\r
+ }\r
+#endif\r
+\r
+ /* Set the Rx Fido threshold */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+\r
+ /* Configure communication direction 1Line and enabled SPI if needed */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_RX(hspi);\r
+ }\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Receive data in 8 Bit mode */\r
+ if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)\r
+ {\r
+ /* Transfer loop */\r
+ while(hspi->RxXferCount > 0)\r
+ {\r
+ /* Check the RXNE flag */\r
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)\r
+ {\r
+ /* read the received data */\r
+ (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;\r
+ hspi->RxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Timeout management */\r
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))\r
+ {\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Transfer loop */\r
+ while(hspi->RxXferCount > 0)\r
+ {\r
+ /* Check the RXNE flag */\r
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)\r
+ {\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Timeout management */\r
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))\r
+ {\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Handle the CRC Transmission */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* freeze the CRC before the latest data */\r
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;\r
+\r
+ /* Read the latest data */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* the latest data has not been received */\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+\r
+ /* Receive last data in 16 Bit mode */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ }\r
+ /* Receive last data in 8 Bit mode */\r
+ else\r
+ {\r
+ *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ }\r
+\r
+ /* Wait until TXE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* Flag Error*/\r
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+\r
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
+ {\r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+ {\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ }\r
+ }\r
+#endif\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ }\r
+#endif\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ }\r
+\r
+error :\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Transmit and Receive an amount of data in blocking mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pTxData: pointer to transmission data buffer\r
+ * @param pRxData: pointer to reception data buffer\r
+ * @param Size: amount of data to be sent and received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+#if (USE_SPI_CRC != 0U)\r
+ __IO uint16_t tmpreg;\r
+#endif\r
+ uint32_t tickstart = HAL_GetTick();\r
+ /* Variable used to alternate Rx and Tx during transfer */\r
+ uint32_t txallowed = 1U;\r
+\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pRxData;\r
+ hspi->RxXferCount = Size;\r
+ hspi->RxXferSize = Size;\r
+ hspi->pTxBuffPtr = pTxData;\r
+ hspi->TxXferCount = Size;\r
+ hspi->TxXferSize = Size;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* Set the Rx Fifo threshold */\r
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Transmit and Receive data in 16 Bit mode */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))\r
+ {\r
+ /* Check TXE flag */\r
+ if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))\r
+ {\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+ /* Next Data is a reception (Rx). Tx not allowed */\r
+ txallowed = 0U;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Enable CRC Transmission */\r
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
+ if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
+ {\r
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
+ }\r
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+ }\r
+#endif\r
+ }\r
+ /* Check RXNE flag */\r
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))\r
+ {\r
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+ /* Next Data is a reception (Rx). Tx not allowed */\r
+ txallowed = 1U;\r
+ }\r
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ }\r
+ }\r
+ /* Transmit and Receive data in 8 Bit mode */\r
+ else\r
+ {\r
+ while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))\r
+ {\r
+ /* check TXE flag */\r
+ if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))\r
+ {\r
+ if(hspi->TxXferCount > 1)\r
+ {\r
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount -= 2;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--;\r
+ /* Next Data is a reception (Rx). Tx not allowed */\r
+ txallowed = 0U;\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Enable CRC Transmission */\r
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
+ if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
+ {\r
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
+ }\r
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+ }\r
+#endif\r
+ }\r
+\r
+ /* Wait until RXNE flag is reset */\r
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))\r
+ {\r
+ if(hspi->RxXferCount > 1)\r
+ {\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount -= 2;\r
+ if(hspi->RxXferCount <= 1)\r
+ {\r
+ /* set fiforxthreshold before to switch on 8 bit data size */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ hspi->RxXferCount--;\r
+ /* Next Data is a Transmission (Tx). Tx is allowed */\r
+ txallowed = 1U;\r
+ }\r
+ }\r
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ }\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Read CRC from DR to close CRC calculation process */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Wait until TXE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+\r
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
+ {\r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ {\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ errorcode = HAL_TIMEOUT;\r
+ goto error;\r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ /* Clear CRC Flag */\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+\r
+ errorcode = HAL_ERROR;\r
+ }\r
+#endif\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ }\r
+\r
+error :\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ /* prepare the transfer */\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = (uint8_t *)NULL;\r
+ hspi->RxXferSize = 0;\r
+ hspi->RxXferCount = 0;\r
+ hspi->RxISR = NULL;\r
+\r
+ /* Set the function for IT treatment */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r
+ {\r
+ hspi->TxISR = SPI_TxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ hspi->TxISR = SPI_TxISR_8BIT;\r
+ }\r
+\r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_TX(hspi);\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+error :\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ /* Configure communication */\r
+ hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ hspi->pTxBuffPtr = (uint8_t *)NULL;\r
+ hspi->TxXferSize = 0;\r
+ hspi->TxXferCount = 0;\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ /* the receive process is not supported in 2Lines direction master mode */\r
+ /* in this we call the TransmitReceive process */\r
+ return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);\r
+ }\r
+\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->CRCSize = 1;\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+ {\r
+ hspi->CRCSize = 2;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hspi->CRCSize = 0;\r
+ }\r
+\r
+ hspi->TxISR = NULL;\r
+ /* check the data size to adapt Rx threshold and the set the function for IT treatment */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16 bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ hspi->RxISR = SPI_RxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8 bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ hspi->RxISR = SPI_RxISR_8BIT;\r
+ }\r
+\r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_RX(hspi);\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+error :\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pTxData: pointer to transmission data buffer\r
+ * @param pRxData: pointer to reception data buffer\r
+ * @param Size: amount of data to be sent and received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(!((hspi->State == HAL_SPI_STATE_READY) || \\r
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ hspi->CRCSize = 0;\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->CRCSize = 1;\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+ {\r
+ hspi->CRCSize = 2;\r
+ }\r
+ }\r
+\r
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+ }\r
+\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pTxData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = pRxData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+\r
+ /* Set the function for IT treatment */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r
+ {\r
+ hspi->RxISR = SPI_2linesRxISR_16BIT;\r
+ hspi->TxISR = SPI_2linesTxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ hspi->RxISR = SPI_2linesRxISR_8BIT;\r
+ hspi->TxISR = SPI_2linesTxISR_8BIT;\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* check if packing mode is enabled and if there is more than 2 data to receive */\r
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16 bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8 bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+\r
+ /* Enable TXE, RXNE and ERR interrupt */\r
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+error :\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with DMA.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = (uint8_t *)NULL;\r
+ hspi->RxXferSize = 0;\r
+ hspi->RxXferCount = 0;\r
+\r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_TX(hspi);\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* Set the SPI TxDMA Half transfer complete callback */\r
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\r
+\r
+ /* Set the SPI TxDMA transfer complete callback */\r
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r
+\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ /* packing mode is enabled only if the DMA setting is HALWORD */\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r
+ {\r
+ /* Check the even/odd of the data size + crc if enabled */\r
+ if((hspi->TxXferCount & 0x1) == 0)\r
+ {\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = (hspi->TxXferCount >> 1);\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;\r
+ }\r
+ }\r
+\r
+ /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */\r
+ SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));\r
+ SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r
+\r
+ /* Enable the Tx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Enable Tx DMA Request */\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+error :\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with DMA.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ hspi->pTxBuffPtr = (uint8_t *)NULL;\r
+ hspi->TxXferSize = 0;\r
+ hspi->TxXferCount = 0;\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ /* the receive process is not supported in 2Lines direction master mode */\r
+ /* in this case we call the TransmitReceive process */\r
+ return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);\r
+ }\r
+\r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_RX(hspi);\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* packing mode management is enabled by the DMA settings */\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r
+ {\r
+ /* Restriction the DMA data received is not allowed in this mode */\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+ if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+\r
+ /* Set the SPI RxDMA Half transfer complete callback */\r
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
+\r
+ /* Set the SPI Rx DMA transfer complete callback */\r
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r
+\r
+ /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */\r
+ SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));\r
+ SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r
+\r
+ /* Enable Rx DMA Request */\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
+\r
+ /* Enable the Rx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+error:\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pTxData: pointer to transmission data buffer\r
+ * @param pRxData: pointer to reception data buffer\r
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef errorcode = HAL_OK;\r
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(!((hspi->State == HAL_SPI_STATE_READY) ||\r
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))\r
+ {\r
+ errorcode = HAL_BUSY;\r
+ goto error;\r
+ }\r
+\r
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))\r
+ {\r
+ errorcode = HAL_ERROR;\r
+ goto error;\r
+ }\r
+\r
+ /* check if the transmit Receive function is not called by a receive master */\r
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+ }\r
+\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Reset CRC Calculation + increase the rxsize */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+#endif\r
+\r
+ /* Reset the threshold bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);\r
+\r
+ /* the packing mode management is enabled by the DMA settings according the spi data size */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+\r
+ if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+ {\r
+ if((hspi->TxXferSize & 0x1) == 0x0)\r
+ {\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = hspi->TxXferCount >> 1;\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;\r
+ }\r
+ }\r
+\r
+ if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+\r
+ if((hspi->RxXferCount & 0x1) == 0x0 )\r
+ {\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+ hspi->RxXferCount = hspi->RxXferCount >> 1;\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+ hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Set the SPI Rx DMA transfer complete callback if the transfer request is a\r
+ reception request (RXNE) */\r
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)\r
+ {\r
+ /* Set the SPI Rx DMA Half transfer complete callback */\r
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
+ }\r
+ else\r
+ {\r
+ /* Set the SPI Rx DMA Half transfer complete callback */\r
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;\r
+ }\r
+\r
+ /* Set the DMA error callback */\r
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r
+\r
+ /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */\r
+ SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));\r
+ SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r
+\r
+ /* Enable Rx DMA Request */\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
+\r
+ /* Enable the Rx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);\r
+\r
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r
+ is performed in DMA reception complete callback */\r
+ hspi->hdmatx->XferHalfCpltCallback = NULL;\r
+ hspi->hdmatx->XferCpltCallback = NULL;\r
+\r
+ /* Set the DMA error callback */\r
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r
+\r
+ /* Enable the Tx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Enable Tx DMA Request */\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+error :\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return errorcode;\r
+}\r
+\r
+/**\r
+ * @brief Pause the DMA Transfer.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ /* Disable the SPI DMA Tx & Rx requests */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ /* Enable the SPI DMA Tx & Rx requests */\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\r
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\r
+ */\r
+\r
+ /* Abort the SPI DMA tx Stream */\r
+ if(hspi->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hspi->hdmatx);\r
+ }\r
+ /* Abort the SPI DMA rx Stream */\r
+ if(hspi->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hspi->hdmarx);\r
+ }\r
+\r
+ /* Disable the SPI DMA Tx & Rx requests */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles SPI interrupt request.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval None\r
+ */\r
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\r
+{\r
+ uint32_t itsource = hspi->Instance->CR2;\r
+ uint32_t itflag = hspi->Instance->SR;\r
+\r
+ /* SPI in mode Receiver ----------------------------------------------------*/\r
+ if(((itflag & SPI_FLAG_OVR) == RESET) &&\r
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))\r
+ {\r
+ hspi->RxISR(hspi);\r
+ return;\r
+ }\r
+\r
+ /* SPI in mode Transmitter ---------------------------------------------------*/\r
+ if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))\r
+ {\r
+ hspi->TxISR(hspi);\r
+ return;\r
+ }\r
+\r
+ /* SPI in Error Treatment ---------------------------------------------------*/\r
+ if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)\r
+ {\r
+ /* SPI Overrun error interrupt occurred -------------------------------------*/\r
+ if((itflag & SPI_FLAG_OVR) != RESET)\r
+ {\r
+ if(hspi->State != HAL_SPI_STATE_BUSY_TX)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_OVR;\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* SPI Mode Fault error interrupt occurred -------------------------------------*/\r
+ if((itflag & SPI_FLAG_MODF) != RESET)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_MODF;\r
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);\r
+ }\r
+\r
+ /* SPI Frame error interrupt occurred ----------------------------------------*/\r
+ if((itflag & SPI_FLAG_FRE) != RESET)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FRE;\r
+ __HAL_SPI_CLEAR_FREFLAG(hspi);\r
+ }\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ /* All SPI errors are treated as Blocking errors : transfer is aborted.\r
+ Set the SPI state to ready so as to be able to restart the process,\r
+ Disable Rx/Tx Interrupts, and disable DMA Rx/Tx requests, if ongoing */\r
+\r
+ /* Disable TXE, RXNE, MODF, OVR, FRE, and CRCERR (Master mode fault, Overrun error, TI frame format error, CRC protocol error) interrupts */\r
+ CLEAR_BIT(hspi->Instance->CR1, (SPI_CR2_RXNEIE | SPI_CR2_TXEIE | SPI_CR2_ERRIE));\r
+ CLEAR_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r
+\r
+ /* Restore SPI State to Ready */\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+ /* Disable the SPI DMA requests if enabled */\r
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))\r
+ {\r
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\r
+\r
+ /* Abort the SPI DMA Rx channel */\r
+ if(hspi->hdmarx != NULL)\r
+ {\r
+ /* Set the SPI DMA Abort callback :\r
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r
+\r
+ /* Abort DMA RX */\r
+ if(HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly hspi->hdmarx->XferAbortCallback function in case of error */\r
+ hspi->hdmarx->XferAbortCallback(hspi->hdmarx);\r
+ }\r
+ }\r
+ /* Abort the SPI DMA Tx channel */\r
+ if(hspi->hdmatx != NULL)\r
+ {\r
+ /* Set the SPI DMA Abort callback :\r
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r
+\r
+ /* Abort DMA TX */\r
+ if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly hspi->hdmatx->XferAbortCallback function in case of error */\r
+ hspi->hdmatx->XferAbortCallback(hspi->hdmatx);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callback.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callback.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_RxCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx and Rx Transfer completed callback.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callback.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callback.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx and Rx Half Transfer callback.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SPI error callback.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hspi);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_ErrorCallback should be implemented in the user file\r
+ */\r
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\r
+ and user can use HAL_SPI_GetError() API to check the latest error occurred\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ * @brief SPI control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the SPI.\r
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\r
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the SPI handle state.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval SPI state\r
+ */\r
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Return SPI handle state */\r
+ return hspi->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the SPI error code.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval SPI error code in bitmap format\r
+ */\r
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\r
+{\r
+ return hspi->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Private_Functions\r
+ * @brief Private functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA SPI transmit process complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal Mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable Tx DMA Request */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+ {\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+\r
+ hspi->TxXferCount = 0;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ return;\r
+ }\r
+ }\r
+ HAL_SPI_TxCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI receive process complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ __IO uint16_t tmpreg;\r
+ /* CRC handling */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Wait until TXE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ }\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ {\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ }\r
+ }\r
+#endif\r
+\r
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+ hspi->RxXferCount = 0;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ }\r
+#endif\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ return;\r
+ }\r
+ }\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI transmit receive process complete callback.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+#if (USE_SPI_CRC != 0U)\r
+ __IO uint16_t tmpreg;\r
+ /* CRC handling */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))\r
+ {\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ }\r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ }\r
+#endif\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+ /* Disable Rx/Tx DMA Request */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ hspi->TxXferCount = 0;\r
+ hspi->RxXferCount = 0;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ }\r
+#endif\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ return;\r
+ }\r
+ HAL_SPI_TxRxCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI half transmit process complete callback.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ HAL_SPI_TxHalfCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI half receive process complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ HAL_SPI_RxHalfCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI half transmit receive process complete callback.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ HAL_SPI_TxRxHalfCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI communication error callback.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* Stop the disable DMA transfer on SPI side */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_DMA;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_ErrorCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI communication abort callback\r
+ * (To be called at end of DMA Abort procedure).\r
+ * @param hdma: DMA handle.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hspi->RxXferCount = 0U;\r
+ hspi->TxXferCount = 0U;\r
+\r
+ HAL_SPI_ErrorCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Receive data in packing mode */\r
+ if(hspi->RxXferCount > 1)\r
+ {\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount -= 2;\r
+ if(hspi->RxXferCount == 1)\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ }\r
+ /* Receive data in 8 Bit mode */\r
+ else\r
+ {\r
+ *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);\r
+ hspi->RxXferCount--;\r
+ }\r
+\r
+ /* check end of the reception */\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;\r
+ return;\r
+ }\r
+#endif\r
+\r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ hspi->CRCSize--;\r
+\r
+ /* check end of the reception */\r
+ if(hspi->CRCSize == 0)\r
+ {\r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Transmit data in packing Bit mode */\r
+ if(hspi->TxXferCount >= 2)\r
+ {\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount -= 2;\r
+ }\r
+ /* Transmit data in 8 Bit mode */\r
+ else\r
+ {\r
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--;\r
+ }\r
+\r
+ /* check the end of the transmission */\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+#endif\r
+\r
+ /* Disable TXE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Receive data in 16 Bit mode */\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;\r
+ return;\r
+ }\r
+#endif\r
+\r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Receive data in 16 Bit mode */\r
+ __IO uint16_t tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ SPI_CloseRxTx_ISR(hspi);\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Transmit data in 16 Bit mode */\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+\r
+ /* Enable CRC Transmission */\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+#endif\r
+\r
+ /* Disable TXE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+ * @brief Manage the CRC 8-bit receive in Interrupt context.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ __IO uint8_t tmpreg;\r
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);\r
+\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ hspi->CRCSize--;\r
+\r
+ if(hspi->CRCSize == 0)\r
+ {\r
+ SPI_CloseRx_ISR(hspi);\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Manage the receive 8-bit in Interrupt context.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);\r
+ hspi->RxXferCount--;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Enable CRC Transmission */\r
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+#endif\r
+\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->RxISR = SPI_RxISR_8BITCRC;\r
+ return;\r
+ }\r
+#endif\r
+ SPI_CloseRx_ISR(hspi);\r
+ }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+ * @brief Manage the CRC 16-bit receive in Interrupt context.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ __IO uint16_t tmpreg;\r
+\r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ SPI_CloseRx_ISR(hspi);\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Manage the 16-bit receive in Interrupt context.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Enable CRC Transmission */\r
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+#endif\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->RxISR = SPI_RxISR_16BITCRC;\r
+ return;\r
+ }\r
+#endif\r
+ SPI_CloseRx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle the data 8-bit transmit in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--;\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Enable CRC Transmission */\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+#endif\r
+ SPI_CloseTx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle the data 16-bit transmit in Interrupt mode.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Transmit data in 16 Bit mode */\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+#if (USE_SPI_CRC != 0U)\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Enable CRC Transmission */\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+#endif\r
+ SPI_CloseTx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle SPI Communication Timeout.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param Flag : SPI flag to check\r
+ * @param State : flag state to check\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ while((hspi->Instance->SR & Flag) != State)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
+ on both master and slave sides in order to resynchronize the master\r
+ and slave for their respective CRC calculation */\r
+\r
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+ {\r
+ /* Disable SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+ }\r
+\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+\r
+ hspi->State= HAL_SPI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle SPI FIFO Communication Timeout.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param Fifo : Fifo to check\r
+ * @param State : Fifo state to check\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)\r
+{\r
+ __IO uint8_t tmpreg;\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ while((hspi->Instance->SR & Fifo) != State)\r
+ {\r
+ if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))\r
+ {\r
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
+ on both master and slave sides in order to resynchronize the master\r
+ and slave for their respective CRC calculation */\r
+\r
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+ {\r
+ /* Disable SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+ }\r
+\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle the check of the RX transaction complete.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param Timeout : Timeout duration\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)\r
+{\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+ {\r
+ /* Disable SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+ }\r
+\r
+ /* Control the BSY flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+ {\r
+ /* Empty the FRLVL fifo */\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle the check of the RXTX or TX transaction complete.\r
+ * @param hspi: SPI handle\r
+ * @param Timeout : Timeout duration\r
+ */\r
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)\r
+{\r
+ /* Procedure to check the transaction complete */\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Control the BSY flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle the end of the RXTX transaction.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Disable ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+#endif\r
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ {\r
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_TxRxCpltCallback(hspi);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+#if (USE_SPI_CRC != 0U)\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Handle the end of the RX transaction.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r
+ }\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+#if (USE_SPI_CRC != 0U)\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+#endif\r
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+#if (USE_SPI_CRC != 0U)\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Handle the end of the TX transaction.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Disable TXE and ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r
+ }\r
+\r
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+ {\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ HAL_SPI_TxCpltCallback(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sram.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SRAM HAL module driver.\r
+ * This file provides a generic firmware to drive SRAM memories \r
+ * mounted as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control SRAM memories. It uses the FMC layer functions to interface \r
+ with SRAM devices. \r
+ The following sequence should be followed to configure the FMC to interface\r
+ with SRAM/PSRAM memories: \r
+ \r
+ (#) Declare a SRAM_HandleTypeDef handle structure, for example:\r
+ SRAM_HandleTypeDef hsram; and: \r
+ \r
+ (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed \r
+ values of the structure member.\r
+ \r
+ (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined \r
+ base register instance for NOR or SRAM device \r
+ \r
+ (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined\r
+ base register instance for NOR or SRAM extended mode \r
+ \r
+ (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended \r
+ mode timings; for example:\r
+ FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;\r
+ and fill its fields with the allowed values of the structure member.\r
+ \r
+ (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function\r
+ performs the following sequence:\r
+ \r
+ (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()\r
+ (##) Control register configuration using the FMC NORSRAM interface function \r
+ FMC_NORSRAM_Init()\r
+ (##) Timing register configuration using the FMC NORSRAM interface function \r
+ FMC_NORSRAM_Timing_Init()\r
+ (##) Extended mode Timing register configuration using the FMC NORSRAM interface function \r
+ FMC_NORSRAM_Extended_Timing_Init()\r
+ (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() \r
+\r
+ (#) At this stage you can perform read/write accesses from/to the memory connected \r
+ to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the\r
+ following APIs:\r
+ (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access\r
+ (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer\r
+ \r
+ (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/\r
+ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation \r
+ \r
+ (#) You can continuously monitor the SRAM device HAL state by calling the function\r
+ HAL_SRAM_GetState() \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SRAM SRAM \r
+ * @brief SRAM driver modules\r
+ * @{\r
+ */\r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions.\r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SRAM Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to initialize/de-initialize\r
+ the SRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Performs the SRAM device initialization sequence\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param Timing: Pointer to SRAM control timing structure \r
+ * @param ExtTiming: Pointer to SRAM extended mode timing structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)\r
+{ \r
+ /* Check the SRAM handle parameter */\r
+ if(hsram == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hsram->State == HAL_SRAM_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hsram->Lock = HAL_UNLOCKED;\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SRAM_MspInit(hsram);\r
+ }\r
+ \r
+ /* Initialize SRAM control Interface */\r
+ FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));\r
+\r
+ /* Initialize SRAM timing Interface */\r
+ FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); \r
+\r
+ /* Initialize SRAM extended mode timing Interface */\r
+ FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); \r
+ \r
+ /* Enable the NORSRAM device */\r
+ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Performs the SRAM device De-initialization sequence.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)\r
+{ \r
+ /* De-Initialize the low level hardware (MSP) */\r
+ HAL_SRAM_MspDeInit(hsram);\r
+ \r
+ /* Configure the SRAM registers with their reset values */\r
+ FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);\r
+\r
+ hsram->State = HAL_SRAM_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsram);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SRAM MSP Init.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsram);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SRAM MSP DeInit.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hsram);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback.\r
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete error callback.\r
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hdma);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SRAM Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the SRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads 8-bit buffer from SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Read data from memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint8_t *)psramaddress;\r
+ pDstBuffer++;\r
+ psramaddress++;\r
+ }\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 8-bit buffer to SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;\r
+ \r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+\r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint8_t *)psramaddress = *pSrcBuffer; \r
+ pSrcBuffer++;\r
+ psramaddress++; \r
+ } \r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads 16-bit buffer from SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Read data from memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint16_t *)psramaddress;\r
+ pDstBuffer++;\r
+ psramaddress++;\r
+ }\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 16-bit buffer to SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress; \r
+ \r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+\r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint16_t *)psramaddress = *pSrcBuffer; \r
+ pSrcBuffer++;\r
+ psramaddress++; \r
+ } \r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads 32-bit buffer from SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Read data from memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint32_t *)pAddress;\r
+ pDstBuffer++;\r
+ pAddress++;\r
+ }\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 32-bit buffer to SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+\r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint32_t *)pAddress = *pSrcBuffer; \r
+ pSrcBuffer++;\r
+ pAddress++; \r
+ } \r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads a Words data from the SRAM memory using DMA transfer.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram); \r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;\r
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;\r
+\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes a Words data buffer to SRAM memory using DMA transfer.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;\r
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;\r
+\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions \r
+ * @brief Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the SRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables dynamically SRAM write operation.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+\r
+ /* Enable write operation */\r
+ FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); \r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically SRAM write operation.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY;\r
+ \r
+ /* Disable write operation */\r
+ FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); \r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_PROTECTED;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SRAM State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the SRAM controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Returns the SRAM controller state\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)\r
+{\r
+ return hsram->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Timer (TIM) peripheral:\r
+ * + Time Base Initialization\r
+ * + Time Base Start\r
+ * + Time Base Start Interruption\r
+ * + Time Base Start DMA\r
+ * + Time Output Compare/PWM Initialization\r
+ * + Time Output Compare/PWM Channel Configuration\r
+ * + Time Output Compare/PWM Start\r
+ * + Time Output Compare/PWM Start Interruption\r
+ * + Time Output Compare/PWM Start DMA\r
+ * + Time Input Capture Initialization\r
+ * + Time Input Capture Channel Configuration\r
+ * + Time Input Capture Start\r
+ * + Time Input Capture Start Interruption \r
+ * + Time Input Capture Start DMA\r
+ * + Time One Pulse Initialization\r
+ * + Time One Pulse Channel Configuration\r
+ * + Time One Pulse Start \r
+ * + Time Encoder Interface Initialization\r
+ * + Time Encoder Interface Start\r
+ * + Time Encoder Interface Start Interruption\r
+ * + Time Encoder Interface Start DMA\r
+ * + Commutation Event configuration with Interruption and DMA\r
+ * + Time OCRef clear configuration\r
+ * + Time External Clock configuration\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### TIMER Generic features #####\r
+ ==============================================================================\r
+ [..] The Timer features include: \r
+ (#) 16-bit up, down, up/down auto-reload counter.\r
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the \r
+ counter clock frequency either by any factor between 1 and 65536.\r
+ (#) Up to 4 independent channels for:\r
+ (++) Input Capture\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions \r
+ depending from feature used :\r
+ (++) Time Base : HAL_TIM_Base_MspInit() \r
+ (++) Input Capture : HAL_TIM_IC_MspInit()\r
+ (++) Output Compare : HAL_TIM_OC_MspInit()\r
+ (++) PWM generation : HAL_TIM_PWM_MspInit()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
+ \r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); \r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __GPIOx_CLK_ENABLE(); \r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); \r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the \r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before \r
+ any start function.\r
+ \r
+ (#) Configure the TIM in the desired functioning mode using one of the \r
+ initialization function of this driver:\r
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an \r
+ Output Compare signal.\r
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a \r
+ PWM signal.\r
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an \r
+ external signal.\r
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer \r
+ in One Pulse Mode.\r
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
+ \r
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used: \r
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
+\r
+ (#) The DMA Burst is managed with the two following functions:\r
+ HAL_TIM_DMABurst_WriteStart()\r
+ HAL_TIM_DMABurst_ReadStart()\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM TIM\r
+ * @brief TIM HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef * sSlaveConfig);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions \r
+ * @brief Time Base functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Base functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM base. \r
+ (+) De-initialize the TIM base.\r
+ (+) Start the Time Base.\r
+ (+) Stop the Time Base.\r
+ (+) Start the Time Base and enable interrupt.\r
+ (+) Stop the Time Base and disable interrupt.\r
+ (+) Start the Time Base and enable DMA transfer.\r
+ (+) Stop the Time Base and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Time base Unit according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
+{ \r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance)); \r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ \r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Set the Time Base configuration */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Base peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Base MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Base MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Change the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the TIM Update interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ /* Disable the TIM Update interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); \r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);\r
+ \r
+ /* Enable the TIM Update DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions \r
+ * @brief Time Output Compare functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Output Compare functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Output Compare. \r
+ (+) De-initialize the TIM Output Compare.\r
+ (+) Start the Time Output Compare.\r
+ (+) Stop the Time Output Compare.\r
+ (+) Start the Time Output Compare and enable interrupt.\r
+ (+) Stop the Time Output Compare and disable interrupt.\r
+ (+) Start the Time Output Compare and enable DMA transfer.\r
+ (+) Stop the Time Output Compare and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Output Compare according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ \r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Init the base time for the Output Compare */ \r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Output Compare MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module. \r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ } \r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ } \r
+ \r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ } \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions \r
+ * @brief Time PWM functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time PWM functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM OPWM. \r
+ (+) De-initialize the TIM PWM.\r
+ (+) Start the Time PWM.\r
+ (+) Stop the Time PWM.\r
+ (+) Start the Time PWM and enable interrupt.\r
+ (+) Stop the Time PWM and disable interrupt.\r
+ (+) Start the Time PWM and enable DMA transfer.\r
+ (+) Stop the Time PWM and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM PWM Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+\r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspInit(htim);\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Init the base time for the PWM */ \r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM PWM MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Output Capture/Compare 3 request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions \r
+ * @brief Time Input Capture functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Input Capture functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Input Capture. \r
+ (+) De-initialize the TIM Input Capture.\r
+ (+) Start the Time Input Capture.\r
+ (+) Stop the Time Input Capture.\r
+ (+) Start the Time Input Capture and enable interrupt.\r
+ (+) Stop the Time Input Capture and disable interrupt.\r
+ (+) Start the Time Input Capture and enable DMA transfer.\r
+ (+) Stop the Time Input Capture and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Input Capture Time base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); \r
+\r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Init the base time for the input capture */ \r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM INput Capture MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Input Capture MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+\r
+ /* Return function status */\r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+\r
+ /* Return function status */\r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ } \r
+ \r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement on in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The destination Buffer address.\r
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); \r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */ \r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement on in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions \r
+ * @brief Time One Pulse functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time One Pulse functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM One Pulse. \r
+ (+) De-initialize the TIM One Pulse.\r
+ (+) Start the Time One Pulse.\r
+ (+) Stop the Time One Pulse.\r
+ (+) Start the Time One Pulse and enable interrupt.\r
+ (+) Stop the Time One Pulse and disable interrupt.\r
+ (+) Start the Time One Pulse and enable DMA transfer.\r
+ (+) Stop the Time One Pulse and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM One Pulse Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OnePulseMode: Select the One pulse mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
+ \r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OnePulse_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Configure the Time base in the One Pulse Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+ \r
+ /* Reset the OPM Bit */\r
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
+\r
+ /* Configure the OPM Mode */\r
+ htim->Instance->CR1 |= OnePulseMode;\r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM One Pulse \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_OnePulse_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM One Pulse MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Enable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r
+ \r
+ No need to enable the counter, it's enabled automatically by hardware \r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Disable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Enable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r
+ \r
+ No need to enable the counter, it's enabled automatically by hardware \r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+ \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); \r
+ \r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ /* Disable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions \r
+ * @brief Time Encoder functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Encoder functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Encoder. \r
+ (+) De-initialize the TIM Encoder.\r
+ (+) Start the Time Encoder.\r
+ (+) Stop the Time Encoder.\r
+ (+) Start the Time Encoder and enable interrupt.\r
+ (+) Stop the Time Encoder and disable interrupt.\r
+ (+) Start the Time Encoder and enable DMA transfer.\r
+ (+) Stop the Time Encoder and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Encoder Interface configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
+\r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED; \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_Encoder_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Reset the SMS bits */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ \r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = htim->Instance->CCER;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr |= sConfig->EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));\r
+ \r
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);\r
+ tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);\r
+ \r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+\r
+ /* Write to TIMx CCER */\r
+ htim->Instance->CCER = tmpccer;\r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Encoder interface \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Encoder_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Encoder Interface MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the encoder interface channels */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break; \r
+ }\r
+ case TIM_CHANNEL_2:\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r
+ break;\r
+ } \r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break; \r
+ }\r
+ } \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ break; \r
+ }\r
+ case TIM_CHANNEL_2:\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ break;\r
+ } \r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break; \r
+ }\r
+ } \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the encoder interface channels */\r
+ /* Enable the capture compare Interrupts 1 and/or 2 */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break; \r
+ }\r
+ case TIM_CHANNEL_2:\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); \r
+ break;\r
+ } \r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break; \r
+ }\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r
+ if(Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts 1 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ } \r
+ else if(Channel == TIM_CHANNEL_2)\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ } \r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts 1 and 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @param pData1: The destination Buffer address for IC1.\r
+ * @param pData2: The destination Buffer address for IC2.\r
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); \r
+ \r
+ /* Enable the TIM Input Capture DMA request */ \r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r
+ \r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_ALL:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);\r
+ \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r
+ if(Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare DMA Request 1 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ } \r
+ else if(Channel == TIM_CHANNEL_2)\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare DMA Request 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ } \r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare DMA Request 1 and 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management \r
+ * @brief IRQ handler management \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IRQ handler management #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides Timer IRQ handler function.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles TIM interrupts requests.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Capture compare 1 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)\r
+ {\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ \r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)\r
+ {\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ }\r
+ /* Capture compare 2 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)\r
+ { \r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 3 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)\r
+ { \r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim); \r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 4 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)\r
+ { \r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* TIM Update event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+ }\r
+ }\r
+ /* TIM Break input event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
+ HAL_TIMEx_BreakCallback(htim);\r
+ }\r
+ }\r
+ \r
+ /* TIM Break input event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
+ HAL_TIMEx_BreakCallback(htim);\r
+ }\r
+ }\r
+\r
+ /* TIM Trigger detection event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
+ HAL_TIM_TriggerCallback(htim);\r
+ }\r
+ }\r
+ /* TIM commutation event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r
+ HAL_TIMEx_CommutationCallback(htim);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. \r
+ (+) Configure External Clock source.\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master and the Slave synchronization.\r
+ (+) Configure the DMA Burst Mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the TIM Output Compare Channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Output Compare configuration structure\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim); \r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 1 in Output Compare */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 2 in Output Compare */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 3 in Output Compare */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 4 in Output Compare */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture Channels according to the specified\r
+ * parameters in the TIM_IC_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Input Capture configuration structure\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TIM_TI1_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI2_SetConfig(htim->Instance, \r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Set the IC2PSC value */\r
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI3_SetConfig(htim->Instance, \r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC3PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
+\r
+ /* Set the IC3PSC value */\r
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI4_SetConfig(htim->Instance, \r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC4PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
+\r
+ /* Set the IC4PSC value */\r
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);\r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM PWM configuration structure\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ __HAL_LOCK(htim);\r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); \r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 1 in PWM mode */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 2 in PWM mode */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 3 in PWM mode */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 4 in PWM mode */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; \r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse Channels according to the specified\r
+ * parameters in the TIM_OnePulse_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM One Pulse configuration structure\r
+ * @param OutputChannel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @param InputChannel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)\r
+{\r
+ TIM_OC_InitTypeDef temp1;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
+\r
+ if(OutputChannel != InputChannel) \r
+ {\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Extract the Output compare configuration from sConfig structure */ \r
+ temp1.OCMode = sConfig->OCMode;\r
+ temp1.Pulse = sConfig->Pulse;\r
+ temp1.OCPolarity = sConfig->OCPolarity;\r
+ temp1.OCNPolarity = sConfig->OCNPolarity;\r
+ temp1.OCIdleState = sConfig->OCIdleState;\r
+ temp1.OCNIdleState = sConfig->OCNIdleState; \r
+ \r
+ switch (OutputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ \r
+ TIM_OC1_SetConfig(htim->Instance, &temp1); \r
+ }\r
+ break;\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ TIM_OC2_SetConfig(htim->Instance, &temp1);\r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ } \r
+ switch (InputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
+ \r
+ /* Select the Slave Mode */ \r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ }\r
+ break;\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
+ \r
+ /* Select the Slave Mode */ \r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMABASE_CR1 \r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT \r
+ * @arg TIM_DMABASE_PSC \r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3 \r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_DCR\r
+ * @param BurstRequestSrc: TIM DMA Request sources.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer: The Buffer address.\r
+ * @param BurstLength: DMA Burst length. This parameter can be one value\r
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t* BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((BurstBuffer == 0 ) && (BurstLength > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = BurstBaseAddress | BurstLength; \r
+ \r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); \r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM DMA Burst mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstRequestSrc: TIM DMA Request sources to disable\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ \r
+ /* Abort the DMA transfer (at least disable the DMA channel) */\r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMABASE_CR1 \r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT \r
+ * @arg TIM_DMABASE_PSC \r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3 \r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_DCR\r
+ * @param BurstRequestSrc: TIM DMA Request sources.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer: The Buffer address.\r
+ * @param BurstLength: DMA Burst length. This parameter can be one value\r
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((BurstBuffer == 0 ) && (BurstLength > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = BurstBaseAddress | BurstLength; \r
+ \r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA burst reading \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstRequestSrc: TIM DMA Request sources to disable.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ \r
+ /* Abort the DMA transfer (at least disable the DMA channel) */\r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Generate a software event\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param EventSource: specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source \r
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source \r
+ * @note TIM6 and TIM7 can only generate an update event. \r
+ * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.\r
+ * @retval HAL status\r
+ */ \r
+\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Set the event sources */\r
+ htim->Instance->EGR = EventSource;\r
+ \r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Configures the OCRef clear feature\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that\r
+ * contains the OCREF clear feature and parameters for the TIM peripheral. \r
+ * @param Channel: specifies the TIM Channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */ \r
+__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)\r
+ {\r
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+ \r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sClearInputConfig->ClearInputPrescaler,\r
+ sClearInputConfig->ClearInputPolarity,\r
+ sClearInputConfig->ClearInputFilter);\r
+ }\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_2: \r
+ { \r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_3: \r
+ { \r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_4: \r
+ { \r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; \r
+ }\r
+ } \r
+ break;\r
+ default: \r
+ break;\r
+ } \r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Configures the clock source to be used\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that\r
+ * contains the clock source information for the TIM peripheral. \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) \r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
+ \r
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ \r
+ switch (sClockSourceConfig->ClockSource)\r
+ {\r
+ case TIM_CLOCKSOURCE_INTERNAL:\r
+ { \r
+ assert_param(IS_TIM_INSTANCE(htim->Instance)); \r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLOCKSOURCE_ETRMODE1:\r
+ {\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sClockSourceConfig->ClockPrescaler, \r
+ sClockSourceConfig->ClockPolarity, \r
+ sClockSourceConfig->ClockFilter);\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ /* Reset the SMS and TS Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+ /* Select the External clock mode1 and the ETRF trigger */\r
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLOCKSOURCE_ETRMODE2:\r
+ {\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sClockSourceConfig->ClockPrescaler, \r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ /* Enable the External clock mode2 */\r
+ htim->Instance->SMCR |= TIM_SMCR_ECE;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLOCKSOURCE_TI1:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+ \r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI1_ConfigInputStage(htim->Instance, \r
+ sClockSourceConfig->ClockPolarity, \r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_TI2:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+ \r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI2_ConfigInputStage(htim->Instance, \r
+ sClockSourceConfig->ClockPolarity, \r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_TI1ED:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+ \r
+ TIM_TI1_ConfigInputStage(htim->Instance, \r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR0:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR1:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR2:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR3:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input\r
+ * or a XOR combination between CH1_input, CH2_input & CH3_input\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param TI1_Selection: Indicate whether or not channel 1 is connected to the\r
+ * output of a XOR gate.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
+ * pins are connected to the TI1 input (XOR combination)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
+{\r
+ uint32_t tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); \r
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Reset the TI1 selection */\r
+ tmpcr2 &= ~TIM_CR2_TI1S;\r
+\r
+ /* Set the TI1 selection */\r
+ tmpcr2 |= TI1_Selection;\r
+ \r
+ /* Write to TIMxCR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the ) and the Slave \r
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the Trigger Selection Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+ /* Reset the slave mode Bits */\r
+ tmpsmcr &= ~TIM_SMCR_SMS;\r
+ /* Set the slave mode */\r
+ tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ \r
+ /* Configure the trigger prescaler, filter, and polarity */\r
+ switch (sSlaveConfig->InputTrigger)\r
+ {\r
+ case TIM_TS_ETRF:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ /* Configure the ETR Trigger source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sSlaveConfig->TriggerPrescaler, \r
+ sSlaveConfig->TriggerPolarity, \r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1F_ED:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = htim->Instance->CCER;\r
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = htim->Instance->CCMR1; \r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+ htim->Instance->CCER = tmpccer; \r
+ \r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1FP1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI1 Filter and Polarity */\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI2FP2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Configure TI2 Filter and Polarity */\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR0:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR1:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR2:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR3:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode in interrupt mode\r
+ * @param htim: TIM handle.\r
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the ) and the Slave \r
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, \r
+ TIM_SlaveConfigTypeDef * sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);\r
+ \r
+ /* Enable Trigger Interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
+ \r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read the captured value from Capture Compare unit\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval Captured value\r
+ */\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 1 value */\r
+ tmpreg = htim->Instance->CCR1;\r
+ \r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 2 value */\r
+ tmpreg = htim->Instance->CCR2;\r
+ \r
+ break;\r
+ }\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 3 value */\r
+ tmpreg = htim->Instance->CCR3;\r
+ \r
+ break;\r
+ }\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 4 value */\r
+ tmpreg = htim->Instance->CCR4;\r
+ \r
+ break;\r
+ }\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### TIM Callbacks functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides TIM callback functions:\r
+ (+) Timer Period elapsed callback\r
+ (+) Timer Output Compare callback\r
+ (+) Timer Input capture callback\r
+ (+) Timer Trigger callback\r
+ (+) Timer Error callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Period elapsed callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
+ */\r
+ \r
+}\r
+/**\r
+ * @brief Output Compare callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+/**\r
+ * @brief Input Capture callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Timer error callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Base state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM OC state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM PWM state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Input Capture state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM One Pulse Mode state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Encoder Mode state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ HAL_TIM_ErrorCallback(htim);\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY; \r
+ \r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+/**\r
+ * @brief TIM DMA Capture complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY; \r
+ \r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ \r
+ HAL_TIM_IC_CaptureCallback(htim); \r
+ \r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; \r
+ \r
+ htim->State= HAL_TIM_STATE_READY; \r
+ \r
+ HAL_TIM_TriggerCallback(htim);\r
+}\r
+\r
+/**\r
+ * @brief Time Base configuration\r
+ * @param TIMx: TIM peripheral\r
+ * @param Structure: pointer on TIM Time Base required parameters \r
+ * @retval None\r
+ */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
+{\r
+ uint32_t tmpcr1 = 0;\r
+ tmpcr1 = TIMx->CR1;\r
+ \r
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
+ if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) \r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
+ tmpcr1 |= Structure->CounterMode;\r
+ }\r
+ \r
+ if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) \r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= ~TIM_CR1_CKD;\r
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Auto-reload value */\r
+ TIMx->ARR = (uint32_t)Structure->Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = (uint32_t)Structure->Prescaler;\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) \r
+ {\r
+ /* Set the Repetition Counter value */\r
+ TIMx->RCR = Structure->RepetitionCounter;\r
+ }\r
+\r
+ /* Generate an update event to reload the Prescaler \r
+ and the repetition counter(only for TIM1 and TIM8) value immediately */\r
+ TIMx->EGR = TIM_EGR_UG;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 1 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC1M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC1S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= OC_Config->OCPolarity;\r
+\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ { \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= OC_Config->OCNPolarity;\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC1NE;\r
+ \r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS1;\r
+ tmpcr2 &= ~TIM_CR2_OIS1N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= OC_Config->OCIdleState;\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= OC_Config->OCNIdleState;\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer; \r
+} \r
+\r
+/**\r
+ * @brief Time Output Compare 2 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0;\r
+ \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC2M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC2S;\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 4);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 4);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC2NE;\r
+ \r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS2;\r
+ tmpcr2 &= ~TIM_CR2_OIS2N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 2);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 2);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 3 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the Channel 3: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC3M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC3S; \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 8);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 8);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC3NE;\r
+ \r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS3;\r
+ tmpcr2 &= ~TIM_CR2_OIS3N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 4);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 4);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 4 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC4M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC4S;\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC4P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 12);\r
+ \r
+ /*if((TIMx == TIM1) || (TIMx == TIM8))*/\r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ {\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS4;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 6);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 4 configuration\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sSlaveConfig: The slave configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef * sSlaveConfig)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the Trigger Selection Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+ /* Reset the slave mode Bits */\r
+ tmpsmcr &= ~TIM_SMCR_SMS;\r
+ /* Set the slave mode */\r
+ tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ \r
+ /* Configure the trigger prescaler, filter, and polarity */\r
+ switch (sSlaveConfig->InputTrigger)\r
+ {\r
+ case TIM_TS_ETRF:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ /* Configure the ETR Trigger source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sSlaveConfig->TriggerPrescaler, \r
+ sSlaveConfig->TriggerPolarity, \r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1F_ED:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = htim->Instance->CCER;\r
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = htim->Instance->CCMR1; \r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+ htim->Instance->CCER = tmpccer; \r
+ \r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1FP1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI1 Filter and Polarity */\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI2FP2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Configure TI2 Filter and Polarity */\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR0:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR1:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR2:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR3:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None \r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 \r
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
+ {\r
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
+ tmpccmr1 |= TIM_ICSelection;\r
+ } \r
+ else\r
+ {\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
+ }\r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI1.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = TIMx->CCER;\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1; \r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= (TIM_ICFilter << 4);\r
+ \r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_ICPolarity;\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 \r
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
+ tmpccmr1 |= (TIM_ICSelection << 8);\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI2.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= (TIM_ICFilter << 12);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= (TIM_ICPolarity << 4);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 \r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
+ tmpccmr2 |= TIM_ICSelection;\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);\r
+\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r
+ tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 \r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
+ tmpccmr2 |= (TIM_ICSelection << 8);\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r
+ tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ITRx: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source and the slave mode*/\r
+ tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));\r
+\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param ChannelState: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); \r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+\r
+ tmp = TIM_CCER_CC1E << Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim_ex.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Timer extension peripheral:\r
+ * + Time Hall Sensor Interface Initialization\r
+ * + Time Hall Sensor Interface Start\r
+ * + Time Complementary signal bread and dead time configuration \r
+ * + Time Master and Slave synchronization configuration\r
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)\r
+ * + Time OCRef clear configuration\r
+ * + Timer remapping capabilities configuration \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### TIMER Extended features #####\r
+ ==============================================================================\r
+ [..] \r
+ The Timer Extension features include: \r
+ (#) Complementary outputs with programmable dead-time for :\r
+ (++) Input Capture\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output\r
+ (#) Synchronization circuit to control the timer with external signals and to \r
+ interconnect several timers together.\r
+ (#) Break input to put the timer output signals in reset state or in a known state.\r
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for \r
+ positioning purposes \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions \r
+ depending from feature used :\r
+ (++) Complementary Output Compare : HAL_TIM_OC_MspInit()\r
+ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()\r
+ (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+ (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()\r
+ \r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); \r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __GPIOx_CLK_ENABLE(); \r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); \r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the \r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before \r
+ any start function.\r
+ \r
+ (#) Configure the TIM in the desired functioning mode using one of the \r
+ initialization function of this driver:\r
+ (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the \r
+ Timer Hall Sensor Interface and the commutation event with the corresponding \r
+ Interrupt and DMA request if needed (Note that One Timer is used to interface \r
+ with the Hall sensor Interface and another Timer should be used to use \r
+ the commutation event).\r
+\r
+ (#) Activate the TIM peripheral using one of the start functions: \r
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()\r
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r
+\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx TIMEx\r
+ * @brief TIM Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define BDTR_BKF_SHIFT (16)\r
+#define BDTR_BK2F_SHIFT (20)\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup TIMEx_Private_Functions\r
+ * @{\r
+ */\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); \r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+ * @brief Timer Hall Sensor functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Hall Sensor functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure TIM HAL Sensor. \r
+ (+) De-initialize TIM HAL Sensor.\r
+ (+) Start the Hall Sensor Interface.\r
+ (+) Stop the Hall Sensor Interface.\r
+ (+) Start the Hall Sensor Interface and enable interrupts.\r
+ (+) Stop the Hall Sensor Interface and disable interrupts.\r
+ (+) Start the Hall Sensor Interface and enable DMA transfers.\r
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Hall Sensor configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)\r
+{\r
+ TIM_OC_InitTypeDef OC_Config;\r
+ \r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+\r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIMEx_HallSensor_MspInit(htim);\r
+ \r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+ \r
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */\r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r
+ \r
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */\r
+ htim->Instance->CR2 |= TIM_CR2_TI1S;\r
+ \r
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r
+ \r
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ \r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r
+ \r
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
+ OC_Config.OCMode = TIM_OCMODE_PWM2;\r
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
+ OC_Config.Pulse = sConfig->Commutation_Delay; \r
+ \r
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r
+ \r
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r
+ register to 101 */\r
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF; \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Hall Sensor interface \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIMEx_HallSensor_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Hall Sensor MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall sensor Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1, 2 and 3\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Enable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts event */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param pData: The destination Buffer address.\r
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ /* Enable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ \r
+ /* Set the DMA Input Capture 1 Callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream for Capture 1*/\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); \r
+ \r
+ /* Enable the capture compare 1 Interrupt */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ \r
+ /* Disable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+ * @brief Timer Complementary Output Compare functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Complementary Output Compare functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary Output Compare/PWM.\r
+ (+) Stop the Complementary Output Compare/PWM.\r
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.\r
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module. \r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+ \r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer = 0; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+{\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+ * @brief Timer Complementary PWM functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Complementary PWM functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary PWM.\r
+ (+) Stop the Complementary PWM.\r
+ (+) Start the Complementary PWM and enable interrupts.\r
+ (+) Stop the Complementary PWM and disable interrupts.\r
+ (+) Start the Complementary PWM and enable DMA transfers.\r
+ (+) Stop the Complementary PWM and disable DMA transfers.\r
+ (+) Start the Complementary Input Capture measurement.\r
+ (+) Stop the Complementary Input Capture.\r
+ (+) Start the Complementary Input Capture and enable interrupts.\r
+ (+) Stop the Complementary Input Capture and disable interrupts.\r
+ (+) Start the Complementary Input Capture and enable DMA transfers.\r
+ (+) Stop the Complementary Input Capture and disable DMA transfers.\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); \r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode on the \r
+ * complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+ \r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode on the \r
+ * complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode on the \r
+ * complementary output\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary\r
+ * output\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+ * @brief Timer Complementary One Pulse functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Complementary One Pulse functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation on the complemetary \r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+ \r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); \r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation on the complementary \r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+\r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); \r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ } \r
+ \r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. \r
+ (+) Configure External Clock source.\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master and the Slave synchronization.\r
+ (+) Configure the commutation event in case of use of the Hall sensor interface.\r
+ (+) Configure the DMA Burst Mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Configure the TIM commutation event sequence.\r
+ * @note This function is mandatory to use the commutation event in order to \r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer) \r
+ * configured in Hall sensor interface, this interface Timer will generate the \r
+ * commutation at its TRGO output (connected to Timer used in this function) each time \r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed \r
+ * @param CommutationSource: the Commutation Event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ { \r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+ \r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with interrupt.\r
+ * @note This function is mandatory to use the commutation event in order to \r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer) \r
+ * configured in Hall sensor interface, this interface Timer will generate the \r
+ * commutation at its TRGO output (connected to Timer used in this function) each time \r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource: the Commutation Event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ { \r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+ \r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+ \r
+ /* Enable the Commutation Interrupt Request */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with DMA.\r
+ * @note This function is mandatory to use the commutation event in order to \r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer) \r
+ * configured in Hall sensor interface, this interface Timer will generate the \r
+ * commutation at its TRGO output (connected to Timer used in this function) each time \r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource: the Commutation Event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ { \r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+ \r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+ \r
+ /* Enable the Commutation DMA Request */\r
+ /* Set the DMA Commutation Callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;\r
+ \r
+ /* Enable the Commutation DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare Channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: TIM Output Compare handle\r
+ * @param sConfig: TIM Output Compare configuration structure\r
+ * @param Channel : TIM Channels to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected \r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim); \r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 1 in Output Compare */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 2 in Output Compare */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 3 in Output Compare */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 4 in Output Compare */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 5 in Output Compare */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 6 in Output Compare */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: TIM PWM handle\r
+ * @param sConfig: TIM PWM configuration structure\r
+ * @param Channel : TIM Channels to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected \r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, \r
+ TIM_OC_InitTypeDef* sConfig, \r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 1 in PWM mode */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 2 in PWM mode */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 3 in PWM mode */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 4 in PWM mode */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 5 in PWM mode */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel5*/\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 5 in PWM mode */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel6 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; \r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the OCRef clear feature\r
+ * @param htim: TIM handle\r
+ * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that\r
+ * contains the OCREF clear feature and parameters for the TIM peripheral. \r
+ * @param Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @arg TIM_Channel_5: TIM Channel 5\r
+ * @arg TIM_Channel_6: TIM Channel 6\r
+ * @retval None\r
+ */ \r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+ uint32_t Channel)\r
+{ \r
+ uint32_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+ \r
+ switch (sClearInputConfig->ClearInputSource)\r
+ {\r
+ case TIM_CLEARINPUTSOURCE_NONE:\r
+ {\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ \r
+ /* Clear the OCREF clear selection bit */\r
+ tmpsmcr &= ~TIM_SMCR_OCCS;\r
+ \r
+ /* Clear the ETR Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+ \r
+ /* Set TIMx_SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLEARINPUTSOURCE_OCREFCLR:\r
+ {\r
+ /* Clear the OCREF clear selection bit */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_OCCS;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLEARINPUTSOURCE_ETR:\r
+ {\r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+ \r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClearInputConfig->ClearInputPrescaler,\r
+ sClearInputConfig->ClearInputPolarity,\r
+ sClearInputConfig->ClearInputFilter);\r
+ \r
+ /* Set the OCREF clear selection bit */\r
+ htim->Instance->SMCR |= TIM_SMCR_OCCS;\r
+ }\r
+ break;\r
+ default: \r
+ break;\r
+ }\r
+ \r
+ switch (Channel)\r
+ { \r
+ case TIM_CHANNEL_1:\r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_2: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_3: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_4: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_5: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_6: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; \r
+ }\r
+ } \r
+ break;\r
+ default: \r
+ break;\r
+ } \r
+ \r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Configures the TIM in master mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module. \r
+ * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that\r
+ * contains the selected trigger output (TRGO) and the Master/Slave \r
+ * mode. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)\r
+{\r
+ uint32_t tmpcr2; \r
+ uint32_t tmpsmcr; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */\r
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));\r
+ \r
+ /* Clear the MMS2 bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS2;\r
+ /* Select the TRGO2 source*/\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;\r
+ }\r
+ \r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS;\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;\r
+\r
+ /* Reset the MSM Bit */\r
+ tmpsmcr &= ~TIM_SMCR_MSM;\r
+ /* Set master mode */\r
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;\r
+ \r
+ /* Update TIMx CR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+ \r
+ /* Update TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+} \r
+ \r
+/**\r
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r
+ * and the AOE(automatic output enable).\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that\r
+ * contains the BDTR Register configuration information for the TIM peripheral. \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, \r
+ TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)\r
+{\r
+ uint32_t tmpbdtr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));\r
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));\r
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+ \r
+ /* Clear the BDTR bits */\r
+ tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | \r
+ TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | \r
+ TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |\r
+ TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);\r
+\r
+ /* Set the BDTR bits */\r
+ tmpbdtr |= sBreakDeadTimeConfig->DeadTime;\r
+ tmpbdtr |= sBreakDeadTimeConfig->LockLevel;\r
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;\r
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;\r
+ tmpbdtr |= sBreakDeadTimeConfig->BreakState;\r
+ tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;\r
+ tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;\r
+ tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);\r
+ tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);\r
+ tmpbdtr |= sBreakDeadTimeConfig->Break2State;\r
+ tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;\r
+ \r
+ /* Set TIMx_BDTR */\r
+ htim->Instance->BDTR = tmpbdtr;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+/**\r
+ * @brief Configures the break input source.\r
+ * @param htim: TIM handle.\r
+ * @param BreakInput: Break input to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_BREAKINPUT_BRK: Timer break input\r
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input\r
+ * @param sBreakInputConfig: Break input source configuration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,\r
+ uint32_t BreakInput,\r
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)\r
+\r
+{\r
+ uint32_t tmporx = 0;\r
+ uint32_t bkin_enable_mask = 0;\r
+ uint32_t bkin_enable_bitpos = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+ \r
+ switch(sBreakInputConfig->Source)\r
+ {\r
+ case TIM_BREAKINPUTSOURCE_BKIN:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKINE;\r
+ bkin_enable_bitpos = 0;\r
+ }\r
+ break;\r
+ \r
+ case TIM_BREAKINPUTSOURCE_DFSDM1:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKDF1BKE;\r
+ bkin_enable_bitpos = 8;\r
+ }\r
+ break; \r
+\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ switch(BreakInput)\r
+ {\r
+ case TIM_BREAKINPUT_BRK:\r
+ {\r
+ /* Get the TIMx_AF1 register value */\r
+ tmporx = htim->Instance->AF1;\r
+ \r
+ /* Enable the break input */\r
+ tmporx &= ~bkin_enable_mask;\r
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+ \r
+ /* Set TIMx_AF1 */\r
+ htim->Instance->AF1 = tmporx; \r
+ }\r
+ break;\r
+ case TIM_BREAKINPUT_BRK2:\r
+ {\r
+ /* Get the TIMx_AF2 register value */\r
+ tmporx = htim->Instance->AF2;\r
+ \r
+ /* Enable the break input */\r
+ tmporx &= ~bkin_enable_mask;\r
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+ \r
+ /* Set TIMx_AF2 */\r
+ htim->Instance->AF2 = tmporx; \r
+ }\r
+ break; \r
+ default:\r
+ break;\r
+ }\r
+ \r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Remap: specifies the TIM input remapping source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)\r
+ * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.\r
+ * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. \r
+ * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. \r
+ * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)\r
+ * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.\r
+ * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.\r
+ * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.\r
+ * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) \r
+ * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous \r
+ * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock\r
+ * (HSE divided by a programmable prescaler) \r
+ * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r
+{\r
+ __HAL_LOCK(htim);\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_REMAP(Remap));\r
+ \r
+ /* Set the Timer remapping configuration */\r
+ htim->Instance->OR = Remap;\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Group channel 5 and channel 1, 2 or 3\r
+ * @param htim: TIM handle.\r
+ * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.\r
+ * This parameter can be any combination of the following values:\r
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC\r
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF\r
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF\r
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_GROUPCH5(OCRef));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Clear GC5Cx bit fields */\r
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);\r
+ \r
+ /* Set GC5Cx bit fields */\r
+ htim->Instance->CCR5 |= OCRef;\r
+ \r
+ htim->State = HAL_TIM_STATE_READY; \r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions \r
+ * @brief Extended Callbacks functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extension Callbacks functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides Extension TIM callback functions:\r
+ (+) Timer Commutation callback\r
+ (+) Timer Break callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Hall commutation changed callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_CommutationCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Break detection callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+ \r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_BreakCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions \r
+ * @brief Extended Peripheral State functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extension Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Hall Sensor interface state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA Commutation callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ HAL_TIMEx_CommutationCallback(htim); \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel xN.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.\r
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. \r
+ * @retval None\r
+ */\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));\r
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));\r
+\r
+ tmp = TIM_CCER_CC1NE << Channel;\r
+\r
+ /* Reset the CCxNE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxNE Bit */ \r
+ TIMx->CCER |= (uint32_t)(ChannelNState << Channel);\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 5 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC5E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2; \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC5P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 16);\r
+\r
+ if(IS_TIM_BREAK_INSTANCE(TIMx))\r
+ { \r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS5;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 8);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR5 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer; \r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 6 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC6E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2; \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 20);\r
+\r
+ if(IS_TIM_BREAK_INSTANCE(TIMx))\r
+ { \r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS6;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 10);\r
+ }\r
+ \r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR6 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer; \r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_uart.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief UART HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The UART HAL driver can be used as follows:\r
+\r
+ (#) Declare a UART_HandleTypeDef handle structure.\r
+\r
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) UART pins configuration:\r
+ (+++) Enable the clock for the UART GPIOs.\r
+ (+++) Configure these UART pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r
+ and HAL_UART_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r
+ and HAL_UART_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required\r
+ Tx/Rx parameters.\r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware\r
+ flow control and Mode(Receiver/Transmitter) in the Init structure.\r
+\r
+ (#) For the UART asynchronous mode, initialize the UART registers by calling\r
+ the HAL_UART_Init() API.\r
+\r
+ (#) For the UART Half duplex mode, initialize the UART registers by calling\r
+ the HAL_HalfDuplex_Init() API.\r
+\r
+ (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.\r
+\r
+ (#) For the Multi-Processor mode, initialize the UART registers by calling\r
+ the HAL_MultiProcessor_Init() API.\r
+\r
+ [..]\r
+ (@) The specific UART interrupts (Transmission complete interrupt,\r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit\r
+ and receive process.\r
+\r
+ [..]\r
+ (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the\r
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized\r
+ HAL_UART_MspInit() API.\r
+\r
+ [..]\r
+ Three operation modes are available within this driver :\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()\r
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()\r
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()\r
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_ErrorCallback\r
+\r
+ *** DMA mode IO operation ***\r
+ ==============================\r
+ [..]\r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()\r
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback\r
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()\r
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback\r
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_UART_ErrorCallback\r
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause()\r
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume()\r
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop()\r
+\r
+ *** UART HAL driver macros list ***\r
+ =============================================\r
+ [..]\r
+ Below the list of most used macros in UART HAL driver.\r
+\r
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral\r
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral\r
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not\r
+ (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag\r
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt\r
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt\r
+ (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not\r
+\r
+ [..]\r
+ (@) You can refer to the UART HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART UART\r
+ * @brief HAL UART module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup UART_Private_Constants UART Private Constants\r
+ * @{\r
+ */\r
+#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions\r
+ * @{\r
+ */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);\r
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup UART_Exported_Functions UART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
+ in asynchronous mode.\r
+ (+) For the asynchronous mode only these parameters can be configured:\r
+ (++) Baud Rate\r
+ (++) Word Length\r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ please refer to Reference manual for possible UART frame formats.\r
+ (++) Hardware flow control\r
+ (++) Receiver/transmitter modes\r
+ (++) Over Sampling Method\r
+ [..]\r
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs\r
+ follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor\r
+ configuration procedures (details for the procedures are available in reference manual (RM0329)).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the UART mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle .\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r
+ }\r
+ else\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+ }\r
+\r
+ if(huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In asynchronous mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Initializes the half-duplex mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle .\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In half-duplex mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the LIN mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle .\r
+ * @param huart: UART handle.\r
+ * @param BreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection\r
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r
+ assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));\r
+\r
+ if(huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In LIN mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\r
+\r
+ /* Set the USART LIN Break detection length. */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the multiprocessor mode according to the specified\r
+ * parameters in the UART_InitTypeDef and initialize the associated handle.\r
+ * @param huart: UART handle.\r
+ * @param Address: UART node address (4-, 6-, 7- or 8-bit long).\r
+ * @param WakeUpMethod: specifies the UART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection\r
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark\r
+ * @note If the user resorts to idle line detection wake up, the Address parameter\r
+ * is useless and ignored by the initialization function.\r
+ * @note If the user resorts to address mark wake up, the address length detection\r
+ * is configured by default to 4 bits only. For the UART to be able to\r
+ * manage 6-, 7- or 8-bit long addresses detection\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the wake up method parameter */\r
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r
+\r
+ if(huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In multiprocessor mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)\r
+ {\r
+ /* If address mark wake up method is chosen, set the USART address node */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));\r
+ }\r
+\r
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */\r
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the RS485 Driver enable feature according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle.\r
+ * @param huart: UART handle.\r
+ * @param Polarity: select the driver enable polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high\r
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low\r
+ * @param AssertionTime: Driver Enable assertion time:\r
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)\r
+ * signal and the beginning of the start bit. It is expressed in sample time\r
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)\r
+ * @param DeassertionTime: Driver Enable deassertion time:\r
+ * 5-bit value defining the time between the end of the last stop bit, in a\r
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.\r
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the\r
+ * oversampling rate).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)\r
+{\r
+ uint32_t temp = 0x0;\r
+\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Check the Driver Enable UART instance */\r
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));\r
+\r
+ /* Check the Driver Enable polarity */\r
+ assert_param(IS_UART_DE_POLARITY(Polarity));\r
+\r
+ /* Check the Driver Enable assertion time */\r
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));\r
+\r
+ /* Check the Driver Enable deassertion time */\r
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));\r
+\r
+ if(huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);\r
+\r
+ /* Set the Driver Enable polarity */\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);\r
+\r
+ /* Set the Driver Enable assertion and deassertion times */\r
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);\r
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);\r
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the UART peripheral\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ huart->Instance->CR1 = 0x0U;\r
+ huart->Instance->CR2 = 0x0U;\r
+ huart->Instance->CR3 = 0x0U;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_UART_MspDeInit(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_RESET;\r
+ huart->RxState = HAL_UART_STATE_RESET;\r
+\r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief UART MSP Init\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART MSP DeInit\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspDeInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions\r
+ * @brief UART Transmit/Receive functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the UART asynchronous\r
+ and Half duplex data transfers.\r
+\r
+ (#) There are two mode of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (+) Non-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_UART_Transmit()\r
+ (+) HAL_UART_Receive()\r
+\r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_UART_Transmit_IT()\r
+ (+) HAL_UART_Receive_IT()\r
+ (+) HAL_UART_IRQHandler()\r
+ (+) UART_Transmit_IT()\r
+ (+) UART_Receive_IT()\r
+\r
+ (#) Non-Blocking mode API's with DMA are :\r
+ (+) HAL_UART_Transmit_DMA()\r
+ (+) HAL_UART_Receive_DMA()\r
+ (+) HAL_UART_DMAPause()\r
+ (+) HAL_UART_DMAResume()\r
+ (+) HAL_UART_DMAStop()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r
+ (+) HAL_UART_TxHalfCpltCallback()\r
+ (+) HAL_UART_TxCpltCallback()\r
+ (+) HAL_UART_RxHalfCpltCallback()\r
+ (+) HAL_UART_RxCpltCallback()\r
+ (+) HAL_UART_ErrorCallback()\r
+\r
+\r
+ -@- In the Half duplex communication, it is forbidden to run the transmit\r
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Send an amount of data in blocking mode.\r
+ * @param huart: UART handle.\r
+ * @param pData: Pointer to data buffer.\r
+ * @param Size: Amount of data to be sent.\r
+ * @param Timeout: Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Check that a Tx process is not already ongoing */\r
+ if(huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if((pData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+ while(huart->TxXferCount > 0U)\r
+ {\r
+ huart->TxXferCount--;\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData;\r
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r
+ pData += 2;\r
+ }\r
+ else\r
+ {\r
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);\r
+ }\r
+ }\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* At end of Tx process, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode.\r
+ * @param huart: UART handle.\r
+ * @param pData: pointer to data buffer.\r
+ * @param Size: amount of data to be received.\r
+ * @param Timeout: Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if(huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if((pData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ huart->RxXferSize = Size;\r
+ huart->RxXferCount = Size;\r
+\r
+ /* Computation of UART mask to apply to RDR register */\r
+ UART_MASK_COMPUTATION(huart);\r
+ uhMask = huart->Mask;\r
+\r
+ /* as long as data have to be received */\r
+ while(huart->RxXferCount > 0U)\r
+ {\r
+ huart->RxXferCount--;\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData ;\r
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r
+ pData +=2U;\r
+ }\r
+ else\r
+ {\r
+ *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ }\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode.\r
+ * @param huart: UART handle.\r
+ * @param pData: pointer to data buffer.\r
+ * @param Size: amount of data to be sent.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Tx process is not already ongoing */\r
+ if(huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if((pData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Transmit Data Register Empty Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode.\r
+ * @param huart: UART handle.\r
+ * @param pData: pointer to data buffer.\r
+ * @param Size: amount of data to be received.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Rx process is not already ongoing */\r
+ if(huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if((pData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+ huart->RxXferCount = Size;\r
+\r
+ /* Computation of UART mask to apply to RDR register */\r
+ UART_MASK_COMPUTATION(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Parity Error Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the UART Data Register not empty Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode.\r
+ * @param huart: UART handle.\r
+ * @param pData: pointer to data buffer.\r
+ * @param Size: amount of data to be sent.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ /* Check that a Tx process is not already ongoing */\r
+ if(huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if((pData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r
+\r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ huart->hdmatx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the UART transmit DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode.\r
+ * @param huart: UART handle.\r
+ * @param pData: pointer to data buffer.\r
+ * @param Size: amount of data to be received.\r
+ * @note When the UART parity is enabled (PCE = 1), the received data contain\r
+ * the parity bit (MSB position).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if(huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if((pData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r
+\r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ huart->hdmarx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Parity Error Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the UART CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pause the DMA Transfer.\r
+ * @param huart: UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&\r
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))\r
+ {\r
+ /* Disable the UART DMA Tx request */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&\r
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the UART DMA Rx request */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the DMA Transfer.\r
+ * @param huart: UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if(huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the UART DMA Tx request */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);\r
+\r
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the UART DMA Rx request */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* If the UART peripheral is still not enabled, enable it */\r
+ if ((huart->Instance->CR1 & USART_CR1_UE) == 0U)\r
+ {\r
+ /* Enable UART peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA Transfer.\r
+ * @param huart: UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /\r
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:\r
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r
+ the stream and the corresponding call back is executed. */\r
+\r
+ /* Stop UART DMA Tx request if ongoing */\r
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&\r
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel */\r
+ if(huart->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(huart->hdmatx);\r
+ }\r
+\r
+ UART_EndTxTransfer(huart);\r
+ }\r
+\r
+ /* Stop UART DMA Rx request if ongoing */\r
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&\r
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel */\r
+ if(huart->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(huart->hdmarx);\r
+ }\r
+\r
+ UART_EndRxTransfer(huart);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles UART interrupt request.\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);\r
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);\r
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);\r
+ uint32_t errorflags;\r
+\r
+ /* If no error occurs */\r
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r
+ if (errorflags == RESET)\r
+ {\r
+ /* UART in mode Receiver ---------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ UART_Receive_IT(huart);\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* If some errors occur */\r
+ if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r
+ {\r
+\r
+ /* UART parity error interrupt occurred -------------------------------------*/\r
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r
+ {\r
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_PE;\r
+ }\r
+\r
+ /* UART frame error interrupt occurred --------------------------------------*/\r
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_FE;\r
+ }\r
+\r
+ /* UART noise error interrupt occurred --------------------------------------*/\r
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_NE;\r
+ }\r
+ \r
+ /* UART Over-Run interrupt occurred -----------------------------------------*/\r
+ if(((isrflags & USART_ISR_ORE) != RESET) &&\r
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))\r
+ {\r
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;\r
+ }\r
+\r
+ /* Call UART Error Call back function if need be --------------------------*/\r
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)\r
+ {\r
+ /* UART in mode Receiver ---------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ UART_Receive_IT(huart);\r
+ }\r
+\r
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+ consider error as blocking */\r
+ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||\r
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ /* Blocking error : transfer is aborted\r
+ Set the UART state ready to be able to start again the process,\r
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
+ UART_EndRxTransfer(huart);\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel */\r
+ if(huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback :\r
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\r
+\r
+ /* Abort DMA RX */\r
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_UART_ErrorCallback(huart);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_UART_ErrorCallback(huart);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Non Blocking error : transfer could go on.\r
+ Error is notified to user through user error callback */\r
+ HAL_UART_ErrorCallback(huart);\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ }\r
+ }\r
+ return;\r
+\r
+ } /* End if some error occurs */\r
+\r
+ /* UART in mode Transmitter ------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r
+ {\r
+ UART_Transmit_IT(huart);\r
+ return;\r
+ }\r
+\r
+ /* UART in mode Transmitter (transmission end) -----------------------------*/\r
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r
+ {\r
+ UART_EndTransmit_IT(huart);\r
+ return;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief This function handles UART Communication Timeout.\r
+ * @param huart UART handle\r
+ * @param Flag specifies the UART flag to check.\r
+ * @param Status The new Flag status (SET or RESET).\r
+ * @param Tickstart Tick start value\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+ /* Wait until flag is set */\r
+ while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DMA UART transmit process complete callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal mode*/\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r
+ {\r
+ huart->TxXferCount = 0U;\r
+\r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+ }\r
+ /* DMA Circular mode */\r
+ else\r
+ {\r
+ HAL_UART_TxCpltCallback(huart);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA UART transmit process half complete callback\r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_UART_TxHalfCpltCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process complete callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r
+ {\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the UART CR3 register */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+ }\r
+ HAL_UART_RxCpltCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process half complete callback\r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_UART_RxHalfCpltCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief DMA UART communication error callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ huart->RxXferCount = 0U;\r
+ huart->TxXferCount = 0U;\r
+ /* Stop UART DMA Tx request if ongoing */\r
+ if ( (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )\r
+ {\r
+ UART_EndTxTransfer(huart);\r
+ }\r
+\r
+ /* Stop UART DMA Rx request if ongoing */\r
+ if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )\r
+ {\r
+ UART_EndRxTransfer(huart);\r
+ }\r
+ SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA);\r
+ HAL_UART_ErrorCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief DMA UART communication abort callback, when call by HAL services on Error\r
+ * (To be called at end of DMA Abort procedure following error occurrence).\r
+ * @param hdma: DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);\r
+ huart->RxXferCount = 0U;\r
+ huart->TxXferCount = 0U;\r
+\r
+ HAL_UART_ErrorCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param huart: UART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callbacks.\r
+ * @param huart: UART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART error callbacks\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_ErrorCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Transmit_IT()\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t* tmp;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+\r
+ if(huart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Transmit Data Register Empty Interrupt */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) huart->pTxBuffPtr;\r
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r
+ huart->pTxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);\r
+ }\r
+\r
+ huart->TxXferCount--;\r
+\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Wrap up transmission in non-blocking mode.\r
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable the UART Transmit Complete Interrupt */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ /* Tx process is ended, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ HAL_UART_TxCpltCallback(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Receive_IT()\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask = huart->Mask;\r
+\r
+ /* Check that a Rx process is ongoing */\r
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) huart->pRxBuffPtr ;\r
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r
+ huart->pRxBuffPtr +=2;\r
+ }\r
+ else\r
+ {\r
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+\r
+ if(--huart->RxXferCount == 0)\r
+ {\r
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Rx process is completed, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ HAL_UART_RxCpltCallback(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\r
+ * @param huart: UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TXEIE and TCIE interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+\r
+ /* At end of Tx process, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+}\r
+\r
+\r
+/**\r
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\r
+ * @param huart: UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief UART control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the UART.\r
+ (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.\r
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode\r
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode\r
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r
+ (+) UART_SetConfig() API configures the UART peripheral\r
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features\r
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization\r
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter\r
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver\r
+ (+) HAL_LIN_SendBreak() API transmits the break characters\r
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address\r
+ detection length to more than 4 bits for multiprocessor address mark wake up.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;\r
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_MME);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,\r
+ * as it may not have been in mute mode at this very moment).\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Enter UART mute mode (means UART actually enters mute mode).\r
+ * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief return the UART state\r
+ * @param huart: uart handle\r
+ * @retval HAL state\r
+ */\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t temp1= 0x00U, temp2 = 0x00U;\r
+ temp1 = huart->gState;\r
+ temp2 = huart->RxState;\r
+\r
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+* @brief Return the UART error code\r
+* @param huart : pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART.\r
+* @retval UART Error Code\r
+*/\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r
+{\r
+ return huart->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @brief Configure the UART peripheral\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpreg = 0x00000000U;\r
+ UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;\r
+ uint16_t brrtemp = 0x0000U;\r
+ uint16_t usartdiv = 0x0000U;\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\r
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r
+ assert_param(IS_UART_PARITY(huart->Init.Parity));\r
+ assert_param(IS_UART_MODE(huart->Init.Mode));\r
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));\r
+\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure\r
+ * the UART Word Length, Parity, Mode and oversampling:\r
+ * set the M bits according to huart->Init.WordLength value\r
+ * set PCE and PS bits according to huart->Init.Parity value\r
+ * set TE and RE bits according to huart->Init.Mode value\r
+ * set OVER8 bit according to huart->Init.OverSampling value */\r
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;\r
+ MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR2 Configuration -----------------------*/\r
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according\r
+ * to huart->Init.StopBits value */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r
+\r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* Configure\r
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according\r
+ * to huart->Init.HwFlowCtl value\r
+ * - one-bit sampling method versus three samples' majority rule according\r
+ * to huart->Init.OneBitSampling */\r
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;\r
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);\r
+\r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ UART_GETCLOCKSOURCE(huart, clocksource);\r
+\r
+ /* Check UART Over Sampling to set Baud Rate Register */\r
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
+ {\r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_PCLK1:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_PCLK2:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_SYSCLK:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ brrtemp = usartdiv & 0xFFF0U;\r
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r
+ huart->Instance->BRR = brrtemp;\r
+ }\r
+ else\r
+ {\r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_PCLK1:\r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_PCLK2:\r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI:\r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_SYSCLK:\r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_LSE:\r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+\r
+ return ret;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the UART peripheral advanced features\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check whether the set of advanced features to configure is properly set */\r
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));\r
+\r
+ /* if required, configure TX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);\r
+ }\r
+\r
+ /* if required, configure RX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);\r
+ }\r
+\r
+ /* if required, configure data inversion */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);\r
+ }\r
+\r
+ /* if required, configure RX/TX pins swap */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);\r
+ }\r
+\r
+ /* if required, configure RX overrun detection disabling */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r
+ {\r
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);\r
+ }\r
+\r
+ /* if required, configure DMA disabling on reception error */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);\r
+ }\r
+\r
+ /* if required, configure auto Baud rate detection scheme */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);\r
+ /* set auto Baudrate detection parameters if detection is enabled */\r
+ if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);\r
+ }\r
+ }\r
+\r
+ /* if required, configure MSB first on communication line */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);\r
+ }\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Check the UART Idle State\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tickstart = 0U;\r
+\r
+ /* Initialize the UART ErrorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the Transmitter is enabled */\r
+ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+ {\r
+ /* Timeout Occurred */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+ {\r
+ /* Timeout Occurred */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Initialize the UART State */\r
+ huart->gState= HAL_UART_STATE_READY;\r
+ huart->RxState= HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the UART transmitter and disables the UART receiver.\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Clear TE and RE bits */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);\r
+\r
+ huart->gState= HAL_UART_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the UART receiver and disables the UART transmitter.\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Clear TE and RE bits */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Send break characters */\r
+ SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief By default in multiprocessor mode, when the wake up method is set\r
+ * to address mark, the UART handles only 4-bit long addresses detection;\r
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit\r
+ * long).\r
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,\r
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.\r
+ * @param huart: UART handle.\r
+ * @param AddressLength: this parameter can be one of the following values:\r
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address\r
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the address length parameter */\r
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the address length */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_usart.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief USART HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter\r
+ * Peripheral (USART).\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The USART HAL driver can be used as follows:\r
+\r
+ (#) Declare a USART_HandleTypeDef handle structure.\r
+ (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) USART pins configuration:\r
+ (+++) Enable the clock for the USART GPIOs.\r
+ (+++) Configure these USART pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),\r
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (+++) The specific USART interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()\r
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware \r
+ flow control and Mode(Receiver/Transmitter) in the husart Init structure.\r
+\r
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:\r
+ (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customed HAL_USART_MspInit(&husart) API.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART USART\r
+ * @brief HAL USART Synchronous module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup USART_Private_Constants\r
+ * @{\r
+ */\r
+#define DUMMY_DATA ((uint16_t) 0xFFFFU)\r
+#define TEACK_REACK_TIMEOUT ((uint32_t) 1000U)\r
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \\r
+ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup USART_Private_Functions\r
+ * @{\r
+ */\r
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAError(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart);\r
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Functions USART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USART\r
+ in asynchronous and in synchronous modes.\r
+ (+) For the asynchronous mode only these parameters can be configured:\r
+ (++) Baud Rate\r
+ (++) Word Length\r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ (++) USART polarity\r
+ (++) USART phase\r
+ (++) USART LastBit\r
+ (++) Receiver/transmitter modes\r
+\r
+ [..]\r
+ The HAL_USART_Init() function follows the USART synchronous configuration\r
+ procedure (details for the procedure are available in reference manual).\r
+\r
+@endverbatim\r
+\r
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
+ 8-bit or 9-bit), the possible USART frame formats are as listed in the\r
+ following table:\r
+\r
+ +---------------------------------------------------------------+\r
+ | M1M0 bits | PCE bit | USART frame |\r
+ |-----------------------|---------------------------------------|\r
+ | 10 | 0 | | SB | 7-bit data | STB | |\r
+ |-----------|-----------|---------------------------------------|\r
+ | 10 | 1 | | SB | 6-bit data | PB | STB | |\r
+ +---------------------------------------------------------------+\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the USART mode according to the specified\r
+ * parameters in the USART_InitTypeDef and create the associated handle.\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)\r
+{\r
+ /* Check the USART handle allocation */\r
+ if(husart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_INSTANCE(husart->Instance));\r
+\r
+ if(husart->State == HAL_USART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ husart->Lock = HAL_UNLOCKED;\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_USART_MspInit(husart);\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Set the Usart Communication parameters */\r
+ if (USART_SetConfig(husart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* In Synchronous mode, the following bits must be kept cleared:\r
+ - LINEN bit in the USART_CR2 register\r
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_USART_ENABLE(husart);\r
+\r
+ /* TEACK and/or REACK to check before moving husart->State to Ready */\r
+ return (USART_CheckIdleState(husart));\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the USART peripheral\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* Check the USART handle allocation */\r
+ if(husart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_INSTANCE(husart->Instance));\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ husart->Instance->CR1 = 0x0U;\r
+ husart->Instance->CR2 = 0x0U;\r
+ husart->Instance->CR3 = 0x0U;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_USART_MspDeInit(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_RESET;\r
+\r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USART MSP Init\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_MspInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief USART MSP DeInit\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_MspDeInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions \r
+ * @brief USART Transmit and Receive functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the USART synchronous\r
+ data transfers.\r
+\r
+ [..] The USART supports master mode only: it cannot receive or send data related to an input\r
+ clock (SCLK is always an output).\r
+\r
+ (#) There are two mode of transfer:\r
+ (++) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (++) No-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (++) HAL_USART_Transmit()in simplex mode\r
+ (++) HAL_USART_Receive() in full duplex receive only\r
+ (++) HAL_USART_TransmitReceive() in full duplex mode\r
+\r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (++) HAL_USART_Transmit_IT()in simplex mode\r
+ (++) HAL_USART_Receive_IT() in full duplex receive only\r
+ (++) HAL_USART_TransmitReceive_IT()in full duplex mode\r
+ (++) HAL_USART_IRQHandler()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_USART_Transmit_DMA()in simplex mode\r
+ (++) HAL_USART_Receive_DMA() in full duplex receive only\r
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode\r
+ (++) HAL_USART_DMAPause()\r
+ (++) HAL_USART_DMAResume()\r
+ (++) HAL_USART_DMAStop()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (++) HAL_USART_TxCpltCallback()\r
+ (++) HAL_USART_RxCpltCallback()\r
+ (++) HAL_USART_TxHalfCpltCallback()\r
+ (++) HAL_USART_RxHalfCpltCallback()\r
+ (++) HAL_USART_ErrorCallback()\r
+ (++) HAL_USART_TxRxCpltCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Simplex Send an amount of data in blocking mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint32_t tickstart = 0U;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+ \r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ /* Check the remaining data to be sent */\r
+ while(husart->TxXferCount > 0U)\r
+ {\r
+ husart->TxXferCount--;\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pTxData;\r
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r
+ pTxData += 2;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);\r
+ }\r
+ }\r
+\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode\r
+ * @note To receive synchronous data, dummy data are simultaneously transmitted\r
+ * @param husart: USART handle\r
+ * @param pRxData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+ uint32_t tickstart = 0U;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+ \r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+ uhMask = husart->Mask;\r
+\r
+ /* as long as data have to be received */\r
+ while(husart->RxXferCount > 0U)\r
+ {\r
+ husart->RxXferCount--;\r
+\r
+ /* Wait until TC flag is set to send dummy byte in order to generate the\r
+ * clock for the slave to send data.\r
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value\r
+ * can be written for all the cases. */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FFU);\r
+\r
+ /* Wait for RXNE Flag */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pRxData ;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ pRxData +=2;\r
+ }\r
+ else\r
+ {\r
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to TX data buffer\r
+ * @param pRxData: pointer to RX data buffer\r
+ * @param Size: amount of data to be sent (same amount to be received)\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+ uint32_t tickstart = 0U;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+ \r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ husart->RxXferSize = Size;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+ uhMask = husart->Mask;\r
+\r
+ /* Check the remain data to be sent */\r
+ while(husart->TxXferCount > 0)\r
+ {\r
+ husart->TxXferCount--;\r
+ husart->RxXferCount--;\r
+\r
+ /* Wait until TC flag is set to send data */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pTxData;\r
+ husart->Instance->TDR = (*tmp & uhMask);\r
+ pTxData += 2;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);\r
+ }\r
+\r
+ /* Wait for RXNE Flag */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pRxData ;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ pRxData +=2U;\r
+ }\r
+ else\r
+ {\r
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r
+{\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)\r
+ are not managed by the USART Transmit Process to avoid the overrun interrupt\r
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"\r
+ to benefit for the frame error and noise interrupts the usart mode should be\r
+ configured only for transmit "USART_MODE_TX" */\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Transmit Data Register Empty Interrupt */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode\r
+ * To receive synchronous data, dummy data are simultaneously transmitted\r
+ * @param husart: USART handle\r
+ * @param pRxData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pRxData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ /* Enable the USART Parity Error Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the USART Data Register not empty Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+\r
+ /* Send dummy byte in order to generate the clock for the Slave to send the next data */\r
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)\r
+ {\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FFU);\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to TX data buffer\r
+ * @param pRxData: pointer to RX data buffer\r
+ * @param Size: amount of data to be sent (same amount to be received)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;\r
+\r
+ /* Enable the USART Data Register not empty Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ /* Enable the USART Parity Error Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Transmit Data Register Empty Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ /* Set the USART DMA transfer complete callback */\r
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ husart->hdmatx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+ SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r
+ \r
+ /* Enable the USART transmit DMA channel */\r
+ tmp = (uint32_t*)&pTxData;\r
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode\r
+ * @param husart: USART handle\r
+ * @param pRxData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @note When the USART parity is enabled (PCE = 1), the received data contain\r
+ * the parity bit (MSB position)\r
+ * @retval HAL status\r
+ * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pRxData == NULL ) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->pTxBuffPtr = pRxData;\r
+ husart->TxXferSize = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ /* Set the USART DMA Rx transfer complete callback */\r
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r
+\r
+ /* Set the USART DMA Rx transfer error callback */\r
+ husart->hdmarx->XferErrorCallback = USART_DMAError;\r
+ \r
+ /* Set the DMA abort callback */\r
+ husart->hdmatx->XferAbortCallback = NULL;\r
+ \r
+ /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing\r
+ is performed in DMA reception complete callback */\r
+ husart->hdmatx->XferHalfCpltCallback = NULL;\r
+ husart->hdmatx->XferCpltCallback = NULL;\r
+ \r
+ /* Set the DMA error callback */\r
+ husart->hdmatx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+ SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r
+\r
+ /* Enable the USART receive DMA channel */\r
+ tmp = (uint32_t*)&pRxData;\r
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Enable the USART transmit DMA channel: the transmit stream is used in order\r
+ to generate in the non-blocking mode the clock to the slave device,\r
+ this mode isn't a simplex receive mode but a full-duplex receive mode */\r
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+ \r
+ /* Enable the USART Parity Error Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+ \r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode \r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to TX data buffer\r
+ * @param pRxData: pointer to RX data buffer\r
+ * @param Size: amount of data to be received/sent\r
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;\r
+\r
+ /* Set the USART DMA Rx transfer complete callback */\r
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r
+\r
+ /* Set the USART DMA Tx transfer complete callback */\r
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r
+\r
+ /* Set the USART DMA Tx transfer error callback */\r
+ husart->hdmatx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Set the USART DMA Rx transfer error callback */\r
+ husart->hdmarx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+ SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r
+\r
+ /* Enable the USART receive DMA channel */\r
+ tmp = (uint32_t*)&pRxData;\r
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Enable the USART transmit DMA channel */\r
+ tmp = (uint32_t*)&pTxData;\r
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+ \r
+ /* Enable the USART Parity Error Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+ \r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the DMA Transfer.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the USART DMA Tx request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+ /* Disable the USART DMA Rx request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Disable the USART DMA Tx request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ /* Disable the USART DMA Rx request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the USART DMA Tx request */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r
+ \r
+ /* Reenable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ SET_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the USART DMA Rx request */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r
+\r
+ /* Enable the USART DMA Rx request before the DMA Tx request */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Enable the USART DMA Tx request */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /\r
+ HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: \r
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete \r
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of \r
+ the stream and the corresponding call back is executed. */\r
+\r
+ /* Stop USART DMA Tx request if ongoing */\r
+ if ((husart->State == HAL_USART_STATE_BUSY_TX) &&\r
+ (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))\r
+ {\r
+ USART_EndTxTransfer(husart);\r
+ \r
+ /* Abort the USART DMA Tx channel */\r
+ if(husart->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(husart->hdmatx);\r
+ }\r
+ \r
+ /* Disable the USART Tx DMA request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ \r
+ /* Stop USART DMA Rx request if ongoing */\r
+ if ((husart->State == HAL_USART_STATE_BUSY_RX) &&\r
+ (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ USART_EndRxTransfer(husart);\r
+ \r
+ /* Abort the USART DMA Rx channel */\r
+ if(husart->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(husart->hdmarx);\r
+ }\r
+ \r
+ /* Disable the USART Rx DMA request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles USART interrupt request.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t isrflags = READ_REG(husart->Instance->ISR);\r
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);\r
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);\r
+ uint32_t errorflags;\r
+ \r
+ /* If no error occurs */\r
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r
+ if (errorflags == RESET)\r
+ {\r
+ /* USART in mode Receiver --------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ USART_Receive_IT(husart);\r
+ }\r
+ else\r
+ {\r
+ USART_TransmitReceive_IT(husart);\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* If some errors occur */\r
+ if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r
+ {\r
+ \r
+ /* USART parity error interrupt occurred ------------------------------------*/\r
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_PE;\r
+ }\r
+ \r
+ /* USART frame error interrupt occurred -------------------------------------*/\r
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_FE;\r
+ }\r
+ \r
+ /* USART noise error interrupt occurred -------------------------------------*/\r
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_NE;\r
+ }\r
+ \r
+ /* USART Over-Run interrupt occurred ----------------------------------------*/\r
+ if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;\r
+ }\r
+ \r
+ /* Call USART Error Call back function if need be --------------------------*/\r
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)\r
+ {\r
+ /* USART in mode Receiver ---------------------------------------------------*/\r
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r
+ {\r
+ USART_Receive_IT(husart);\r
+ }\r
+ \r
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+ consider error as blocking */\r
+ if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||\r
+ (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r
+ { \r
+ /* Blocking error : transfer is aborted\r
+ Set the USART state ready to be able to start again the process,\r
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
+ USART_EndRxTransfer(husart);\r
+ \r
+ /* Disable the USART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ \r
+ /* Abort the USART DMA Rx channel */\r
+ if(husart->hdmarx != NULL)\r
+ { \r
+ /* Set the USART DMA Abort callback : \r
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */\r
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;\r
+ \r
+ /* Abort DMA RX */\r
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */\r
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Non Blocking error : transfer could go on. \r
+ Error is notified to user through user error callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ }\r
+ }\r
+ return;\r
+ \r
+ } /* End if some error occurs */\r
+ \r
+ /* USART in mode Transmitter -----------------------------------------------*/\r
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r
+ {\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ USART_Transmit_IT(husart);\r
+ }\r
+ else\r
+ {\r
+ USART_TransmitReceive_IT(husart);\r
+ }\r
+ return;\r
+ }\r
+ \r
+ /* USART in mode Transmitter (transmission end) -----------------------------*/\r
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r
+ {\r
+ USART_EndTransmit_IT(husart);\r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_USART_RxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callbacks\r
+ * @param husart: usart handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief USART error callbacks\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+ \r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_ErrorCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief USART State and Errors functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to return the State of \r
+ USART communication\r
+ process, return Peripheral Errors occurred during communication process\r
+ (+) HAL_USART_GetState() API can be helpful to check in run-time the state \r
+ of the USART peripheral.\r
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during \r
+ communication. \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the USART state\r
+ * @param husart: USART handle\r
+ * @retval HAL state\r
+ */\r
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)\r
+{\r
+ return husart->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the USART error code\r
+ * @param husart : pointer to a USART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART.\r
+ * @retval USART Error Code\r
+ */\r
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)\r
+{\r
+ return husart->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/**\r
+ * @brief Simplex Send an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Transmit_IT().\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ * @note The USART errors are not managed to avoid the overrun error.\r
+ */\r
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)\r
+{\r
+ uint16_t* tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+\r
+ if(husart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the USART Transmit data register empty interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pTxBuffPtr;\r
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r
+ husart->pTxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); \r
+ }\r
+\r
+ husart->TxXferCount--;\r
+\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Wraps up transmission in non-blocking mode.\r
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)\r
+{\r
+ /* Disable the USART Transmit Complete Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_TxCpltCallback(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Simplex Receive an amount of data in non-blocking mode.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Receive_IT()\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask = husart->Mask;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pRxBuffPtr;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ husart->pRxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);\r
+\r
+ if(--husart->RxXferCount == 0U)\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ /* Disable the USART Parity Error Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_RxCpltCallback(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_TransmitReceive_IT() \r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask = husart->Mask;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r
+ {\r
+ if(husart->TxXferCount != 0x00U)\r
+ {\r
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)\r
+ {\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pTxBuffPtr;\r
+ husart->Instance->TDR = (uint16_t)(*tmp & uhMask);\r
+ husart->pTxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);\r
+ }\r
+ husart->TxXferCount--;\r
+\r
+ /* Check the latest data transmitted */\r
+ if(husart->TxXferCount == 0U)\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);\r
+ }\r
+ }\r
+ }\r
+\r
+ if(husart->RxXferCount != 0x00U)\r
+ {\r
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)\r
+ {\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pRxBuffPtr;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ husart->pRxBuffPtr += 2U;\r
+ }\r
+ else\r
+ {\r
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ husart->RxXferCount--;\r
+ }\r
+ }\r
+\r
+ /* Check the latest data received */\r
+ if(husart->RxXferCount == 0U)\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r
+\r
+ /* Disable the USART Parity Error Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles USART Communication Timeout.\r
+ * @param husart USART handle\r
+ * @param Flag specifies the USART flag to check.\r
+ * @param Status The new Flag status (SET or RESET).\r
+ * @param Tickstart Tick start value\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) \r
+{\r
+ /* Wait until flag is set */\r
+ while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout))\r
+ {\r
+ /* Disable the USART Transmit Complete Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);\r
+ \r
+ /* Disable the USART RXNE Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r
+ \r
+ /* Disable the USART Parity Error Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+ \r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+ \r
+ husart->State= HAL_USART_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA USART transmit process complete callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r
+ { \r
+ husart->TxXferCount = 0U;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r
+ in the USART CR3 register */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);\r
+ }\r
+ }\r
+ /* DMA Circular mode */\r
+ else\r
+ {\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ HAL_USART_TxCpltCallback(husart);\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA USART transmit process half complete callback\r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_USART_TxHalfCpltCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief DMA USART receive process complete callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r
+ { \r
+ husart->RxXferCount = 0U;\r
+ \r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit\r
+ in USART CR3 register */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ /* similarly, disable the DMA TX transfer that was started to provide the\r
+ clock to the slave device */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ HAL_USART_RxCpltCallback(husart);\r
+ }\r
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r
+ else\r
+ {\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+ }\r
+ husart->State= HAL_USART_STATE_READY;\r
+ }\r
+ /* DMA circular mode */\r
+ else\r
+ {\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ HAL_USART_RxCpltCallback(husart);\r
+ }\r
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r
+ else\r
+ {\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA USART receive process half complete callback\r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_USART_RxHalfCpltCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief DMA USART communication error callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ husart->RxXferCount = 0U;\r
+ husart->TxXferCount = 0U;\r
+ \r
+ /* Stop USART DMA Tx request if ongoing */\r
+ if((husart->State == HAL_USART_STATE_BUSY_TX)\r
+ &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))\r
+ {\r
+ USART_EndTxTransfer(husart);\r
+ }\r
+ \r
+ /* Stop USART DMA Rx request if ongoing */\r
+ if((husart->State == HAL_USART_STATE_BUSY_RX)\r
+ &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r
+ {\r
+ USART_EndRxTransfer(husart);\r
+ }\r
+ \r
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;\r
+ husart->State= HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_ErrorCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief DMA USART communication abort callback\r
+ * (To be called at end of DMA Abort procedure).\r
+ * @param hdma: DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ husart->RxXferCount = 0U;\r
+ husart->TxXferCount = 0U;\r
+ \r
+ HAL_USART_ErrorCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).\r
+ * @param husart: USART handle.\r
+ * @retval None\r
+ */\r
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart)\r
+{\r
+ /* At end of Tx process, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ \r
+ /* Disable TXEIE and TCIE interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+}\r
+\r
+/**\r
+ * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).\r
+ * @param husart: USART handle.\r
+ * @retval None\r
+ */\r
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart)\r
+{\r
+ /* At end of Rx process, restore husart->RxState to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ \r
+ /* Disable RXNE, PE and ERR interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+}\r
+\r
+/**\r
+ * @brief Configure the USART peripheral \r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tmpreg = 0x0U;\r
+ USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ uint16_t brrtemp = 0x0000U;\r
+ uint16_t usartdiv = 0x0000U;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));\r
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));\r
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));\r
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));\r
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));\r
+ assert_param(IS_USART_PARITY(husart->Init.Parity));\r
+ assert_param(IS_USART_MODE(husart->Init.Mode));\r
+ assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling)); \r
+\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Clear M, PCE, PS, TE and RE bits and configure \r
+ * the USART Word Length, Parity, Mode and OverSampling: \r
+ * set the M bits according to husart->Init.WordLength value \r
+ * set PCE and PS bits according to husart->Init.Parity value\r
+ * set TE and RE bits according to husart->Init.Mode value\r
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */\r
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;\r
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
+ \r
+ /*---------------------------- USART CR2 Configuration ---------------------*/\r
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:\r
+ * set CPOL bit according to husart->Init.CLKPolarity value\r
+ * set CPHA bit according to husart->Init.CLKPhase value\r
+ * set LBCL bit according to husart->Init.CLKLastBit value\r
+ * set STOP[13:12] bits according to husart->Init.StopBits value */\r
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); \r
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);\r
+ tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);\r
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* no CR3 register configuration */\r
+\r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */\r
+ USART_GETCLOCKSOURCE(husart, clocksource);\r
+ switch (clocksource)\r
+ {\r
+ case USART_CLOCKSOURCE_PCLK1:\r
+ usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_PCLK2:\r
+ usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_HSI:\r
+ usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_SYSCLK:\r
+ usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ } \r
+ \r
+ brrtemp = usartdiv & 0xFFF0U;\r
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r
+ husart->Instance->BRR = brrtemp;\r
+ \r
+ return ret; \r
+}\r
+\r
+/**\r
+ * @brief Check the USART Idle State\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tickstart = 0U;\r
+ \r
+ /* Initialize the USART ErrorCode */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ \r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check if the Transmitter is enabled */\r
+ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ husart->State= HAL_USART_STATE_TIMEOUT; \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ husart->State= HAL_USART_STATE_TIMEOUT; \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Initialize the USART state*/\r
+ husart->State= HAL_USART_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief WWDG HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Window Watchdog (WWDG) peripheral:\r
+ * + Initialization and Configuration function\r
+ * + IO operation functions\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### WWDG specific features #####\r
+ ==============================================================================\r
+ [..]\r
+ Once enabled the WWDG generates a system reset on expiry of a programmed\r
+ time period, unless the program refreshes the counter (T[6;0] downcounter)\r
+ before reaching 0x3F value (i.e. a reset is generated when the counter\r
+ value rolls over from 0x40 to 0x3F).\r
+\r
+ (+) An MCU reset is also generated if the counter value is refreshed\r
+ before the counter has reached the refresh window value. This\r
+ implies that the counter must be refreshed in a limited window.\r
+\r
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.\r
+\r
+ (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has \r
+ occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).\r
+\r
+ (+) The WWDG downcounter input clock is derived from the APB clock divided\r
+ by a programmable prescaler.\r
+\r
+ (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)\r
+\r
+ (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)\r
+ where T[5;0] are the lowest 6 bits of downcounter.\r
+\r
+ (+) WWDG Counter refresh is allowed between the following limits :\r
+ (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)\r
+ (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)\r
+\r
+ (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms\r
+\r
+ (+) The Early Wakeup Interrupt (EWI) can be used if specific safety \r
+ operations or data logging must be performed before the actual reset is\r
+ generated. When the downcounter reaches the value 0x40, an EWI interrupt\r
+ is generated and the corresponding interrupt service routine (ISR) can \r
+ be used to trigger specific actions (such as communications or data \r
+ logging), before resetting the device.\r
+ In some applications, the EWI interrupt can be used to manage a software\r
+ system check and/or system recovery/graceful degradation, without \r
+ generating a WWDG reset. In this case, the corresponding interrupt \r
+ service routine (ISR) should reload the WWDG counter to avoid the WWDG \r
+ reset, then trigger the required actions.\r
+ Note:When the EWI interrupt cannot be served, e.g. due to a system lock \r
+ in a higher priority task, the WWDG reset will eventually be generated.\r
+\r
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),\r
+ the WWDG counter either continues to work normally or stops, depending \r
+ on DBG_WWDG_STOP configuration bit in DBG module, accessible through\r
+ __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().\r
+\r
+ (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup \r
+ Interrupt mode using using HAL_WWDG_Init() function.\r
+ This enables WWDG peripheral and the downcounter starts downcounting \r
+ from given counter value.\r
+ Init function can be called again to modify all watchdog parameters, \r
+ however if EWI mode has been set once, it can't be clear until next \r
+ reset.\r
+\r
+ (+) The application program must refresh the WWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset using\r
+ HAL_WWDG_Refresh() function. This operation must occur only when\r
+ the counter is lower than the window value already programmed.\r
+\r
+ (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when \r
+ the counter reaches 0x40. User can add his own code in weak function \r
+ HAL_WWDG_EarlyWakeupCallback().\r
+\r
+ *** WWDG HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in WWDG HAL driver.\r
+\r
+ (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.\r
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.\r
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+/** @defgroup WWDG WWDG\r
+ * @brief WWDG HAL module driver.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions.\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and start the WWDG according to the specified parameters\r
+ in the WWDG_InitTypeDef of associated handle.\r
+ (+) Initialize the WWDG MSP.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the WWDG according to the specified.\r
+ * parameters in the WWDG_InitTypeDef of associated handle.\r
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* Check the WWDG handle allocation */\r
+ if(hwwdg == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));\r
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));\r
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));\r
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));\r
+ assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));\r
+\r
+ /* Init the low level hardware */\r
+ HAL_WWDG_MspInit(hwwdg);\r
+\r
+ /* Set WWDG Counter */\r
+ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));\r
+\r
+ /* Set WWDG Prescaler and Window */\r
+ WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the WWDG MSP.\r
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @note When rewriting this function in user file, mechanism may be added\r
+ * to avoid multiple initialize when HAL_WWDG_Init function is called\r
+ * again to change parameters.\r
+ * @retval None\r
+ */\r
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hwwdg);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_WWDG_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Refresh the WWDG.\r
+ (+) Handle WWDG interrupt request and associated function callback.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Refresh the WWDG.\r
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* Write to WWDG CR the WWDG Counter value to refresh with */\r
+ WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle WWDG interrupt request.\r
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations\r
+ * or data logging must be performed before the actual reset is generated.\r
+ * The EWI interrupt is enabled by calling HAL_WWDG_Init function with \r
+ * EWIMode set to WWDG_EWI_ENABLE.\r
+ * When the downcounter reaches the value 0x40, and EWI interrupt is\r
+ * generated and the corresponding Interrupt Service Routine (ISR) can\r
+ * be used to trigger specific actions (such as communications or data\r
+ * logging), before resetting the device.\r
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval None\r
+ */\r
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* Check if Early Wakeup Interrupt is enable */\r
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)\r
+ {\r
+ /* Check if WWDG Early Wakeup Interrupt occurred */\r
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)\r
+ {\r
+ /* Clear the WWDG Early Wakeup flag */\r
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);\r
+\r
+ /* Early Wakeup callback */ \r
+ HAL_WWDG_EarlyWakeupCallback(hwwdg);\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief WWDG Early Wakeup callback.\r
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hwwdg);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_fmc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief FMC Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Flexible Memory Controller (FMC) peripheral memories:\r
+ * + Initialization/de-initialization functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### FMC peripheral features #####\r
+ ==============================================================================\r
+ [..] The Flexible memory controller (FMC) includes three memory controllers:\r
+ (+) The NOR/PSRAM memory controller\r
+ (+) The NAND memory controller\r
+ (+) The Synchronous DRAM (SDRAM) controller \r
+ \r
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static\r
+ memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:\r
+ (+) to translate AHB transactions into the appropriate external device protocol\r
+ (+) to meet the access time requirements of the external memory devices\r
+ \r
+ [..] All external memories share the addresses, data and control signals with the controller.\r
+ Each external device is accessed by means of a unique Chip Select. The FMC performs\r
+ only one access at a time to an external device.\r
+ The main features of the FMC controller are the following:\r
+ (+) Interface with static-memory mapped devices including:\r
+ (++) Static random access memory (SRAM)\r
+ (++) Read-only memory (ROM)\r
+ (++) NOR Flash memory/OneNAND Flash memory\r
+ (++) PSRAM (4 memory banks)\r
+ (++) 16-bit PC Card compatible devices\r
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of\r
+ data\r
+ (+) Interface with synchronous DRAM (SDRAM) memories\r
+ (+) Independent Chip Select control for each memory bank\r
+ (+) Independent configuration for each memory bank\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL FMC Low Layer\r
+ * @brief FMC driver modules\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions\r
+ * @brief NORSRAM Controller functions \r
+ *\r
+ @verbatim \r
+ ============================================================================== \r
+ ##### How to use NORSRAM device driver #####\r
+ ==============================================================================\r
+ \r
+ [..] \r
+ This driver contains a set of APIs to interface with the FMC NORSRAM banks in order\r
+ to run the NORSRAM external devices.\r
+ \r
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() \r
+ (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()\r
+ (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()\r
+ (+) FMC NORSRAM bank extended timing configuration using the function \r
+ FMC_NORSRAM_Extended_Timing_Init()\r
+ (+) FMC NORSRAM bank enable/disable write operation using the functions\r
+ FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()\r
+ \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC NORSRAM interface\r
+ (+) De-initialize the FMC NORSRAM interface \r
+ (+) Configure the FMC clock and associated GPIOs \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initialize the FMC_NORSRAM device according to the specified\r
+ * control parameters in the FMC_NORSRAM_InitTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Init: Pointer to NORSRAM Initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)\r
+{ \r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));\r
+ assert_param(IS_FMC_MUX(Init->DataAddressMux));\r
+ assert_param(IS_FMC_MEMORY(Init->MemoryType));\r
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));\r
+ assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));\r
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));\r
+ assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));\r
+ assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));\r
+ assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));\r
+ assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));\r
+ assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));\r
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); \r
+ assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));\r
+ assert_param(IS_FMC_PAGESIZE(Init->PageSize));\r
+\r
+ /* Get the BTCR register value */\r
+ tmpr = Device->BTCR[Init->NSBank];\r
+ \r
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,\r
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */\r
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \\r
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \\r
+ FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \\r
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \\r
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));\r
+ \r
+ /* Set NORSRAM device control parameters */\r
+ tmpr |= (uint32_t)(Init->DataAddressMux |\\r
+ Init->MemoryType |\\r
+ Init->MemoryDataWidth |\\r
+ Init->BurstAccessMode |\\r
+ Init->WaitSignalPolarity |\\r
+ Init->WaitSignalActive |\\r
+ Init->WriteOperation |\\r
+ Init->WaitSignal |\\r
+ Init->ExtendedMode |\\r
+ Init->AsynchronousWait |\\r
+ Init->WriteBurst |\\r
+ Init->ContinuousClock |\\r
+ Init->PageSize |\\r
+ Init->WriteFifo);\r
+ \r
+ if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)\r
+ {\r
+ tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;\r
+ }\r
+ \r
+ Device->BTCR[Init->NSBank] = tmpr;\r
+\r
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */\r
+ if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))\r
+ { \r
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);\r
+ }\r
+ if(Init->NSBank != FMC_NORSRAM_BANK1)\r
+ {\r
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInitialize the FMC_NORSRAM peripheral \r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param ExDevice: Pointer to NORSRAM extended mode device instance \r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Disable the FMC_NORSRAM device */\r
+ __FMC_NORSRAM_DISABLE(Device, Bank);\r
+ \r
+ /* De-initialize the FMC_NORSRAM device */\r
+ /* FMC_NORSRAM_BANK1 */\r
+ if(Bank == FMC_NORSRAM_BANK1)\r
+ {\r
+ Device->BTCR[Bank] = 0x000030DB; \r
+ }\r
+ /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */\r
+ else\r
+ { \r
+ Device->BTCR[Bank] = 0x000030D2; \r
+ }\r
+ \r
+ Device->BTCR[Bank + 1] = 0x0FFFFFFF;\r
+ ExDevice->BWTR[Bank] = 0x0FFFFFFF;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the FMC_NORSRAM Timing according to the specified\r
+ * parameters in the FMC_NORSRAM_TimingTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Timing: Pointer to NORSRAM Timing structure\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Get the BTCR register value */\r
+ tmpr = Device->BTCR[Bank + 1];\r
+\r
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
+ tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \\r
+ FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \\r
+ FMC_BTR1_ACCMOD));\r
+ \r
+ /* Set FMC_NORSRAM device timing parameters */ \r
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\\r
+ ((Timing->AddressHoldTime) << 4) |\\r
+ ((Timing->DataSetupTime) << 8) |\\r
+ ((Timing->BusTurnAroundDuration) << 16) |\\r
+ (((Timing->CLKDivision)-1) << 20) |\\r
+ (((Timing->DataLatency)-2) << 24) |\\r
+ (Timing->AccessMode)\r
+ );\r
+ \r
+ Device->BTCR[Bank + 1] = tmpr;\r
+ \r
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */\r
+ if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))\r
+ {\r
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); \r
+ tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);\r
+ Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified\r
+ * parameters in the FMC_NORSRAM_TimingTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Timing: Pointer to NORSRAM Timing structure\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)\r
+{ \r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));\r
+ \r
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */\r
+ if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); \r
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank)); \r
+ \r
+ /* Get the BWTR register value */\r
+ tmpr = Device->BWTR[Bank];\r
+\r
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
+ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \\r
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));\r
+ \r
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\\r
+ ((Timing->AddressHoldTime) << 4) |\\r
+ ((Timing->DataSetupTime) << 8) |\\r
+ ((Timing->BusTurnAroundDuration) << 16) |\\r
+ (Timing->AccessMode));\r
+\r
+ Device->BWTR[Bank] = tmpr;\r
+ }\r
+ else\r
+ {\r
+ Device->BWTR[Bank] = 0x0FFFFFFF;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_NORSRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC NORSRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically FMC_NORSRAM write operation.\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Enable write operation */\r
+ Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NORSRAM write operation.\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Disable write operation */\r
+ Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions\r
+ * @brief NAND Controller functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use NAND device driver #####\r
+ ==============================================================================\r
+ [..]\r
+ This driver contains a set of APIs to interface with the FMC NAND banks in order\r
+ to run the NAND external devices.\r
+ \r
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit() \r
+ (+) FMC NAND bank control configuration using the function FMC_NAND_Init()\r
+ (+) FMC NAND bank common space timing configuration using the function \r
+ FMC_NAND_CommonSpace_Timing_Init()\r
+ (+) FMC NAND bank attribute space timing configuration using the function \r
+ FMC_NAND_AttributeSpace_Timing_Init()\r
+ (+) FMC NAND bank enable/disable ECC correction feature using the functions\r
+ FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()\r
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC NAND interface\r
+ (+) De-initialize the FMC NAND interface \r
+ (+) Configure the FMC clock and associated GPIOs\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND device according to the specified\r
+ * control parameters in the FMC_NAND_HandleTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Init: Pointer to NAND Initialization structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NAND_DEVICE(Device));\r
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));\r
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));\r
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));\r
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));\r
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));\r
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); \r
+\r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PCR;\r
+\r
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */\r
+ tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \\r
+ FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \\r
+ FMC_PCR_TAR | FMC_PCR_ECCPS)); \r
+ /* Set NAND device control parameters */\r
+ tmpr |= (uint32_t)(Init->Waitfeature |\\r
+ FMC_PCR_MEMORY_TYPE_NAND |\\r
+ Init->MemoryDataWidth |\\r
+ Init->EccComputation |\\r
+ Init->ECCPageSize |\\r
+ ((Init->TCLRSetupTime) << 9) |\\r
+ ((Init->TARSetupTime) << 13)); \r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PCR = tmpr;\r
+ \r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified\r
+ * parameters in the FMC_NAND_PCC_TimingTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Timing: Pointer to NAND timing structure\r
+ * @param Bank: NAND bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NAND_DEVICE(Device));\r
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PMEM;\r
+\r
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */\r
+ tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \\r
+ FMC_PMEM_MEMHIZ3)); \r
+ /* Set FMC_NAND device timing parameters */\r
+ tmpr |= (uint32_t)(Timing->SetupTime |\\r
+ ((Timing->WaitSetupTime) << 8) |\\r
+ ((Timing->HoldSetupTime) << 16) |\\r
+ ((Timing->HiZSetupTime) << 24)\r
+ );\r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PMEM = tmpr;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified\r
+ * parameters in the FMC_NAND_PCC_TimingTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Timing: Pointer to NAND timing structure\r
+ * @param Bank: NAND bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PATT;\r
+\r
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */\r
+ tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \\r
+ FMC_PATT_ATTHIZ3));\r
+ /* Set FMC_NAND device timing parameters */\r
+ tmpr |= (uint32_t)(Timing->SetupTime |\\r
+ ((Timing->WaitSetupTime) << 8) |\\r
+ ((Timing->HoldSetupTime) << 16) |\\r
+ ((Timing->HiZSetupTime) << 24));\r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PATT = tmpr;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the FMC_NAND device \r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Disable the NAND Bank */\r
+ __FMC_NAND_DISABLE(Device);\r
+ \r
+ /* Set the FMC_NAND_BANK3 registers to their reset values */\r
+ Device->PCR = 0x00000018U;\r
+ Device->SR = 0x00000040U;\r
+ Device->PMEM = 0xFCFCFCFCU;\r
+ Device->PATT = 0xFCFCFCFCU; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FMC_NAND_Group3 Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_NAND Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC NAND interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ \r
+/**\r
+ * @brief Enables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Enable ECC feature */\r
+ Device->PCR |= FMC_PCR_ECCEN;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) \r
+{ \r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Disable ECC feature */\r
+ Device->PCR &= ~FMC_PCR_ECCEN;\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param ECCval: Pointer to ECC value\r
+ * @param Bank: NAND bank number\r
+ * @param Timeout: Timeout wait value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until FIFO is empty */\r
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Get the ECCR register value */\r
+ *ECCval = (uint32_t)Device->ECCR;\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_SDRAM\r
+ * @brief SDRAM Controller functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use SDRAM device driver #####\r
+ ==============================================================================\r
+ [..] \r
+ This driver contains a set of APIs to interface with the FMC SDRAM banks in order\r
+ to run the SDRAM external devices.\r
+ \r
+ (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() \r
+ (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()\r
+ (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()\r
+ (+) FMC SDRAM bank enable/disable write operation using the functions\r
+ FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() \r
+ (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC SDRAM interface\r
+ (+) De-initialize the FMC SDRAM interface \r
+ (+) Configure the FMC clock and associated GPIOs\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the FMC_SDRAM device according to the specified\r
+ * control parameters in the FMC_SDRAM_InitTypeDef\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Init: Pointer to SDRAM Initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)\r
+{\r
+ uint32_t tmpr1 = 0;\r
+ uint32_t tmpr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));\r
+ assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));\r
+ assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));\r
+ assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));\r
+ assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));\r
+ assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));\r
+ assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));\r
+ assert_param(IS_FMC_READ_BURST(Init->ReadBurst));\r
+ assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); \r
+\r
+ /* Set SDRAM bank configuration parameters */\r
+ if (Init->SDBank != FMC_SDRAM_BANK2) \r
+ {\r
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+\r
+ tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\\r
+ Init->RowBitsNumber |\\r
+ Init->MemoryDataWidth |\\r
+ Init->InternalBankNumber |\\r
+ Init->CASLatency |\\r
+ Init->WriteProtection |\\r
+ Init->SDClockPeriod |\\r
+ Init->ReadBurst |\\r
+ Init->ReadPipeDelay\r
+ ); \r
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
+ }\r
+ else /* FMC_Bank2_SDRAM */ \r
+ {\r
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear SDCLK, RBURST, and RPIPE bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+ \r
+ tmpr1 |= (uint32_t)(Init->SDClockPeriod |\\r
+ Init->ReadBurst |\\r
+ Init->ReadPipeDelay);\r
+ \r
+ tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+\r
+ tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\\r
+ Init->RowBitsNumber |\\r
+ Init->MemoryDataWidth |\\r
+ Init->InternalBankNumber |\\r
+ Init->CASLatency |\\r
+ Init->WriteProtection);\r
+\r
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
+ Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the FMC_SDRAM device timing according to the specified\r
+ * parameters in the FMC_SDRAM_TimingTypeDef\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Timing: Pointer to SDRAM Timing structure\r
+ * @param Bank: SDRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr1 = 0;\r
+ uint32_t tmpr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));\r
+ assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));\r
+ assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));\r
+ assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));\r
+ assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));\r
+ assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));\r
+ assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Set SDRAM device timing parameters */ \r
+ if (Bank != FMC_SDRAM_BANK2) \r
+ {\r
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ \r
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\\r
+ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
+ (((Timing->SelfRefreshTime)-1) << 8) |\\r
+ (((Timing->RowCycleDelay)-1) << 12) |\\r
+ (((Timing->WriteRecoveryTime)-1) <<16) |\\r
+ (((Timing->RPDelay)-1) << 20) |\\r
+ (((Timing->RCDDelay)-1) << 24));\r
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;\r
+ }\r
+ else /* FMC_Bank2_SDRAM */\r
+ {\r
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear TRC and TRP bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));\r
+ \r
+ tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\\r
+ (((Timing->RPDelay)-1) << 20)); \r
+ \r
+ tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ \r
+ tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\\r
+ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
+ (((Timing->SelfRefreshTime)-1) << 8) |\\r
+ (((Timing->WriteRecoveryTime)-1) <<16) |\\r
+ (((Timing->RCDDelay)-1) << 24)); \r
+\r
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;\r
+ Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the FMC_SDRAM peripheral \r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* De-initialize the SDRAM device */\r
+ Device->SDCR[Bank] = 0x000002D0;\r
+ Device->SDTR[Bank] = 0x0FFFFFFF; \r
+ Device->SDCMR = 0x00000000;\r
+ Device->SDRTR = 0x00000000;\r
+ Device->SDSR = 0x00000000;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_SDRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC SDRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically FMC_SDRAM write protection.\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Bank: SDRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Enable write protection */\r
+ Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_SDRAM write protection.\r
+ * @param hsdram: FMC_SDRAM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Disable write protection */\r
+ Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
+ \r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief Send Command to the FMC SDRAM bank\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Command: Pointer to SDRAM command structure \r
+ * @param Timing: Pointer to SDRAM Timing structure\r
+ * @param Timeout: Timeout wait value\r
+ * @retval HAL state\r
+ */ \r
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r
+{\r
+ __IO uint32_t tmpr = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));\r
+ assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));\r
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));\r
+ assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); \r
+\r
+ /* Set command register */\r
+ tmpr = (uint32_t)((Command->CommandMode) |\\r
+ (Command->CommandTarget) |\\r
+ (((Command->AutoRefreshNumber)-1) << 5) |\\r
+ ((Command->ModeRegisterDefinition) << 9)\r
+ );\r
+ \r
+ Device->SDCMR = tmpr;\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* wait until command is send */\r
+ while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Program the SDRAM Memory Refresh rate.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param RefreshRate: The SDRAM refresh rate value. \r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_REFRESH_RATE(RefreshRate));\r
+ \r
+ /* Set the refresh rate in command register */\r
+ Device->SDRTR |= (RefreshRate<<1);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param AutoRefreshNumber: Specifies the auto Refresh number. \r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));\r
+ \r
+ /* Set the Auto-refresh number in command register */\r
+ Device->SDCMR |= (AutoRefreshNumber << 5); \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Returns the indicated FMC SDRAM bank mode status.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param Bank: Defines the FMC SDRAM bank. This parameter can be \r
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. \r
+ * @retval The FMC SDRAM bank mode status, could be on of the following values:\r
+ * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or \r
+ * FMC_SDRAM_POWER_DOWN_MODE. \r
+ */\r
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+\r
+ /* Get the corresponding bank mode */\r
+ if(Bank == FMC_SDRAM_BANK1)\r
+ {\r
+ tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);\r
+ }\r
+ \r
+ /* Return the mode status */\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_sdmmc.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief SDMMC Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the SDMMC peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### SDMMC peripheral features #####\r
+ ============================================================================== \r
+ [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2\r
+ peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA\r
+ devices.\r
+ \r
+ [..] The SDMMC features include the following:\r
+ (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support\r
+ for three different databus modes: 1-bit (default), 4-bit and 8-bit\r
+ (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)\r
+ (+) Full compliance with SD Memory Card Specifications Version 2.0\r
+ (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two\r
+ different data bus modes: 1-bit (default) and 4-bit\r
+ (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol\r
+ Rev1.1)\r
+ (+) Data transfer up to 48 MHz for the 8 bit mode\r
+ (+) Data and command output enable signals to control external bidirectional drivers.\r
+ \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ This driver is a considered as a driver of service for external devices drivers \r
+ that interfaces with the SDMMC peripheral.\r
+ According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs \r
+ is used in the device's driver to perform SDMMC operations and functionalities.\r
+ \r
+ This driver is almost transparent for the final user, it is only used to implement other\r
+ functionalities of the external device.\r
+ \r
+ [..]\r
+ (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL \r
+ (PLL48CLK). Before start working with SDMMC peripheral make sure that the\r
+ PLL is well configured.\r
+ The SDMMC peripheral uses two clock signals:\r
+ (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)\r
+ (++) APB2 bus clock (PCLK2)\r
+ \r
+ -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:\r
+ Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))\r
+ \r
+ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC\r
+ peripheral.\r
+\r
+ (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) \r
+ function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).\r
+ \r
+ (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.\r
+ \r
+ (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) \r
+ and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. \r
+ \r
+ (+) When using the DMA mode \r
+ (++) Configure the DMA in the MSP layer of the external device\r
+ (++) Active the needed channel Request \r
+ (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro\r
+ __SDMMC_DMA_DISABLE().\r
+ \r
+ (+) To control the CPSM (Command Path State Machine) and send \r
+ commands to the card use the SDMMC_SendCommand(SDMMCx), \r
+ SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has\r
+ to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according \r
+ to the selected command to be sent.\r
+ The parameters that should be filled are:\r
+ (++) Command Argument\r
+ (++) Command Index\r
+ (++) Command Response type\r
+ (++) Command Wait\r
+ (++) CPSM Status (Enable or Disable).\r
+ \r
+ -@@- To check if the command is well received, read the SDMMC_CMDRESP\r
+ register using the SDMMC_GetCommandResponse().\r
+ The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the\r
+ SDMMC_GetResponse() function.\r
+ \r
+ (+) To control the DPSM (Data Path State Machine) and send/receive \r
+ data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), \r
+ SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions.\r
+ \r
+ *** Read Operations ***\r
+ =======================\r
+ [..]\r
+ (#) First, user has to fill the data structure (pointer to\r
+ SDMMC_DataInitTypeDef) according to the selected data type to be received.\r
+ The parameters that should be filled are:\r
+ (++) Data TimeOut\r
+ (++) Data Length\r
+ (++) Data Block size\r
+ (++) Data Transfer direction: should be from card (To SDMMC)\r
+ (++) Data Transfer mode\r
+ (++) DPSM Status (Enable or Disable)\r
+ \r
+ (#) Configure the SDMMC resources to receive the data from the card\r
+ according to selected transfer mode (Refer to Step 8, 9 and 10).\r
+ \r
+ (#) Send the selected Read command (refer to step 11).\r
+ \r
+ (#) Use the SDMMC flags/interrupts to check the transfer status.\r
+ \r
+ *** Write Operations ***\r
+ ========================\r
+ [..]\r
+ (#) First, user has to fill the data structure (pointer to\r
+ SDMMC_DataInitTypeDef) according to the selected data type to be received.\r
+ The parameters that should be filled are:\r
+ (++) Data TimeOut\r
+ (++) Data Length\r
+ (++) Data Block size\r
+ (++) Data Transfer direction: should be to card (To CARD)\r
+ (++) Data Transfer mode\r
+ (++) DPSM Status (Enable or Disable)\r
+ \r
+ (#) Configure the SDMMC resources to send the data to the card according to \r
+ selected transfer mode.\r
+ \r
+ (#) Send the selected Write command.\r
+ \r
+ (#) Use the SDMMC flags/interrupts to check the transfer status.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDMMC_LL SDMMC Low Layer\r
+ * @brief Low layer module for SD\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization/de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SDMMC according to the specified\r
+ * parameters in the SDMMC_InitTypeDef and create the associated handle.\r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @param Init: SDMMC initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));\r
+ assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); \r
+ assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));\r
+ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));\r
+ assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));\r
+ assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));\r
+ assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));\r
+ \r
+ /* Set SDMMC configuration parameters */\r
+ tmpreg |= (Init.ClockEdge |\\r
+ Init.ClockBypass |\\r
+ Init.ClockPowerSave |\\r
+ Init.BusWide |\\r
+ Init.HardwareFlowControl |\\r
+ Init.ClockDiv\r
+ ); \r
+ \r
+ /* Write to SDMMC CLKCR */\r
+ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### I/O operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the SDMMC data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Read data (word) from Rx FIFO in blocking mode (polling) \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval HAL status\r
+ */\r
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ /* Read data from Rx FIFO */ \r
+ return (SDMMCx->FIFO);\r
+}\r
+\r
+/**\r
+ * @brief Write data (word) to Tx FIFO in blocking mode (polling) \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @param pWriteData: pointer to data to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)\r
+{ \r
+ /* Write data to FIFO */ \r
+ SDMMCx->FIFO = *pWriteData;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the SDMMC data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set SDMMC Power state to ON. \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)\r
+{ \r
+ /* Set power state to ON */ \r
+ SDMMCx->POWER = SDMMC_POWER_PWRCTRL;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Set SDMMC Power state to OFF. \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ /* Set power state to OFF */\r
+ SDMMCx->POWER = (uint32_t)0x00000000;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get SDMMC Power state. \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval Power status of the controller. The returned value can be one of the \r
+ * following values:\r
+ * - 0x00: Power OFF\r
+ * - 0x02: Power UP\r
+ * - 0x03: Power ON \r
+ */\r
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) \r
+{\r
+ return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);\r
+}\r
+\r
+/**\r
+ * @brief Configure the SDMMC command path according to the specified parameters in\r
+ * SDMMC_CmdInitTypeDef structure and send the command \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains \r
+ * the configuration information for the SDMMC command\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));\r
+ assert_param(IS_SDMMC_RESPONSE(Command->Response));\r
+ assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));\r
+ assert_param(IS_SDMMC_CPSM(Command->CPSM));\r
+\r
+ /* Set the SDMMC Argument value */\r
+ SDMMCx->ARG = Command->Argument;\r
+\r
+ /* Set SDMMC command parameters */\r
+ tmpreg |= (uint32_t)(Command->CmdIndex |\\r
+ Command->Response |\\r
+ Command->WaitForInterrupt |\\r
+ Command->CPSM);\r
+ \r
+ /* Write to SDMMC CMD register */\r
+ MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Return the command index of last command for which response received\r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval Command index of the last command response received\r
+ */\r
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ return (uint8_t)(SDMMCx->RESPCMD);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the response received from the card for the last command\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @param Response: Specifies the SDMMC response register. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_RESP1: Response Register 1\r
+ * @arg SDMMC_RESP2: Response Register 2\r
+ * @arg SDMMC_RESP3: Response Register 3\r
+ * @arg SDMMC_RESP4: Response Register 4 \r
+ * @retval The Corresponding response register value\r
+ */\r
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_RESP(Response));\r
+ \r
+ /* Get the response */\r
+ tmp = (uint32_t)&(SDMMCx->RESP1) + Response;\r
+ \r
+ return (*(__IO uint32_t *) tmp);\r
+} \r
+\r
+/**\r
+ * @brief Configure the SDMMC data path according to the specified \r
+ * parameters in the SDMMC_DataInitTypeDef.\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @param Data : pointer to a SDMMC_DataInitTypeDef structure \r
+ * that contains the configuration information for the SDMMC data.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));\r
+ assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));\r
+ assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));\r
+ assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));\r
+ assert_param(IS_SDMMC_DPSM(Data->DPSM));\r
+\r
+ /* Set the SDMMC Data TimeOut value */\r
+ SDMMCx->DTIMER = Data->DataTimeOut;\r
+\r
+ /* Set the SDMMC DataLength value */\r
+ SDMMCx->DLEN = Data->DataLength;\r
+\r
+ /* Set the SDMMC data configuration parameters */\r
+ tmpreg |= (uint32_t)(Data->DataBlockSize |\\r
+ Data->TransferDir |\\r
+ Data->TransferMode |\\r
+ Data->DPSM);\r
+ \r
+ /* Write to SDMMC DCTRL */\r
+ MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);\r
+\r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Returns number of remaining data bytes to be transferred.\r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval Number of remaining data bytes to be transferred\r
+ */\r
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ return (SDMMCx->DCOUNT);\r
+}\r
+\r
+/**\r
+ * @brief Get the FIFO data\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @retval Data received\r
+ */\r
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ return (SDMMCx->FIFO);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets one of the two options of inserting read wait interval.\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.\r
+ * This parameter can be:\r
+ * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK\r
+ * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));\r
+\r
+ /* Set SDMMC read wait mode */\r
+ MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_usb.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 22-April-2016\r
+ * @brief USB Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r
+ \r
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r
+\r
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_LL_USB_DRIVER\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LL_USB_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization/de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the USB Core\r
+ * @param USBx: USB Instance\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+ {\r
+ \r
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+\r
+ /* Init The ULPI Interface */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r
+ \r
+ /* Select vbus source */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r
+ if(cfg.use_external_vbus == 1)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r
+ }\r
+ /* Reset after a PHY select */\r
+ USB_CoreReset(USBx); \r
+ }\r
+ else /* FS interface (embedded Phy) */\r
+ {\r
+ /* Select FS Embedded PHY */\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r
+ \r
+ /* Reset after a PHY select and set Host mode */\r
+ USB_CoreReset(USBx);\r
+ \r
+ /* Deactivate the power down*/\r
+ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;\r
+ }\r
+ \r
+ if(cfg.dma_enable == ENABLE)\r
+ {\r
+ USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);\r
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;\r
+ } \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EnableGlobalInt\r
+ * Enables the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_DisableGlobalInt\r
+ * Disable the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief USB_SetCurrentMode : Set functional mode\r
+ * @param USBx : Selected device\r
+ * @param mode : current core mode\r
+ * This parameter can be one of these values:\r
+ * @arg USB_OTG_DEVICE_MODE: Peripheral mode\r
+ * @arg USB_OTG_HOST_MODE: Host mode\r
+ * @arg USB_OTG_DRD_MODE: Dual Role Device mode \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)\r
+{\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); \r
+ \r
+ if ( mode == USB_OTG_HOST_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; \r
+ }\r
+ else if ( mode == USB_OTG_DEVICE_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; \r
+ }\r
+ HAL_Delay(50);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevInit : Initializes the USB_OTG controller registers \r
+ * for device mode\r
+ * @param USBx : Selected device\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ uint32_t i = 0;\r
+\r
+ /*Activate VBUS Sensing B */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+ \r
+ if (cfg.vbus_sensing_enable == 0)\r
+ {\r
+ /* Deactivate VBUS Sensing B */\r
+ USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;\r
+ \r
+ /* B-peripheral session valid override enable*/ \r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r
+ }\r
+ \r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0;\r
+\r
+ /* Device mode configuration */\r
+ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r
+ \r
+ if(cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+ {\r
+ if(cfg.speed == USB_OTG_SPEED_HIGH)\r
+ { \r
+ /* Set High speed phy */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);\r
+ }\r
+ else \r
+ {\r
+ /* set High speed phy in Full speed mode */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set Full speed phy */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);\r
+ }\r
+\r
+ /* Flush the FIFOs */\r
+ USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */\r
+ USB_FlushRxFifo(USBx);\r
+ \r
+ /* Clear all pending Device Interrupts */\r
+ USBx_DEVICE->DIEPMSK = 0;\r
+ USBx_DEVICE->DOEPMSK = 0;\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ USBx_DEVICE->DAINTMSK = 0;\r
+ \r
+ for (i = 0; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = 0;\r
+ }\r
+ \r
+ USBx_INEP(i)->DIEPTSIZ = 0;\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ }\r
+ \r
+ for (i = 0; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = 0;\r
+ }\r
+ \r
+ USBx_OUTEP(i)->DOEPTSIZ = 0;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ \r
+ USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r
+ \r
+ if (cfg.dma_enable == 1)\r
+ {\r
+ /*Set threshold parameters */\r
+ USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);\r
+ USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);\r
+ \r
+ i= USBx_DEVICE->DTHRCTL;\r
+ }\r
+ \r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0;\r
+ \r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xBFFFFFFF;\r
+\r
+ /* Enable the common interrupts */\r
+ if (cfg.dma_enable == DISABLE)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r
+ }\r
+ \r
+ /* Enable interrupts matching to the Device mode ONLY */\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\\r
+ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\\r
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r
+ \r
+ if(cfg.Sof_enable)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r
+ }\r
+\r
+ if (cfg.vbus_sensing_enable == ENABLE)\r
+ {\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO\r
+ * @param USBx : Selected device\r
+ * @param num : FIFO number\r
+ * This parameter can be a value from 1 to 15\r
+ 15 means Flush all Tx FIFOs\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); \r
+ \r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_FlushRxFifo : Flush Rx FIFO\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r
+ \r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register \r
+ * depending the PHY type and the enumeration speed of the device.\r
+ * @param USBx : Selected device\r
+ * @param speed : device speed\r
+ * This parameter can be one of these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ * @retval Hal status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)\r
+{\r
+ USBx_DEVICE->DCFG |= speed;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_GetDevSpeed :Return the Dev Speed \r
+ * @param USBx : Selected device\r
+ * @retval speed : device speed\r
+ * This parameter can be one of these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ */\r
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint8_t speed = 0;\r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)\r
+ {\r
+ speed = USB_OTG_SPEED_HIGH;\r
+ }\r
+ else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||\r
+ ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))\r
+ {\r
+ speed = USB_OTG_SPEED_FULL;\r
+ }\r
+ else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+ {\r
+ speed = USB_OTG_SPEED_LOW;\r
+ }\r
+ \r
+ return speed;\r
+}\r
+\r
+/**\r
+ * @brief Activate and configure an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r
+ \r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ } \r
+\r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r
+ \r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Activate and configure a dedicated endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ static __IO uint32_t debug = 0;\r
+ \r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ } \r
+ \r
+ \r
+ debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ \r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));\r
+ \r
+ debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);\r
+ debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;\r
+ debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); \r
+ } \r
+ \r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief De-activate and de-initialize an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); \r
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; \r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); \r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-activate and de-initialize a dedicated endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; \r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r
+{\r
+ uint16_t pktcnt = 0;\r
+ \r
+ /* IN endpoint */\r
+ if (ep->is_in == 1)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); \r
+ } \r
+ }\r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r
+ }\r
+ else\r
+ {\r
+ if (ep->type != EP_TYPE_ISOC)\r
+ {\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+ } \r
+ \r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); \r
+ } \r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */ \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r
+ \r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; \r
+ }\r
+ else\r
+ {\r
+ pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); \r
+ }\r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;\r
+ }\r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+ }\r
+ /* EP enable */\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r
+{\r
+ /* IN endpoint */\r
+ if (ep->is_in == 1)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ \r
+ if(ep->xfer_len > ep->maxpacket)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r
+ \r
+ }\r
+ \r
+ if (dma == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r
+ }\r
+ else\r
+ {\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);\r
+ }\r
+ }\r
+ \r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); \r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r
+ \r
+ if (ep->xfer_len > 0)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+ \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); \r
+ \r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);\r
+ }\r
+ \r
+ /* EP enable */\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated \r
+ * with the EP/channel\r
+ * @param USBx : Selected device \r
+ * @param src : pointer to source buffer\r
+ * @param ch_ep_num : endpoint or host channel number\r
+ * @param len : Number of bytes to write\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)\r
+{\r
+ uint32_t count32b= 0 , i= 0;\r
+ \r
+ if (dma == 0)\r
+ {\r
+ count32b = (len + 3) / 4;\r
+ for (i = 0; i < count32b; i++, src += 4)\r
+ {\r
+ USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadPacket : read a packet from the Tx FIFO associated \r
+ * with the EP/channel\r
+ * @param USBx : Selected device \r
+ * @param src : source pointer\r
+ * @param ch_ep_num : endpoint or host channel number\r
+ * @param len : Number of bytes to read\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval pointer to destination buffer\r
+ */\r
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r
+{\r
+ uint32_t i=0;\r
+ uint32_t count32b = (len + 3) / 4;\r
+ \r
+ for ( i = 0; i < count32b; i++, dest += 4 )\r
+ {\r
+ *(__packed uint32_t *)dest = USBx_DFIFO(0);\r
+ \r
+ }\r
+ return ((void *)dest);\r
+}\r
+\r
+/**\r
+ * @brief USB_EPSetStall : set a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); \r
+ } \r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); \r
+ } \r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_EPClearStall : Clear a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ } \r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_StopDevice : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t i;\r
+ \r
+ /* Clear Pending interrupt */\r
+ for (i = 0; i < 15 ; i++)\r
+ {\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ \r
+ /* Clear interrupt masks */\r
+ USBx_DEVICE->DIEPMSK = 0;\r
+ USBx_DEVICE->DOEPMSK = 0;\r
+ USBx_DEVICE->DAINTMSK = 0;\r
+ \r
+ /* Flush the FIFO */\r
+ USB_FlushRxFifo(USBx);\r
+ USB_FlushTxFifo(USBx , 0x10 ); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevAddress : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @param address : new device address to be assigned\r
+ * This parameter can be a value from 0 to 255\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r
+{\r
+ USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);\r
+ USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;\r
+ HAL_Delay(3);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;\r
+ HAL_Delay(3);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_ReadInterrupts: return the global USB interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v = 0;\r
+ \r
+ v = USBx->GINTSTS;\r
+ v &= USBx->GINTMSK;\r
+ return v; \r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v;\r
+ v = USBx_DEVICE->DAINT;\r
+ v &= USBx_DEVICE->DAINTMSK;\r
+ return ((v & 0xffff0000) >> 16);\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v;\r
+ v = USBx_DEVICE->DAINT;\r
+ v &= USBx_DEVICE->DAINTMSK;\r
+ return ((v & 0xFFFF));\r
+}\r
+\r
+/**\r
+ * @brief Returns Device OUT EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device OUT EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r
+{\r
+ uint32_t v;\r
+ v = USBx_OUTEP(epnum)->DOEPINT;\r
+ v &= USBx_DEVICE->DOEPMSK;\r
+ return v;\r
+}\r
+\r
+/**\r
+ * @brief Returns Device IN EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device IN EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r
+{\r
+ uint32_t v, msk, emp;\r
+ \r
+ msk = USBx_DEVICE->DIEPMSK;\r
+ emp = USBx_DEVICE->DIEPEMPMSK;\r
+ msk |= ((emp >> epnum) & 0x1) << 7;\r
+ v = USBx_INEP(epnum)->DIEPINT & msk;\r
+ return v;\r
+}\r
+\r
+/**\r
+ * @brief USB_ClearInterrupts: clear a USB interrupt\r
+ * @param USBx : Selected device\r
+ * @param interrupt : interrupt flag\r
+ * @retval None\r
+ */\r
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r
+{\r
+ USBx->GINTSTS |= interrupt; \r
+}\r
+\r
+/**\r
+ * @brief Returns USB core mode\r
+ * @param USBx : Selected device\r
+ * @retval return core mode : Host or Device\r
+ * This parameter can be one of these values:\r
+ * 0 : Host \r
+ * 1 : Device\r
+ */\r
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return ((USBx->GINTSTS ) & 0x1);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Activate EP0 for Setup transactions\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ /* Set the MPS of the IN EP based on the enumeration speed */\r
+ USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+ {\r
+ USBx_INEP(0)->DIEPCTL |= 3;\r
+ }\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Prepare the EP0 to start the first control setup\r
+ * @param USBx : Selected device\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @param psetup : pointer to setup packet\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)\r
+{\r
+ USBx_OUTEP(0)->DOEPTSIZ = 0;\r
+ USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);\r
+ USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; \r
+ \r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;\r
+ /* EP enable */\r
+ USBx_OUTEP(0)->DOEPCTL = 0x80008000;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Reset the USB Core (needed after USB clock settings change)\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0;\r
+\r
+ /* Wait for AHB master IDLE state. */\r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);\r
+ \r
+ /* Core Soft Reset */\r
+ count = 0;\r
+ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r
+\r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_HostInit : Initializes the USB OTG controller registers \r
+ * for Host mode \r
+ * @param USBx : Selected device\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ uint32_t i;\r
+ \r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0;\r
+ \r
+ /*Activate VBUS Sensing B */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+ \r
+ /* Disable the FS/LS support mode only */\r
+ if((cfg.speed == USB_OTG_SPEED_FULL)&&\r
+ (USBx != USB_OTG_FS))\r
+ {\r
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; \r
+ }\r
+ else\r
+ {\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); \r
+ }\r
+\r
+ /* Make sure the FIFOs are flushed. */\r
+ USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */\r
+ USB_FlushRxFifo(USBx);\r
+\r
+ /* Clear all pending HC Interrupts */\r
+ for (i = 0; i < cfg.Host_channels; i++)\r
+ {\r
+ USBx_HC(i)->HCINT = 0xFFFFFFFF;\r
+ USBx_HC(i)->HCINTMSK = 0;\r
+ }\r
+ \r
+ /* Enable VBUS driving */\r
+ USB_DriveVbus(USBx, 1);\r
+ \r
+ HAL_Delay(200);\r
+ \r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0;\r
+ \r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xFFFFFFFF;\r
+ \r
+ if(USBx == USB_OTG_FS)\r
+ {\r
+ /* set Rx FIFO size */\r
+ USBx->GRXFSIZ = (uint32_t )0x80; \r
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);\r
+ USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);\r
+ }\r
+ else\r
+ {\r
+ /* set Rx FIFO size */\r
+ USBx->GRXFSIZ = (uint32_t )0x200; \r
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);\r
+ USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);\r
+ }\r
+ \r
+ /* Enable the common interrupts */\r
+ if (cfg.dma_enable == DISABLE)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r
+ }\r
+ \r
+ /* Enable interrupts matching to the Host mode ONLY */\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\\r
+ USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the \r
+ * HCFG register on the PHY type and set the right frame interval\r
+ * @param USBx : Selected device\r
+ * @param freq : clock frequency\r
+ * This parameter can be one of these values:\r
+ * HCFG_48_MHZ : Full Speed 48 MHz Clock \r
+ * HCFG_6_MHZ : Low Speed 6 MHz Clock \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)\r
+{\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r
+ USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);\r
+ \r
+ if (freq == HCFG_48_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)48000;\r
+ }\r
+ else if (freq == HCFG_6_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)6000;\r
+ } \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+* @brief USB_OTG_ResetPort : Reset Host Port\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ * @note : (1)The application must wait at least 10 ms\r
+ * before clearing the reset bit.\r
+ */\r
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ __IO uint32_t hprt0;\r
+ \r
+ hprt0 = USBx_HPRT0;\r
+ \r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); \r
+ HAL_Delay (10); /* See Note #1 */\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DriveVbus : activate or de-activate vbus\r
+ * @param state : VBUS state\r
+ * This parameter can be one of these values:\r
+ * 0 : VBUS Active \r
+ * 1 : VBUS Inactive\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r
+{\r
+ __IO uint32_t hprt0;\r
+\r
+ hprt0 = USBx_HPRT0;\r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))\r
+ {\r
+ USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); \r
+ }\r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))\r
+ {\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); \r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Return Host Core speed\r
+ * @param USBx : Selected device\r
+ * @retval speed : Host speed\r
+ * This parameter can be one of these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ */\r
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ __IO uint32_t hprt0;\r
+ \r
+ hprt0 = USBx_HPRT0;\r
+ return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r
+}\r
+\r
+/**\r
+ * @brief Return Host Current Frame number\r
+ * @param USBx : Selected device\r
+ * @retval current frame number\r
+*/\r
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r
+}\r
+\r
+/**\r
+ * @brief Initialize a host channel\r
+ * @param USBx : Selected device\r
+ * @param ch_num : Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param epnum : Endpoint number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param dev_address : Current device address\r
+ * This parameter can be a value from 0 to 255\r
+ * @param speed : Current device speed\r
+ * This parameter can be one of these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ * @param ep_type : Endpoint Type\r
+ * This parameter can be one of these values:\r
+ * @arg EP_TYPE_CTRL: Control type\r
+ * @arg EP_TYPE_ISOC: Isochronous type\r
+ * @arg EP_TYPE_BULK: Bulk type\r
+ * @arg EP_TYPE_INTR: Interrupt type\r
+ * @param mps : Max Packet Size\r
+ * This parameter can be a value from 0 to32K\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, \r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps)\r
+{\r
+ \r
+ /* Clear old interrupt conditions for this host channel. */\r
+ USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;\r
+ \r
+ /* Enable channel interrupts required for this transfer. */\r
+ switch (ep_type) \r
+ {\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_STALLM |\\r
+ USB_OTG_HCINTMSK_TXERRM |\\r
+ USB_OTG_HCINTMSK_DTERRM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_NAKM ;\r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ } \r
+ else \r
+ {\r
+ if(USBx != USB_OTG_FS)\r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case EP_TYPE_INTR:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_STALLM |\\r
+ USB_OTG_HCINTMSK_TXERRM |\\r
+ USB_OTG_HCINTMSK_DTERRM |\\r
+ USB_OTG_HCINTMSK_NAKM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_FRMORM ; \r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ }\r
+ \r
+ break;\r
+ case EP_TYPE_ISOC:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_ACKM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_FRMORM ; \r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); \r
+ }\r
+ break;\r
+ }\r
+ \r
+ /* Enable the top level host channel interrupt. */\r
+ USBx_HOST->HAINTMSK |= (1 << ch_num);\r
+ \r
+ /* Make sure host channel interrupts are enabled. */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r
+ \r
+ /* Program the HCCHAR register */\r
+ USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\\r
+ (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\\r
+ ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\\r
+ (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\\r
+ ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\\r
+ (mps & USB_OTG_HCCHAR_MPSIZ));\r
+ \r
+ if (ep_type == EP_TYPE_INTR)\r
+ {\r
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r
+ }\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Start a transfer over a host channel\r
+ * @param USBx : Selected device\r
+ * @param hc : pointer to host channel structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL state\r
+ */\r
+#if defined (__CC_ARM) /*!< ARM Compiler */\r
+#pragma O0\r
+#elif defined (__GNUC__) /*!< GNU Compiler */\r
+#pragma GCC optimize ("O0")\r
+#endif /* __CC_ARM */\r
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)\r
+{\r
+ uint8_t is_oddframe = 0; \r
+ uint16_t len_words = 0; \r
+ uint16_t num_packets = 0;\r
+ uint16_t max_hc_pkt_count = 256;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))\r
+ {\r
+ if((dma == 0) && (hc->do_ping == 1))\r
+ {\r
+ USB_DoPing(USBx, hc->ch_num);\r
+ return HAL_OK;\r
+ }\r
+ else if(dma == 1)\r
+ {\r
+ USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r
+ hc->do_ping = 0;\r
+ }\r
+ }\r
+ \r
+ /* Compute the expected number of packets associated to the transfer */\r
+ if (hc->xfer_len > 0)\r
+ {\r
+ num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;\r
+ \r
+ if (num_packets > max_hc_pkt_count)\r
+ {\r
+ num_packets = max_hc_pkt_count;\r
+ hc->xfer_len = num_packets * hc->max_packet;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ num_packets = 1;\r
+ }\r
+ if (hc->ep_is_in)\r
+ {\r
+ hc->xfer_len = num_packets * hc->max_packet;\r
+ }\r
+ \r
+ /* Initialize the HCTSIZn register */\r
+ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\\r
+ ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\r
+ (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);\r
+ \r
+ if (dma)\r
+ {\r
+ /* xfer_buff MUST be 32-bits aligned */\r
+ USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;\r
+ }\r
+ \r
+ is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;\r
+ USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r
+ USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);\r
+ \r
+ /* Set host channel enable */\r
+ tmpreg = USBx_HC(hc->ch_num)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hc->ch_num)->HCCHAR = tmpreg;\r
+ \r
+ if (dma == 0) /* Slave mode */\r
+ { \r
+ if((hc->ep_is_in == 0) && (hc->xfer_len > 0))\r
+ {\r
+ switch(hc->ep_type) \r
+ {\r
+ /* Non periodic transfer */\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+ \r
+ len_words = (hc->xfer_len + 3) / 4;\r
+ \r
+ /* check if there is enough space in FIFO space */\r
+ if(len_words > (USBx->HNPTXSTS & 0xFFFF))\r
+ {\r
+ /* need to process data in nptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r
+ }\r
+ break;\r
+ /* Periodic transfer */\r
+ case EP_TYPE_INTR:\r
+ case EP_TYPE_ISOC:\r
+ len_words = (hc->xfer_len + 3) / 4;\r
+ /* check if there is enough space in FIFO space */\r
+ if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */\r
+ {\r
+ /* need to process data in ptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; \r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+ \r
+ /* Write packet into the Tx FIFO. */\r
+ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);\r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read all host channel interrupts status\r
+ * @param USBx : Selected device\r
+ * @retval HAL state\r
+ */\r
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return ((USBx_HOST->HAINT) & 0xFFFF);\r
+}\r
+\r
+/**\r
+ * @brief Halt a host channel\r
+ * @param USBx : Selected device\r
+ * @param hc_num : Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ /* Check for space in the request queue to issue the halt. */\r
+ if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+ \r
+ if ((USBx->HNPTXSTS & 0xFFFF) == 0)\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); \r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+ \r
+ if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); \r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initiate Do Ping protocol\r
+ * @param USBx : Selected device\r
+ * @param hc_num : Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)\r
+{\r
+ uint8_t num_packets = 1;\r
+ uint32_t tmpreg = 0;\r
+\r
+ USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\r
+ USB_OTG_HCTSIZ_DOPING;\r
+ \r
+ /* Set host channel enable */\r
+ tmpreg = USBx_HC(ch_num)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(ch_num)->HCCHAR = tmpreg;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Stop Host Core\r
+ * @param USBx : Selected device\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint8_t i;\r
+ uint32_t count = 0;\r
+ uint32_t value;\r
+ \r
+ USB_DisableGlobalInt(USBx);\r
+ \r
+ /* Flush FIFO */\r
+ USB_FlushTxFifo(USBx, 0x10);\r
+ USB_FlushRxFifo(USBx);\r
+ \r
+ /* Flush out any leftover queued requests. */\r
+ for (i = 0; i <= 15; i++)\r
+ { \r
+\r
+ value = USBx_HC(i)->HCCHAR ;\r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value &= ~USB_OTG_HCCHAR_CHENA; \r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ USBx_HC(i)->HCCHAR = value;\r
+ }\r
+ \r
+ /* Halt all channels to put them into a known state. */ \r
+ for (i = 0; i <= 15; i++)\r
+ {\r
+ value = USBx_HC(i)->HCCHAR ;\r
+ \r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value |= USB_OTG_HCCHAR_CHENA; \r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ \r
+ USBx_HC(i)->HCCHAR = value;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+ }\r
+\r
+ /* Clear any pending Host interrupts */\r
+ USBx_HOST->HAINT = 0xFFFFFFFF;\r
+ USBx->GINTSTS = 0xFFFFFFFF;\r
+ USB_EnableGlobalInt(USBx);\r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+# common make include for libraries\r
+\r
+reverse = $(if $(wordlist 2,2,$(1)),$(call reverse,$(wordlist 2,$(words $(1)),$(1))) $(firstword $(1)),$(1))\r
+\r
+LIB_OUT := ../$(PJDIR)/$(ARDIR)/$(LIBNAME)\r
+OBJ_OUT := ../$(PJDIR)/$(OBJDIR)/$(LIBNAME:.a=)\r
+\r
+CFLAGS := $(patsubst -I%,-I../$(PJDIR)/%,$(CFLAGS))\r
+ASFLAGS := $(patsubst -I%,-I../$(PJDIR)/%,$(ASFLAGS))\r
+\r
+SRCS_CC := $(filter-out %template.c,$(SRCS_C))\r
+SRCS_CC := $(filter-out $(LIB_EXCL),$(SRCS_CC))\r
+\r
+OBJSC := $(patsubst %.c,%.o,$(SRCS_CC)) \r
+OBJSC := $(patsubst %,$(OBJ_OUT)/%,$(OBJSC)) \r
+\r
+OBJSS := $(patsubst %.s,%.o,$(SRCS_S))\r
+OBJSS := $(patsubst %,$(OBJ_OUT)/%,$(OBJSS)) \r
+\r
+DEP := ../$(PJDIR)/$(ARDIR)/$(LIBNAME:.a=.d)\r
+DEP1 := ../$(PJDIR)/$(ARDIR)/$(LIBNAME:.a=.d.d)\r
+#DEP2 := ../$(PJDIR)/$(ARDIR)/$(LIBNAME:.a=.d.d.d)\r
+SRCS = $(SRCS_C) $(SRCS_S)\r
+#OBJS = $(call reverse, $(sort $(OBJSC) $(OBJSS)))\r
+#OBJS = $(sort $(OBJSC) $(OBJSS))\r
+OBJS = $(OBJSC) $(OBJSS)\r
+\r
+#test1:\r
+# @echo $(LIB_OBJS)\r
+# @echo $(SRCS_C)\r
+# @echo $(SRCS_S)\r
+\r
+.PHONY: all\r
+\r
+all: $(LIB_OUT)\r
+ @touch $(LIB_OUT)\r
+\r
+zz:\r
+ @echo $(OBJ_OUT)\r
+ @echo $(LIB_OUT)\r
+ @echo $(SRCS)\r
+ @echo $(OBJS)\r
+\r
+$(LIB_OUT): $(OBJS)\r
+ @echo ar $@\r
+ @$(AR) $(ARFLAGS) $@ $^\r
+# @echo $(LIB_OUT)\r
+ @cat $(OBJS:.o=.d) \\r
+ | sed -e 's/.*://' -e 's/\\$$//' \\r
+ | fmt -1 | sort | uniq \\r
+ | sed -e 's,^ \([^.]\), '../$(PJDIR)/$(LIBDIR)/'\1,' \\r
+ | sed -n 's,'../$(PJDIR)/',,p' \\r
+ | sed -e 's/$$/ \\/' -e '$$ s/\\$$//' -e '1 i '$(ARDIR)/$(LIBNAME)': \\' \\r
+ > $(DEP)\r
+\r
+.PHONY: clean\r
+clean:\r
+ @-rm -f $(OBJS) $(OBJS:.o=.d) $(LIB_OUT) $(DEP) $(DEP1) $(DEP2)\r
+\r
+#depend dep: $(DEP)\r
+\r
+#$(DEP): Src/*.c\r
+# $(CCDEP) $(CFLAGS) -MM $^ | sed -e 's@.*.o:@Src/&@' > $(DEP) \r
+\r
+#$(DEP): $(LIB_SRCS_C)\r
+# $(CCDEP) $(CFLAGS) -MM $^ > $(DEP) \r
+\r
+#$(DEP): $(SRCS)\r
+# @rm -f $(DEP)\r
+# @$(foreach SRC,$(SRCS_S),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.s=.o) $(SRC) >> $(DEP) || { rm $(DEP); exit 1; };)\r
+# @$(foreach SRC,$(SRCS_C),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.c=.o) $(SRC) >> $(DEP) || { rm $(DEP); exit 1; };)\r
+\r
+#.c.o:\r
+$(OBJSC): $(OBJ_OUT)/%.o: %.c\r
+ @mkdir -p $(dir $@)\r
+# @echo cc \[$(PJNAME): $(LIBNAME)\] $<\r
+ifeq ($(SHOWPJ),1)\r
+ @echo cc \[$(PJNAME)\] $<\r
+else\r
+ @echo cc $<\r
+endif\r
+# @echo $(CFLAGS)\r
+ @$(CC) $(CFLAGS) -MMD -c -o $@ $<\r
+\r
+#.s.o:\r
+$(OBJSS): $(OBJ_OUT)/%.o: %.s\r
+ @mkdir -p $(dir $@)\r
+ @echo as $<\r
+ @$(AS) $(ASFLAGS) -MMD -c -o $@ $<\r
+\r
+-include $(OBJS:.o=.d)\r
+#-include $(DEP)\r
+ \r
--- /dev/null
+# Compile the STM32F7xx HAL Driver Library
+
+LIBN := libstm32f7xxhal.a
+LIBD := STM32F7xx_HAL_Driver
+LIBP := fw
+
+# this part is to be included at the top of the project Makefile
+ifeq '$(INCLIBS)' 'inc'
+
+$(info including $(LIBN))
+
+LIBS += $(ARDIR)/$(LIBN)
+LIBDIRS += $(LIBDIR)/$(LIBD)
+PORTDIRS += $(PORTDIR)/$(LIBP)
+LIBS_OPT += -DUSE_HAL_DRIVER
+SRCS_ADD += $(LIBDIR)/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c
+
+INC += $(LIBDIR)/$(LIBD)/Inc
+INC += $(PORTDIR)/$(LIBP)
+
+endif
+
+#this part is to be called to build the lib
+ifeq '$(INCLIBS)' 'mk'
+export
+#$(info making $(LIBN))
+
+LIBNAME := $(LIBN)
+
+SRCS_C := $(wildcard $(LIBD)/Src/*.c)
+SRCS_S := $(wildcard $(LIBD)/Src/*.s)
+
+include lib.mk
+
+endif
+
+LIBN :=
+LIBD :=
+LIBP :=
--- /dev/null
+/hdma.*Instance/ {
+ b=$3;
+ a=$1;
+ sub("hdma_","",a);
+ sub(".Instance","",a);
+ a=toupper(a);
+ sub("UART","USART",a);
+ sub(";","",b);
+ sub("\r","",b);
+ printf("#define DMA_IRQ_%s %s_IRQHandler\n",a,b);
+ split(b,c,"_");
+ d1 = substr(c[1], 1, length(c[1])-1);
+ n1 = substr(c[1], length(c[1]), 1);
+ d2 = substr(c[2], 1, length(c[2])-1);
+ n2 = substr(c[2], length(c[2]), 1);
+ if (d2 = "Stream") {
+ printf("#ifdef DMAv2\n");
+ if (n2 <= 3) {
+ printf("#define TCIF_%s ((DMA%s->LISR & DMA_LISR_TCIF%d)!=0)\n",a,n1,n2);
+ printf("#define CTCIF_%s (DMA%s->LIFCR |= DMA_LIFCR_CTCIF%d)\n",a,n1,n2);
+ } else {
+ printf("#define TCIF_%s ((DMA%s->HISR & DMA_HISR_TCIF%d)!=0)\n",a,n1,n2);
+ printf("#define CTCIF_%s (DMA%s->HIFCR |= DMA_HIFCR_CTCIF%d)\n",a,n1,n2);
+ }
+ printf("#endif\n");
+ printf("#ifdef DMAv1\n");
+ printf("#define TCIF_%s ((DMA%s->ISR & DMA_ISR_TCIF%d)!=0)\n",a,n1,n2);
+ printf("#define CTCIF_%s (DMA%s->IFCR |= DMA_IFCR_CTCIF%d)\n",a,n1,n2);
+ printf("#endif\n");
+
+ };
+ printf("\n");
+}
--- /dev/null
+INC += $(CUBEDIR)/$(PJNAME)/Inc\r
+#CSRCDIRS += $(CUBEDIR)/$(PJNAME)/Src\r
+\r
+C_ISR_NAME := $(notdir $(wildcard $(CUBEDIR)/$(PJNAME)/Src/stm*it.c))\r
+C_ISR_FILE := $(CUBEDIR)/$(PJNAME)/Src/cube_$(C_ISR_NAME)\r
+C_MAIN_FILE := $(CUBEDIR)/$(PJNAME)/Src/cube_main.c \r
+C_DMA_FILE := $(CUBEDIR)/$(PJNAME)/Inc/cube_dma.h\r
+ifeq ($(CHIBIOS_PORT),)\r
+C_IRQH_FILE :=\r
+else\r
+C_IRQH_FILE := $(CUBEDIR)/$(PJNAME)/Inc/$(CHIBIOS_PORT)-irqs.h\r
+endif\r
+C_AWK_DMA := $(COMDIR)/pj/cube-hal-dma.awk\r
+C_AWK_IRQ := $(COMDIR)/pj/cube-hal-irqs.awk\r
+\r
+CLEAN_ADD += $(C_ISR_FILE) $(C_MAIN_FILE) $(C_DMA_FILE) $(C_IRQH_FILE)\r
+GEN_ADD += $(C_ISR_FILE) $(C_MAIN_FILE) $(C_DMA_FILE) $(C_IRQH_FILE)\r
+SRCS_ADD += $(patsubst %_it.c,, $(patsubst %main.c,, $(wildcard $(CUBEDIR)/$(PJNAME)/Src/*.c)))\r
+SRCS_ADD += $(C_MAIN_FILE) $(C_ISR_FILE)\r
+C_DEPS += $(C_DMA_FILE)\r
+FILES_ADD += $(C_AWK_DMA) \r
+\r
+$(C_MAIN_FILE): $(CUBEDIR)/$(PJNAME)/Src/main.c\r
+ @echo gen $@\r
+# @echo generate $(C_MAIN_FILE) calling main1\(\)\r
+ifeq ($(CHIBIOS_PORT),)\r
+ @cat $< \\r
+ | sed -e '/USER CODE END PFP/ i void main1\(void\);' \\r
+ | sed -e '/USER CODE BEGIN WHILE/ i main1();' \\r
+ | sed -e '/int main(void)/ i __weak' \\r
+ > $@\r
+else\r
+ @cat $< \\r
+ | sed -e '/USER CODE END PFP/ i void main1\(void\);' \\r
+ | sed -e '/USER CODE BEGIN WHILE/ i main1();' \\r
+ | sed -e '/int main(void)/ i __weak' \\r
+ | sed -e 's/SCB_EnableICache()/\/\/removed by cube-hal.mk/' \\r
+ | sed -e 's/SCB_EnableDCache()/\/\/removed by cube-hal.mk/' \\r
+ > $@\r
+endif\r
+\r
+ifeq ($(CHIBIOS_PORT),)\r
+else\r
+FILES_ADD += $(C_AWK_IRQ)\r
+$(C_ISR_FILE): $(C_IRQH_FILE)\r
+\r
+$(C_IRQH_FILE): $(C_AWK_IRQ) $(CHIBIOS_IRQ_S_FILE)\r
+ifeq ($(CHIBIOS_IRQ_S_FILE),)\r
+ @echo missing startup_stm32xx.s file && false -\r
+endif\r
+ @echo gen $@\r
+ @test -f $(CHIBIOS_IRQ_S_FILE) && cat $(CHIBIOS_IRQ_S_FILE) \\r
+ |sed -e 's/\r$///' | gawk -f $(C_AWK_IRQ) \\r
+ > $@\r
+endif\r
+\r
+$(C_ISR_FILE): $(CUBEDIR)/$(PJNAME)/Src/$(C_ISR_NAME)\r
+ @echo gen $@\r
+# @echo generate $(C_ISR_FILE) declaring ISRs as weak symbols\r
+ifeq ($(CHIBIOS_PORT),)\r
+ @cat $< \\r
+ | sed -e '/IRQHandler(void)/ i __weak' \\r
+ > $@\r
+else\r
+ @cat $< \\r
+ | sed -e '/USER CODE END 0/ i #include "$(CHIBIOS_PORT)-irqs.h"' \\r
+ | sed -e '/Handler(void)/ i __weak' \\r
+ > $@\r
+endif\r
+ \r
+$(C_DMA_FILE): $(CUBEDIR)/$(PJNAME)/Src/main.c $(C_AWK_DMA)\r
+ @echo gen $@\r
+# @echo generate $(C_DMA_FILE) \r
+ @cat $(CUBEDIR)/$(PJNAME)/Src/*.c \\r
+ | gawk -f $(C_AWK_DMA) \\r
+ > $(C_DMA_FILE)\r
--- /dev/null
+DEVICE_FAMILY := STM32F7xx
+DEVICE_TYPE := STM32F767xx
+STARTUP_FILE := stm32f767xx
+SYSTEM_FILE := stm32f7xx
+LDSCRIPT := stm32f767xi.ld
+
+CMSIS = $(LIBDIR)/CMSIS-hal
+CMSIS_DEVSUP = $(CMSIS)/Device/ST/$(DEVICE_FAMILY)
+CMSIS_CORESUP = $(CMSIS)/Include
+CMSIS_OPT = -D$(DEVICE_TYPE)
+GCC_OPT = -Wall -fno-common -fno-strict-aliasing -Wfatal-errors
+CPU_OPT = -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16
+
+INC := $(INCDIR)
+INC += $(CMSIS_DEVSUP)/Include $(CMSIS_CORESUP)
+
+STARTUP_SRC = $(CMSIS_DEVSUP)/Source/Templates/gcc/startup_$(STARTUP_FILE).s
+STARTUP_OBJ = $(OBJ_OUT)/startup_$(STARTUP_FILE).o
+#SYSTEM_SRC = $(CMSIS_DEVSUP)/Source/Templates/system_$(SYSTEM_FILE).c
+#SYSTEM_OBJ = $(OBJ_OUT)/system_$(SYSTEM_FILE).o
+
+include $(CSRCDIR)/stm-common.mk
--- /dev/null
+OCD = @echo "set OCD in project makefile"
+
+OCD-jlink := openocd -f interface/jlink.cfg -f target/stm32f7x.cfg
+OCD-vsllink := openocd -f interface/vsllink.cfg -c "transport select jtag" -f target/stm32f7x.cfg
+OCD-arm-usb-ocd := openocd -f interface/ftdi/olimex-arm-usb-ocd.cfg -f target/stm32f7x.cfg
+OCD-stlink := openocd -f interface/stlink-v2.cfg -c "transport select hla_swd" -f target/stm32f7x.cfg
+OCD-discovery := openocd -f board/stm32f7discovery.cfg
+OCD-nucleo := openocd -f interface/stlink-v2-1.cfg -c "transport select hla_swd" -f target/stm32f7x.cfg
+
+OCD_RESET = $(OCD) -c init -c "reset run" -c shutdown
+OCD_FLASH = $(OCD) -c init -c "reset halt" \
+ -c "flash write_image erase "$(BIN)" 0x08000000" \
+ -c "reset run" \
+ -c shutdown
+
+OCD_ZFLASH = $(OCD) -c init -c "reset halt" \
+ -c "flash write_image erase "$(BINZ)" $(ZSTRT)" \
+ -c "reset run" \
+ -c shutdown
+
+OCD_FFLASH = $(OCD) -c init -c "reset halt" \
+ -c "flash write_image erase "$(BIN)" $(FSTRT)" \
+ -c "reset run" \
+ -c shutdown
+
+#OCD_GDB = $(OCD) -c "{stm32f7x}.cpu configure -rtos auto;"
+OCD_GDB = $(OCD)
--- /dev/null
+#Common makefile include for all projectes\r
+\r
+ifeq ($(SPECS),none)\r
+ SPECS :=\r
+else\r
+ifeq ($(SPECS),)\r
+ SPECS := -specs=nano.specs\r
+endif\r
+endif\r
+\r
+ifeq ($(SYSTEM),)\r
+S_GCC :=\r
+ifeq ($(S_GCC),)\r
+SYSTEM := $(shell ls -rd /usr/local/gcc-arm-none-eabi-* 2>/dev/null |head -n 1)/bin/arm-none-eabi\r
+S_GCC := $(shell which $(SYSTEM)-gcc 2>/dev/null)\r
+endif\r
+ifeq ($(S_GCC),)\r
+SYSTEM := arm-none-eabi\r
+S_GCC := $(shell which $(SYSTEM)-gcc 2>/dev/null)\r
+endif\r
+ifeq ($(S_GCC),)\r
+SYSTEM := echo "arm-none-eabi toolchain not found "; false -\r
+S_GCC :=\r
+endif\r
+$(info using gcc: $(S_GCC) ) \r
+endif\r
+\r
+SRCS_C += $(SRCS_ADD)\r
+SRCS_C += $(wildcard $(patsubst %,%/*.c,$(PORTDIRS))) \r
+SRCS_C += $(wildcard $(patsubst %,%/*.c,$(CSRCDIRS)))\r
+SRCS_C += $(LIBSRCS)\r
+VPATH := $(COMDIR)\r
+\r
+GLBL_GCC = -ffunction-sections -fdata-sections -fmessage-length=0\r
+CFLAGS1 = $(CPU_OPT) $(CMSIS_OPT) $(OTHER_OPT) $(LIBS_OPT) $(GCC_OPT) $(OPTIMIZE) $(GLBL_GCC)\r
+CFLAGS = $(CFLAGS1) $(patsubst %,-I%,$(INC)) \r
+ASFLAGS = $(CFLAGS) -x assembler-with-cpp\r
+LDFLAGS = $(CFLAGS1) $(SPECS) -Wl,--gc-sections,-Map=$(MAP),-cref$(LDOPT) -T $(LDDIR)/$(LDSCRIPT) $(patsubst %,-L%,$(LDINC)) \r
+ARFLAGS = cr\r
+OBJCOPYBIN = -Obinary\r
+OBJCOPYHEX = -Oihex\r
+OBJCOPYS19 = -Osrec\r
+OBJDUMPFLAGS = -S\r
+\r
+CC = $(SYSTEM)-gcc\r
+CCDEP = $(SYSTEM)-gcc\r
+LD = $(SYSTEM)-gcc\r
+AR = $(SYSTEM)-ar\r
+AS = $(SYSTEM)-gcc\r
+OBJCOPY = $(SYSTEM)-objcopy\r
+OBJDUMP = $(SYSTEM)-objdump\r
+SIZE = $(SYSTEM)-size\r
+GDB = $(SYSTEM)-gdb\r
+\r
+OBJ_OUT = $(OBJDIR)\r
+\r
+OUT = $(PJNAME).out\r
+BIN = $(PJNAME).bin\r
+BINZ = $(PJNAME).bin.gz\r
+LST = $(PJNAME).list\r
+HEX = $(PJNAME).hex\r
+S19 = $(PJNAME).s19\r
+MAP = $(PJNAME).map\r
+DEP = $(PJNAME).d\r
+\r
+OBJSC := $(patsubst %.c,%.o,$(SRCS_C)) \r
+OBJSC := $(patsubst $(COMDIR)/%,%,$(OBJSC)) \r
+OBJSC := $(patsubst %,$(OBJ_OUT)/%,$(OBJSC)) \r
+#OBJSC := $(abspath $(OBJSC)) \r
+\r
+OBJSS := $(patsubst %.s,%.o,$(SRCS_S))\r
+OBJSS := $(patsubst $(COMDIR)/%,%,$(OBJSS)) \r
+OBJSS := $(patsubst %,$(OBJ_OUT)/%,$(OBJSS)) \r
+#OBJSS := $(abspath $(OBJSS)) \r
+\r
+SRCS = $(SRCS_C) $(SRCS_S)\r
+OBJS = $(OBJSC) $(OBJSS) $(STARTUP_OBJ) $(SYSTEM_OBJ)\r
+\r
+info:\r
+ $(info using cc toolchain : $(SYSTEM))\r
+ $(info project export to : $(EXPDIR)/$(PJNAME))\r
+ $(info using cc options : $(CFLAGS))\r
+# $(info using as options : $(ASFLAGS))\r
+ $(info using ld options : $(LDFLAGS))\r
+ $(info objects to build : $(OBJS))\r
+ $(info archives to build : $(LIBS))\r
+ $(info sources : $(SRCS))\r
+# $(info c sources : $(SRCS_C))\r
+# @$(CC) --version\r
+\r
+all: $(BIN)\r
+\r
+ifeq '$(BL)' '-bl1'\r
+#all: $(BINZ)\r
+endif\r
+\r
+ifeq '$(BL)' '-bl'\r
+#all: $(S19)\r
+endif\r
+\r
+filelist: $(OUT)\r
+ make --debug=v |grep -E "(Prerequisite )|(makefile )" |sed -e s/\`/\'/ |cut -d "'" -f 2 |sort |uniq |grep -v -E "([.][ado])|([.]out)\$$" >filelist\r
+ -test -d cube && find cube/ -iname "*.ioc" >>filelist \r
+ @echo $(FILES_ADD) >>filelist \r
+\r
+pjexport: filelist\r
+ -mkdir -p $(EXPDIR)/$(PJNAME)\r
+ -mkdir -p $(EXPDIR)/$(PJNAME)/a\r
+ -mkdir -p $(EXPDIR)/$(PJNAME)/o\r
+ cp -v --parents `cat filelist` ../Makefile $(EXPDIR)/$(PJNAME) \r
+\r
+reset:\r
+ $(OCD_RESET)\r
+\r
+ifeq '$(BL)' '-bl1'\r
+flashz: $(BINZ)\r
+ $(OCD_ZFLASH)\r
+\r
+flash: $(BIN)\r
+ $(OCD_FFLASH)\r
+\r
+else\r
+ifeq '$(BL)' '-bl'\r
+flash: $(BIN) $(HEX) \r
+ $(BLTCS) -i $(BIN) -o $(BIN).out\r
+ $(OCD_BFLASH) \r
+\r
+else\r
+flash: $(BIN) $(HEX)\r
+ $(OCD_FLASH)\r
+endif\r
+endif\r
+ \r
+gdb:\r
+ $(OCD_GDB)\r
+\r
+ifeq '$(BL)' '-bl' \r
+boot: $(S19) $(BLTCMD)\r
+ $(BLT) $(S19)\r
+endif\r
+\r
+$(HEX): $(OUT)\r
+ @echo objcopy $(HEX)\r
+ @$(OBJCOPY) $(OBJCOPYHEX) $(OUT) $(HEX)\r
+\r
+$(S19): $(BIN) $(BLTCS)\r
+ $(BLTCS) -i $(BIN) -o $(BIN).out\r
+ $(SREC) $(BIN).out -binary -offset $(VTOR_INIT) -o $(S19)\r
+ $(SREC_INFO) $(S19)\r
+ -rm -f $(BIN).out\r
+ \r
+$(BIN): $(OUT)\r
+ @echo objcopy $(BIN)\r
+ @$(OBJCOPY) $(OBJCOPYBIN) $(OUT) $(BIN)\r
+ @echo objdump $(LST)\r
+ @$(OBJDUMP) $(OBJDUMPFLAGS) $(OUT) > $(LST)\r
+ @echo size $(OUT)\r
+ @$(SIZE) $(OUT)\r
+ifeq '$(BL)' '-bl1'\r
+ @echo gzip $(BIN)\r
+ @gzip -c $(BIN) >$(BINZ) \r
+endif \r
+ @echo Make finished\r
+ \r
+#$(BINZ): $(BIN)\r
+# @echo gzip $(BIN)\r
+# @gzip -c $(BIN) >$(BINZ) \r
+\r
+$(OUT): $(GEN_ADD) $(LIBS) $(OBJS) $(LDDIR)/$(LDSCRIPT)\r
+ @echo ld $@\r
+# @echo $(LD) $(LDFLAGS) -o $@\r
+ @$(LD) $(LDFLAGS) -o $@ $(OBJS) -Wl,--start-group,--whole-archive $(LIBS) -Wl,--end-group,--no-whole-archive $(STDLIBS)\r
+\r
+#$(LIBS):\r
+# ${MAKE} -C $@\r
+# @$(foreach LIB,$(LIBDIRS),${MAKE} -C $(LIB) || exit 1;)\r
+ \r
+-include $(LIBS:.a=.d)\r
+\r
+gen: clean-gen $(GEN_ADD)\r
+\r
+clean:\r
+ @-rm -f $(OBJS) $(OBJS:.o=.d) $(OBJS:.o=.sl) $(OUT) $(BIN) $(BINZ) $(HEX) $(S19) $(LST) $(MAP) $(DEP) $(CLEAN_ADD)\r
+ @$(foreach LIB,$(LIBS),${MAKE} -s -C $(LIBDIR) -f $(patsubst $(ARDIR)/%.a,%.mk,$(LIB)) clean || exit 1;)\r
+ @-rm -f jlink.reset jlink.flash filelist\r
+\r
+clean-nl:\r
+ @-rm -f $(OBJS) $(OBJS:.o=.d) $(OBJS:.o=.sl) $(OUT) $(BIN) $(BINZ) $(HEX) $(S19) $(LST) $(MAP) $(DEP)\r
+# @$(foreach LIB,$(LIBS),${MAKE} -s -C $(LIBDIR) -f $(patsubst $(ARDIR)/%.a,%.mk,$(LIB)) clean || exit 1;)\r
+ @-rm -f jlink.reset jlink.flash filelist\r
+\r
+clean-add:\r
+ @-rm -f $(CLEAN_ADD)\r
+\r
+clean-gen:\r
+ @-rm -f $(GEN_ADD)\r
+\r
+depend dep: $(DEP)\r
+\r
+#$(DEP): Src/*.c\r
+# $(CCDEP) $(CFLAGS) -MM $^ | sed -e 's@.*.o:@Src/&@' > $(DEP) \r
+\r
+#$(DEP): $(LIB_SRCS_C)\r
+# $(CCDEP) $(CFLAGS) -MM $^ > $(DEP) \r
+\r
+#$(DEP): $(SRCS)\r
+# @rm -f $(DEP)\r
+# @$(foreach SRC,$(SRCS_S),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.s=.o) $(SRC) >> $(DEP);)\r
+# @$(foreach SRC,$(SRCS_C),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.c=.o) $(SRC) >> $(DEP);)\r
+\r
+$(LIBS): %.a:\r
+ @-mkdir -p a\r
+ ${MAKE} -C $(LIBDIR) -f $(patsubst $(ARDIR)/%,%,$*).mk\r
+\r
+$(SYSTEM_OBJ): $(SYSTEM_SRC)\r
+ @echo cc $<\r
+ @$(CC) $(CFLAGS) -MMD -c -o $@ $<\r
+\r
+$(STARTUP_OBJ): $(STARTUP_SRC)\r
+ @echo as $<\r
+ @$(AS) $(CFLAGS) -MMD -c -o $@ $<\r
+\r
+$(OBJSC): $(OBJ_OUT)/%.o: %.c\r
+ @mkdir -p $(dir $@)\r
+ifeq ($(SHOWPJ),1)\r
+ @echo cc \[$(PJNAME)\] $<\r
+else\r
+ @echo cc $<\r
+endif\r
+# @echo $(CFLAGS) \r
+ @$(CC) $(CFLAGS) -MMD -c -o $@ -Wa,-adhln=$(@:.o=.sl) $<\r
+# @$(CC) $(CFLAGS) --save-temps -MMD -c -o $@ $<\r
+# @$(CC) $(CFLAGS) -MMD -c -o $@ $<\r
+\r
+$(OBJSS): $(OBJ_OUT)/%.o: %.s\r
+ @mkdir -p $(dir $@)\r
+ @echo as $<\r
+ @$(AS) $(ASFLAGS) -MMD -c -o $@ $<\r
+\r
+-include $(OBJS:.o=.d)\r
+#-include $(DEP)\r
+\r
+$(OBJS) $(LIBS): Makefile $(COMDIR)/pj/pjhdr.mk $(COMDIR)/pj/pj.mk $(COMDIR)/lib/lib.mk\r
--- /dev/null
+ZZZ := $(shell rm -fv cln)
+
+ifeq ($(AUTOJ),1)
+CORES := $(shell expr `grep -c ^processor /proc/cpuinfo` + 1)
+NUMJOBS := -j $(CORES)
+MAKEFLAGS += $(NUMJOBS)
+endif
+
+#$(info $(CORES))
+
+PJNAME := $(notdir $(CURDIR))
+PJDIR := ../$(notdir $(CURDIR))
+
+ifeq ($(EXPDIR),)
+EXPDIR := ../../export
+endif
+
+OBJDIR := o
+ARDIR := a
+SRCDIR := src
+INCDIR := inc
+LDDIR := $(COMDIR)/ld
+LDINC :=
+LDOPT :=
+LIBDIR := $(COMDIR)/lib
+CSRCDIR := $(COMDIR)/src
+PORTDIR := port
+CUBEDIR := cube
+
+LIBS :=
+LIBDIRS :=
+LIBSRCS :=
+PORTDIRS :=
+CSRCDIRS :=
+LIBS_OPT :=
+SRCS_ADD :=
+CLEAN_ADD :=
+
+current_mk = $(patsubst %.mk,%, $(notdir $(lastword $(MAKEFILE_LIST))))
+
+.phony all:
--- /dev/null
+CSRCD := $(call current_mk)\r
+\r
+#$(info including $(CSRCD))\r
+\r
+INC += $(CSRCDIR)/$(CSRCD)\r
--- /dev/null
+CSRCD := $(call current_mk)\r
+#CSRCD := syscalls\r
+\r
+ifeq '$(INCLIBS)' 'src'\r
+\r
+$(info including $(CSRCD))\r
+\r
+INC += $(CSRCDIR)/$(CSRCD)\r
+CSRCDIRS += $(CSRCDIR)/$(CSRCD) \r
+\r
+endif\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* SYSCALLS.C: System Calls for the newlib */\r
+/* most of this is from newlib-lpc and a Keil-demo */\r
+/* */\r
+/* These are "reentrant functions" as needed by */\r
+/* the WinARM-newlib-config, see newlib-manual. */\r
+/* Collected and modified by Martin Thomas */\r
+/* */\r
+/***********************************************************************/\r
+\r
+\r
+#include <stdlib.h>\r
+#include <reent.h>\r
+#include <errno.h>\r
+#include <sys/stat.h>\r
+\r
+_ssize_t _read_r(\r
+ struct _reent *r, \r
+ int file, \r
+ void *ptr, \r
+ size_t len)\r
+{\r
+ /*\r
+ unsigned char *p;\r
+ while ( AT91F_US_RxReady((AT91PS_USART)AT91C_BASE_DBGU) == 0 ) {\r
+ ;\r
+ }\r
+ \r
+ p = ptr;\r
+ \r
+ *p= AT91F_US_GetChar((AT91PS_USART)AT91C_BASE_DBGU);\r
+ */\r
+ return (_ssize_t)1;\r
+}\r
+\r
+\r
+_ssize_t _write_r (\r
+ struct _reent *r, \r
+ int file, \r
+ const void *ptr, \r
+ size_t len)\r
+{\r
+ /*\r
+ size_t todo;\r
+ const unsigned char *p;\r
+ \r
+ todo = len;\r
+ p = ptr;\r
+\r
+ for( ; todo != 0; todo--) {\r
+ if ( *p == '\n' ) {\r
+ while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)) {\r
+ ;\r
+ }\r
+ AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, '\r');\r
+ }\r
+ while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)) {\r
+ ;\r
+ }\r
+ AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *p++);\r
+ }\r
+ */\r
+ return (_ssize_t)len; // Number of bytes written.\r
+}\r
+\r
+\r
+int _close_r(\r
+ struct _reent *r, \r
+ int file)\r
+{\r
+ return 0;\r
+}\r
+\r
+\r
+_off_t _lseek_r(\r
+ struct _reent *r, \r
+ int file, \r
+ _off_t ptr, \r
+ int dir)\r
+{\r
+ return (_off_t)0; /* Always indicate we are at file beginning. */\r
+}\r
+\r
+\r
+int _fstat_r(\r
+ struct _reent *r, \r
+ int file, \r
+ struct stat *st)\r
+{\r
+ /* Always set as character device. */\r
+ st->st_mode = S_IFCHR;\r
+ /* assigned to strong type with implicit */\r
+ /* signed/unsigned conversion. Required by */\r
+ /* newlib. */\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+int _isatty(int file); /* avoid warning */\r
+\r
+int _isatty(int file)\r
+{\r
+ return 1;\r
+}\r
+\r
+void abort(void)\r
+{\r
+ while(1);\r
+}\r
+\r
+#if 0\r
+static void _exit (int n) {\r
+label: goto label; /* endless loop */\r
+}\r
+#endif \r
+\r
+\r
+#ifdef USE_CHIBIOS\r
+\r
+void * _sbrk_r(struct _reent *r, int incr)\r
+{\r
+#if CH_USE_MEMCORE\r
+ void *p;\r
+\r
+ chDbgCheck(incr > 0, "_sbrk_r");\r
+\r
+ (void)r;\r
+ p = chCoreAlloc((size_t)incr);\r
+ if (p == NULL) {\r
+ __errno_r(r) = ENOMEM;\r
+ return (caddr_t)-1;\r
+ }\r
+ return (caddr_t)p;\r
+#else\r
+ __errno_r(r) = ENOMEM;\r
+ return (caddr_t)-1;\r
+#endif\r
+}\r
+\r
+\r
+#else\r
+/**** Locally used variables. ****/\r
+// mt: "cleaner": extern char* end;\r
+extern char end[]; /* end is set in the linker command */\r
+ /* file and is the end of statically */\r
+ /* allocated data (thus start of heap). */\r
+\r
+static char *heap_ptr; /* Points to current end of the heap. */\r
+\r
+/************************** _sbrk_r *************************************\r
+ * Support function. Adjusts end of heap to provide more memory to\r
+ * memory allocator. Simple and dumb with no sanity checks.\r
+\r
+ * struct _reent *r -- re-entrancy structure, used by newlib to\r
+ * support multiple threads of operation.\r
+ * ptrdiff_t nbytes -- number of bytes to add.\r
+ * Returns pointer to start of new heap area.\r
+ *\r
+ * Note: This implementation is not thread safe (despite taking a\r
+ * _reent structure as a parameter).\r
+ * Since _s_r is not used in the current implementation, \r
+ * the following messages must be suppressed.\r
+ */\r
+void * _sbrk_r(\r
+ struct _reent *_s_r, \r
+ ptrdiff_t nbytes)\r
+{\r
+ char *base; /* errno should be set to ENOMEM on error */\r
+\r
+ if (!heap_ptr) { /* Initialize if first time through. */\r
+ heap_ptr = end;\r
+ }\r
+ base = heap_ptr; /* Point to end of heap. */\r
+ heap_ptr += nbytes; /* Increase heap. */\r
+ \r
+ return base; /* Return pointer to start of new heap area. */\r
+}\r
+#endif\r
+++ /dev/null
-#include <stdio.h>
-#include <stdlib.h>
-
-#include "mTaskSymbols.h"
-#include "interpret.h"
-#include "misc.h"
-#include "task.h"
-#include "sds.h"
-
-#ifdef ARDUINO
-#define trace(op, ...) ;
-#else
-#define trace(op, ...) printf("pc: %d, sp: %d, op: " op, pc, sp, ##__VA_ARGS__);
-#endif
-
-void run_task(struct task *t)
-{
- uint8_t *program = t->bc;
- int plen = t->tlen;
- int pc = 0;
- int sp = 0;
- char stack[STACKSIZE] = {0};
- printf("Running task with length: %d\n", plen);
- while(pc != plen){
- printf("program: %d\n", program[pc]);
- printf("stack: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
- stack[0], stack[1], stack[2], stack[3], stack[4],
- stack[5], stack[6], stack[7], stack[8], stack[9]);
-
- switch(program[pc++]){
- case BCNOP: trace("nop\n");
- break;
- case BCLAB: trace("label: 0x%02x!!!!!!\n", program[pc]);
- pc++;
- break;
- case BCPUSH: trace("push %d\n", program[pc]*265+program[pc+1]);
- stack[sp++] = program[pc]*265 + program[pc+1];
- pc+=2;
- break;
- case BCPOP: trace("pop\n");
- sp--;
- break;
- case BCSDSSTORE: trace("sds store: %d\n", program[pc]);
- sds_store(program[pc++], stack[--sp]);
- break;
- case BCSDSFETCH: trace("sds fetch: %d\n", program[pc]);
- stack[sp++] = sds_fetch(program[pc++]);
- break;
- case BCSDSPUBLISH: trace("sds publish %d\n", program[pc]);
- sds_publish(program[pc++]);
- break;
- case BCNOT: trace("not\n");
- stack[sp] = stack[sp] > 0 ? 0 : 1;
- break;
- case BCADD: trace("add\n");
- stack[sp-2] = stack[sp-1] + stack[sp-2];
- sp -= 1;
- break;
- case BCSUB: trace("sub\n");
- stack[sp-2] = stack[sp-1] - stack[sp-2];
- sp -= 1;
- break;
- case BCMUL: trace("mul\n");
- stack[sp-2] = stack[sp-1] * stack[sp-2];
- sp -= 1;
- break;
- case BCDIV: trace("div\n");
- stack[sp-2] = stack[sp-1] / stack[sp-2];
- sp -= 1;
- break;
- case BCAND: trace("and\n");
- stack[sp-2] = stack[sp-1] && stack[sp-2];
- sp -= 1;
- break;
- case BCOR: trace("or\n");
- stack[sp-2] = stack[sp-1] || stack[sp-2];
- sp -= 1;
- break;
- case BCEQ: trace("eq\n");
- stack[sp-2] = stack[sp-1] == stack[sp-2];
- sp -= 1;
- break;
- case BCNEQ: trace("neq\n");
- stack[sp-2] = stack[sp-1] != stack[sp-2];
- sp -= 1;
- break;
- case BCLES: trace("les\n");
- stack[sp-2] = stack[sp-1] < stack[sp-2];
- sp -= 1;
- break;
- case BCGRE: trace("gre\n");
- stack[sp-2] = stack[sp-1] > stack[sp-2];
- sp -= 1;
- break;
- case BCLEQ: trace("leq\n");
- stack[sp-2] = stack[sp-1] <= stack[sp-2];
- sp -= 1;
- break;
- case BCGEQ: trace("geq\n");
- stack[sp-2] = stack[sp-1] >= stack[sp-2];
- sp -= 1;
- break;
- case BCJMP: trace("jmp to %d\n", program[pc]);
- pc = program[pc]-1;
- break;
- case BCJMPT: trace("jmpt to %d\n", program[pc]);
- pc = stack[--sp] ? program[pc]-1 : pc+1;
- break;
- case BCJMPF: trace("jmpf to %d\n", program[pc]);
- pc = stack[--sp] ? pc+1 : program[pc]-1;
- break;
- case BCSERIALAVAIL: trace("SerialAvailable()\n");
- break;
- case BCSERIALPRINT: trace("SerialPrint()\n");
- break;
- case BCSERIALPRINTLN: trace("SerialPrintln()\n");
- break;
- case BCSERIALREAD: trace("SerialRead()\n");
- break;
- case BCSERIALPARSEINT: trace("SerialParseInt()\n");
- break;
- case BCANALOGREAD: trace("AnalogRead(%d)\n", program[pc]);
- pc++;
- break;
- case BCANALOGWRITE: trace("AnalogWrite(%d)\n", program[pc]);
- pc++;
- break;
- case BCDIGITALREAD: trace("DigitalRead(%d)\n", program[pc]);
- pc++;
- break;
- case BCDIGITALWRITE: trace("DigitalWrite(%d)\n", program[pc]);
- pc++;
- break;
- default:
- trace("unrecognized\n");
- die("Unrecognized command: %d\n", program[pc-1]);
- }
- }
- debug("Task terminated\n");
-}
+++ /dev/null
-#ifndef INTEPRET_H
-#define INTEPRET_H
-
-#define STACKSIZE 1024
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "task.h"
-
-void run_task(struct task *task);
-
-#endif
+++ /dev/null
-#ifndef MTASK_H
-#define MTASK_H
-#define BCNOP 1
-#define BCLAB 2
-#define BCPUSH 3
-#define BCPOP 4
-#define BCSDSSTORE 5
-#define BCSDSFETCH 6
-#define BCSDSPUBLISH 7
-#define BCNOT 8
-#define BCADD 9
-#define BCSUB 10
-#define BCMUL 11
-#define BCDIV 12
-#define BCAND 13
-#define BCOR 14
-#define BCEQ 15
-#define BCNEQ 16
-#define BCLES 17
-#define BCGRE 18
-#define BCLEQ 19
-#define BCGEQ 20
-#define BCJMP 21
-#define BCJMPT 22
-#define BCJMPF 23
-#define BCSERIALAVAIL 24
-#define BCSERIALPRINT 25
-#define BCSERIALPRINTLN 26
-#define BCSERIALREAD 27
-#define BCSERIALPARSEINT 28
-#define BCANALOGREAD 29
-#define BCANALOGWRITE 30
-#define BCDIGITALREAD 31
-#define BCDIGITALWRITE 32
-#define BCTEST 33
-#endif
+++ /dev/null
-#define _DEFAULT_SOURCE
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-#ifdef ARDUINO
-#include <Arduino.h>
-#include <HardwareSerial.h>
-#else
-#include <stdbool.h>
-#include <netdb.h>
-#include <netinet/in.h>
-#include <signal.h>
-#include <stdio.h>
-#include <sys/socket.h>
-#include <sys/time.h>
-#include <sys/types.h>
-#include <unistd.h>
-#endif
-
-#include "interpret.h"
-#include "mTaskSymbols.h"
-#include "sds.h"
-#include "task.h"
-#include "misc.h"
-
-#define MAXSDS 50
-
-#define MSG_GET_TASK 't'
-#define MSG_DEL_TASK 'd'
-#define MSG_SDS_SPEC 's'
-#define MSG_SDS_UPD 'u'
-
-//Globals
-#ifndef ARDUINO
-struct timeval tv1;
-int sock_fd = -1;
-int fd = -1;
-int *argc;
-char **argv;
-char bt;
-#endif
-
-#ifndef ARDUINO
-long millis() {
- if (gettimeofday(&tv1, NULL) == -1)
- pdie("gettimeofday");
- return tv1.tv_sec*1000 + tv1.tv_usec/1000;
-}
-#endif
-
-bool input_available(){
-#ifdef ARDUINO
- return Serial.available();
-#else
- struct timeval tv;
- fd_set fds;
- tv.tv_sec = 0;
- tv.tv_usec = 0;
- FD_ZERO(&fds);
- FD_SET(fd, &fds);
- if (select(fd+1, &fds, NULL, NULL, &tv) == -1)
- pdie("select");
- return FD_ISSET(fd, &fds);
-#endif
-}
-
-uint8_t read_byte()
-{
-#ifdef ARDUINO
- return Serial.read();
-#else
- read(fd, &bt, 1);
- return bt;
-#endif
-}
-
-void write_byte(uint8_t b)
-{
-#ifdef ARDUINO
- Serial.write(b);
-#else
- write(fd, &b, 1);
-#endif
-}
-
-void sleep(int ms)
-{
-#ifdef ARDUINO
- delay(ms);
-#else
- usleep(ms*1000);
-#endif
-}
-
-#ifndef ARDUINO
-void killHandler(int i)
-{
- printf("%i caught, Bye...\n", i);
- exit(1);
-}
-#endif
-
-void read_message()
-{
- //Find next task
- uint8_t c = read_byte();
- debug("Receiving input: %c\n", c);
- switch(c){
- case MSG_SDS_SPEC:
- debug("Receiving an sds\n");
- sds_register();
- break;
- case MSG_SDS_UPD:
- debug("Receiving an sds\n");
- //TODO do something with the return value
- sds_update();
- break;
- case MSG_DEL_TASK:
- debug("Receiving a delete task request\n");
- task_delete();
- break;
- case MSG_GET_TASK:
- debug("Receiving a task\n");
- c = task_register();
-// write(fd_out, &c, 1);
-// write(fd_out,
- break;
- case '\n':
- break;
-// case '\0':
-// debug("iTasks server shut down\n");
-// exit(EXIT_SUCCESS);
- default:
- debug("Unknown message: %X\n", c);
- }
-}
-
-void open_filedescriptors()
-{
-}
-
-void usage(FILE *o, char *arg0){
- fprintf(o,
- "Usage: %s [opts]\n"
- "\n"
- "Options\n"
- "-p PORT Custom port number, default: 8123\n"
- , arg0);
-}
-
-void setup()
-{
-#ifdef ARDUINO
- Serial.begin(9600);
-#else
- int port = 8123, opti = 1;
- //Register signal handler
- if(signal(SIGINT, killHandler) == SIG_ERR){
- die("Couldn't register signal handler...\n");
- }
- if(signal(SIGTERM, killHandler) == SIG_ERR){
- die("Couldn't register signal handler...\n");
- }
- //Command line arguments
- while(opti < *argc){
- if(strcmp((*argv)+opti, "-h") == 0){
- usage(stdout, argv[0]);
- exit(EXIT_SUCCESS);
- } else if(strcmp(argv[opti], "-p") == 0 && opti+1<*argc){
- port = atoi(argv[++opti]);
- if(port < 1)
- die("Port numbers are > 1\n");
- } else {
- usage(stderr, argv[0]);
- exit(EXIT_FAILURE);
- }
- opti++;
- }
-
- //Open file descriptors
- struct sockaddr_in sa;
-
- memset(&sa, 0, sizeof(sa));
- sa.sin_family = AF_INET;
- sa.sin_addr.s_addr = INADDR_ANY;
- sa.sin_port = htons(port);
-
- if((sock_fd = socket(AF_INET, SOCK_STREAM, 0)) == -1)
- pdie("socket");
- if(bind(sock_fd, (struct sockaddr*)&sa, sizeof(sa)) == -1)
- pdie("bind");
- if(listen(sock_fd, 10) == -1)
- pdie("listen");
-
- printf("Listening on %d\n", port);
- fflush(stdout);
- if((fd = accept(sock_fd, (struct sockaddr*)NULL, NULL)) == -1)
- pdie("accept");
-#endif
-
- //Initialize systems
- sds_init();
- task_init();
-}
-
-void loop()
-{
- int ct;
- long cyclestart;
- struct task *curtask;
- if(input_available())
- read_message();
- //Run tasks
- cyclestart = millis();
- for(ct = 0; ct<MAXTASKS; ct++){
- //See whether the task is even in use
- if((curtask = task_get(ct)) == NULL){
-// debug("Task %d not implemented\n", ct);
- continue;
- }
- //See whether the task interval has passed
- if(cyclestart-curtask->lastrun < curtask->interval){
-// debug("Task %d not scheduled\n", ct);
- continue;
- }
-#ifdef DEBUG
- printf("Current task to run: %d\n", ct);
- getchar();
-#endif
- run_task(curtask);
- }
- debug("Waiting for 500ms\n");
- sleep(500);
- debug("done waiting\n");
- write_byte('\n');
-}
-
-int main(int ac, char *av[])
-{
-#ifndef ARDUINO
- argc = ∾
- argv = av;
-#endif
- setup();
-
- write_byte('\n');
-
- while(true){
- //Check for new tasks
- }
- return 0;
-}
+++ /dev/null
-#ifndef MAIN_H
-#define MAIN_H
-
-#include <stdint.h>
-
-uint8_t read_byte();
-void write_byte(uint8_t b);
-#endif
+++ /dev/null
-#ifndef MISC_H
-#define MISC_H
-#include "main.h"
-
-#define read16() 256*read_byte() + read_byte()
-#ifdef ARDUINO
-#define debug(s, ...) ;
-#define pdie(s) ;
-#define die(s, ...) ;
-#else
-
-#ifdef DEBUG
-#define debug(s, ...) printf(s, ##__VA_ARGS__);
-#else
-#define debug(s, ...) ;
-#endif
-
-#define pdie(s) {perror(s); exit(1);}
-#define die(s, ...) {fprintf(stderr, s, ##__VA_ARGS__); exit(1);}
-#endif
-
-#endif
+++ /dev/null
-#include <stdlib.h>
-#include <string.h>
-
-#ifndef ARDUINO
-#include <unistd.h>
-#include <stdio.h>
-#endif
-
-#include "main.h"
-#include "interpret.h"
-#include "misc.h"
-#include "sds.h"
-
-struct sds sdss[MAXSDSS];
-uint8_t c;
-
-void sds_init()
-{
- memset(&sdss, 0, sizeof(struct sds)*MAXSDSS);
-}
-
-void sds_register()
-{
- uint8_t cs;
- for(cs = 0; cs<MAXSDSS; cs++)
- if(!sdss[cs].used)
- break;
-
- if(cs == MAXSDSS)
- die("Trying to add too much tasks...\n");
-
- memset(&sdss[cs], 0, sizeof(struct sds));
- //Read identifier
- sdss[cs].id = read16();
- //Read value
- sdss[cs].value = read16();
-
- debug("\nReceived sds %d: %d\n", sdss[cs].id, sdss[cs].value);
- sdss[cs].used = true;
-}
-
-bool sds_update()
-{
- uint8_t cs, id;
- //Read identifier
- id = read_byte();
-
- for(cs = 0; cs<MAXSDSS; cs++){
- if(!sdss[cs].used)
- continue;
- if(sdss[cs].id == id){
- //Read value
- sdss[cs].value = read16();
- return true;
- }
- }
- return false;
-}
-
-void sds_publish(int id)
-{
- uint8_t cs;
- for(cs = 0; cs<MAXSDSS; cs++){
- if(sdss[cs].used && sdss[cs].id == id){
- debug("Publish %d=%d\n", sdss[cs].id, sdss[cs].value);
- write_byte('u');
- write_byte(0);
- write_byte(sdss[cs].id);
- write_byte(sdss[cs].value/265);
- write_byte(sdss[cs].value%265);
- return;
- }
- }
- debug("SDS identifier unknown: %d\n", id);
-}
-
-int sds_fetch(int id)
-{
- uint8_t cs;
- for(cs = 0; cs<MAXSDSS; cs++)
- if(sdss[cs].used && sdss[cs].id == id)
- return sdss[cs].value;
- debug("SDS identifier unknown: %d\n", id);
- return 0;
-}
-
-void sds_store(int id, int val)
-{
- uint8_t cs;
- for(cs = 0; cs<MAXSDSS; cs++) {
- if(sdss[cs].used && sdss[cs].id == id){
- sdss[cs].value = val;
- return;
- }
- }
- debug("SDS identifier unknown: %d\n", id);
-}
+++ /dev/null
-#ifndef SDS_H
-#define SDS_H
-
-#include <stdbool.h>
-
-#define MAXSDSS 100
-
-struct sds {
- int id;
- int value;
- bool used;
-};
-
-void sds_init();
-void sds_register();
-bool sds_update();
-void sds_publish(int id);
-int sds_fetch(int id);
-void sds_store(int id, int val);
-
-#endif
+++ /dev/null
-#include <stdlib.h>
-#include <string.h>
-
-#ifdef ARDUINO
-#include <Arduino.h>
-#include <HardwareSerial.h>
-#else
-#include <unistd.h>
-#include <stdio.h>
-#endif
-
-#include "misc.h"
-#include "task.h"
-
-struct task tasks[MAXTASKS];
-
-void task_init()
-{
- memset(&tasks, 0, sizeof(struct task)*MAXTASKS);
-}
-
-int task_register()
-{
- uint8_t ct;
-
- for(ct = 0; ct<MAXTASKS; ct++)
- if(!tasks[ct].used)
- break;
- if(ct == MAXTASKS)
- die("Trying to add too much tasks...\n");
-
- memset(&tasks[ct], 0, sizeof(struct task));
- //Read interval
- tasks[ct].interval = read16();
- //Read tasklength
- tasks[ct].tlen = read16();
-
- if(tasks[ct].tlen > MAXTASKSIZE)
- die("Task is too long: %d\n", tasks[ct].tlen);
- //Read task bytecode
- for(unsigned int i = 0; i<tasks[ct].tlen; i++){
- tasks[ct].bc[i] = read_byte();
- debug("t[][%i]: 0x%02x %d\n", i,
- tasks[ct].bc[i], tasks[ct].bc[i]);
- }
- //Return the task number for later removal
- debug("Received a task of length %d\n", tasks[ct].tlen);
- tasks[ct].used = true;
- return ct;
-}
-
-void task_delete()
-{
- tasks[read_byte()].used = false;
-}
-
-struct task *task_get(int num)
-{
- return tasks[num].used ? &tasks[num] : NULL;
-}
+++ /dev/null
-#ifndef TASK_H
-#define TASK_H
-
-#define MAXTASKS 5
-#define MAXTASKSIZE 1024
-
-#include <stdint.h>
-#include <stdbool.h>
-
-struct task {
- uint8_t bc[MAXTASKSIZE];
- uint16_t tlen;
- uint16_t interval;
- long lastrun;
- bool used;
-};
-
-void task_init();
-int task_register();
-void task_delete();
-struct task *task_get(int num);
-
-#endif
repositories / mTask.git / commitdiff